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clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson b3867679 1a2789cf

+463 -215
+463 -215
drivers/clk/qcom/gcc-msm8996.c
··· 38 38 .div = 1, 39 39 .hw.init = &(struct clk_init_data){ 40 40 .name = "xo", 41 - .parent_names = (const char *[]){ "xo_board" }, 41 + .parent_data = &(const struct clk_parent_data){ 42 + .fw_name = "cxo", .name = "xo_board", 43 + }, 42 44 .num_parents = 1, 43 45 .ops = &clk_fixed_factor_ops, 44 46 }, ··· 54 52 .enable_mask = BIT(0), 55 53 .hw.init = &(struct clk_init_data){ 56 54 .name = "gpll0_early", 57 - .parent_names = (const char *[]){ "xo" }, 55 + .parent_hws = (const struct clk_hw*[]){ 56 + &xo.hw, 57 + }, 58 58 .num_parents = 1, 59 59 .ops = &clk_alpha_pll_ops, 60 60 }, ··· 68 64 .div = 2, 69 65 .hw.init = &(struct clk_init_data){ 70 66 .name = "gpll0_early_div", 71 - .parent_names = (const char *[]){ "gpll0_early" }, 67 + .parent_hws = (const struct clk_hw*[]){ 68 + &gpll0_early.clkr.hw, 69 + }, 72 70 .num_parents = 1, 73 71 .ops = &clk_fixed_factor_ops, 74 72 }, ··· 81 75 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 82 76 .clkr.hw.init = &(struct clk_init_data){ 83 77 .name = "gpll0", 84 - .parent_names = (const char *[]){ "gpll0_early" }, 78 + .parent_hws = (const struct clk_hw*[]){ 79 + &gpll0_early.clkr.hw, 80 + }, 85 81 .num_parents = 1, 86 82 .ops = &clk_alpha_pll_postdiv_ops, 87 83 }, ··· 96 88 .enable_mask = BIT(0), 97 89 .hw.init = &(struct clk_init_data){ 98 90 .name = "gcc_mmss_gpll0_div_clk", 99 - .parent_names = (const char *[]){ "gpll0" }, 91 + .parent_hws = (const struct clk_hw*[]){ 92 + &gpll0.clkr.hw, 93 + }, 100 94 .num_parents = 1, 101 95 .flags = CLK_SET_RATE_PARENT, 102 96 .ops = &clk_branch2_ops, ··· 113 103 .enable_mask = BIT(2), 114 104 .hw.init = &(struct clk_init_data){ 115 105 .name = "gcc_mss_gpll0_div_clk", 116 - .parent_names = (const char *[]){ "gpll0" }, 106 + .parent_hws = (const struct clk_hw*[]){ 107 + &gpll0.clkr.hw, 108 + }, 117 109 .num_parents = 1, 118 110 .flags = CLK_SET_RATE_PARENT, 119 111 .ops = &clk_branch2_ops ··· 131 119 .enable_mask = BIT(4), 132 120 .hw.init = &(struct clk_init_data){ 133 121 .name = "gpll4_early", 134 - .parent_names = (const char *[]){ "xo" }, 122 + .parent_hws = (const struct clk_hw*[]){ 123 + &xo.hw, 124 + }, 135 125 .num_parents = 1, 136 126 .ops = &clk_alpha_pll_ops, 137 127 }, ··· 145 131 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 146 132 .clkr.hw.init = &(struct clk_init_data){ 147 133 .name = "gpll4", 148 - .parent_names = (const char *[]){ "gpll4_early" }, 134 + .parent_hws = (const struct clk_hw*[]){ 135 + &gpll4_early.clkr.hw, 136 + }, 149 137 .num_parents = 1, 150 138 .ops = &clk_alpha_pll_postdiv_ops, 151 139 }, ··· 157 141 { P_SLEEP_CLK, 5 } 158 142 }; 159 143 160 - static const char * const gcc_sleep_clk[] = { 161 - "sleep_clk" 144 + static const struct clk_parent_data gcc_sleep_clk[] = { 145 + { .fw_name = "sleep_clk", .name = "sleep_clk" } 162 146 }; 163 147 164 148 static const struct parent_map gcc_xo_gpll0_map[] = { ··· 166 150 { P_GPLL0, 1 } 167 151 }; 168 152 169 - static const char * const gcc_xo_gpll0[] = { 170 - "xo", 171 - "gpll0" 153 + static const struct clk_parent_data gcc_xo_gpll0[] = { 154 + { .hw = &xo.hw }, 155 + { .hw = &gpll0.clkr.hw } 172 156 }; 173 157 174 158 static const struct parent_map gcc_xo_sleep_clk_map[] = { ··· 176 160 { P_SLEEP_CLK, 5 } 177 161 }; 178 162 179 - static const char * const gcc_xo_sleep_clk[] = { 180 - "xo", 181 - "sleep_clk" 163 + static const struct clk_parent_data gcc_xo_sleep_clk[] = { 164 + { .hw = &xo.hw }, 165 + { .fw_name = "sleep_clk", .name = "sleep_clk" } 182 166 }; 183 167 184 168 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { ··· 187 171 { P_GPLL0_EARLY_DIV, 6 } 188 172 }; 189 173 190 - static const char * const gcc_xo_gpll0_gpll0_early_div[] = { 191 - "xo", 192 - "gpll0", 193 - "gpll0_early_div" 174 + static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = { 175 + { .hw = &xo.hw }, 176 + { .hw = &gpll0.clkr.hw }, 177 + { .hw = &gpll0_early_div.hw } 194 178 }; 195 179 196 180 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { ··· 199 183 { P_GPLL4, 5 } 200 184 }; 201 185 202 - static const char * const gcc_xo_gpll0_gpll4[] = { 203 - "xo", 204 - "gpll0", 205 - "gpll4" 186 + static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 187 + { .hw = &xo.hw }, 188 + { .hw = &gpll0.clkr.hw }, 189 + { .hw = &gpll4.clkr.hw } 206 190 }; 207 191 208 192 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { ··· 211 195 { P_AUD_REF_CLK, 2 } 212 196 }; 213 197 214 - static const char * const gcc_xo_gpll0_aud_ref_clk[] = { 215 - "xo", 216 - "gpll0", 217 - "aud_ref_clk" 198 + static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = { 199 + { .hw = &xo.hw }, 200 + { .hw = &gpll0.clkr.hw }, 201 + { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" } 218 202 }; 219 203 220 204 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { ··· 224 208 { P_GPLL0_EARLY_DIV, 6 } 225 209 }; 226 210 227 - static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { 228 - "xo", 229 - "gpll0", 230 - "sleep_clk", 231 - "gpll0_early_div" 211 + static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { 212 + { .hw = &xo.hw }, 213 + { .hw = &gpll0.clkr.hw }, 214 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 215 + { .hw = &gpll0_early_div.hw } 232 216 }; 233 217 234 218 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { ··· 238 222 { P_GPLL0_EARLY_DIV, 6 } 239 223 }; 240 224 241 - static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { 242 - "xo", 243 - "gpll0", 244 - "gpll4", 245 - "gpll0_early_div" 225 + static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { 226 + { .hw = &xo.hw }, 227 + { .hw = &gpll0.clkr.hw }, 228 + { .hw = &gpll4.clkr.hw }, 229 + { .hw = &gpll0_early_div.hw } 246 230 }; 247 231 248 232 static const struct freq_tbl ftbl_system_noc_clk_src[] = { ··· 262 246 .freq_tbl = ftbl_system_noc_clk_src, 263 247 .clkr.hw.init = &(struct clk_init_data){ 264 248 .name = "system_noc_clk_src", 265 - .parent_names = gcc_xo_gpll0_gpll0_early_div, 249 + .parent_data = gcc_xo_gpll0_gpll0_early_div, 266 250 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 267 251 .ops = &clk_rcg2_ops, 268 252 }, ··· 282 266 .freq_tbl = ftbl_config_noc_clk_src, 283 267 .clkr.hw.init = &(struct clk_init_data){ 284 268 .name = "config_noc_clk_src", 285 - .parent_names = gcc_xo_gpll0, 269 + .parent_data = gcc_xo_gpll0, 286 270 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 287 271 .ops = &clk_rcg2_ops, 288 272 }, ··· 304 288 .freq_tbl = ftbl_periph_noc_clk_src, 305 289 .clkr.hw.init = &(struct clk_init_data){ 306 290 .name = "periph_noc_clk_src", 307 - .parent_names = gcc_xo_gpll0, 291 + .parent_data = gcc_xo_gpll0, 308 292 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 309 293 .ops = &clk_rcg2_ops, 310 294 }, ··· 325 309 .freq_tbl = ftbl_usb30_master_clk_src, 326 310 .clkr.hw.init = &(struct clk_init_data){ 327 311 .name = "usb30_master_clk_src", 328 - .parent_names = gcc_xo_gpll0_gpll0_early_div, 312 + .parent_data = gcc_xo_gpll0_gpll0_early_div, 329 313 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 330 314 .ops = &clk_rcg2_ops, 331 315 }, ··· 343 327 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 344 328 .clkr.hw.init = &(struct clk_init_data){ 345 329 .name = "usb30_mock_utmi_clk_src", 346 - .parent_names = gcc_xo_gpll0_gpll0_early_div, 330 + .parent_data = gcc_xo_gpll0_gpll0_early_div, 347 331 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 348 332 .ops = &clk_rcg2_ops, 349 333 }, ··· 361 345 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 362 346 .clkr.hw.init = &(struct clk_init_data){ 363 347 .name = "usb3_phy_aux_clk_src", 364 - .parent_names = gcc_xo_sleep_clk, 348 + .parent_data = gcc_xo_sleep_clk, 365 349 .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), 366 350 .ops = &clk_rcg2_ops, 367 351 }, ··· 380 364 .freq_tbl = ftbl_usb20_master_clk_src, 381 365 .clkr.hw.init = &(struct clk_init_data){ 382 366 .name = "usb20_master_clk_src", 383 - .parent_names = gcc_xo_gpll0_gpll0_early_div, 367 + .parent_data = gcc_xo_gpll0_gpll0_early_div, 384 368 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 385 369 .ops = &clk_rcg2_ops, 386 370 }, ··· 393 377 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 394 378 .clkr.hw.init = &(struct clk_init_data){ 395 379 .name = "usb20_mock_utmi_clk_src", 396 - .parent_names = gcc_xo_gpll0_gpll0_early_div, 380 + .parent_data = gcc_xo_gpll0_gpll0_early_div, 397 381 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 398 382 .ops = &clk_rcg2_ops, 399 383 }, ··· 419 403 .freq_tbl = ftbl_sdcc1_apps_clk_src, 420 404 .clkr.hw.init = &(struct clk_init_data){ 421 405 .name = "sdcc1_apps_clk_src", 422 - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, 406 + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, 423 407 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), 424 408 .ops = &clk_rcg2_floor_ops, 425 409 }, ··· 439 423 .freq_tbl = ftbl_sdcc1_ice_core_clk_src, 440 424 .clkr.hw.init = &(struct clk_init_data){ 441 425 .name = "sdcc1_ice_core_clk_src", 442 - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, 426 + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, 443 427 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), 444 428 .ops = &clk_rcg2_ops, 445 429 }, ··· 464 448 .freq_tbl = ftbl_sdcc2_apps_clk_src, 465 449 .clkr.hw.init = &(struct clk_init_data){ 466 450 .name = "sdcc2_apps_clk_src", 467 - .parent_names = gcc_xo_gpll0_gpll4, 451 + .parent_data = gcc_xo_gpll0_gpll4, 468 452 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 469 453 .ops = &clk_rcg2_floor_ops, 470 454 }, ··· 478 462 .freq_tbl = ftbl_sdcc2_apps_clk_src, 479 463 .clkr.hw.init = &(struct clk_init_data){ 480 464 .name = "sdcc3_apps_clk_src", 481 - .parent_names = gcc_xo_gpll0_gpll4, 465 + .parent_data = gcc_xo_gpll0_gpll4, 482 466 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 483 467 .ops = &clk_rcg2_floor_ops, 484 468 }, ··· 502 486 .freq_tbl = ftbl_sdcc4_apps_clk_src, 503 487 .clkr.hw.init = &(struct clk_init_data){ 504 488 .name = "sdcc4_apps_clk_src", 505 - .parent_names = gcc_xo_gpll0, 489 + .parent_data = gcc_xo_gpll0, 506 490 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 507 491 .ops = &clk_rcg2_floor_ops, 508 492 }, ··· 527 511 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 528 512 .clkr.hw.init = &(struct clk_init_data){ 529 513 .name = "blsp1_qup1_spi_apps_clk_src", 530 - .parent_names = gcc_xo_gpll0, 514 + .parent_data = gcc_xo_gpll0, 531 515 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 532 516 .ops = &clk_rcg2_ops, 533 517 }, ··· 546 530 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 547 531 .clkr.hw.init = &(struct clk_init_data){ 548 532 .name = "blsp1_qup1_i2c_apps_clk_src", 549 - .parent_names = gcc_xo_gpll0, 533 + .parent_data = gcc_xo_gpll0, 550 534 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 551 535 .ops = &clk_rcg2_ops, 552 536 }, ··· 579 563 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 580 564 .clkr.hw.init = &(struct clk_init_data){ 581 565 .name = "blsp1_uart1_apps_clk_src", 582 - .parent_names = gcc_xo_gpll0, 566 + .parent_data = gcc_xo_gpll0, 583 567 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 584 568 .ops = &clk_rcg2_ops, 585 569 }, ··· 593 577 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 594 578 .clkr.hw.init = &(struct clk_init_data){ 595 579 .name = "blsp1_qup2_spi_apps_clk_src", 596 - .parent_names = gcc_xo_gpll0, 580 + .parent_data = gcc_xo_gpll0, 597 581 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 598 582 .ops = &clk_rcg2_ops, 599 583 }, ··· 606 590 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 607 591 .clkr.hw.init = &(struct clk_init_data){ 608 592 .name = "blsp1_qup2_i2c_apps_clk_src", 609 - .parent_names = gcc_xo_gpll0, 593 + .parent_data = gcc_xo_gpll0, 610 594 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 611 595 .ops = &clk_rcg2_ops, 612 596 }, ··· 620 604 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 621 605 .clkr.hw.init = &(struct clk_init_data){ 622 606 .name = "blsp1_uart2_apps_clk_src", 623 - .parent_names = gcc_xo_gpll0, 607 + .parent_data = gcc_xo_gpll0, 624 608 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 625 609 .ops = &clk_rcg2_ops, 626 610 }, ··· 634 618 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 635 619 .clkr.hw.init = &(struct clk_init_data){ 636 620 .name = "blsp1_qup3_spi_apps_clk_src", 637 - .parent_names = gcc_xo_gpll0, 621 + .parent_data = gcc_xo_gpll0, 638 622 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 639 623 .ops = &clk_rcg2_ops, 640 624 }, ··· 647 631 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 648 632 .clkr.hw.init = &(struct clk_init_data){ 649 633 .name = "blsp1_qup3_i2c_apps_clk_src", 650 - .parent_names = gcc_xo_gpll0, 634 + .parent_data = gcc_xo_gpll0, 651 635 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 652 636 .ops = &clk_rcg2_ops, 653 637 }, ··· 661 645 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 662 646 .clkr.hw.init = &(struct clk_init_data){ 663 647 .name = "blsp1_uart3_apps_clk_src", 664 - .parent_names = gcc_xo_gpll0, 648 + .parent_data = gcc_xo_gpll0, 665 649 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 666 650 .ops = &clk_rcg2_ops, 667 651 }, ··· 675 659 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 676 660 .clkr.hw.init = &(struct clk_init_data){ 677 661 .name = "blsp1_qup4_spi_apps_clk_src", 678 - .parent_names = gcc_xo_gpll0, 662 + .parent_data = gcc_xo_gpll0, 679 663 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 680 664 .ops = &clk_rcg2_ops, 681 665 }, ··· 688 672 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 689 673 .clkr.hw.init = &(struct clk_init_data){ 690 674 .name = "blsp1_qup4_i2c_apps_clk_src", 691 - .parent_names = gcc_xo_gpll0, 675 + .parent_data = gcc_xo_gpll0, 692 676 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 693 677 .ops = &clk_rcg2_ops, 694 678 }, ··· 702 686 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 703 687 .clkr.hw.init = &(struct clk_init_data){ 704 688 .name = "blsp1_uart4_apps_clk_src", 705 - .parent_names = gcc_xo_gpll0, 689 + .parent_data = gcc_xo_gpll0, 706 690 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 707 691 .ops = &clk_rcg2_ops, 708 692 }, ··· 716 700 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 717 701 .clkr.hw.init = &(struct clk_init_data){ 718 702 .name = "blsp1_qup5_spi_apps_clk_src", 719 - .parent_names = gcc_xo_gpll0, 703 + .parent_data = gcc_xo_gpll0, 720 704 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 721 705 .ops = &clk_rcg2_ops, 722 706 }, ··· 729 713 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 730 714 .clkr.hw.init = &(struct clk_init_data){ 731 715 .name = "blsp1_qup5_i2c_apps_clk_src", 732 - .parent_names = gcc_xo_gpll0, 716 + .parent_data = gcc_xo_gpll0, 733 717 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 734 718 .ops = &clk_rcg2_ops, 735 719 }, ··· 743 727 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 744 728 .clkr.hw.init = &(struct clk_init_data){ 745 729 .name = "blsp1_uart5_apps_clk_src", 746 - .parent_names = gcc_xo_gpll0, 730 + .parent_data = gcc_xo_gpll0, 747 731 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 748 732 .ops = &clk_rcg2_ops, 749 733 }, ··· 757 741 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 758 742 .clkr.hw.init = &(struct clk_init_data){ 759 743 .name = "blsp1_qup6_spi_apps_clk_src", 760 - .parent_names = gcc_xo_gpll0, 744 + .parent_data = gcc_xo_gpll0, 761 745 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 762 746 .ops = &clk_rcg2_ops, 763 747 }, ··· 770 754 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 771 755 .clkr.hw.init = &(struct clk_init_data){ 772 756 .name = "blsp1_qup6_i2c_apps_clk_src", 773 - .parent_names = gcc_xo_gpll0, 757 + .parent_data = gcc_xo_gpll0, 774 758 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 775 759 .ops = &clk_rcg2_ops, 776 760 }, ··· 784 768 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 785 769 .clkr.hw.init = &(struct clk_init_data){ 786 770 .name = "blsp1_uart6_apps_clk_src", 787 - .parent_names = gcc_xo_gpll0, 771 + .parent_data = gcc_xo_gpll0, 788 772 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 789 773 .ops = &clk_rcg2_ops, 790 774 }, ··· 798 782 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 799 783 .clkr.hw.init = &(struct clk_init_data){ 800 784 .name = "blsp2_qup1_spi_apps_clk_src", 801 - .parent_names = gcc_xo_gpll0, 785 + .parent_data = gcc_xo_gpll0, 802 786 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 803 787 .ops = &clk_rcg2_ops, 804 788 }, ··· 811 795 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 812 796 .clkr.hw.init = &(struct clk_init_data){ 813 797 .name = "blsp2_qup1_i2c_apps_clk_src", 814 - .parent_names = gcc_xo_gpll0, 798 + .parent_data = gcc_xo_gpll0, 815 799 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 816 800 .ops = &clk_rcg2_ops, 817 801 }, ··· 825 809 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 826 810 .clkr.hw.init = &(struct clk_init_data){ 827 811 .name = "blsp2_uart1_apps_clk_src", 828 - .parent_names = gcc_xo_gpll0, 812 + .parent_data = gcc_xo_gpll0, 829 813 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 830 814 .ops = &clk_rcg2_ops, 831 815 }, ··· 839 823 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 840 824 .clkr.hw.init = &(struct clk_init_data){ 841 825 .name = "blsp2_qup2_spi_apps_clk_src", 842 - .parent_names = gcc_xo_gpll0, 826 + .parent_data = gcc_xo_gpll0, 843 827 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 844 828 .ops = &clk_rcg2_ops, 845 829 }, ··· 852 836 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 853 837 .clkr.hw.init = &(struct clk_init_data){ 854 838 .name = "blsp2_qup2_i2c_apps_clk_src", 855 - .parent_names = gcc_xo_gpll0, 839 + .parent_data = gcc_xo_gpll0, 856 840 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 857 841 .ops = &clk_rcg2_ops, 858 842 }, ··· 866 850 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 867 851 .clkr.hw.init = &(struct clk_init_data){ 868 852 .name = "blsp2_uart2_apps_clk_src", 869 - .parent_names = gcc_xo_gpll0, 853 + .parent_data = gcc_xo_gpll0, 870 854 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 871 855 .ops = &clk_rcg2_ops, 872 856 }, ··· 880 864 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 881 865 .clkr.hw.init = &(struct clk_init_data){ 882 866 .name = "blsp2_qup3_spi_apps_clk_src", 883 - .parent_names = gcc_xo_gpll0, 867 + .parent_data = gcc_xo_gpll0, 884 868 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 885 869 .ops = &clk_rcg2_ops, 886 870 }, ··· 893 877 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 894 878 .clkr.hw.init = &(struct clk_init_data){ 895 879 .name = "blsp2_qup3_i2c_apps_clk_src", 896 - .parent_names = gcc_xo_gpll0, 880 + .parent_data = gcc_xo_gpll0, 897 881 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 898 882 .ops = &clk_rcg2_ops, 899 883 }, ··· 907 891 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 908 892 .clkr.hw.init = &(struct clk_init_data){ 909 893 .name = "blsp2_uart3_apps_clk_src", 910 - .parent_names = gcc_xo_gpll0, 894 + .parent_data = gcc_xo_gpll0, 911 895 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 912 896 .ops = &clk_rcg2_ops, 913 897 }, ··· 921 905 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 922 906 .clkr.hw.init = &(struct clk_init_data){ 923 907 .name = "blsp2_qup4_spi_apps_clk_src", 924 - .parent_names = gcc_xo_gpll0, 908 + .parent_data = gcc_xo_gpll0, 925 909 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 926 910 .ops = &clk_rcg2_ops, 927 911 }, ··· 934 918 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 935 919 .clkr.hw.init = &(struct clk_init_data){ 936 920 .name = "blsp2_qup4_i2c_apps_clk_src", 937 - .parent_names = gcc_xo_gpll0, 921 + .parent_data = gcc_xo_gpll0, 938 922 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 939 923 .ops = &clk_rcg2_ops, 940 924 }, ··· 948 932 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 949 933 .clkr.hw.init = &(struct clk_init_data){ 950 934 .name = "blsp2_uart4_apps_clk_src", 951 - .parent_names = gcc_xo_gpll0, 935 + .parent_data = gcc_xo_gpll0, 952 936 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 953 937 .ops = &clk_rcg2_ops, 954 938 }, ··· 962 946 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 963 947 .clkr.hw.init = &(struct clk_init_data){ 964 948 .name = "blsp2_qup5_spi_apps_clk_src", 965 - .parent_names = gcc_xo_gpll0, 949 + .parent_data = gcc_xo_gpll0, 966 950 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 967 951 .ops = &clk_rcg2_ops, 968 952 }, ··· 975 959 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 976 960 .clkr.hw.init = &(struct clk_init_data){ 977 961 .name = "blsp2_qup5_i2c_apps_clk_src", 978 - .parent_names = gcc_xo_gpll0, 962 + .parent_data = gcc_xo_gpll0, 979 963 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 980 964 .ops = &clk_rcg2_ops, 981 965 }, ··· 989 973 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 990 974 .clkr.hw.init = &(struct clk_init_data){ 991 975 .name = "blsp2_uart5_apps_clk_src", 992 - .parent_names = gcc_xo_gpll0, 976 + .parent_data = gcc_xo_gpll0, 993 977 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 994 978 .ops = &clk_rcg2_ops, 995 979 }, ··· 1003 987 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 1004 988 .clkr.hw.init = &(struct clk_init_data){ 1005 989 .name = "blsp2_qup6_spi_apps_clk_src", 1006 - .parent_names = gcc_xo_gpll0, 990 + .parent_data = gcc_xo_gpll0, 1007 991 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1008 992 .ops = &clk_rcg2_ops, 1009 993 }, ··· 1016 1000 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 1017 1001 .clkr.hw.init = &(struct clk_init_data){ 1018 1002 .name = "blsp2_qup6_i2c_apps_clk_src", 1019 - .parent_names = gcc_xo_gpll0, 1003 + .parent_data = gcc_xo_gpll0, 1020 1004 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1021 1005 .ops = &clk_rcg2_ops, 1022 1006 }, ··· 1030 1014 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 1031 1015 .clkr.hw.init = &(struct clk_init_data){ 1032 1016 .name = "blsp2_uart6_apps_clk_src", 1033 - .parent_names = gcc_xo_gpll0, 1017 + .parent_data = gcc_xo_gpll0, 1034 1018 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1035 1019 .ops = &clk_rcg2_ops, 1036 1020 }, ··· 1048 1032 .freq_tbl = ftbl_pdm2_clk_src, 1049 1033 .clkr.hw.init = &(struct clk_init_data){ 1050 1034 .name = "pdm2_clk_src", 1051 - .parent_names = gcc_xo_gpll0, 1035 + .parent_data = gcc_xo_gpll0, 1052 1036 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1053 1037 .ops = &clk_rcg2_ops, 1054 1038 }, ··· 1067 1051 .freq_tbl = ftbl_tsif_ref_clk_src, 1068 1052 .clkr.hw.init = &(struct clk_init_data){ 1069 1053 .name = "tsif_ref_clk_src", 1070 - .parent_names = gcc_xo_gpll0_aud_ref_clk, 1054 + .parent_data = gcc_xo_gpll0_aud_ref_clk, 1071 1055 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), 1072 1056 .ops = &clk_rcg2_ops, 1073 1057 }, ··· 1079 1063 .parent_map = gcc_sleep_clk_map, 1080 1064 .clkr.hw.init = &(struct clk_init_data){ 1081 1065 .name = "gcc_sleep_clk_src", 1082 - .parent_names = gcc_sleep_clk, 1066 + .parent_data = gcc_sleep_clk, 1083 1067 .num_parents = ARRAY_SIZE(gcc_sleep_clk), 1084 1068 .ops = &clk_rcg2_ops, 1085 1069 }, ··· 1092 1076 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1093 1077 .clkr.hw.init = &(struct clk_init_data){ 1094 1078 .name = "hmss_rbcpr_clk_src", 1095 - .parent_names = gcc_xo_gpll0, 1079 + .parent_data = gcc_xo_gpll0, 1096 1080 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1097 1081 .ops = &clk_rcg2_ops, 1098 1082 }, ··· 1104 1088 .parent_map = gcc_xo_gpll0_map, 1105 1089 .clkr.hw.init = &(struct clk_init_data){ 1106 1090 .name = "hmss_gpll0_clk_src", 1107 - .parent_names = gcc_xo_gpll0, 1091 + .parent_data = gcc_xo_gpll0, 1108 1092 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1109 1093 .ops = &clk_rcg2_ops, 1110 1094 }, ··· 1125 1109 .freq_tbl = ftbl_gp1_clk_src, 1126 1110 .clkr.hw.init = &(struct clk_init_data){ 1127 1111 .name = "gp1_clk_src", 1128 - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1112 + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1129 1113 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), 1130 1114 .ops = &clk_rcg2_ops, 1131 1115 }, ··· 1139 1123 .freq_tbl = ftbl_gp1_clk_src, 1140 1124 .clkr.hw.init = &(struct clk_init_data){ 1141 1125 .name = "gp2_clk_src", 1142 - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1126 + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1143 1127 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), 1144 1128 .ops = &clk_rcg2_ops, 1145 1129 }, ··· 1153 1137 .freq_tbl = ftbl_gp1_clk_src, 1154 1138 .clkr.hw.init = &(struct clk_init_data){ 1155 1139 .name = "gp3_clk_src", 1156 - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1140 + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, 1157 1141 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), 1158 1142 .ops = &clk_rcg2_ops, 1159 1143 }, ··· 1172 1156 .freq_tbl = ftbl_pcie_aux_clk_src, 1173 1157 .clkr.hw.init = &(struct clk_init_data){ 1174 1158 .name = "pcie_aux_clk_src", 1175 - .parent_names = gcc_xo_sleep_clk, 1159 + .parent_data = gcc_xo_sleep_clk, 1176 1160 .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), 1177 1161 .ops = &clk_rcg2_ops, 1178 1162 }, ··· 1193 1177 .freq_tbl = ftbl_ufs_axi_clk_src, 1194 1178 .clkr.hw.init = &(struct clk_init_data){ 1195 1179 .name = "ufs_axi_clk_src", 1196 - .parent_names = gcc_xo_gpll0, 1180 + .parent_data = gcc_xo_gpll0, 1197 1181 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1198 1182 .ops = &clk_rcg2_ops, 1199 1183 }, ··· 1213 1197 .freq_tbl = ftbl_ufs_ice_core_clk_src, 1214 1198 .clkr.hw.init = &(struct clk_init_data){ 1215 1199 .name = "ufs_ice_core_clk_src", 1216 - .parent_names = gcc_xo_gpll0, 1200 + .parent_data = gcc_xo_gpll0, 1217 1201 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1218 1202 .ops = &clk_rcg2_ops, 1219 1203 }, ··· 1234 1218 .freq_tbl = ftbl_qspi_ser_clk_src, 1235 1219 .clkr.hw.init = &(struct clk_init_data){ 1236 1220 .name = "qspi_ser_clk_src", 1237 - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, 1221 + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, 1238 1222 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), 1239 1223 .ops = &clk_rcg2_ops, 1240 1224 }, ··· 1247 1231 .enable_mask = BIT(0), 1248 1232 .hw.init = &(struct clk_init_data){ 1249 1233 .name = "gcc_sys_noc_usb3_axi_clk", 1250 - .parent_names = (const char *[]){ "usb30_master_clk_src" }, 1234 + .parent_hws = (const struct clk_hw*[]){ 1235 + &usb30_master_clk_src.clkr.hw, 1236 + }, 1251 1237 .num_parents = 1, 1252 1238 .flags = CLK_SET_RATE_PARENT, 1253 1239 .ops = &clk_branch2_ops, ··· 1264 1246 .enable_mask = BIT(0), 1265 1247 .hw.init = &(struct clk_init_data){ 1266 1248 .name = "gcc_sys_noc_ufs_axi_clk", 1267 - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, 1249 + .parent_hws = (const struct clk_hw*[]){ 1250 + &ufs_axi_clk_src.clkr.hw, 1251 + }, 1268 1252 .num_parents = 1, 1269 1253 .flags = CLK_SET_RATE_PARENT, 1270 1254 .ops = &clk_branch2_ops, ··· 1281 1261 .enable_mask = BIT(0), 1282 1262 .hw.init = &(struct clk_init_data){ 1283 1263 .name = "gcc_periph_noc_usb20_ahb_clk", 1284 - .parent_names = (const char *[]){ "usb20_master_clk_src" }, 1264 + .parent_hws = (const struct clk_hw*[]){ 1265 + &usb20_master_clk_src.clkr.hw, 1266 + }, 1285 1267 .num_parents = 1, 1286 1268 .flags = CLK_SET_RATE_PARENT, 1287 1269 .ops = &clk_branch2_ops, ··· 1298 1276 .enable_mask = BIT(0), 1299 1277 .hw.init = &(struct clk_init_data){ 1300 1278 .name = "gcc_mmss_noc_cfg_ahb_clk", 1301 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 1279 + .parent_hws = (const struct clk_hw*[]){ 1280 + &config_noc_clk_src.clkr.hw, 1281 + }, 1302 1282 .num_parents = 1, 1303 1283 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1304 1284 .ops = &clk_branch2_ops, ··· 1328 1304 .enable_mask = BIT(0), 1329 1305 .hw.init = &(struct clk_init_data){ 1330 1306 .name = "gcc_usb30_master_clk", 1331 - .parent_names = (const char *[]){ "usb30_master_clk_src" }, 1307 + .parent_hws = (const struct clk_hw*[]){ 1308 + &usb30_master_clk_src.clkr.hw, 1309 + }, 1332 1310 .num_parents = 1, 1333 1311 .flags = CLK_SET_RATE_PARENT, 1334 1312 .ops = &clk_branch2_ops, ··· 1345 1319 .enable_mask = BIT(0), 1346 1320 .hw.init = &(struct clk_init_data){ 1347 1321 .name = "gcc_usb30_sleep_clk", 1348 - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, 1322 + .parent_hws = (const struct clk_hw*[]){ 1323 + &gcc_sleep_clk_src.clkr.hw, 1324 + }, 1349 1325 .num_parents = 1, 1350 1326 .flags = CLK_SET_RATE_PARENT, 1351 1327 .ops = &clk_branch2_ops, ··· 1362 1334 .enable_mask = BIT(0), 1363 1335 .hw.init = &(struct clk_init_data){ 1364 1336 .name = "gcc_usb30_mock_utmi_clk", 1365 - .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" }, 1337 + .parent_hws = (const struct clk_hw*[]){ 1338 + &usb30_mock_utmi_clk_src.clkr.hw, 1339 + }, 1366 1340 .num_parents = 1, 1367 1341 .flags = CLK_SET_RATE_PARENT, 1368 1342 .ops = &clk_branch2_ops, ··· 1379 1349 .enable_mask = BIT(0), 1380 1350 .hw.init = &(struct clk_init_data){ 1381 1351 .name = "gcc_usb3_phy_aux_clk", 1382 - .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" }, 1352 + .parent_hws = (const struct clk_hw*[]){ 1353 + &usb3_phy_aux_clk_src.clkr.hw, 1354 + }, 1383 1355 .num_parents = 1, 1384 1356 .flags = CLK_SET_RATE_PARENT, 1385 1357 .ops = &clk_branch2_ops, ··· 1397 1365 .enable_mask = BIT(0), 1398 1366 .hw.init = &(struct clk_init_data){ 1399 1367 .name = "gcc_usb3_phy_pipe_clk", 1400 - .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" }, 1368 + .parent_data = &(const struct clk_parent_data){ 1369 + .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src", 1370 + }, 1401 1371 .num_parents = 1, 1402 1372 .flags = CLK_SET_RATE_PARENT, 1403 1373 .ops = &clk_branch2_ops, ··· 1414 1380 .enable_mask = BIT(0), 1415 1381 .hw.init = &(struct clk_init_data){ 1416 1382 .name = "gcc_usb20_master_clk", 1417 - .parent_names = (const char *[]){ "usb20_master_clk_src" }, 1383 + .parent_hws = (const struct clk_hw*[]){ 1384 + &usb20_master_clk_src.clkr.hw, 1385 + }, 1418 1386 .num_parents = 1, 1419 1387 .flags = CLK_SET_RATE_PARENT, 1420 1388 .ops = &clk_branch2_ops, ··· 1431 1395 .enable_mask = BIT(0), 1432 1396 .hw.init = &(struct clk_init_data){ 1433 1397 .name = "gcc_usb20_sleep_clk", 1434 - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, 1398 + .parent_hws = (const struct clk_hw*[]){ 1399 + &gcc_sleep_clk_src.clkr.hw, 1400 + }, 1435 1401 .num_parents = 1, 1436 1402 .flags = CLK_SET_RATE_PARENT, 1437 1403 .ops = &clk_branch2_ops, ··· 1448 1410 .enable_mask = BIT(0), 1449 1411 .hw.init = &(struct clk_init_data){ 1450 1412 .name = "gcc_usb20_mock_utmi_clk", 1451 - .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" }, 1413 + .parent_hws = (const struct clk_hw*[]){ 1414 + &usb20_mock_utmi_clk_src.clkr.hw, 1415 + }, 1452 1416 .num_parents = 1, 1453 1417 .flags = CLK_SET_RATE_PARENT, 1454 1418 .ops = &clk_branch2_ops, ··· 1465 1425 .enable_mask = BIT(0), 1466 1426 .hw.init = &(struct clk_init_data){ 1467 1427 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 1468 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1428 + .parent_hws = (const struct clk_hw*[]){ 1429 + &periph_noc_clk_src.clkr.hw, 1430 + }, 1469 1431 .num_parents = 1, 1470 1432 .flags = CLK_SET_RATE_PARENT, 1471 1433 .ops = &clk_branch2_ops, ··· 1482 1440 .enable_mask = BIT(0), 1483 1441 .hw.init = &(struct clk_init_data){ 1484 1442 .name = "gcc_sdcc1_apps_clk", 1485 - .parent_names = (const char *[]){ "sdcc1_apps_clk_src" }, 1443 + .parent_hws = (const struct clk_hw*[]){ 1444 + &sdcc1_apps_clk_src.clkr.hw, 1445 + }, 1486 1446 .num_parents = 1, 1487 1447 .flags = CLK_SET_RATE_PARENT, 1488 1448 .ops = &clk_branch2_ops, ··· 1499 1455 .enable_mask = BIT(0), 1500 1456 .hw.init = &(struct clk_init_data){ 1501 1457 .name = "gcc_sdcc1_ahb_clk", 1502 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1458 + .parent_hws = (const struct clk_hw*[]){ 1459 + &periph_noc_clk_src.clkr.hw, 1460 + }, 1503 1461 .num_parents = 1, 1504 1462 .flags = CLK_SET_RATE_PARENT, 1505 1463 .ops = &clk_branch2_ops, ··· 1516 1470 .enable_mask = BIT(0), 1517 1471 .hw.init = &(struct clk_init_data){ 1518 1472 .name = "gcc_sdcc1_ice_core_clk", 1519 - .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" }, 1473 + .parent_hws = (const struct clk_hw*[]){ 1474 + &sdcc1_ice_core_clk_src.clkr.hw, 1475 + }, 1520 1476 .num_parents = 1, 1521 1477 .flags = CLK_SET_RATE_PARENT, 1522 1478 .ops = &clk_branch2_ops, ··· 1533 1485 .enable_mask = BIT(0), 1534 1486 .hw.init = &(struct clk_init_data){ 1535 1487 .name = "gcc_sdcc2_apps_clk", 1536 - .parent_names = (const char *[]){ "sdcc2_apps_clk_src" }, 1488 + .parent_hws = (const struct clk_hw*[]){ 1489 + &sdcc2_apps_clk_src.clkr.hw, 1490 + }, 1537 1491 .num_parents = 1, 1538 1492 .flags = CLK_SET_RATE_PARENT, 1539 1493 .ops = &clk_branch2_ops, ··· 1550 1500 .enable_mask = BIT(0), 1551 1501 .hw.init = &(struct clk_init_data){ 1552 1502 .name = "gcc_sdcc2_ahb_clk", 1553 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1503 + .parent_hws = (const struct clk_hw*[]){ 1504 + &periph_noc_clk_src.clkr.hw, 1505 + }, 1554 1506 .num_parents = 1, 1555 1507 .flags = CLK_SET_RATE_PARENT, 1556 1508 .ops = &clk_branch2_ops, ··· 1567 1515 .enable_mask = BIT(0), 1568 1516 .hw.init = &(struct clk_init_data){ 1569 1517 .name = "gcc_sdcc3_apps_clk", 1570 - .parent_names = (const char *[]){ "sdcc3_apps_clk_src" }, 1518 + .parent_hws = (const struct clk_hw*[]){ 1519 + &sdcc3_apps_clk_src.clkr.hw, 1520 + }, 1571 1521 .num_parents = 1, 1572 1522 .flags = CLK_SET_RATE_PARENT, 1573 1523 .ops = &clk_branch2_ops, ··· 1584 1530 .enable_mask = BIT(0), 1585 1531 .hw.init = &(struct clk_init_data){ 1586 1532 .name = "gcc_sdcc3_ahb_clk", 1587 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1533 + .parent_hws = (const struct clk_hw*[]){ 1534 + &periph_noc_clk_src.clkr.hw, 1535 + }, 1588 1536 .num_parents = 1, 1589 1537 .flags = CLK_SET_RATE_PARENT, 1590 1538 .ops = &clk_branch2_ops, ··· 1601 1545 .enable_mask = BIT(0), 1602 1546 .hw.init = &(struct clk_init_data){ 1603 1547 .name = "gcc_sdcc4_apps_clk", 1604 - .parent_names = (const char *[]){ "sdcc4_apps_clk_src" }, 1548 + .parent_hws = (const struct clk_hw*[]){ 1549 + &sdcc4_apps_clk_src.clkr.hw, 1550 + }, 1605 1551 .num_parents = 1, 1606 1552 .flags = CLK_SET_RATE_PARENT, 1607 1553 .ops = &clk_branch2_ops, ··· 1618 1560 .enable_mask = BIT(0), 1619 1561 .hw.init = &(struct clk_init_data){ 1620 1562 .name = "gcc_sdcc4_ahb_clk", 1621 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1563 + .parent_hws = (const struct clk_hw*[]){ 1564 + &periph_noc_clk_src.clkr.hw, 1565 + }, 1622 1566 .num_parents = 1, 1623 1567 .flags = CLK_SET_RATE_PARENT, 1624 1568 .ops = &clk_branch2_ops, ··· 1636 1576 .enable_mask = BIT(17), 1637 1577 .hw.init = &(struct clk_init_data){ 1638 1578 .name = "gcc_blsp1_ahb_clk", 1639 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1579 + .parent_hws = (const struct clk_hw*[]){ 1580 + &periph_noc_clk_src.clkr.hw, 1581 + }, 1640 1582 .num_parents = 1, 1641 1583 .flags = CLK_SET_RATE_PARENT, 1642 1584 .ops = &clk_branch2_ops, ··· 1654 1592 .enable_mask = BIT(16), 1655 1593 .hw.init = &(struct clk_init_data){ 1656 1594 .name = "gcc_blsp1_sleep_clk", 1657 - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, 1595 + .parent_hws = (const struct clk_hw*[]){ 1596 + &gcc_sleep_clk_src.clkr.hw, 1597 + }, 1658 1598 .num_parents = 1, 1659 1599 .flags = CLK_SET_RATE_PARENT, 1660 1600 .ops = &clk_branch2_ops, ··· 1671 1607 .enable_mask = BIT(0), 1672 1608 .hw.init = &(struct clk_init_data){ 1673 1609 .name = "gcc_blsp1_qup1_spi_apps_clk", 1674 - .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" }, 1610 + .parent_hws = (const struct clk_hw*[]){ 1611 + &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1612 + }, 1675 1613 .num_parents = 1, 1676 1614 .flags = CLK_SET_RATE_PARENT, 1677 1615 .ops = &clk_branch2_ops, ··· 1688 1622 .enable_mask = BIT(0), 1689 1623 .hw.init = &(struct clk_init_data){ 1690 1624 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1691 - .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" }, 1625 + .parent_hws = (const struct clk_hw*[]){ 1626 + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1627 + }, 1692 1628 .num_parents = 1, 1693 1629 .flags = CLK_SET_RATE_PARENT, 1694 1630 .ops = &clk_branch2_ops, ··· 1705 1637 .enable_mask = BIT(0), 1706 1638 .hw.init = &(struct clk_init_data){ 1707 1639 .name = "gcc_blsp1_uart1_apps_clk", 1708 - .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" }, 1640 + .parent_hws = (const struct clk_hw*[]){ 1641 + &blsp1_uart1_apps_clk_src.clkr.hw, 1642 + }, 1709 1643 .num_parents = 1, 1710 1644 .flags = CLK_SET_RATE_PARENT, 1711 1645 .ops = &clk_branch2_ops, ··· 1722 1652 .enable_mask = BIT(0), 1723 1653 .hw.init = &(struct clk_init_data){ 1724 1654 .name = "gcc_blsp1_qup2_spi_apps_clk", 1725 - .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" }, 1655 + .parent_hws = (const struct clk_hw*[]){ 1656 + &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1657 + }, 1726 1658 .num_parents = 1, 1727 1659 .flags = CLK_SET_RATE_PARENT, 1728 1660 .ops = &clk_branch2_ops, ··· 1739 1667 .enable_mask = BIT(0), 1740 1668 .hw.init = &(struct clk_init_data){ 1741 1669 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1742 - .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" }, 1670 + .parent_hws = (const struct clk_hw*[]){ 1671 + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1672 + }, 1743 1673 .num_parents = 1, 1744 1674 .flags = CLK_SET_RATE_PARENT, 1745 1675 .ops = &clk_branch2_ops, ··· 1756 1682 .enable_mask = BIT(0), 1757 1683 .hw.init = &(struct clk_init_data){ 1758 1684 .name = "gcc_blsp1_uart2_apps_clk", 1759 - .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" }, 1685 + .parent_hws = (const struct clk_hw*[]){ 1686 + &blsp1_uart2_apps_clk_src.clkr.hw, 1687 + }, 1760 1688 .num_parents = 1, 1761 1689 .flags = CLK_SET_RATE_PARENT, 1762 1690 .ops = &clk_branch2_ops, ··· 1773 1697 .enable_mask = BIT(0), 1774 1698 .hw.init = &(struct clk_init_data){ 1775 1699 .name = "gcc_blsp1_qup3_spi_apps_clk", 1776 - .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" }, 1700 + .parent_hws = (const struct clk_hw*[]){ 1701 + &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1702 + }, 1777 1703 .num_parents = 1, 1778 1704 .flags = CLK_SET_RATE_PARENT, 1779 1705 .ops = &clk_branch2_ops, ··· 1790 1712 .enable_mask = BIT(0), 1791 1713 .hw.init = &(struct clk_init_data){ 1792 1714 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1793 - .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" }, 1715 + .parent_hws = (const struct clk_hw*[]){ 1716 + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1717 + }, 1794 1718 .num_parents = 1, 1795 1719 .flags = CLK_SET_RATE_PARENT, 1796 1720 .ops = &clk_branch2_ops, ··· 1807 1727 .enable_mask = BIT(0), 1808 1728 .hw.init = &(struct clk_init_data){ 1809 1729 .name = "gcc_blsp1_uart3_apps_clk", 1810 - .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" }, 1730 + .parent_hws = (const struct clk_hw*[]){ 1731 + &blsp1_uart3_apps_clk_src.clkr.hw, 1732 + }, 1811 1733 .num_parents = 1, 1812 1734 .flags = CLK_SET_RATE_PARENT, 1813 1735 .ops = &clk_branch2_ops, ··· 1824 1742 .enable_mask = BIT(0), 1825 1743 .hw.init = &(struct clk_init_data){ 1826 1744 .name = "gcc_blsp1_qup4_spi_apps_clk", 1827 - .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" }, 1745 + .parent_hws = (const struct clk_hw*[]){ 1746 + &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1747 + }, 1828 1748 .num_parents = 1, 1829 1749 .flags = CLK_SET_RATE_PARENT, 1830 1750 .ops = &clk_branch2_ops, ··· 1841 1757 .enable_mask = BIT(0), 1842 1758 .hw.init = &(struct clk_init_data){ 1843 1759 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1844 - .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" }, 1760 + .parent_hws = (const struct clk_hw*[]){ 1761 + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1762 + }, 1845 1763 .num_parents = 1, 1846 1764 .flags = CLK_SET_RATE_PARENT, 1847 1765 .ops = &clk_branch2_ops, ··· 1858 1772 .enable_mask = BIT(0), 1859 1773 .hw.init = &(struct clk_init_data){ 1860 1774 .name = "gcc_blsp1_uart4_apps_clk", 1861 - .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" }, 1775 + .parent_hws = (const struct clk_hw*[]){ 1776 + &blsp1_uart4_apps_clk_src.clkr.hw, 1777 + }, 1862 1778 .num_parents = 1, 1863 1779 .flags = CLK_SET_RATE_PARENT, 1864 1780 .ops = &clk_branch2_ops, ··· 1875 1787 .enable_mask = BIT(0), 1876 1788 .hw.init = &(struct clk_init_data){ 1877 1789 .name = "gcc_blsp1_qup5_spi_apps_clk", 1878 - .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" }, 1790 + .parent_hws = (const struct clk_hw*[]){ 1791 + &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1792 + }, 1879 1793 .num_parents = 1, 1880 1794 .flags = CLK_SET_RATE_PARENT, 1881 1795 .ops = &clk_branch2_ops, ··· 1892 1802 .enable_mask = BIT(0), 1893 1803 .hw.init = &(struct clk_init_data){ 1894 1804 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1895 - .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" }, 1805 + .parent_hws = (const struct clk_hw*[]){ 1806 + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1807 + }, 1896 1808 .num_parents = 1, 1897 1809 .flags = CLK_SET_RATE_PARENT, 1898 1810 .ops = &clk_branch2_ops, ··· 1909 1817 .enable_mask = BIT(0), 1910 1818 .hw.init = &(struct clk_init_data){ 1911 1819 .name = "gcc_blsp1_uart5_apps_clk", 1912 - .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" }, 1820 + .parent_hws = (const struct clk_hw*[]){ 1821 + &blsp1_uart5_apps_clk_src.clkr.hw, 1822 + }, 1913 1823 .num_parents = 1, 1914 1824 .flags = CLK_SET_RATE_PARENT, 1915 1825 .ops = &clk_branch2_ops, ··· 1926 1832 .enable_mask = BIT(0), 1927 1833 .hw.init = &(struct clk_init_data){ 1928 1834 .name = "gcc_blsp1_qup6_spi_apps_clk", 1929 - .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" }, 1835 + .parent_hws = (const struct clk_hw*[]){ 1836 + &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1837 + }, 1930 1838 .num_parents = 1, 1931 1839 .flags = CLK_SET_RATE_PARENT, 1932 1840 .ops = &clk_branch2_ops, ··· 1943 1847 .enable_mask = BIT(0), 1944 1848 .hw.init = &(struct clk_init_data){ 1945 1849 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1946 - .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" }, 1850 + .parent_hws = (const struct clk_hw*[]){ 1851 + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1852 + }, 1947 1853 .num_parents = 1, 1948 1854 .flags = CLK_SET_RATE_PARENT, 1949 1855 .ops = &clk_branch2_ops, ··· 1960 1862 .enable_mask = BIT(0), 1961 1863 .hw.init = &(struct clk_init_data){ 1962 1864 .name = "gcc_blsp1_uart6_apps_clk", 1963 - .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" }, 1865 + .parent_hws = (const struct clk_hw*[]){ 1866 + &blsp1_uart6_apps_clk_src.clkr.hw, 1867 + }, 1964 1868 .num_parents = 1, 1965 1869 .flags = CLK_SET_RATE_PARENT, 1966 1870 .ops = &clk_branch2_ops, ··· 1978 1878 .enable_mask = BIT(15), 1979 1879 .hw.init = &(struct clk_init_data){ 1980 1880 .name = "gcc_blsp2_ahb_clk", 1981 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 1881 + .parent_hws = (const struct clk_hw*[]){ 1882 + &periph_noc_clk_src.clkr.hw, 1883 + }, 1982 1884 .num_parents = 1, 1983 1885 .flags = CLK_SET_RATE_PARENT, 1984 1886 .ops = &clk_branch2_ops, ··· 1996 1894 .enable_mask = BIT(14), 1997 1895 .hw.init = &(struct clk_init_data){ 1998 1896 .name = "gcc_blsp2_sleep_clk", 1999 - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, 1897 + .parent_hws = (const struct clk_hw*[]){ 1898 + &gcc_sleep_clk_src.clkr.hw, 1899 + }, 2000 1900 .num_parents = 1, 2001 1901 .flags = CLK_SET_RATE_PARENT, 2002 1902 .ops = &clk_branch2_ops, ··· 2013 1909 .enable_mask = BIT(0), 2014 1910 .hw.init = &(struct clk_init_data){ 2015 1911 .name = "gcc_blsp2_qup1_spi_apps_clk", 2016 - .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" }, 1912 + .parent_hws = (const struct clk_hw*[]){ 1913 + &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1914 + }, 2017 1915 .num_parents = 1, 2018 1916 .flags = CLK_SET_RATE_PARENT, 2019 1917 .ops = &clk_branch2_ops, ··· 2030 1924 .enable_mask = BIT(0), 2031 1925 .hw.init = &(struct clk_init_data){ 2032 1926 .name = "gcc_blsp2_qup1_i2c_apps_clk", 2033 - .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" }, 1927 + .parent_hws = (const struct clk_hw*[]){ 1928 + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1929 + }, 2034 1930 .num_parents = 1, 2035 1931 .flags = CLK_SET_RATE_PARENT, 2036 1932 .ops = &clk_branch2_ops, ··· 2047 1939 .enable_mask = BIT(0), 2048 1940 .hw.init = &(struct clk_init_data){ 2049 1941 .name = "gcc_blsp2_uart1_apps_clk", 2050 - .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" }, 1942 + .parent_hws = (const struct clk_hw*[]){ 1943 + &blsp2_uart1_apps_clk_src.clkr.hw, 1944 + }, 2051 1945 .num_parents = 1, 2052 1946 .flags = CLK_SET_RATE_PARENT, 2053 1947 .ops = &clk_branch2_ops, ··· 2064 1954 .enable_mask = BIT(0), 2065 1955 .hw.init = &(struct clk_init_data){ 2066 1956 .name = "gcc_blsp2_qup2_spi_apps_clk", 2067 - .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" }, 1957 + .parent_hws = (const struct clk_hw*[]){ 1958 + &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1959 + }, 2068 1960 .num_parents = 1, 2069 1961 .flags = CLK_SET_RATE_PARENT, 2070 1962 .ops = &clk_branch2_ops, ··· 2081 1969 .enable_mask = BIT(0), 2082 1970 .hw.init = &(struct clk_init_data){ 2083 1971 .name = "gcc_blsp2_qup2_i2c_apps_clk", 2084 - .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" }, 1972 + .parent_hws = (const struct clk_hw*[]){ 1973 + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1974 + }, 2085 1975 .num_parents = 1, 2086 1976 .flags = CLK_SET_RATE_PARENT, 2087 1977 .ops = &clk_branch2_ops, ··· 2098 1984 .enable_mask = BIT(0), 2099 1985 .hw.init = &(struct clk_init_data){ 2100 1986 .name = "gcc_blsp2_uart2_apps_clk", 2101 - .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" }, 1987 + .parent_hws = (const struct clk_hw*[]){ 1988 + &blsp2_uart2_apps_clk_src.clkr.hw, 1989 + }, 2102 1990 .num_parents = 1, 2103 1991 .flags = CLK_SET_RATE_PARENT, 2104 1992 .ops = &clk_branch2_ops, ··· 2115 1999 .enable_mask = BIT(0), 2116 2000 .hw.init = &(struct clk_init_data){ 2117 2001 .name = "gcc_blsp2_qup3_spi_apps_clk", 2118 - .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" }, 2002 + .parent_hws = (const struct clk_hw*[]){ 2003 + &blsp2_qup3_spi_apps_clk_src.clkr.hw, 2004 + }, 2119 2005 .num_parents = 1, 2120 2006 .flags = CLK_SET_RATE_PARENT, 2121 2007 .ops = &clk_branch2_ops, ··· 2132 2014 .enable_mask = BIT(0), 2133 2015 .hw.init = &(struct clk_init_data){ 2134 2016 .name = "gcc_blsp2_qup3_i2c_apps_clk", 2135 - .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" }, 2017 + .parent_hws = (const struct clk_hw*[]){ 2018 + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 2019 + }, 2136 2020 .num_parents = 1, 2137 2021 .flags = CLK_SET_RATE_PARENT, 2138 2022 .ops = &clk_branch2_ops, ··· 2149 2029 .enable_mask = BIT(0), 2150 2030 .hw.init = &(struct clk_init_data){ 2151 2031 .name = "gcc_blsp2_uart3_apps_clk", 2152 - .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" }, 2032 + .parent_hws = (const struct clk_hw*[]){ 2033 + &blsp2_uart3_apps_clk_src.clkr.hw, 2034 + }, 2153 2035 .num_parents = 1, 2154 2036 .flags = CLK_SET_RATE_PARENT, 2155 2037 .ops = &clk_branch2_ops, ··· 2166 2044 .enable_mask = BIT(0), 2167 2045 .hw.init = &(struct clk_init_data){ 2168 2046 .name = "gcc_blsp2_qup4_spi_apps_clk", 2169 - .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" }, 2047 + .parent_hws = (const struct clk_hw*[]){ 2048 + &blsp2_qup4_spi_apps_clk_src.clkr.hw, 2049 + }, 2170 2050 .num_parents = 1, 2171 2051 .flags = CLK_SET_RATE_PARENT, 2172 2052 .ops = &clk_branch2_ops, ··· 2183 2059 .enable_mask = BIT(0), 2184 2060 .hw.init = &(struct clk_init_data){ 2185 2061 .name = "gcc_blsp2_qup4_i2c_apps_clk", 2186 - .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" }, 2062 + .parent_hws = (const struct clk_hw*[]){ 2063 + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 2064 + }, 2187 2065 .num_parents = 1, 2188 2066 .flags = CLK_SET_RATE_PARENT, 2189 2067 .ops = &clk_branch2_ops, ··· 2200 2074 .enable_mask = BIT(0), 2201 2075 .hw.init = &(struct clk_init_data){ 2202 2076 .name = "gcc_blsp2_uart4_apps_clk", 2203 - .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" }, 2077 + .parent_hws = (const struct clk_hw*[]){ 2078 + &blsp2_uart4_apps_clk_src.clkr.hw, 2079 + }, 2204 2080 .num_parents = 1, 2205 2081 .flags = CLK_SET_RATE_PARENT, 2206 2082 .ops = &clk_branch2_ops, ··· 2217 2089 .enable_mask = BIT(0), 2218 2090 .hw.init = &(struct clk_init_data){ 2219 2091 .name = "gcc_blsp2_qup5_spi_apps_clk", 2220 - .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" }, 2092 + .parent_hws = (const struct clk_hw*[]){ 2093 + &blsp2_qup5_spi_apps_clk_src.clkr.hw, 2094 + }, 2221 2095 .num_parents = 1, 2222 2096 .flags = CLK_SET_RATE_PARENT, 2223 2097 .ops = &clk_branch2_ops, ··· 2234 2104 .enable_mask = BIT(0), 2235 2105 .hw.init = &(struct clk_init_data){ 2236 2106 .name = "gcc_blsp2_qup5_i2c_apps_clk", 2237 - .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" }, 2107 + .parent_hws = (const struct clk_hw*[]){ 2108 + &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 2109 + }, 2238 2110 .num_parents = 1, 2239 2111 .flags = CLK_SET_RATE_PARENT, 2240 2112 .ops = &clk_branch2_ops, ··· 2251 2119 .enable_mask = BIT(0), 2252 2120 .hw.init = &(struct clk_init_data){ 2253 2121 .name = "gcc_blsp2_uart5_apps_clk", 2254 - .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" }, 2122 + .parent_hws = (const struct clk_hw*[]){ 2123 + &blsp2_uart5_apps_clk_src.clkr.hw, 2124 + }, 2255 2125 .num_parents = 1, 2256 2126 .flags = CLK_SET_RATE_PARENT, 2257 2127 .ops = &clk_branch2_ops, ··· 2268 2134 .enable_mask = BIT(0), 2269 2135 .hw.init = &(struct clk_init_data){ 2270 2136 .name = "gcc_blsp2_qup6_spi_apps_clk", 2271 - .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" }, 2137 + .parent_hws = (const struct clk_hw*[]){ 2138 + &blsp2_qup6_spi_apps_clk_src.clkr.hw, 2139 + }, 2272 2140 .num_parents = 1, 2273 2141 .flags = CLK_SET_RATE_PARENT, 2274 2142 .ops = &clk_branch2_ops, ··· 2285 2149 .enable_mask = BIT(0), 2286 2150 .hw.init = &(struct clk_init_data){ 2287 2151 .name = "gcc_blsp2_qup6_i2c_apps_clk", 2288 - .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" }, 2152 + .parent_hws = (const struct clk_hw*[]){ 2153 + &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 2154 + }, 2289 2155 .num_parents = 1, 2290 2156 .flags = CLK_SET_RATE_PARENT, 2291 2157 .ops = &clk_branch2_ops, ··· 2302 2164 .enable_mask = BIT(0), 2303 2165 .hw.init = &(struct clk_init_data){ 2304 2166 .name = "gcc_blsp2_uart6_apps_clk", 2305 - .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" }, 2167 + .parent_hws = (const struct clk_hw*[]){ 2168 + &blsp2_uart6_apps_clk_src.clkr.hw, 2169 + }, 2306 2170 .num_parents = 1, 2307 2171 .flags = CLK_SET_RATE_PARENT, 2308 2172 .ops = &clk_branch2_ops, ··· 2319 2179 .enable_mask = BIT(0), 2320 2180 .hw.init = &(struct clk_init_data){ 2321 2181 .name = "gcc_pdm_ahb_clk", 2322 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 2182 + .parent_hws = (const struct clk_hw*[]){ 2183 + &periph_noc_clk_src.clkr.hw, 2184 + }, 2323 2185 .num_parents = 1, 2324 2186 .flags = CLK_SET_RATE_PARENT, 2325 2187 .ops = &clk_branch2_ops, ··· 2336 2194 .enable_mask = BIT(0), 2337 2195 .hw.init = &(struct clk_init_data){ 2338 2196 .name = "gcc_pdm2_clk", 2339 - .parent_names = (const char *[]){ "pdm2_clk_src" }, 2197 + .parent_hws = (const struct clk_hw*[]){ 2198 + &pdm2_clk_src.clkr.hw, 2199 + }, 2340 2200 .num_parents = 1, 2341 2201 .flags = CLK_SET_RATE_PARENT, 2342 2202 .ops = &clk_branch2_ops, ··· 2354 2210 .enable_mask = BIT(13), 2355 2211 .hw.init = &(struct clk_init_data){ 2356 2212 .name = "gcc_prng_ahb_clk", 2357 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2213 + .parent_hws = (const struct clk_hw*[]){ 2214 + &config_noc_clk_src.clkr.hw, 2215 + }, 2358 2216 .num_parents = 1, 2359 2217 .flags = CLK_SET_RATE_PARENT, 2360 2218 .ops = &clk_branch2_ops, ··· 2371 2225 .enable_mask = BIT(0), 2372 2226 .hw.init = &(struct clk_init_data){ 2373 2227 .name = "gcc_tsif_ahb_clk", 2374 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 2228 + .parent_hws = (const struct clk_hw*[]){ 2229 + &periph_noc_clk_src.clkr.hw, 2230 + }, 2375 2231 .num_parents = 1, 2376 2232 .flags = CLK_SET_RATE_PARENT, 2377 2233 .ops = &clk_branch2_ops, ··· 2388 2240 .enable_mask = BIT(0), 2389 2241 .hw.init = &(struct clk_init_data){ 2390 2242 .name = "gcc_tsif_ref_clk", 2391 - .parent_names = (const char *[]){ "tsif_ref_clk_src" }, 2243 + .parent_hws = (const struct clk_hw*[]){ 2244 + &tsif_ref_clk_src.clkr.hw, 2245 + }, 2392 2246 .num_parents = 1, 2393 2247 .flags = CLK_SET_RATE_PARENT, 2394 2248 .ops = &clk_branch2_ops, ··· 2405 2255 .enable_mask = BIT(0), 2406 2256 .hw.init = &(struct clk_init_data){ 2407 2257 .name = "gcc_tsif_inactivity_timers_clk", 2408 - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, 2258 + .parent_hws = (const struct clk_hw*[]){ 2259 + &gcc_sleep_clk_src.clkr.hw, 2260 + }, 2409 2261 .num_parents = 1, 2410 2262 .flags = CLK_SET_RATE_PARENT, 2411 2263 .ops = &clk_branch2_ops, ··· 2423 2271 .enable_mask = BIT(10), 2424 2272 .hw.init = &(struct clk_init_data){ 2425 2273 .name = "gcc_boot_rom_ahb_clk", 2426 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2274 + .parent_hws = (const struct clk_hw*[]){ 2275 + &config_noc_clk_src.clkr.hw, 2276 + }, 2427 2277 .num_parents = 1, 2428 2278 .flags = CLK_SET_RATE_PARENT, 2429 2279 .ops = &clk_branch2_ops, ··· 2453 2299 .enable_mask = BIT(0), 2454 2300 .hw.init = &(struct clk_init_data){ 2455 2301 .name = "gcc_hmss_rbcpr_clk", 2456 - .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" }, 2302 + .parent_hws = (const struct clk_hw*[]){ 2303 + &hmss_rbcpr_clk_src.clkr.hw, 2304 + }, 2457 2305 .num_parents = 1, 2458 2306 .flags = CLK_SET_RATE_PARENT, 2459 2307 .ops = &clk_branch2_ops, ··· 2470 2314 .enable_mask = BIT(0), 2471 2315 .hw.init = &(struct clk_init_data){ 2472 2316 .name = "gcc_gp1_clk", 2473 - .parent_names = (const char *[]){ "gp1_clk_src" }, 2317 + .parent_hws = (const struct clk_hw*[]){ 2318 + &gp1_clk_src.clkr.hw, 2319 + }, 2474 2320 .num_parents = 1, 2475 2321 .flags = CLK_SET_RATE_PARENT, 2476 2322 .ops = &clk_branch2_ops, ··· 2487 2329 .enable_mask = BIT(0), 2488 2330 .hw.init = &(struct clk_init_data){ 2489 2331 .name = "gcc_gp2_clk", 2490 - .parent_names = (const char *[]){ "gp2_clk_src" }, 2332 + .parent_hws = (const struct clk_hw*[]){ 2333 + &gp2_clk_src.clkr.hw, 2334 + }, 2491 2335 .num_parents = 1, 2492 2336 .flags = CLK_SET_RATE_PARENT, 2493 2337 .ops = &clk_branch2_ops, ··· 2504 2344 .enable_mask = BIT(0), 2505 2345 .hw.init = &(struct clk_init_data){ 2506 2346 .name = "gcc_gp3_clk", 2507 - .parent_names = (const char *[]){ "gp3_clk_src" }, 2347 + .parent_hws = (const struct clk_hw*[]){ 2348 + &gp3_clk_src.clkr.hw, 2349 + }, 2508 2350 .num_parents = 1, 2509 2351 .flags = CLK_SET_RATE_PARENT, 2510 2352 .ops = &clk_branch2_ops, ··· 2521 2359 .enable_mask = BIT(0), 2522 2360 .hw.init = &(struct clk_init_data){ 2523 2361 .name = "gcc_pcie_0_slv_axi_clk", 2524 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2362 + .parent_hws = (const struct clk_hw*[]){ 2363 + &system_noc_clk_src.clkr.hw, 2364 + }, 2525 2365 .num_parents = 1, 2526 2366 .flags = CLK_SET_RATE_PARENT, 2527 2367 .ops = &clk_branch2_ops, ··· 2538 2374 .enable_mask = BIT(0), 2539 2375 .hw.init = &(struct clk_init_data){ 2540 2376 .name = "gcc_pcie_0_mstr_axi_clk", 2541 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2377 + .parent_hws = (const struct clk_hw*[]){ 2378 + &system_noc_clk_src.clkr.hw, 2379 + }, 2542 2380 .num_parents = 1, 2543 2381 .flags = CLK_SET_RATE_PARENT, 2544 2382 .ops = &clk_branch2_ops, ··· 2555 2389 .enable_mask = BIT(0), 2556 2390 .hw.init = &(struct clk_init_data){ 2557 2391 .name = "gcc_pcie_0_cfg_ahb_clk", 2558 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2392 + .parent_hws = (const struct clk_hw*[]){ 2393 + &config_noc_clk_src.clkr.hw, 2394 + }, 2559 2395 .num_parents = 1, 2560 2396 .flags = CLK_SET_RATE_PARENT, 2561 2397 .ops = &clk_branch2_ops, ··· 2572 2404 .enable_mask = BIT(0), 2573 2405 .hw.init = &(struct clk_init_data){ 2574 2406 .name = "gcc_pcie_0_aux_clk", 2575 - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, 2407 + .parent_hws = (const struct clk_hw*[]){ 2408 + &pcie_aux_clk_src.clkr.hw, 2409 + }, 2576 2410 .num_parents = 1, 2577 2411 .flags = CLK_SET_RATE_PARENT, 2578 2412 .ops = &clk_branch2_ops, ··· 2590 2420 .enable_mask = BIT(0), 2591 2421 .hw.init = &(struct clk_init_data){ 2592 2422 .name = "gcc_pcie_0_pipe_clk", 2593 - .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" }, 2423 + .parent_data = &(const struct clk_parent_data){ 2424 + .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src", 2425 + }, 2594 2426 .num_parents = 1, 2595 2427 .flags = CLK_SET_RATE_PARENT, 2596 2428 .ops = &clk_branch2_ops, ··· 2607 2435 .enable_mask = BIT(0), 2608 2436 .hw.init = &(struct clk_init_data){ 2609 2437 .name = "gcc_pcie_1_slv_axi_clk", 2610 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2438 + .parent_hws = (const struct clk_hw*[]){ 2439 + &system_noc_clk_src.clkr.hw, 2440 + }, 2611 2441 .num_parents = 1, 2612 2442 .flags = CLK_SET_RATE_PARENT, 2613 2443 .ops = &clk_branch2_ops, ··· 2624 2450 .enable_mask = BIT(0), 2625 2451 .hw.init = &(struct clk_init_data){ 2626 2452 .name = "gcc_pcie_1_mstr_axi_clk", 2627 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2453 + .parent_hws = (const struct clk_hw*[]){ 2454 + &system_noc_clk_src.clkr.hw, 2455 + }, 2628 2456 .num_parents = 1, 2629 2457 .flags = CLK_SET_RATE_PARENT, 2630 2458 .ops = &clk_branch2_ops, ··· 2641 2465 .enable_mask = BIT(0), 2642 2466 .hw.init = &(struct clk_init_data){ 2643 2467 .name = "gcc_pcie_1_cfg_ahb_clk", 2644 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2468 + .parent_hws = (const struct clk_hw*[]){ 2469 + &config_noc_clk_src.clkr.hw, 2470 + }, 2645 2471 .num_parents = 1, 2646 2472 .flags = CLK_SET_RATE_PARENT, 2647 2473 .ops = &clk_branch2_ops, ··· 2658 2480 .enable_mask = BIT(0), 2659 2481 .hw.init = &(struct clk_init_data){ 2660 2482 .name = "gcc_pcie_1_aux_clk", 2661 - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, 2483 + .parent_hws = (const struct clk_hw*[]){ 2484 + &pcie_aux_clk_src.clkr.hw, 2485 + }, 2662 2486 .num_parents = 1, 2663 2487 .flags = CLK_SET_RATE_PARENT, 2664 2488 .ops = &clk_branch2_ops, ··· 2676 2496 .enable_mask = BIT(0), 2677 2497 .hw.init = &(struct clk_init_data){ 2678 2498 .name = "gcc_pcie_1_pipe_clk", 2679 - .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" }, 2499 + .parent_data = &(const struct clk_parent_data){ 2500 + .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src", 2501 + }, 2680 2502 .num_parents = 1, 2681 2503 .flags = CLK_SET_RATE_PARENT, 2682 2504 .ops = &clk_branch2_ops, ··· 2693 2511 .enable_mask = BIT(0), 2694 2512 .hw.init = &(struct clk_init_data){ 2695 2513 .name = "gcc_pcie_2_slv_axi_clk", 2696 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2514 + .parent_hws = (const struct clk_hw*[]){ 2515 + &system_noc_clk_src.clkr.hw, 2516 + }, 2697 2517 .num_parents = 1, 2698 2518 .flags = CLK_SET_RATE_PARENT, 2699 2519 .ops = &clk_branch2_ops, ··· 2710 2526 .enable_mask = BIT(0), 2711 2527 .hw.init = &(struct clk_init_data){ 2712 2528 .name = "gcc_pcie_2_mstr_axi_clk", 2713 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2529 + .parent_hws = (const struct clk_hw*[]){ 2530 + &system_noc_clk_src.clkr.hw, 2531 + }, 2714 2532 .num_parents = 1, 2715 2533 .flags = CLK_SET_RATE_PARENT, 2716 2534 .ops = &clk_branch2_ops, ··· 2727 2541 .enable_mask = BIT(0), 2728 2542 .hw.init = &(struct clk_init_data){ 2729 2543 .name = "gcc_pcie_2_cfg_ahb_clk", 2730 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2544 + .parent_hws = (const struct clk_hw*[]){ 2545 + &config_noc_clk_src.clkr.hw, 2546 + }, 2731 2547 .num_parents = 1, 2732 2548 .flags = CLK_SET_RATE_PARENT, 2733 2549 .ops = &clk_branch2_ops, ··· 2744 2556 .enable_mask = BIT(0), 2745 2557 .hw.init = &(struct clk_init_data){ 2746 2558 .name = "gcc_pcie_2_aux_clk", 2747 - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, 2559 + .parent_hws = (const struct clk_hw*[]){ 2560 + &pcie_aux_clk_src.clkr.hw, 2561 + }, 2748 2562 .num_parents = 1, 2749 2563 .flags = CLK_SET_RATE_PARENT, 2750 2564 .ops = &clk_branch2_ops, ··· 2762 2572 .enable_mask = BIT(0), 2763 2573 .hw.init = &(struct clk_init_data){ 2764 2574 .name = "gcc_pcie_2_pipe_clk", 2765 - .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" }, 2575 + .parent_data = &(const struct clk_parent_data){ 2576 + .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src", 2577 + }, 2766 2578 .num_parents = 1, 2767 2579 .flags = CLK_SET_RATE_PARENT, 2768 2580 .ops = &clk_branch2_ops, ··· 2779 2587 .enable_mask = BIT(0), 2780 2588 .hw.init = &(struct clk_init_data){ 2781 2589 .name = "gcc_pcie_phy_cfg_ahb_clk", 2782 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2590 + .parent_hws = (const struct clk_hw*[]){ 2591 + &config_noc_clk_src.clkr.hw, 2592 + }, 2783 2593 .num_parents = 1, 2784 2594 .flags = CLK_SET_RATE_PARENT, 2785 2595 .ops = &clk_branch2_ops, ··· 2796 2602 .enable_mask = BIT(0), 2797 2603 .hw.init = &(struct clk_init_data){ 2798 2604 .name = "gcc_pcie_phy_aux_clk", 2799 - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, 2605 + .parent_hws = (const struct clk_hw*[]){ 2606 + &pcie_aux_clk_src.clkr.hw, 2607 + }, 2800 2608 .num_parents = 1, 2801 2609 .flags = CLK_SET_RATE_PARENT, 2802 2610 .ops = &clk_branch2_ops, ··· 2813 2617 .enable_mask = BIT(0), 2814 2618 .hw.init = &(struct clk_init_data){ 2815 2619 .name = "gcc_ufs_axi_clk", 2816 - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, 2620 + .parent_hws = (const struct clk_hw*[]){ 2621 + &ufs_axi_clk_src.clkr.hw, 2622 + }, 2817 2623 .num_parents = 1, 2818 2624 .flags = CLK_SET_RATE_PARENT, 2819 2625 .ops = &clk_branch2_ops, ··· 2830 2632 .enable_mask = BIT(0), 2831 2633 .hw.init = &(struct clk_init_data){ 2832 2634 .name = "gcc_ufs_ahb_clk", 2833 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2635 + .parent_hws = (const struct clk_hw*[]){ 2636 + &config_noc_clk_src.clkr.hw, 2637 + }, 2834 2638 .num_parents = 1, 2835 2639 .flags = CLK_SET_RATE_PARENT, 2836 2640 .ops = &clk_branch2_ops, ··· 2845 2645 .div = 16, 2846 2646 .hw.init = &(struct clk_init_data){ 2847 2647 .name = "ufs_tx_cfg_clk_src", 2848 - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, 2648 + .parent_hws = (const struct clk_hw*[]){ 2649 + &ufs_axi_clk_src.clkr.hw, 2650 + }, 2849 2651 .num_parents = 1, 2850 2652 .flags = CLK_SET_RATE_PARENT, 2851 2653 .ops = &clk_fixed_factor_ops, ··· 2861 2659 .enable_mask = BIT(0), 2862 2660 .hw.init = &(struct clk_init_data){ 2863 2661 .name = "gcc_ufs_tx_cfg_clk", 2864 - .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" }, 2662 + .parent_hws = (const struct clk_hw*[]){ 2663 + &ufs_tx_cfg_clk_src.hw, 2664 + }, 2865 2665 .num_parents = 1, 2866 2666 .flags = CLK_SET_RATE_PARENT, 2867 2667 .ops = &clk_branch2_ops, ··· 2876 2672 .div = 16, 2877 2673 .hw.init = &(struct clk_init_data){ 2878 2674 .name = "ufs_rx_cfg_clk_src", 2879 - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, 2675 + .parent_hws = (const struct clk_hw*[]){ 2676 + &ufs_axi_clk_src.clkr.hw, 2677 + }, 2880 2678 .num_parents = 1, 2881 2679 .flags = CLK_SET_RATE_PARENT, 2882 2680 .ops = &clk_fixed_factor_ops, ··· 2918 2712 .enable_mask = BIT(0), 2919 2713 .hw.init = &(struct clk_init_data){ 2920 2714 .name = "gcc_ufs_rx_cfg_clk", 2921 - .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" }, 2715 + .parent_hws = (const struct clk_hw*[]){ 2716 + &ufs_rx_cfg_clk_src.hw, 2717 + }, 2922 2718 .num_parents = 1, 2923 2719 .flags = CLK_SET_RATE_PARENT, 2924 2720 .ops = &clk_branch2_ops, ··· 2936 2728 .enable_mask = BIT(0), 2937 2729 .hw.init = &(struct clk_init_data){ 2938 2730 .name = "gcc_ufs_tx_symbol_0_clk", 2939 - .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" }, 2731 + .parent_data = &(const struct clk_parent_data){ 2732 + .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src", 2733 + }, 2940 2734 .num_parents = 1, 2941 2735 .flags = CLK_SET_RATE_PARENT, 2942 2736 .ops = &clk_branch2_ops, ··· 2954 2744 .enable_mask = BIT(0), 2955 2745 .hw.init = &(struct clk_init_data){ 2956 2746 .name = "gcc_ufs_rx_symbol_0_clk", 2957 - .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" }, 2747 + .parent_data = &(const struct clk_parent_data){ 2748 + .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src", 2749 + }, 2958 2750 .num_parents = 1, 2959 2751 .flags = CLK_SET_RATE_PARENT, 2960 2752 .ops = &clk_branch2_ops, ··· 2972 2760 .enable_mask = BIT(0), 2973 2761 .hw.init = &(struct clk_init_data){ 2974 2762 .name = "gcc_ufs_rx_symbol_1_clk", 2975 - .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" }, 2763 + .parent_data = &(const struct clk_parent_data){ 2764 + .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src", 2765 + }, 2976 2766 .num_parents = 1, 2977 2767 .flags = CLK_SET_RATE_PARENT, 2978 2768 .ops = &clk_branch2_ops, ··· 2987 2773 .div = 2, 2988 2774 .hw.init = &(struct clk_init_data){ 2989 2775 .name = "ufs_ice_core_postdiv_clk_src", 2990 - .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, 2776 + .parent_hws = (const struct clk_hw*[]){ 2777 + &ufs_ice_core_clk_src.clkr.hw, 2778 + }, 2991 2779 .num_parents = 1, 2992 2780 .flags = CLK_SET_RATE_PARENT, 2993 2781 .ops = &clk_fixed_factor_ops, ··· 3003 2787 .enable_mask = BIT(0), 3004 2788 .hw.init = &(struct clk_init_data){ 3005 2789 .name = "gcc_ufs_unipro_core_clk", 3006 - .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" }, 2790 + .parent_hws = (const struct clk_hw*[]){ 2791 + &ufs_ice_core_postdiv_clk_src.hw, 2792 + }, 3007 2793 .num_parents = 1, 3008 2794 .flags = CLK_SET_RATE_PARENT, 3009 2795 .ops = &clk_branch2_ops, ··· 3020 2802 .enable_mask = BIT(0), 3021 2803 .hw.init = &(struct clk_init_data){ 3022 2804 .name = "gcc_ufs_ice_core_clk", 3023 - .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, 2805 + .parent_hws = (const struct clk_hw*[]){ 2806 + &ufs_ice_core_clk_src.clkr.hw, 2807 + }, 3024 2808 .num_parents = 1, 3025 2809 .flags = CLK_SET_RATE_PARENT, 3026 2810 .ops = &clk_branch2_ops, ··· 3061 2841 .enable_mask = BIT(0), 3062 2842 .hw.init = &(struct clk_init_data){ 3063 2843 .name = "gcc_aggre0_snoc_axi_clk", 3064 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2844 + .parent_hws = (const struct clk_hw*[]){ 2845 + &system_noc_clk_src.clkr.hw, 2846 + }, 3065 2847 .num_parents = 1, 3066 2848 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3067 2849 .ops = &clk_branch2_ops, ··· 3078 2856 .enable_mask = BIT(0), 3079 2857 .hw.init = &(struct clk_init_data){ 3080 2858 .name = "gcc_aggre0_cnoc_ahb_clk", 3081 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2859 + .parent_hws = (const struct clk_hw*[]){ 2860 + &config_noc_clk_src.clkr.hw, 2861 + }, 3082 2862 .num_parents = 1, 3083 2863 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3084 2864 .ops = &clk_branch2_ops, ··· 3095 2871 .enable_mask = BIT(0), 3096 2872 .hw.init = &(struct clk_init_data){ 3097 2873 .name = "gcc_smmu_aggre0_axi_clk", 3098 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 2874 + .parent_hws = (const struct clk_hw*[]){ 2875 + &system_noc_clk_src.clkr.hw, 2876 + }, 3099 2877 .num_parents = 1, 3100 2878 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3101 2879 .ops = &clk_branch2_ops, ··· 3112 2886 .enable_mask = BIT(0), 3113 2887 .hw.init = &(struct clk_init_data){ 3114 2888 .name = "gcc_smmu_aggre0_ahb_clk", 3115 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2889 + .parent_hws = (const struct clk_hw*[]){ 2890 + &config_noc_clk_src.clkr.hw, 2891 + }, 3116 2892 .num_parents = 1, 3117 2893 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3118 2894 .ops = &clk_branch2_ops, ··· 3129 2901 .enable_mask = BIT(0), 3130 2902 .hw.init = &(struct clk_init_data){ 3131 2903 .name = "gcc_aggre2_ufs_axi_clk", 3132 - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, 2904 + .parent_hws = (const struct clk_hw*[]){ 2905 + &ufs_axi_clk_src.clkr.hw, 2906 + }, 3133 2907 .num_parents = 1, 3134 2908 .flags = CLK_SET_RATE_PARENT, 3135 2909 .ops = &clk_branch2_ops, ··· 3146 2916 .enable_mask = BIT(0), 3147 2917 .hw.init = &(struct clk_init_data){ 3148 2918 .name = "gcc_aggre2_usb3_axi_clk", 3149 - .parent_names = (const char *[]){ "usb30_master_clk_src" }, 2919 + .parent_hws = (const struct clk_hw*[]){ 2920 + &usb30_master_clk_src.clkr.hw, 2921 + }, 3150 2922 .num_parents = 1, 3151 2923 .flags = CLK_SET_RATE_PARENT, 3152 2924 .ops = &clk_branch2_ops, ··· 3163 2931 .enable_mask = BIT(0), 3164 2932 .hw.init = &(struct clk_init_data){ 3165 2933 .name = "gcc_dcc_ahb_clk", 3166 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2934 + .parent_hws = (const struct clk_hw*[]){ 2935 + &config_noc_clk_src.clkr.hw, 2936 + }, 3167 2937 .num_parents = 1, 3168 2938 .ops = &clk_branch2_ops, 3169 2939 }, ··· 3179 2945 .enable_mask = BIT(0), 3180 2946 .hw.init = &(struct clk_init_data){ 3181 2947 .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk", 3182 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 2948 + .parent_hws = (const struct clk_hw*[]){ 2949 + &config_noc_clk_src.clkr.hw, 2950 + }, 3183 2951 .num_parents = 1, 3184 2952 .ops = &clk_branch2_ops, 3185 2953 }, ··· 3195 2959 .enable_mask = BIT(0), 3196 2960 .hw.init = &(struct clk_init_data){ 3197 2961 .name = "gcc_qspi_ahb_clk", 3198 - .parent_names = (const char *[]){ "periph_noc_clk_src" }, 2962 + .parent_hws = (const struct clk_hw*[]){ 2963 + &periph_noc_clk_src.clkr.hw, 2964 + }, 3199 2965 .num_parents = 1, 3200 2966 .flags = CLK_SET_RATE_PARENT, 3201 2967 .ops = &clk_branch2_ops, ··· 3212 2974 .enable_mask = BIT(0), 3213 2975 .hw.init = &(struct clk_init_data){ 3214 2976 .name = "gcc_qspi_ser_clk", 3215 - .parent_names = (const char *[]){ "qspi_ser_clk_src" }, 2977 + .parent_hws = (const struct clk_hw*[]){ 2978 + &qspi_ser_clk_src.clkr.hw, 2979 + }, 3216 2980 .num_parents = 1, 3217 2981 .flags = CLK_SET_RATE_PARENT, 3218 2982 .ops = &clk_branch2_ops, ··· 3348 3108 .enable_mask = BIT(0), 3349 3109 .hw.init = &(struct clk_init_data){ 3350 3110 .name = "gcc_mss_cfg_ahb_clk", 3351 - .parent_names = (const char *[]){ "config_noc_clk_src" }, 3111 + .parent_hws = (const struct clk_hw*[]){ 3112 + &config_noc_clk_src.clkr.hw, 3113 + }, 3352 3114 .num_parents = 1, 3353 3115 .ops = &clk_branch2_ops, 3354 3116 }, ··· 3364 3122 .enable_mask = BIT(0), 3365 3123 .hw.init = &(struct clk_init_data){ 3366 3124 .name = "gcc_mss_mnoc_bimc_axi_clk", 3367 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 3125 + .parent_hws = (const struct clk_hw*[]){ 3126 + &system_noc_clk_src.clkr.hw, 3127 + }, 3368 3128 .num_parents = 1, 3369 3129 .ops = &clk_branch2_ops, 3370 3130 }, ··· 3380 3136 .enable_mask = BIT(0), 3381 3137 .hw.init = &(struct clk_init_data){ 3382 3138 .name = "gcc_mss_snoc_axi_clk", 3383 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 3139 + .parent_hws = (const struct clk_hw*[]){ 3140 + &system_noc_clk_src.clkr.hw, 3141 + }, 3384 3142 .num_parents = 1, 3385 3143 .ops = &clk_branch2_ops, 3386 3144 }, ··· 3396 3150 .enable_mask = BIT(0), 3397 3151 .hw.init = &(struct clk_init_data){ 3398 3152 .name = "gcc_mss_q6_bimc_axi_clk", 3399 - .parent_names = (const char *[]){ "system_noc_clk_src" }, 3153 + .parent_hws = (const struct clk_hw*[]){ 3154 + &system_noc_clk_src.clkr.hw, 3155 + }, 3400 3156 .num_parents = 1, 3401 3157 .ops = &clk_branch2_ops, 3402 3158 },