Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.4-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
"Found a couple of brown paper bag bugs with the prev pull request
(including a SMP build breakage report from Guenter). Since these are
urgent I also decided to send over a bunch of other pending fixes
which could have otherwise waited an rc or two.
Summary:
- A bunch of brown paper bag bugs (MAINTAINERS list email, SMP build
failure)
- cpu_relax() now compiler barrier for UP as well
- handling of userspace Bus Errors for ARCompact builds"
* tag 'arc-4.4-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: Fix silly typo in MAINTAINERS file
ARC: cpu_relax() to be compiler barrier even for UP
ARC: use ASL assembler mnemonic
ARC: [arcompact] Handle bus error from userspace as Interrupt not exception
ARC: remove extraneous header include
ARCv2: lib: memcpy: use local symbols
+74
-56
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
-4
arch/arc/include/asm/processor.h
-4
arch/arc/include/asm/processor.h
···
57
57
* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
58
58
* get optimised away by gcc
59
59
*/
60
-
#ifdef CONFIG_SMP
61
60
#define cpu_relax() __asm__ __volatile__ ("" : : : "memory")
62
-
#else
63
-
#define cpu_relax() do { } while (0)
64
-
#endif
65
61
66
62
#define cpu_relax_lowlatency() cpu_relax()
67
63
+19
arch/arc/kernel/entry-arcv2.S
+19
arch/arc/kernel/entry-arcv2.S
···
91
91
flag 1
92
92
END(EV_DCError)
93
93
94
+
; ---------------------------------------------
95
+
; Memory Error Exception Handler
96
+
; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
97
+
; Instruction fetch or Data access, under a single Exception Vector
98
+
; ---------------------------------------------
99
+
100
+
ENTRY(mem_service)
101
+
102
+
EXCEPTION_PROLOGUE
103
+
104
+
lr r0, [efa]
105
+
mov r1, sp
106
+
107
+
FAKE_RET_FROM_EXCPN
108
+
109
+
bl do_memory_error
110
+
b ret_from_exception
111
+
END(mem_service)
112
+
94
113
ENTRY(EV_Misaligned)
95
114
96
115
EXCEPTION_PROLOGUE
+25
-4
arch/arc/kernel/entry-compact.S
+25
-4
arch/arc/kernel/entry-compact.S
···
142
142
.zero 4
143
143
144
144
/* Each Interrupt level needs its own scratch */
145
-
#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
146
-
147
145
ARCFP_DATA int2_saved_reg
148
146
.type int2_saved_reg, @object
149
147
.size int2_saved_reg, 4
150
148
int2_saved_reg:
151
149
.zero 4
152
-
153
-
#endif
154
150
155
151
; ---------------------------------------------
156
152
.section .text, "ax",@progbits
···
210
214
END(handle_interrupt_level2)
211
215
212
216
#endif
217
+
218
+
; ---------------------------------------------
219
+
; User Mode Memory Bus Error Interrupt Handler
220
+
; (Kernel mode memory errors handled via seperate exception vectors)
221
+
; ---------------------------------------------
222
+
ENTRY(mem_service)
223
+
224
+
INTERRUPT_PROLOGUE 2
225
+
226
+
mov r0, ilink2
227
+
mov r1, sp
228
+
229
+
; User process needs to be killed with SIGBUS, but first need to get
230
+
; out of the L2 interrupt context (drop to pure kernel mode) and jump
231
+
; off to "C" code where SIGBUS in enqueued
232
+
lr r3, [status32]
233
+
bclr r3, r3, STATUS_A2_BIT
234
+
or r3, r3, (STATUS_E1_MASK|STATUS_E2_MASK)
235
+
sr r3, [status32_l2]
236
+
mov ilink2, 1f
237
+
rtie
238
+
1:
239
+
bl do_memory_error
240
+
b ret_from_exception
241
+
END(mem_service)
213
242
214
243
; ---------------------------------------------
215
244
; Level 1 ISR
-17
arch/arc/kernel/entry.S
-17
arch/arc/kernel/entry.S
···
93
93
END(instr_service)
94
94
95
95
; ---------------------------------------------
96
-
; Memory Error Exception Handler
97
-
; ---------------------------------------------
98
-
99
-
ENTRY(mem_service)
100
-
101
-
EXCEPTION_PROLOGUE
102
-
103
-
lr r0, [efa]
104
-
mov r1, sp
105
-
106
-
FAKE_RET_FROM_EXCPN
107
-
108
-
bl do_memory_error
109
-
b ret_from_exception
110
-
END(mem_service)
111
-
112
-
; ---------------------------------------------
113
96
; Machine Check Exception Handler
114
97
; ---------------------------------------------
115
98
+26
-26
arch/arc/lib/memcpy-archs.S
+26
-26
arch/arc/lib/memcpy-archs.S
···
50
50
51
51
;;; if size <= 8
52
52
cmp r2, 8
53
-
bls.d @smallchunk
53
+
bls.d @.Lsmallchunk
54
54
mov.f lp_count, r2
55
55
56
56
and.f r4, r0, 0x03
57
57
rsub lp_count, r4, 4
58
-
lpnz @aligndestination
58
+
lpnz @.Laligndestination
59
59
;; LOOP BEGIN
60
60
ldb.ab r5, [r1,1]
61
61
sub r2, r2, 1
62
62
stb.ab r5, [r3,1]
63
-
aligndestination:
63
+
.Laligndestination:
64
64
65
65
;;; Check the alignment of the source
66
66
and.f r4, r1, 0x03
67
-
bnz.d @sourceunaligned
67
+
bnz.d @.Lsourceunaligned
68
68
69
69
;;; CASE 0: Both source and destination are 32bit aligned
70
70
;;; Convert len to Dwords, unfold x4
71
71
lsr.f lp_count, r2, ZOLSHFT
72
-
lpnz @copy32_64bytes
72
+
lpnz @.Lcopy32_64bytes
73
73
;; LOOP START
74
74
LOADX (r6, r1)
75
75
PREFETCH_READ (r1)
···
81
81
STOREX (r8, r3)
82
82
STOREX (r10, r3)
83
83
STOREX (r4, r3)
84
-
copy32_64bytes:
84
+
.Lcopy32_64bytes:
85
85
86
86
and.f lp_count, r2, ZOLAND ;Last remaining 31 bytes
87
-
smallchunk:
88
-
lpnz @copyremainingbytes
87
+
.Lsmallchunk:
88
+
lpnz @.Lcopyremainingbytes
89
89
;; LOOP START
90
90
ldb.ab r5, [r1,1]
91
91
stb.ab r5, [r3,1]
92
-
copyremainingbytes:
92
+
.Lcopyremainingbytes:
93
93
94
94
j [blink]
95
95
;;; END CASE 0
96
96
97
-
sourceunaligned:
97
+
.Lsourceunaligned:
98
98
cmp r4, 2
99
-
beq.d @unalignedOffby2
99
+
beq.d @.LunalignedOffby2
100
100
sub r2, r2, 1
101
101
102
-
bhi.d @unalignedOffby3
102
+
bhi.d @.LunalignedOffby3
103
103
ldb.ab r5, [r1, 1]
104
104
105
105
;;; CASE 1: The source is unaligned, off by 1
···
114
114
or r5, r5, r6
115
115
116
116
;; Both src and dst are aligned
117
-
lpnz @copy8bytes_1
117
+
lpnz @.Lcopy8bytes_1
118
118
;; LOOP START
119
119
ld.ab r6, [r1, 4]
120
120
prefetch [r1, 28] ;Prefetch the next read location
···
131
131
132
132
st.ab r7, [r3, 4]
133
133
st.ab r9, [r3, 4]
134
-
copy8bytes_1:
134
+
.Lcopy8bytes_1:
135
135
136
136
;; Write back the remaining 16bits
137
137
EXTRACT_1 (r6, r5, 16)
···
141
141
stb.ab r5, [r3, 1]
142
142
143
143
and.f lp_count, r2, 0x07 ;Last 8bytes
144
-
lpnz @copybytewise_1
144
+
lpnz @.Lcopybytewise_1
145
145
;; LOOP START
146
146
ldb.ab r6, [r1,1]
147
147
stb.ab r6, [r3,1]
148
-
copybytewise_1:
148
+
.Lcopybytewise_1:
149
149
j [blink]
150
150
151
-
unalignedOffby2:
151
+
.LunalignedOffby2:
152
152
;;; CASE 2: The source is unaligned, off by 2
153
153
ldh.ab r5, [r1, 2]
154
154
sub r2, r2, 1
···
159
159
#ifdef __BIG_ENDIAN__
160
160
asl.nz r5, r5, 16
161
161
#endif
162
-
lpnz @copy8bytes_2
162
+
lpnz @.Lcopy8bytes_2
163
163
;; LOOP START
164
164
ld.ab r6, [r1, 4]
165
165
prefetch [r1, 28] ;Prefetch the next read location
···
176
176
177
177
st.ab r7, [r3, 4]
178
178
st.ab r9, [r3, 4]
179
-
copy8bytes_2:
179
+
.Lcopy8bytes_2:
180
180
181
181
#ifdef __BIG_ENDIAN__
182
182
lsr.nz r5, r5, 16
···
184
184
sth.ab r5, [r3, 2]
185
185
186
186
and.f lp_count, r2, 0x07 ;Last 8bytes
187
-
lpnz @copybytewise_2
187
+
lpnz @.Lcopybytewise_2
188
188
;; LOOP START
189
189
ldb.ab r6, [r1,1]
190
190
stb.ab r6, [r3,1]
191
-
copybytewise_2:
191
+
.Lcopybytewise_2:
192
192
j [blink]
193
193
194
-
unalignedOffby3:
194
+
.LunalignedOffby3:
195
195
;;; CASE 3: The source is unaligned, off by 3
196
196
;;; Hence, I need to read 1byte for achieve the 32bit alignment
197
197
···
201
201
#ifdef __BIG_ENDIAN__
202
202
asl.ne r5, r5, 24
203
203
#endif
204
-
lpnz @copy8bytes_3
204
+
lpnz @.Lcopy8bytes_3
205
205
;; LOOP START
206
206
ld.ab r6, [r1, 4]
207
207
prefetch [r1, 28] ;Prefetch the next read location
···
218
218
219
219
st.ab r7, [r3, 4]
220
220
st.ab r9, [r3, 4]
221
-
copy8bytes_3:
221
+
.Lcopy8bytes_3:
222
222
223
223
#ifdef __BIG_ENDIAN__
224
224
lsr.nz r5, r5, 24
···
226
226
stb.ab r5, [r3, 1]
227
227
228
228
and.f lp_count, r2, 0x07 ;Last 8bytes
229
-
lpnz @copybytewise_3
229
+
lpnz @.Lcopybytewise_3
230
230
;; LOOP START
231
231
ldb.ab r6, [r1,1]
232
232
stb.ab r6, [r3,1]
233
-
copybytewise_3:
233
+
.Lcopybytewise_3:
234
234
j [blink]
235
235
236
236
END(memcpy)
+3
-3
arch/arc/mm/tlbex.S
+3
-3
arch/arc/mm/tlbex.S
···
88
88
#ifdef CONFIG_SMP
89
89
sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
90
90
GET_CPU_ID r0 ; get to per cpu scratch mem,
91
-
lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
91
+
asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
92
92
add r0, @ex_saved_reg1, r0
93
93
#else
94
94
st r0, [@ex_saved_reg1]
···
107
107
.macro TLBMISS_RESTORE_REGS
108
108
#ifdef CONFIG_SMP
109
109
GET_CPU_ID r0 ; get to per cpu scratch mem
110
-
lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
110
+
asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
111
111
add r0, @ex_saved_reg1, r0
112
112
ld_s r3, [r0,12]
113
113
ld_s r2, [r0, 8]
···
256
256
257
257
.macro CONV_PTE_TO_TLB
258
258
and r3, r0, PTE_BITS_RWX ; r w x
259
-
lsl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
259
+
asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
260
260
and.f 0, r0, _PAGE_GLOBAL
261
261
or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
262
262