Merge tag 'drm-fixes-2022-02-18' of git://anongit.freedesktop.org/drm/drm

+8

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

··· 2057 2057 { 2058 2058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2059 2059 2060 + /* SMU saves SDMA state for us */ 2061 + if (adev->in_s0ix) 2062 + return 0; 2063 + 2060 2064 return sdma_v4_0_hw_fini(adev); 2061 2065 } 2062 2066 2063 2067 static int sdma_v4_0_resume(void *handle) 2064 2068 { 2065 2069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2070 + 2071 + /* SMU restores SDMA state for us */ 2072 + if (adev->in_s0ix) 2073 + return 0; 2066 2074 2067 2075 return sdma_v4_0_hw_init(adev); 2068 2076 }

+21 -5

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

··· 1238 1238 &dpm_context->dpm_tables.soc_table; 1239 1239 struct smu_umd_pstate_table *pstate_table = 1240 1240 &smu->pstate_table; 1241 + struct amdgpu_device *adev = smu->adev; 1241 1242 1242 1243 pstate_table->gfxclk_pstate.min = gfx_table->min; 1243 1244 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1244 - if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK) 1245 - pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1246 1245 1247 1246 pstate_table->uclk_pstate.min = mem_table->min; 1248 1247 pstate_table->uclk_pstate.peak = mem_table->max; 1249 - if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK) 1250 - pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1251 1248 1252 1249 pstate_table->socclk_pstate.min = soc_table->min; 1253 1250 pstate_table->socclk_pstate.peak = soc_table->max; 1254 - if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK) 1251 + 1252 + switch (adev->asic_type) { 1253 + case CHIP_SIENNA_CICHLID: 1254 + case CHIP_NAVY_FLOUNDER: 1255 + pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1256 + pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1255 1257 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1258 + break; 1259 + case CHIP_DIMGREY_CAVEFISH: 1260 + pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; 1261 + pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; 1262 + pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; 1263 + break; 1264 + case CHIP_BEIGE_GOBY: 1265 + pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; 1266 + pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; 1267 + pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; 1268 + break; 1269 + default: 1270 + break; 1271 + } 1256 1272 1257 1273 return 0; 1258 1274 }

+8

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h

··· 33 33 #define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK 960 34 34 #define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK 1000 35 35 36 + #define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950 37 + #define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK 960 38 + #define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK 676 39 + 40 + #define BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK 2200 41 + #define BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK 960 42 + #define BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK 1000 43 + 36 44 extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu); 37 45 38 46 #endif

+2 -7

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

··· 282 282 283 283 static int yellow_carp_mode_reset(struct smu_context *smu, int type) 284 284 { 285 - int ret = 0, index = 0; 285 + int ret = 0; 286 286 287 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 288 - SMU_MSG_GfxDeviceDriverReset); 289 - if (index < 0) 290 - return index == -EACCES ? 0 : index; 291 - 292 - ret = smu_cmn_send_smc_msg_with_param(smu, (uint16_t)index, type, NULL); 287 + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL); 293 288 if (ret) 294 289 dev_err(smu->adev->dev, "Failed to mode reset!\n"); 295 290

+8 -6

drivers/gpu/drm/drm_atomic_uapi.c

··· 76 76 state->mode_blob = NULL; 77 77 78 78 if (mode) { 79 + struct drm_property_blob *blob; 80 + 79 81 drm_mode_convert_to_umode(&umode, mode); 80 - state->mode_blob = 81 - drm_property_create_blob(state->crtc->dev, 82 - sizeof(umode), 83 - &umode); 84 - if (IS_ERR(state->mode_blob)) 85 - return PTR_ERR(state->mode_blob); 82 + blob = drm_property_create_blob(crtc->dev, 83 + sizeof(umode), &umode); 84 + if (IS_ERR(blob)) 85 + return PTR_ERR(blob); 86 86 87 87 drm_mode_copy(&state->mode, mode); 88 + 89 + state->mode_blob = blob; 88 90 state->enable = true; 89 91 drm_dbg_atomic(crtc->dev, 90 92 "Set [MODE:%s] for [CRTC:%d:%s] state %p\n",

+1

drivers/gpu/drm/drm_gem_cma_helper.c

··· 512 512 */ 513 513 vma->vm_pgoff -= drm_vma_node_start(&obj->vma_node); 514 514 vma->vm_flags &= ~VM_PFNMAP; 515 + vma->vm_flags |= VM_DONTEXPAND; 515 516 516 517 if (cma_obj->map_noncoherent) { 517 518 vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);

+1

drivers/gpu/drm/i915/Kconfig

··· 101 101 config DRM_I915_GVT 102 102 bool "Enable Intel GVT-g graphics virtualization host support" 103 103 depends on DRM_I915 104 + depends on X86 104 105 depends on 64BIT 105 106 default n 106 107 help

+2 -1

drivers/gpu/drm/i915/display/intel_fbc.c

··· 1115 1115 1116 1116 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ 1117 1117 if (DISPLAY_VER(i915) >= 11 && 1118 - (plane_state->view.color_plane[0].y + drm_rect_height(&plane_state->uapi.src)) & 3) { 1118 + (plane_state->view.color_plane[0].y + 1119 + (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { 1119 1120 plane_state->no_fbc_reason = "plane end Y offset misaligned"; 1120 1121 return false; 1121 1122 }

+15

drivers/gpu/drm/i915/display/intel_opregion.c

··· 360 360 port++; 361 361 } 362 362 363 + /* 364 + * The port numbering and mapping here is bizarre. The now-obsolete 365 + * swsci spec supports ports numbered [0..4]. Port E is handled as a 366 + * special case, but port F and beyond are not. The functionality is 367 + * supposed to be obsolete for new platforms. Just bail out if the port 368 + * number is out of bounds after mapping. 369 + */ 370 + if (port > 4) { 371 + drm_dbg_kms(&dev_priv->drm, 372 + "[ENCODER:%d:%s] port %c (index %u) out of bounds for display power state notification\n", 373 + intel_encoder->base.base.id, intel_encoder->base.name, 374 + port_name(intel_encoder->port), port); 375 + return -EINVAL; 376 + } 377 + 363 378 if (!enable) 364 379 parm |= 4 << 8; 365 380

+2 -4

drivers/gpu/drm/i915/gem/i915_gem_ttm.c

··· 842 842 } else if (obj->mm.madv != I915_MADV_WILLNEED) { 843 843 bo->priority = I915_TTM_PRIO_PURGE; 844 844 } else if (!i915_gem_object_has_pages(obj)) { 845 - if (bo->priority < I915_TTM_PRIO_HAS_PAGES) 846 - bo->priority = I915_TTM_PRIO_HAS_PAGES; 845 + bo->priority = I915_TTM_PRIO_NO_PAGES; 847 846 } else { 848 - if (bo->priority > I915_TTM_PRIO_NO_PAGES) 849 - bo->priority = I915_TTM_PRIO_NO_PAGES; 847 + bo->priority = I915_TTM_PRIO_HAS_PAGES; 850 848 } 851 849 852 850 ttm_bo_move_to_lru_tail(bo, bo->resource, NULL);

+2 -2

drivers/gpu/drm/i915/gvt/gtt.c

··· 1148 1148 ops->set_pfn(se, s->shadow_page.mfn); 1149 1149 } 1150 1150 1151 - /** 1151 + /* 1152 1152 * Check if can do 2M page 1153 1153 * @vgpu: target vgpu 1154 1154 * @entry: target pfn's gtt entry ··· 2193 2193 } 2194 2194 2195 2195 /** 2196 - * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read 2196 + * intel_vgpu_emulate_ggtt_mmio_read - emulate GTT MMIO register read 2197 2197 * @vgpu: a vGPU 2198 2198 * @off: register offset 2199 2199 * @p_data: data will be returned to guest

+2 -2

drivers/gpu/drm/i915/intel_pm.c

··· 4853 4853 { 4854 4854 int i; 4855 4855 4856 - for (i = 0; i < dbuf_slices[i].active_pipes; i++) { 4856 + for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 4857 4857 if (dbuf_slices[i].active_pipes == active_pipes) 4858 4858 return dbuf_slices[i].join_mbus; 4859 4859 } ··· 4870 4870 { 4871 4871 int i; 4872 4872 4873 - for (i = 0; i < dbuf_slices[i].active_pipes; i++) { 4873 + for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 4874 4874 if (dbuf_slices[i].active_pipes == active_pipes && 4875 4875 dbuf_slices[i].join_mbus == join_mbus) 4876 4876 return dbuf_slices[i].dbuf_mask[pipe];

+84 -83

drivers/gpu/drm/mediatek/mtk_dsi.c

··· 786 786 mtk_dsi_poweroff(dsi); 787 787 } 788 788 789 + static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) 790 + { 791 + int ret; 792 + 793 + ret = drm_simple_encoder_init(drm, &dsi->encoder, 794 + DRM_MODE_ENCODER_DSI); 795 + if (ret) { 796 + DRM_ERROR("Failed to encoder init to drm\n"); 797 + return ret; 798 + } 799 + 800 + dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev); 801 + 802 + ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 803 + DRM_BRIDGE_ATTACH_NO_CONNECTOR); 804 + if (ret) 805 + goto err_cleanup_encoder; 806 + 807 + dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); 808 + if (IS_ERR(dsi->connector)) { 809 + DRM_ERROR("Unable to create bridge connector\n"); 810 + ret = PTR_ERR(dsi->connector); 811 + goto err_cleanup_encoder; 812 + } 813 + drm_connector_attach_encoder(dsi->connector, &dsi->encoder); 814 + 815 + return 0; 816 + 817 + err_cleanup_encoder: 818 + drm_encoder_cleanup(&dsi->encoder); 819 + return ret; 820 + } 821 + 822 + static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 823 + { 824 + int ret; 825 + struct drm_device *drm = data; 826 + struct mtk_dsi *dsi = dev_get_drvdata(dev); 827 + 828 + ret = mtk_dsi_encoder_init(drm, dsi); 829 + if (ret) 830 + return ret; 831 + 832 + return device_reset_optional(dev); 833 + } 834 + 835 + static void mtk_dsi_unbind(struct device *dev, struct device *master, 836 + void *data) 837 + { 838 + struct mtk_dsi *dsi = dev_get_drvdata(dev); 839 + 840 + drm_encoder_cleanup(&dsi->encoder); 841 + } 842 + 843 + static const struct component_ops mtk_dsi_component_ops = { 844 + .bind = mtk_dsi_bind, 845 + .unbind = mtk_dsi_unbind, 846 + }; 847 + 789 848 static int mtk_dsi_host_attach(struct mipi_dsi_host *host, 790 849 struct mipi_dsi_device *device) 791 850 { 792 851 struct mtk_dsi *dsi = host_to_dsi(host); 852 + struct device *dev = host->dev; 853 + int ret; 793 854 794 855 dsi->lanes = device->lanes; 795 856 dsi->format = device->format; 796 857 dsi->mode_flags = device->mode_flags; 858 + dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0); 859 + if (IS_ERR(dsi->next_bridge)) 860 + return PTR_ERR(dsi->next_bridge); 797 861 862 + drm_bridge_add(&dsi->bridge); 863 + 864 + ret = component_add(host->dev, &mtk_dsi_component_ops); 865 + if (ret) { 866 + DRM_ERROR("failed to add dsi_host component: %d\n", ret); 867 + drm_bridge_remove(&dsi->bridge); 868 + return ret; 869 + } 870 + 871 + return 0; 872 + } 873 + 874 + static int mtk_dsi_host_detach(struct mipi_dsi_host *host, 875 + struct mipi_dsi_device *device) 876 + { 877 + struct mtk_dsi *dsi = host_to_dsi(host); 878 + 879 + component_del(host->dev, &mtk_dsi_component_ops); 880 + drm_bridge_remove(&dsi->bridge); 798 881 return 0; 799 882 } 800 883 ··· 1021 938 1022 939 static const struct mipi_dsi_host_ops mtk_dsi_ops = { 1023 940 .attach = mtk_dsi_host_attach, 941 + .detach = mtk_dsi_host_detach, 1024 942 .transfer = mtk_dsi_host_transfer, 1025 - }; 1026 - 1027 - static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) 1028 - { 1029 - int ret; 1030 - 1031 - ret = drm_simple_encoder_init(drm, &dsi->encoder, 1032 - DRM_MODE_ENCODER_DSI); 1033 - if (ret) { 1034 - DRM_ERROR("Failed to encoder init to drm\n"); 1035 - return ret; 1036 - } 1037 - 1038 - dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev); 1039 - 1040 - ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 1041 - DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1042 - if (ret) 1043 - goto err_cleanup_encoder; 1044 - 1045 - dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); 1046 - if (IS_ERR(dsi->connector)) { 1047 - DRM_ERROR("Unable to create bridge connector\n"); 1048 - ret = PTR_ERR(dsi->connector); 1049 - goto err_cleanup_encoder; 1050 - } 1051 - drm_connector_attach_encoder(dsi->connector, &dsi->encoder); 1052 - 1053 - return 0; 1054 - 1055 - err_cleanup_encoder: 1056 - drm_encoder_cleanup(&dsi->encoder); 1057 - return ret; 1058 - } 1059 - 1060 - static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 1061 - { 1062 - int ret; 1063 - struct drm_device *drm = data; 1064 - struct mtk_dsi *dsi = dev_get_drvdata(dev); 1065 - 1066 - ret = mtk_dsi_encoder_init(drm, dsi); 1067 - if (ret) 1068 - return ret; 1069 - 1070 - return device_reset_optional(dev); 1071 - } 1072 - 1073 - static void mtk_dsi_unbind(struct device *dev, struct device *master, 1074 - void *data) 1075 - { 1076 - struct mtk_dsi *dsi = dev_get_drvdata(dev); 1077 - 1078 - drm_encoder_cleanup(&dsi->encoder); 1079 - } 1080 - 1081 - static const struct component_ops mtk_dsi_component_ops = { 1082 - .bind = mtk_dsi_bind, 1083 - .unbind = mtk_dsi_unbind, 1084 943 }; 1085 944 1086 945 static int mtk_dsi_probe(struct platform_device *pdev) 1087 946 { 1088 947 struct mtk_dsi *dsi; 1089 948 struct device *dev = &pdev->dev; 1090 - struct drm_panel *panel; 1091 949 struct resource *regs; 1092 950 int irq_num; 1093 951 int ret; ··· 1043 1019 if (ret < 0) { 1044 1020 dev_err(dev, "failed to register DSI host: %d\n", ret); 1045 1021 return ret; 1046 - } 1047 - 1048 - ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 1049 - &panel, &dsi->next_bridge); 1050 - if (ret) 1051 - goto err_unregister_host; 1052 - 1053 - if (panel) { 1054 - dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel); 1055 - if (IS_ERR(dsi->next_bridge)) { 1056 - ret = PTR_ERR(dsi->next_bridge); 1057 - goto err_unregister_host; 1058 - } 1059 1022 } 1060 1023 1061 1024 dsi->driver_data = of_device_get_match_data(dev); ··· 1109 1098 dsi->bridge.of_node = dev->of_node; 1110 1099 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1111 1100 1112 - drm_bridge_add(&dsi->bridge); 1113 - 1114 - ret = component_add(&pdev->dev, &mtk_dsi_component_ops); 1115 - if (ret) { 1116 - dev_err(&pdev->dev, "failed to add component: %d\n", ret); 1117 - goto err_unregister_host; 1118 - } 1119 - 1120 1101 return 0; 1121 1102 1122 1103 err_unregister_host: ··· 1121 1118 struct mtk_dsi *dsi = platform_get_drvdata(pdev); 1122 1119 1123 1120 mtk_output_dsi_disable(dsi); 1124 - drm_bridge_remove(&dsi->bridge); 1125 - component_del(&pdev->dev, &mtk_dsi_component_ops); 1126 1121 mipi_dsi_host_unregister(&dsi->host); 1127 1122 1128 1123 return 0;

+2 -1

drivers/gpu/drm/radeon/atombios_encoders.c

··· 198 198 * so don't register a backlight device 199 199 */ 200 200 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 201 - (rdev->pdev->device == 0x6741)) 201 + (rdev->pdev->device == 0x6741) && 202 + !dmi_match(DMI_PRODUCT_NAME, "iMac12,1")) 202 203 return; 203 204 204 205 if (!radeon_encoder->enc_priv)

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