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Merge branch 'bpf-arm64-riscv-remove-redundant-icache-flush-after-pack-allocator-finalize'

Puranjay Mohan says:

====================
bpf, arm64/riscv: Remove redundant icache flush after pack allocator finalize

Changelog:
v1: https://lore.kernel.org/all/20260413123256.3296452-1-puranjay@kernel.org/
Changes in v2:
- Remove "#include <asm/cacheflush.h>" as it is not needed now.
- Add Acked-by: Song Liu <song@kernel.org>

When the BPF prog pack allocator was added for arm64 and riscv, the
existing bpf_flush_icache() calls were retained after
bpf_jit_binary_pack_finalize(). However, the finalize path copies the
JITed code via architecture text patching routines (__text_poke on arm64,
patch_text_nosync on riscv) that already perform a full
flush_icache_range() internally. The subsequent bpf_flush_icache()
repeats the same cache maintenance on the same range.

Remove the redundant flush and the now-unused bpf_flush_icache()
definitions on both architectures.
====================

Link: https://patch.msgid.link/20260413191111.3426023-1-puranjay@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>

Alexei Starovoitov b3dde701 4fddde2a

-25
-12
arch/arm64/net/bpf_jit_comp.c
··· 18 18 19 19 #include <asm/asm-extable.h> 20 20 #include <asm/byteorder.h> 21 - #include <asm/cacheflush.h> 22 21 #include <asm/cpufeature.h> 23 22 #include <asm/debug-monitors.h> 24 23 #include <asm/insn.h> ··· 1960 1961 return 0; 1961 1962 } 1962 1963 1963 - static inline void bpf_flush_icache(void *start, void *end) 1964 - { 1965 - flush_icache_range((unsigned long)start, (unsigned long)end); 1966 - } 1967 - 1968 1964 static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 1969 1965 { 1970 1966 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; ··· 2198 2204 prog = orig_prog; 2199 2205 goto out_off; 2200 2206 } 2201 - /* 2202 - * The instructions have now been copied to the ROX region from 2203 - * where they will execute. Now the data cache has to be cleaned to 2204 - * the PoU and the I-cache has to be invalidated for the VAs. 2205 - */ 2206 - bpf_flush_icache(ro_header, ctx.ro_image + ctx.idx); 2207 2207 } else { 2208 2208 jit_data->ctx = ctx; 2209 2209 jit_data->ro_image = ro_image_ptr;
-6
arch/riscv/net/bpf_jit.h
··· 11 11 12 12 #include <linux/bpf.h> 13 13 #include <linux/filter.h> 14 - #include <asm/cacheflush.h> 15 14 16 15 /* verify runtime detection extension status */ 17 16 #define rv_ext_enabled(ext) \ ··· 102 103 static inline void bpf_fill_ill_insns(void *area, unsigned int size) 103 104 { 104 105 memset(area, 0, size); 105 - } 106 - 107 - static inline void bpf_flush_icache(void *start, void *end) 108 - { 109 - flush_icache_range((unsigned long)start, (unsigned long)end); 110 106 } 111 107 112 108 /* Emit a 4-byte riscv instruction. */
-7
arch/riscv/net/bpf_jit_core.c
··· 183 183 prog = orig_prog; 184 184 goto out_offset; 185 185 } 186 - /* 187 - * The instructions have now been copied to the ROX region from 188 - * where they will execute. 189 - * Write any modified data cache blocks out to memory and 190 - * invalidate the corresponding blocks in the instruction cache. 191 - */ 192 - bpf_flush_icache(jit_data->ro_header, ctx->ro_insns + ctx->ninsns); 193 186 for (i = 0; i < prog->len; i++) 194 187 ctx->offset[i] = ninsns_rvoff(ctx->offset[i]); 195 188 bpf_prog_fill_jited_linfo(prog, ctx->offset);