tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"This is radeon and intel fixes, and is a small bit larger than I'm
guessing you'd like it to be.

- i915: fixes 32-bit highmem i915 blank screen, semaphore hang and
runtime pm fix

- radeon: gpuvm stability fix for hangs since 3.15, and hang/reboot
regression on TN/RL devices,

The only slightly controversial one is the change to use GB for the
vm_size, which I'm letting through as its a new interface we defined
in this merge window, and I'd prefer to have the released kernel have
the final interface rather than changing it later"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon: fix cut and paste issue for hawaii.
drm/radeon: fix irq ring buffer overflow handling
drm/i915: Simplify i915_gem_release_all_mmaps()
drm/radeon: fix error handling in radeon_vm_bo_set_addr
drm/i915: fix freeze with blank screen booting highmem
drm/i915: Reorder the semaphore deadlock check, again
drm/radeon/TN: only enable bapm on MSI systems
drm/radeon: fix VM IB handling
drm/radeon: fix handling of radeon_vm_bo_rmv v3
drm/radeon: let's use GB for vm_size (v2)

Linus Torvalds b401796c 9c550218

+147 -89
+9 -16
drivers/gpu/drm/i915/i915_gem.c
··· 1616 1616 return ret; 1617 1617 } 1618 1618 1619 - void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) 1620 - { 1621 - struct i915_vma *vma; 1622 - 1623 - /* 1624 - * Only the global gtt is relevant for gtt memory mappings, so restrict 1625 - * list traversal to objects bound into the global address space. Note 1626 - * that the active list should be empty, but better safe than sorry. 1627 - */ 1628 - WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); 1629 - list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) 1630 - i915_gem_release_mmap(vma->obj); 1631 - list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) 1632 - i915_gem_release_mmap(vma->obj); 1633 - } 1634 - 1635 1619 /** 1636 1620 * i915_gem_release_mmap - remove physical page mappings 1637 1621 * @obj: obj in question ··· 1639 1655 drm_vma_node_unmap(&obj->base.vma_node, 1640 1656 obj->base.dev->anon_inode->i_mapping); 1641 1657 obj->fault_mappable = false; 1658 + } 1659 + 1660 + void 1661 + i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) 1662 + { 1663 + struct drm_i915_gem_object *obj; 1664 + 1665 + list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 1666 + i915_gem_release_mmap(obj); 1642 1667 } 1643 1668 1644 1669 uint32_t
+2 -2
drivers/gpu/drm/i915/i915_gem_render_state.c
··· 31 31 struct i915_render_state { 32 32 struct drm_i915_gem_object *obj; 33 33 unsigned long ggtt_offset; 34 - void *batch; 34 + u32 *batch; 35 35 u32 size; 36 36 u32 len; 37 37 }; ··· 80 80 81 81 static void render_state_free(struct i915_render_state *so) 82 82 { 83 - kunmap(so->batch); 83 + kunmap(kmap_to_page(so->batch)); 84 84 i915_gem_object_ggtt_unpin(so->obj); 85 85 drm_gem_object_unreference(&so->obj->base); 86 86 kfree(so);
+4 -7
drivers/gpu/drm/i915/i915_irq.c
··· 2845 2845 { 2846 2846 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2847 2847 struct intel_engine_cs *signaller; 2848 - u32 seqno, ctl; 2848 + u32 seqno; 2849 2849 2850 2850 ring->hangcheck.deadlock++; 2851 2851 ··· 2857 2857 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) 2858 2858 return -1; 2859 2859 2860 - /* cursory check for an unkickable deadlock */ 2861 - ctl = I915_READ_CTL(signaller); 2862 - if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) 2863 - return -1; 2864 - 2865 2860 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) 2866 2861 return 1; 2867 2862 2868 - if (signaller->hangcheck.deadlock) 2863 + /* cursory check for an unkickable deadlock */ 2864 + if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && 2865 + semaphore_passed(signaller) < 0) 2869 2866 return -1; 2870 2867 2871 2868 return 0;
+2
drivers/gpu/drm/radeon/cik.c
··· 2291 2291 gb_tile_moden = 0; 2292 2292 break; 2293 2293 } 2294 + rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; 2294 2295 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); 2295 2296 } 2296 2297 } else if (num_pipe_configs == 8) { ··· 7377 7376 tmp = RREG32(IH_RB_CNTL); 7378 7377 tmp |= IH_WPTR_OVERFLOW_CLEAR; 7379 7378 WREG32(IH_RB_CNTL, tmp); 7379 + wptr &= ~RB_OVERFLOW; 7380 7380 } 7381 7381 return (wptr & rdev->ih.ptr_mask); 7382 7382 }
+1
drivers/gpu/drm/radeon/evergreen.c
··· 4756 4756 tmp = RREG32(IH_RB_CNTL); 4757 4757 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4758 4758 WREG32(IH_RB_CNTL, tmp); 4759 + wptr &= ~RB_OVERFLOW; 4759 4760 } 4760 4761 return (wptr & rdev->ih.ptr_mask); 4761 4762 }
+1
drivers/gpu/drm/radeon/r600.c
··· 3795 3795 tmp = RREG32(IH_RB_CNTL); 3796 3796 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3797 3797 WREG32(IH_RB_CNTL, tmp); 3798 + wptr &= ~RB_OVERFLOW; 3798 3799 } 3799 3800 return (wptr & rdev->ih.ptr_mask); 3800 3801 }
+11 -4
drivers/gpu/drm/radeon/radeon.h
··· 449 449 450 450 /* protected by vm mutex */ 451 451 struct list_head vm_list; 452 + struct list_head vm_status; 452 453 453 454 /* constant after initialization */ 454 455 struct radeon_vm *vm; ··· 868 867 struct list_head va; 869 868 unsigned id; 870 869 870 + /* BOs freed, but not yet updated in the PT */ 871 + struct list_head freed; 872 + 871 873 /* contains the page directory */ 872 874 struct radeon_bo *page_directory; 873 875 uint64_t pd_gpu_addr; ··· 878 874 879 875 /* array of page tables, one for each page directory entry */ 880 876 struct radeon_vm_pt *page_tables; 877 + 878 + struct radeon_bo_va *ib_bo_va; 881 879 882 880 struct mutex mutex; 883 881 /* last fence for cs using this vm */ ··· 2838 2832 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2839 2833 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2840 2834 struct radeon_vm *vm); 2835 + int radeon_vm_clear_freed(struct radeon_device *rdev, 2836 + struct radeon_vm *vm); 2841 2837 int radeon_vm_bo_update(struct radeon_device *rdev, 2842 - struct radeon_vm *vm, 2843 - struct radeon_bo *bo, 2838 + struct radeon_bo_va *bo_va, 2844 2839 struct ttm_mem_reg *mem); 2845 2840 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2846 2841 struct radeon_bo *bo); ··· 2854 2847 struct radeon_bo_va *bo_va, 2855 2848 uint64_t offset, 2856 2849 uint32_t flags); 2857 - int radeon_vm_bo_rmv(struct radeon_device *rdev, 2858 - struct radeon_bo_va *bo_va); 2850 + void radeon_vm_bo_rmv(struct radeon_device *rdev, 2851 + struct radeon_bo_va *bo_va); 2859 2852 2860 2853 /* audio */ 2861 2854 void r600_audio_update_hdmi(struct work_struct *work);
+18 -2
drivers/gpu/drm/radeon/radeon_cs.c
··· 461 461 struct radeon_vm *vm) 462 462 { 463 463 struct radeon_device *rdev = p->rdev; 464 + struct radeon_bo_va *bo_va; 464 465 int i, r; 465 466 466 467 r = radeon_vm_update_page_directory(rdev, vm); 467 468 if (r) 468 469 return r; 469 470 470 - r = radeon_vm_bo_update(rdev, vm, rdev->ring_tmp_bo.bo, 471 + r = radeon_vm_clear_freed(rdev, vm); 472 + if (r) 473 + return r; 474 + 475 + if (vm->ib_bo_va == NULL) { 476 + DRM_ERROR("Tmp BO not in VM!\n"); 477 + return -EINVAL; 478 + } 479 + 480 + r = radeon_vm_bo_update(rdev, vm->ib_bo_va, 471 481 &rdev->ring_tmp_bo.bo->tbo.mem); 472 482 if (r) 473 483 return r; ··· 490 480 continue; 491 481 492 482 bo = p->relocs[i].robj; 493 - r = radeon_vm_bo_update(rdev, vm, bo, &bo->tbo.mem); 483 + bo_va = radeon_vm_bo_find(vm, bo); 484 + if (bo_va == NULL) { 485 + dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); 486 + return -EINVAL; 487 + } 488 + 489 + r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem); 494 490 if (r) 495 491 return r; 496 492 }
+11 -11
drivers/gpu/drm/radeon/radeon_device.c
··· 1056 1056 if (!radeon_check_pot_argument(radeon_vm_size)) { 1057 1057 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1058 1058 radeon_vm_size); 1059 - radeon_vm_size = 4096; 1059 + radeon_vm_size = 4; 1060 1060 } 1061 1061 1062 - if (radeon_vm_size < 4) { 1063 - dev_warn(rdev->dev, "VM size (%d) to small, min is 4MB\n", 1062 + if (radeon_vm_size < 1) { 1063 + dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", 1064 1064 radeon_vm_size); 1065 - radeon_vm_size = 4096; 1065 + radeon_vm_size = 4; 1066 1066 } 1067 1067 1068 1068 /* 1069 1069 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1070 1070 */ 1071 - if (radeon_vm_size > 1024*1024) { 1072 - dev_warn(rdev->dev, "VM size (%d) to large, max is 1TB\n", 1071 + if (radeon_vm_size > 1024) { 1072 + dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1073 1073 radeon_vm_size); 1074 - radeon_vm_size = 4096; 1074 + radeon_vm_size = 4; 1075 1075 } 1076 1076 1077 1077 /* defines number of bits in page table versus page directory, 1078 1078 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1079 1079 * page table and the remaining bits are in the page directory */ 1080 1080 if (radeon_vm_block_size < 9) { 1081 - dev_warn(rdev->dev, "VM page table size (%d) to small\n", 1081 + dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1082 1082 radeon_vm_block_size); 1083 1083 radeon_vm_block_size = 9; 1084 1084 } 1085 1085 1086 1086 if (radeon_vm_block_size > 24 || 1087 - radeon_vm_size < (1ull << radeon_vm_block_size)) { 1088 - dev_warn(rdev->dev, "VM page table size (%d) to large\n", 1087 + (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1088 + dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1089 1089 radeon_vm_block_size); 1090 1090 radeon_vm_block_size = 9; 1091 1091 } ··· 1238 1238 /* Adjust VM size here. 1239 1239 * Max GPUVM size for cayman+ is 40 bits. 1240 1240 */ 1241 - rdev->vm_manager.max_pfn = radeon_vm_size << 8; 1241 + rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1242 1242 1243 1243 /* Set asic functions */ 1244 1244 r = radeon_asic_init(rdev);
+2 -2
drivers/gpu/drm/radeon/radeon_drv.c
··· 173 173 int radeon_aspm = -1; 174 174 int radeon_runtime_pm = -1; 175 175 int radeon_hard_reset = 0; 176 - int radeon_vm_size = 4096; 176 + int radeon_vm_size = 4; 177 177 int radeon_vm_block_size = 9; 178 178 int radeon_deep_color = 0; 179 179 ··· 243 243 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 244 244 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 245 245 246 - MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)"); 246 + MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 247 247 module_param_named(vm_size, radeon_vm_size, int, 0444); 248 248 249 249 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
+13 -13
drivers/gpu/drm/radeon/radeon_kms.c
··· 579 579 /* new gpu have virtual address space support */ 580 580 if (rdev->family >= CHIP_CAYMAN) { 581 581 struct radeon_fpriv *fpriv; 582 - struct radeon_bo_va *bo_va; 582 + struct radeon_vm *vm; 583 583 int r; 584 584 585 585 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); ··· 587 587 return -ENOMEM; 588 588 } 589 589 590 - r = radeon_vm_init(rdev, &fpriv->vm); 590 + vm = &fpriv->vm; 591 + r = radeon_vm_init(rdev, vm); 591 592 if (r) { 592 593 kfree(fpriv); 593 594 return r; ··· 597 596 if (rdev->accel_working) { 598 597 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 599 598 if (r) { 600 - radeon_vm_fini(rdev, &fpriv->vm); 599 + radeon_vm_fini(rdev, vm); 601 600 kfree(fpriv); 602 601 return r; 603 602 } 604 603 605 604 /* map the ib pool buffer read only into 606 605 * virtual address space */ 607 - bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 608 - rdev->ring_tmp_bo.bo); 609 - r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 606 + vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 607 + rdev->ring_tmp_bo.bo); 608 + r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 609 + RADEON_VA_IB_OFFSET, 610 610 RADEON_VM_PAGE_READABLE | 611 611 RADEON_VM_PAGE_SNOOPED); 612 612 613 613 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 614 614 if (r) { 615 - radeon_vm_fini(rdev, &fpriv->vm); 615 + radeon_vm_fini(rdev, vm); 616 616 kfree(fpriv); 617 617 return r; 618 618 } ··· 642 640 /* new gpu have virtual address space support */ 643 641 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 644 642 struct radeon_fpriv *fpriv = file_priv->driver_priv; 645 - struct radeon_bo_va *bo_va; 643 + struct radeon_vm *vm = &fpriv->vm; 646 644 int r; 647 645 648 646 if (rdev->accel_working) { 649 647 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 650 648 if (!r) { 651 - bo_va = radeon_vm_bo_find(&fpriv->vm, 652 - rdev->ring_tmp_bo.bo); 653 - if (bo_va) 654 - radeon_vm_bo_rmv(rdev, bo_va); 649 + if (vm->ib_bo_va) 650 + radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 655 651 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 656 652 } 657 653 } 658 654 659 - radeon_vm_fini(rdev, &fpriv->vm); 655 + radeon_vm_fini(rdev, vm); 660 656 kfree(fpriv); 661 657 file_priv->driver_priv = NULL; 662 658 }
+64 -25
drivers/gpu/drm/radeon/radeon_vm.c
··· 332 332 bo_va->ref_count = 1; 333 333 INIT_LIST_HEAD(&bo_va->bo_list); 334 334 INIT_LIST_HEAD(&bo_va->vm_list); 335 + INIT_LIST_HEAD(&bo_va->vm_status); 335 336 336 337 mutex_lock(&vm->mutex); 337 338 list_add(&bo_va->vm_list, &vm->va); ··· 467 466 } 468 467 last_offset = tmp->eoffset; 469 468 head = &tmp->vm_list; 469 + } 470 + 471 + if (bo_va->soffset) { 472 + /* add a clone of the bo_va to clear the old address */ 473 + tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); 474 + if (!tmp) { 475 + mutex_unlock(&vm->mutex); 476 + return -ENOMEM; 477 + } 478 + tmp->soffset = bo_va->soffset; 479 + tmp->eoffset = bo_va->eoffset; 480 + tmp->vm = vm; 481 + list_add(&tmp->vm_status, &vm->freed); 470 482 } 471 483 472 484 bo_va->soffset = soffset; ··· 837 823 * Object have to be reserved and mutex must be locked! 838 824 */ 839 825 int radeon_vm_bo_update(struct radeon_device *rdev, 840 - struct radeon_vm *vm, 841 - struct radeon_bo *bo, 826 + struct radeon_bo_va *bo_va, 842 827 struct ttm_mem_reg *mem) 843 828 { 829 + struct radeon_vm *vm = bo_va->vm; 844 830 struct radeon_ib ib; 845 - struct radeon_bo_va *bo_va; 846 831 unsigned nptes, ndw; 847 832 uint64_t addr; 848 833 int r; 849 834 850 - bo_va = radeon_vm_bo_find(vm, bo); 851 - if (bo_va == NULL) { 852 - dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); 853 - return -EINVAL; 854 - } 855 835 856 836 if (!bo_va->soffset) { 857 837 dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n", 858 - bo, vm); 838 + bo_va->bo, vm); 859 839 return -EINVAL; 860 840 } 861 841 ··· 876 868 877 869 trace_radeon_vm_bo_update(bo_va); 878 870 879 - nptes = radeon_bo_ngpu_pages(bo); 871 + nptes = (bo_va->eoffset - bo_va->soffset) / RADEON_GPU_PAGE_SIZE; 880 872 881 873 /* padding, etc. */ 882 874 ndw = 64; ··· 919 911 } 920 912 921 913 /** 914 + * radeon_vm_clear_freed - clear freed BOs in the PT 915 + * 916 + * @rdev: radeon_device pointer 917 + * @vm: requested vm 918 + * 919 + * Make sure all freed BOs are cleared in the PT. 920 + * Returns 0 for success. 921 + * 922 + * PTs have to be reserved and mutex must be locked! 923 + */ 924 + int radeon_vm_clear_freed(struct radeon_device *rdev, 925 + struct radeon_vm *vm) 926 + { 927 + struct radeon_bo_va *bo_va, *tmp; 928 + int r; 929 + 930 + list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) { 931 + list_del(&bo_va->vm_status); 932 + r = radeon_vm_bo_update(rdev, bo_va, NULL); 933 + kfree(bo_va); 934 + if (r) 935 + return r; 936 + } 937 + return 0; 938 + 939 + } 940 + 941 + /** 922 942 * radeon_vm_bo_rmv - remove a bo to a specific vm 923 943 * 924 944 * @rdev: radeon_device pointer 925 945 * @bo_va: requested bo_va 926 946 * 927 947 * Remove @bo_va->bo from the requested vm (cayman+). 928 - * Remove @bo_va->bo from the list of bos associated with the bo_va->vm and 929 - * remove the ptes for @bo_va in the page table. 930 - * Returns 0 for success. 931 948 * 932 949 * Object have to be reserved! 933 950 */ 934 - int radeon_vm_bo_rmv(struct radeon_device *rdev, 935 - struct radeon_bo_va *bo_va) 951 + void radeon_vm_bo_rmv(struct radeon_device *rdev, 952 + struct radeon_bo_va *bo_va) 936 953 { 937 - int r = 0; 954 + struct radeon_vm *vm = bo_va->vm; 938 955 939 - mutex_lock(&bo_va->vm->mutex); 940 - if (bo_va->soffset) 941 - r = radeon_vm_bo_update(rdev, bo_va->vm, bo_va->bo, NULL); 942 - 943 - list_del(&bo_va->vm_list); 944 - mutex_unlock(&bo_va->vm->mutex); 945 956 list_del(&bo_va->bo_list); 946 957 947 - kfree(bo_va); 948 - return r; 958 + mutex_lock(&vm->mutex); 959 + list_del(&bo_va->vm_list); 960 + 961 + if (bo_va->soffset) { 962 + bo_va->bo = NULL; 963 + list_add(&bo_va->vm_status, &vm->freed); 964 + } else { 965 + kfree(bo_va); 966 + } 967 + 968 + mutex_unlock(&vm->mutex); 949 969 } 950 970 951 971 /** ··· 1011 975 int r; 1012 976 1013 977 vm->id = 0; 978 + vm->ib_bo_va = NULL; 1014 979 vm->fence = NULL; 1015 980 vm->last_flush = NULL; 1016 981 vm->last_id_use = NULL; 1017 982 mutex_init(&vm->mutex); 1018 983 INIT_LIST_HEAD(&vm->va); 984 + INIT_LIST_HEAD(&vm->freed); 1019 985 1020 986 pd_size = radeon_vm_directory_size(rdev); 1021 987 pd_entries = radeon_vm_num_pdes(rdev); ··· 1072 1034 kfree(bo_va); 1073 1035 } 1074 1036 } 1075 - 1037 + list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) 1038 + kfree(bo_va); 1076 1039 1077 1040 for (i = 0; i < radeon_vm_num_pdes(rdev); i++) 1078 1041 radeon_bo_unref(&vm->page_tables[i].bo);
+1
drivers/gpu/drm/radeon/si.c
··· 6103 6103 tmp = RREG32(IH_RB_CNTL); 6104 6104 tmp |= IH_WPTR_OVERFLOW_CLEAR; 6105 6105 WREG32(IH_RB_CNTL, tmp); 6106 + wptr &= ~RB_OVERFLOW; 6106 6107 } 6107 6108 return (wptr & rdev->ih.ptr_mask); 6108 6109 }
+8 -7
drivers/gpu/drm/radeon/trinity_dpm.c
··· 1874 1874 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 1875 1875 pi->at[i] = TRINITY_AT_DFLT; 1876 1876 1877 - /* There are stability issues reported on latops with 1878 - * bapm installed when switching between AC and battery 1879 - * power. At the same time, some desktop boards hang 1880 - * if it's not enabled and dpm is enabled. 1877 + /* There are stability issues reported on with 1878 + * bapm enabled when switching between AC and battery 1879 + * power. At the same time, some MSI boards hang 1880 + * if it's not enabled and dpm is enabled. Just enable 1881 + * it for MSI boards right now. 1881 1882 */ 1882 - if (rdev->flags & RADEON_IS_MOBILITY) 1883 - pi->enable_bapm = false; 1884 - else 1883 + if (rdev->pdev->subsystem_vendor == 0x1462) 1885 1884 pi->enable_bapm = true; 1885 + else 1886 + pi->enable_bapm = false; 1886 1887 pi->enable_nbps_policy = true; 1887 1888 pi->enable_sclk_ds = true; 1888 1889 pi->enable_gfx_power_gating = true;