tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Travelling slowed down getting these out.

Two vmwgfx fixes, a radeon revert to avoid a regression, i915 fixes,
and some ioctl sizing issues fixed with 32 on 64"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/audio: don't set speaker allocation on DCE4+
drm/radeon: rework audio option
drm/radeon/audio: don't set speaker allocation on DCE3.2
drm/radeon: make missing smc ucode non-fatal (CI)
drm/radeon: make missing smc ucode non-fatal (r7xx-SI)
drm/radeon/uvd: revert lower msg&fb buffer requirements on UVD3
drm/radeon: stop the leaks in cik_ib_test
drm/radeon/atom: workaround vbios bug in transmitter table on rs780
drm/i915: Disable GGTT PTEs on GEN6+ suspend
drm/i915: Make PTE valid encoding optional
drm: Pad drm_mode_get_connector to 64-bit boundary
drm: Prevent overwriting from userspace underallocating core ioctl structs
drm/vmwgfx: Don't kill clients on VT switch
drm/vmwgfx: Don't put resources with invalid id's on lru list
drm/i915: disable LVDS clock gating on CPT v2

Linus Torvalds b403b73c 1c241131

+207 -72
+8 -1
drivers/gpu/drm/drm_drv.c
··· 402 402 cmd = ioctl->cmd_drv; 403 403 } 404 404 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) { 405 + u32 drv_size; 406 + 405 407 ioctl = &drm_ioctls[nr]; 406 - cmd = ioctl->cmd; 408 + 409 + drv_size = _IOC_SIZE(ioctl->cmd); 407 410 usize = asize = _IOC_SIZE(cmd); 411 + if (drv_size > asize) 412 + asize = drv_size; 413 + 414 + cmd = ioctl->cmd; 408 415 } else 409 416 goto err_i1; 410 417
+4 -1
drivers/gpu/drm/i915/i915_drv.c
··· 505 505 intel_modeset_suspend_hw(dev); 506 506 } 507 507 508 + i915_gem_suspend_gtt_mappings(dev); 509 + 508 510 i915_save_state(dev); 509 511 510 512 intel_opregion_fini(dev); ··· 650 648 mutex_lock(&dev->struct_mutex); 651 649 i915_gem_restore_gtt_mappings(dev); 652 650 mutex_unlock(&dev->struct_mutex); 653 - } 651 + } else if (drm_core_check_feature(dev, DRIVER_MODESET)) 652 + i915_check_and_clear_faults(dev); 654 653 655 654 __i915_drm_thaw(dev); 656 655
+6 -2
drivers/gpu/drm/i915/i915_drv.h
··· 497 497 498 498 /* FIXME: Need a more generic return type */ 499 499 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 500 - enum i915_cache_level level); 500 + enum i915_cache_level level, 501 + bool valid); /* Create a valid PTE */ 501 502 void (*clear_range)(struct i915_address_space *vm, 502 503 unsigned int first_entry, 503 - unsigned int num_entries); 504 + unsigned int num_entries, 505 + bool use_scratch); 504 506 void (*insert_entries)(struct i915_address_space *vm, 505 507 struct sg_table *st, 506 508 unsigned int first_entry, ··· 2067 2065 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 2068 2066 struct drm_i915_gem_object *obj); 2069 2067 2068 + void i915_check_and_clear_faults(struct drm_device *dev); 2069 + void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 2070 2070 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 2071 2071 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 2072 2072 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
+85 -24
drivers/gpu/drm/i915/i915_gem_gtt.c
··· 58 58 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 59 59 60 60 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, 61 - enum i915_cache_level level) 61 + enum i915_cache_level level, 62 + bool valid) 62 63 { 63 - gen6_gtt_pte_t pte = GEN6_PTE_VALID; 64 + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 64 65 pte |= GEN6_PTE_ADDR_ENCODE(addr); 65 66 66 67 switch (level) { ··· 80 79 } 81 80 82 81 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, 83 - enum i915_cache_level level) 82 + enum i915_cache_level level, 83 + bool valid) 84 84 { 85 - gen6_gtt_pte_t pte = GEN6_PTE_VALID; 85 + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 86 86 pte |= GEN6_PTE_ADDR_ENCODE(addr); 87 87 88 88 switch (level) { ··· 107 105 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 108 106 109 107 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, 110 - enum i915_cache_level level) 108 + enum i915_cache_level level, 109 + bool valid) 111 110 { 112 - gen6_gtt_pte_t pte = GEN6_PTE_VALID; 111 + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 113 112 pte |= GEN6_PTE_ADDR_ENCODE(addr); 114 113 115 114 /* Mark the page as writeable. Other platforms don't have a ··· 125 122 } 126 123 127 124 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, 128 - enum i915_cache_level level) 125 + enum i915_cache_level level, 126 + bool valid) 129 127 { 130 - gen6_gtt_pte_t pte = GEN6_PTE_VALID; 128 + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 131 129 pte |= HSW_PTE_ADDR_ENCODE(addr); 132 130 133 131 if (level != I915_CACHE_NONE) ··· 138 134 } 139 135 140 136 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, 141 - enum i915_cache_level level) 137 + enum i915_cache_level level, 138 + bool valid) 142 139 { 143 - gen6_gtt_pte_t pte = GEN6_PTE_VALID; 140 + gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 144 141 pte |= HSW_PTE_ADDR_ENCODE(addr); 145 142 146 143 switch (level) { ··· 241 236 /* PPGTT support for Sandybdrige/Gen6 and later */ 242 237 static void gen6_ppgtt_clear_range(struct i915_address_space *vm, 243 238 unsigned first_entry, 244 - unsigned num_entries) 239 + unsigned num_entries, 240 + bool use_scratch) 245 241 { 246 242 struct i915_hw_ppgtt *ppgtt = 247 243 container_of(vm, struct i915_hw_ppgtt, base); ··· 251 245 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; 252 246 unsigned last_pte, i; 253 247 254 - scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); 248 + scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); 255 249 256 250 while (num_entries) { 257 251 last_pte = first_pte + num_entries; ··· 288 282 dma_addr_t page_addr; 289 283 290 284 page_addr = sg_page_iter_dma_address(&sg_iter); 291 - pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level); 285 + pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); 292 286 if (++act_pte == I915_PPGTT_PT_ENTRIES) { 293 287 kunmap_atomic(pt_vaddr); 294 288 act_pt++; ··· 373 367 } 374 368 375 369 ppgtt->base.clear_range(&ppgtt->base, 0, 376 - ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES); 370 + ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); 377 371 378 372 ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); 379 373 ··· 450 444 { 451 445 ppgtt->base.clear_range(&ppgtt->base, 452 446 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, 453 - obj->base.size >> PAGE_SHIFT); 447 + obj->base.size >> PAGE_SHIFT, 448 + true); 454 449 } 455 450 456 451 extern int intel_iommu_gfx_mapped; ··· 492 485 dev_priv->mm.interruptible = interruptible; 493 486 } 494 487 488 + void i915_check_and_clear_faults(struct drm_device *dev) 489 + { 490 + struct drm_i915_private *dev_priv = dev->dev_private; 491 + struct intel_ring_buffer *ring; 492 + int i; 493 + 494 + if (INTEL_INFO(dev)->gen < 6) 495 + return; 496 + 497 + for_each_ring(ring, dev_priv, i) { 498 + u32 fault_reg; 499 + fault_reg = I915_READ(RING_FAULT_REG(ring)); 500 + if (fault_reg & RING_FAULT_VALID) { 501 + DRM_DEBUG_DRIVER("Unexpected fault\n" 502 + "\tAddr: 0x%08lx\\n" 503 + "\tAddress space: %s\n" 504 + "\tSource ID: %d\n" 505 + "\tType: %d\n", 506 + fault_reg & PAGE_MASK, 507 + fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", 508 + RING_FAULT_SRCID(fault_reg), 509 + RING_FAULT_FAULT_TYPE(fault_reg)); 510 + I915_WRITE(RING_FAULT_REG(ring), 511 + fault_reg & ~RING_FAULT_VALID); 512 + } 513 + } 514 + POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); 515 + } 516 + 517 + void i915_gem_suspend_gtt_mappings(struct drm_device *dev) 518 + { 519 + struct drm_i915_private *dev_priv = dev->dev_private; 520 + 521 + /* Don't bother messing with faults pre GEN6 as we have little 522 + * documentation supporting that it's a good idea. 523 + */ 524 + if (INTEL_INFO(dev)->gen < 6) 525 + return; 526 + 527 + i915_check_and_clear_faults(dev); 528 + 529 + dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 530 + dev_priv->gtt.base.start / PAGE_SIZE, 531 + dev_priv->gtt.base.total / PAGE_SIZE, 532 + false); 533 + } 534 + 495 535 void i915_gem_restore_gtt_mappings(struct drm_device *dev) 496 536 { 497 537 struct drm_i915_private *dev_priv = dev->dev_private; 498 538 struct drm_i915_gem_object *obj; 499 539 540 + i915_check_and_clear_faults(dev); 541 + 500 542 /* First fill our portion of the GTT with scratch pages */ 501 543 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 502 544 dev_priv->gtt.base.start / PAGE_SIZE, 503 - dev_priv->gtt.base.total / PAGE_SIZE); 545 + dev_priv->gtt.base.total / PAGE_SIZE, 546 + true); 504 547 505 548 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 506 549 i915_gem_clflush_object(obj, obj->pin_display); ··· 593 536 594 537 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 595 538 addr = sg_page_iter_dma_address(&sg_iter); 596 - iowrite32(vm->pte_encode(addr, level), &gtt_entries[i]); 539 + iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]); 597 540 i++; 598 541 } 599 542 ··· 605 548 */ 606 549 if (i != 0) 607 550 WARN_ON(readl(&gtt_entries[i-1]) != 608 - vm->pte_encode(addr, level)); 551 + vm->pte_encode(addr, level, true)); 609 552 610 553 /* This next bit makes the above posting read even more important. We 611 554 * want to flush the TLBs only after we're certain all the PTE updates ··· 617 560 618 561 static void gen6_ggtt_clear_range(struct i915_address_space *vm, 619 562 unsigned int first_entry, 620 - unsigned int num_entries) 563 + unsigned int num_entries, 564 + bool use_scratch) 621 565 { 622 566 struct drm_i915_private *dev_priv = vm->dev->dev_private; 623 567 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = ··· 631 573 first_entry, num_entries, max_entries)) 632 574 num_entries = max_entries; 633 575 634 - scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); 576 + scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); 577 + 635 578 for (i = 0; i < num_entries; i++) 636 579 iowrite32(scratch_pte, &gtt_base[i]); 637 580 readl(gtt_base); ··· 653 594 654 595 static void i915_ggtt_clear_range(struct i915_address_space *vm, 655 596 unsigned int first_entry, 656 - unsigned int num_entries) 597 + unsigned int num_entries, 598 + bool unused) 657 599 { 658 600 intel_gtt_clear_range(first_entry, num_entries); 659 601 } ··· 682 622 683 623 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 684 624 entry, 685 - obj->base.size >> PAGE_SHIFT); 625 + obj->base.size >> PAGE_SHIFT, 626 + true); 686 627 687 628 obj->has_global_gtt_mapping = 0; 688 629 } ··· 770 709 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; 771 710 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", 772 711 hole_start, hole_end); 773 - ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count); 712 + ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); 774 713 } 775 714 776 715 /* And finally clear the reserved guard page */ 777 - ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1); 716 + ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); 778 717 } 779 718 780 719 static bool
+6
drivers/gpu/drm/i915/i915_reg.h
··· 604 604 #define ARB_MODE_SWIZZLE_IVB (1<<5) 605 605 #define RENDER_HWS_PGA_GEN7 (0x04080) 606 606 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 607 + #define RING_FAULT_GTTSEL_MASK (1<<11) 608 + #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) 609 + #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) 610 + #define RING_FAULT_VALID (1<<0) 607 611 #define DONE_REG 0x40b0 608 612 #define BSD_HWS_PGA_GEN7 (0x04180) 609 613 #define BLT_HWS_PGA_GEN7 (0x04280) ··· 4283 4279 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 4284 4280 4285 4281 #define SOUTH_DSPCLK_GATE_D 0xc2020 4282 + #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 4286 4283 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 4284 + #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 4287 4285 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 4288 4286 4289 4287 /* CPU: FDI_TX */
+3 -1
drivers/gpu/drm/i915/intel_pm.c
··· 4759 4759 * gating for the panel power sequencer or it will fail to 4760 4760 * start up when no ports are active. 4761 4761 */ 4762 - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 4762 + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 4763 + PCH_DPLUNIT_CLOCK_GATE_DISABLE | 4764 + PCH_CPUNIT_CLOCK_GATE_DISABLE); 4763 4765 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 4764 4766 DPLS_EDP_PPS_FIX_DIS); 4765 4767 /* The below fixes the weird display corruption, a few pixels shifted
+36 -18
drivers/gpu/drm/radeon/atombios_encoders.c
··· 707 707 switch (connector->connector_type) { 708 708 case DRM_MODE_CONNECTOR_DVII: 709 709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 710 - if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) || 711 - (drm_detect_hdmi_monitor(radeon_connector->edid) && 712 - (radeon_connector->audio == RADEON_AUDIO_AUTO))) 713 - return ATOM_ENCODER_MODE_HDMI; 714 - else if (radeon_connector->use_digital) 710 + if (radeon_audio != 0) { 711 + if (radeon_connector->use_digital && 712 + (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 713 + return ATOM_ENCODER_MODE_HDMI; 714 + else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 715 + (radeon_connector->audio == RADEON_AUDIO_AUTO)) 716 + return ATOM_ENCODER_MODE_HDMI; 717 + else if (radeon_connector->use_digital) 718 + return ATOM_ENCODER_MODE_DVI; 719 + else 720 + return ATOM_ENCODER_MODE_CRT; 721 + } else if (radeon_connector->use_digital) { 715 722 return ATOM_ENCODER_MODE_DVI; 716 - else 723 + } else { 717 724 return ATOM_ENCODER_MODE_CRT; 725 + } 718 726 break; 719 727 case DRM_MODE_CONNECTOR_DVID: 720 728 case DRM_MODE_CONNECTOR_HDMIA: 721 729 default: 722 - if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) || 723 - (drm_detect_hdmi_monitor(radeon_connector->edid) && 724 - (radeon_connector->audio == RADEON_AUDIO_AUTO))) 725 - return ATOM_ENCODER_MODE_HDMI; 726 - else 730 + if (radeon_audio != 0) { 731 + if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 732 + return ATOM_ENCODER_MODE_HDMI; 733 + else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 734 + (radeon_connector->audio == RADEON_AUDIO_AUTO)) 735 + return ATOM_ENCODER_MODE_HDMI; 736 + else 737 + return ATOM_ENCODER_MODE_DVI; 738 + } else { 727 739 return ATOM_ENCODER_MODE_DVI; 740 + } 728 741 break; 729 742 case DRM_MODE_CONNECTOR_LVDS: 730 743 return ATOM_ENCODER_MODE_LVDS; ··· 745 732 case DRM_MODE_CONNECTOR_DisplayPort: 746 733 dig_connector = radeon_connector->con_priv; 747 734 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 748 - (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 735 + (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 749 736 return ATOM_ENCODER_MODE_DP; 750 - else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) || 751 - (drm_detect_hdmi_monitor(radeon_connector->edid) && 752 - (radeon_connector->audio == RADEON_AUDIO_AUTO))) 753 - return ATOM_ENCODER_MODE_HDMI; 754 - else 737 + } else if (radeon_audio != 0) { 738 + if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 739 + return ATOM_ENCODER_MODE_HDMI; 740 + else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 741 + (radeon_connector->audio == RADEON_AUDIO_AUTO)) 742 + return ATOM_ENCODER_MODE_HDMI; 743 + else 744 + return ATOM_ENCODER_MODE_DVI; 745 + } else { 755 746 return ATOM_ENCODER_MODE_DVI; 747 + } 756 748 break; 757 749 case DRM_MODE_CONNECTOR_eDP: 758 750 return ATOM_ENCODER_MODE_DP; ··· 1673 1655 * does the same thing and more. 1674 1656 */ 1675 1657 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) && 1676 - (rdev->family != CHIP_RS880)) 1658 + (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880)) 1677 1659 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1678 1660 } 1679 1661 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
+4
drivers/gpu/drm/radeon/cik.c
··· 1694 1694 fw_name); 1695 1695 release_firmware(rdev->smc_fw); 1696 1696 rdev->smc_fw = NULL; 1697 + err = 0; 1697 1698 } else if (rdev->smc_fw->size != smc_req_size) { 1698 1699 printk(KERN_ERR 1699 1700 "cik_smc: Bogus length %zu in firmware \"%s\"\n", ··· 3183 3182 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3184 3183 if (r) { 3185 3184 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3185 + radeon_scratch_free(rdev, scratch); 3186 3186 return r; 3187 3187 } 3188 3188 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); ··· 3200 3198 r = radeon_fence_wait(ib.fence, false); 3201 3199 if (r) { 3202 3200 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3201 + radeon_scratch_free(rdev, scratch); 3202 + radeon_ib_free(rdev, &ib); 3203 3203 return r; 3204 3204 } 3205 3205 for (i = 0; i < rdev->usec_timeout; i++) {
+3
drivers/gpu/drm/radeon/dce6_afmt.c
··· 113 113 u8 *sadb; 114 114 int sad_count; 115 115 116 + /* XXX: setting this register causes hangs on some asics */ 117 + return; 118 + 116 119 if (!dig->afmt->pin) 117 120 return; 118 121
+3
drivers/gpu/drm/radeon/evergreen_hdmi.c
··· 67 67 u8 *sadb; 68 68 int sad_count; 69 69 70 + /* XXX: setting this register causes hangs on some asics */ 71 + return; 72 + 70 73 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 71 74 if (connector->encoder == encoder) 72 75 radeon_connector = to_radeon_connector(connector);
+1
drivers/gpu/drm/radeon/ni.c
··· 804 804 fw_name); 805 805 release_firmware(rdev->smc_fw); 806 806 rdev->smc_fw = NULL; 807 + err = 0; 807 808 } else if (rdev->smc_fw->size != smc_req_size) { 808 809 printk(KERN_ERR 809 810 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
+1
drivers/gpu/drm/radeon/r600.c
··· 2302 2302 fw_name); 2303 2303 release_firmware(rdev->smc_fw); 2304 2304 rdev->smc_fw = NULL; 2305 + err = 0; 2305 2306 } else if (rdev->smc_fw->size != smc_req_size) { 2306 2307 printk(KERN_ERR 2307 2308 "smc: Bogus length %zu in firmware \"%s\"\n",
+3
drivers/gpu/drm/radeon/r600_hdmi.c
··· 309 309 u8 *sadb; 310 310 int sad_count; 311 311 312 + /* XXX: setting this register causes hangs on some asics */ 313 + return; 314 + 312 315 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 313 316 if (connector->encoder == encoder) 314 317 radeon_connector = to_radeon_connector(connector);
+21 -12
drivers/gpu/drm/radeon/radeon_connectors.c
··· 1658 1658 drm_object_attach_property(&radeon_connector->base.base, 1659 1659 rdev->mode_info.underscan_vborder_property, 1660 1660 0); 1661 - drm_object_attach_property(&radeon_connector->base.base, 1662 - rdev->mode_info.audio_property, 1663 - RADEON_AUDIO_DISABLE); 1661 + if (radeon_audio != 0) 1662 + drm_object_attach_property(&radeon_connector->base.base, 1663 + rdev->mode_info.audio_property, 1664 + (radeon_audio == 1) ? 1665 + RADEON_AUDIO_AUTO : 1666 + RADEON_AUDIO_DISABLE); 1664 1667 subpixel_order = SubPixelHorizontalRGB; 1665 1668 connector->interlace_allowed = true; 1666 1669 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) ··· 1757 1754 rdev->mode_info.underscan_vborder_property, 1758 1755 0); 1759 1756 } 1760 - if (ASIC_IS_DCE2(rdev)) { 1757 + if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1761 1758 drm_object_attach_property(&radeon_connector->base.base, 1762 - rdev->mode_info.audio_property, 1763 - RADEON_AUDIO_DISABLE); 1759 + rdev->mode_info.audio_property, 1760 + (radeon_audio == 1) ? 1761 + RADEON_AUDIO_AUTO : 1762 + RADEON_AUDIO_DISABLE); 1764 1763 } 1765 1764 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1766 1765 radeon_connector->dac_load_detect = true; ··· 1804 1799 rdev->mode_info.underscan_vborder_property, 1805 1800 0); 1806 1801 } 1807 - if (ASIC_IS_DCE2(rdev)) { 1802 + if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1808 1803 drm_object_attach_property(&radeon_connector->base.base, 1809 - rdev->mode_info.audio_property, 1810 - RADEON_AUDIO_DISABLE); 1804 + rdev->mode_info.audio_property, 1805 + (radeon_audio == 1) ? 1806 + RADEON_AUDIO_AUTO : 1807 + RADEON_AUDIO_DISABLE); 1811 1808 } 1812 1809 subpixel_order = SubPixelHorizontalRGB; 1813 1810 connector->interlace_allowed = true; ··· 1850 1843 rdev->mode_info.underscan_vborder_property, 1851 1844 0); 1852 1845 } 1853 - if (ASIC_IS_DCE2(rdev)) { 1846 + if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1854 1847 drm_object_attach_property(&radeon_connector->base.base, 1855 - rdev->mode_info.audio_property, 1856 - RADEON_AUDIO_DISABLE); 1848 + rdev->mode_info.audio_property, 1849 + (radeon_audio == 1) ? 1850 + RADEON_AUDIO_AUTO : 1851 + RADEON_AUDIO_DISABLE); 1857 1852 } 1858 1853 connector->interlace_allowed = true; 1859 1854 /* in theory with a DP to VGA converter... */
+1 -2
drivers/gpu/drm/radeon/radeon_cs.c
··· 85 85 VRAM, also but everything into VRAM on AGP cards to avoid 86 86 image corruptions */ 87 87 if (p->ring == R600_RING_TYPE_UVD_INDEX && 88 - p->rdev->family < CHIP_PALM && 89 88 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { 90 - 89 + /* TODO: is this still needed for NI+ ? */ 91 90 p->relocs[i].lobj.domain = 92 91 RADEON_GEM_DOMAIN_VRAM; 93 92
+2 -2
drivers/gpu/drm/radeon/radeon_drv.c
··· 153 153 int radeon_testing = 0; 154 154 int radeon_connector_table = 0; 155 155 int radeon_tv = 1; 156 - int radeon_audio = 1; 156 + int radeon_audio = -1; 157 157 int radeon_disp_priority = 0; 158 158 int radeon_hw_i2c = 0; 159 159 int radeon_pcie_gen2 = -1; ··· 196 196 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 197 197 module_param_named(tv, radeon_tv, int, 0444); 198 198 199 - MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); 199 + MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 200 200 module_param_named(audio, radeon_audio, int, 0444); 201 201 202 202 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
+2 -1
drivers/gpu/drm/radeon/radeon_uvd.c
··· 476 476 return -EINVAL; 477 477 } 478 478 479 - if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) && 479 + /* TODO: is this still necessary on NI+ ? */ 480 + if ((cmd == 0 || cmd == 0x3) && 480 481 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 481 482 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 482 483 start, end);
+1
drivers/gpu/drm/radeon/si.c
··· 1681 1681 fw_name); 1682 1682 release_firmware(rdev->smc_fw); 1683 1683 rdev->smc_fw = NULL; 1684 + err = 0; 1684 1685 } else if (rdev->smc_fw->size != smc_req_size) { 1685 1686 printk(KERN_ERR 1686 1687 "si_smc: Bogus length %zu in firmware \"%s\"\n",
+2 -2
drivers/gpu/drm/radeon/uvd_v1_0.c
··· 212 212 /* enable VCPU clock */ 213 213 WREG32(UVD_VCPU_CNTL, 1 << 9); 214 214 215 - /* enable UMC and NC0 */ 216 - WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13))); 215 + /* enable UMC */ 216 + WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); 217 217 218 218 /* boot up the VCPU */ 219 219 WREG32(UVD_SOFT_RESET, 0);
+12 -5
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
··· 740 740 struct vmw_fpriv *vmw_fp; 741 741 742 742 vmw_fp = vmw_fpriv(file_priv); 743 - ttm_object_file_release(&vmw_fp->tfile); 744 - if (vmw_fp->locked_master) 743 + 744 + if (vmw_fp->locked_master) { 745 + struct vmw_master *vmaster = 746 + vmw_master(vmw_fp->locked_master); 747 + 748 + ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 749 + ttm_vt_unlock(&vmaster->lock); 745 750 drm_master_put(&vmw_fp->locked_master); 751 + } 752 + 753 + ttm_object_file_release(&vmw_fp->tfile); 746 754 kfree(vmw_fp); 747 755 } 748 756 ··· 933 925 934 926 vmw_fp->locked_master = drm_master_get(file_priv->master); 935 927 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 936 - vmw_execbuf_release_pinned_bo(dev_priv); 937 - 938 928 if (unlikely((ret != 0))) { 939 929 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 940 930 drm_master_put(&vmw_fp->locked_master); 941 931 } 942 932 943 - ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 933 + ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 934 + vmw_execbuf_release_pinned_bo(dev_priv); 944 935 945 936 if (!dev_priv->enable_fb) { 946 937 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
+1 -1
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
··· 970 970 if (new_backup) 971 971 res->backup_offset = new_backup_offset; 972 972 973 - if (!res->func->may_evict) 973 + if (!res->func->may_evict || res->id == -1) 974 974 return; 975 975 976 976 write_lock(&dev_priv->resource_lock);
+2
include/uapi/drm/drm_mode.h
··· 223 223 __u32 connection; 224 224 __u32 mm_width, mm_height; /**< HxW in millimeters */ 225 225 __u32 subpixel; 226 + 227 + __u32 pad; 226 228 }; 227 229 228 230 #define DRM_MODE_PROP_PENDING (1<<0)