Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mfd: max77759: add register bitmasks and modify irq configs for charger
Add register bitmasks for charger function.
In addition split the charger IRQs further such that each bit represents
an IRQ downstream of charger regmap irq chip. In addition populate the
ack_base to offload irq ack to the regmap irq chip framework.
Signed-off-by: Amit Sunil Dhamne <amitsd@google.com>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20260325-max77759-charger-v9-3-4486dd297adc@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Amit Sunil Dhamne
and committed by
Greg Kroah-Hartman
b422f7c0
47f8ba23
+222
-39
+85
-10
drivers/mfd/max77759.c
+85
-10
drivers/mfd/max77759.c
···
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* - SYSUVLO_INT
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* - FSHIP_NOT_RD
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* - CHGR_INT: charger
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-
* - CHG_INT
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-
* - CHG_INT2
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+
* - INT1
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+
* - AICL
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+
* - CHGIN
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+
* - WCIN
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+
* - CHG
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+
* - BAT
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+
* - INLIM
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+
* - THM2
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+
* - BYP
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+
* - INT2
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+
* - INSEL
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+
* - SYS_UVLO1
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+
* - SYS_UVLO2
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+
* - BAT_OILO
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+
* - CHG_STA_CC
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+
* - CHG_STA_CV
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+
* - CHG_STA_TO
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+
* - CHG_STA_DONE
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*/
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enum {
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MAX77759_INT_MAXQ,
···
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};
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enum {
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-
MAX77759_CHARGER_INT_1,
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-
MAX77759_CHARGER_INT_2,
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+
MAX77759_CHGR_INT1_AICL,
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+
MAX77759_CHGR_INT1_CHGIN,
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+
MAX77759_CHGR_INT1_WCIN,
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MAX77759_CHGR_INT1_CHG,
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+
MAX77759_CHGR_INT1_BAT,
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+
MAX77759_CHGR_INT1_INLIM,
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MAX77759_CHGR_INT1_THM2,
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+
MAX77759_CHGR_INT1_BYP,
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MAX77759_CHGR_INT2_INSEL,
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MAX77759_CHGR_INT2_SYS_UVLO1,
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+
MAX77759_CHGR_INT2_SYS_UVLO2,
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MAX77759_CHGR_INT2_BAT_OILO,
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MAX77759_CHGR_INT2_CHG_STA_CC,
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MAX77759_CHGR_INT2_CHG_STA_CV,
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MAX77759_CHGR_INT2_CHG_STA_TO,
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MAX77759_CHGR_INT2_CHG_STA_DONE,
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};
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static const struct regmap_irq max77759_pmic_irqs[] = {
···
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};
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static const struct regmap_irq max77759_chgr_irqs[] = {
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-
REGMAP_IRQ_REG(MAX77759_CHARGER_INT_1, 0, GENMASK(7, 0)),
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-
REGMAP_IRQ_REG(MAX77759_CHARGER_INT_2, 1, GENMASK(7, 0)),
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+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0,
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+
MAX77759_CHGR_REG_CHG_INT_AICL),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0,
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MAX77759_CHGR_REG_CHG_INT_CHGIN),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0,
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MAX77759_CHGR_REG_CHG_INT_WCIN),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0,
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MAX77759_CHGR_REG_CHG_INT_CHG),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0,
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MAX77759_CHGR_REG_CHG_INT_BAT),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0,
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MAX77759_CHGR_REG_CHG_INT_INLIM),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0,
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MAX77759_CHGR_REG_CHG_INT_THM2),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0,
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MAX77759_CHGR_REG_CHG_INT_BYP),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1,
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MAX77759_CHGR_REG_CHG_INT2_INSEL),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1,
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MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1,
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MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1,
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+
MAX77759_CHGR_REG_CHG_INT2_BAT_OILO),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1,
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MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1,
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+
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1,
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MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO),
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REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1,
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MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE),
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};
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static const struct regmap_irq_chip max77759_pmic_irq_chip = {
···
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.num_irqs = ARRAY_SIZE(max77759_topsys_irqs),
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};
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-
static const struct regmap_irq_chip max77759_chrg_irq_chip = {
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static const struct regmap_irq_chip max77759_chgr_irq_chip = {
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.name = "max77759-chgr",
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.domain_suffix = "CHGR",
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.status_base = MAX77759_CHGR_REG_CHG_INT,
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.mask_base = MAX77759_CHGR_REG_CHG_INT_MASK,
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+
.ack_base = MAX77759_CHGR_REG_CHG_INT,
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.num_regs = 2,
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.irqs = max77759_chgr_irqs,
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.num_irqs = ARRAY_SIZE(max77759_chgr_irqs),
···
386
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};
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static const struct resource max77759_charger_resources[] = {
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DEFINE_RES_IRQ_NAMED(MAX77759_CHARGER_INT_1, "INT1"),
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-
DEFINE_RES_IRQ_NAMED(MAX77759_CHARGER_INT_2, "INT2"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_AICL, "AICL"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHGIN, "CHGIN"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_WCIN, "WCIN"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHG, "CHG"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BAT, "BAT"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_INLIM, "INLIM"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_THM2, "THM2"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BYP, "BYP"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_INSEL, "INSEL"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO1, "SYS_UVLO1"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO2, "SYS_UVLO2"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_BAT_OILO, "BAT_OILO"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CC, "CHG_STA_CC"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CV, "CHG_STA_CV"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_TO, "CHG_STA_TO"),
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DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_DONE, "CHG_STA_DONE"),
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};
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static const struct mfd_cell max77759_cells[] = {
···
642
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max77759->regmap_charger,
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MAX77759_INT_CHGR,
644
569
parent,
645
-
&max77759_chrg_irq_chip,
570
+
&max77759_chgr_irq_chip,
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&irq_chip_data);
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if (ret)
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return ret;
+137
-29
include/linux/mfd/max77759.h
+137
-29
include/linux/mfd/max77759.h
···
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#define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1
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#define MAX77759_MAXQ_REG_UIC_SWRST 0xe0
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-
#define MAX77759_CHGR_REG_CHG_INT 0xb0
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-
#define MAX77759_CHGR_REG_CHG_INT2 0xb1
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#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2
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#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3
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#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4
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#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5
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#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6
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#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7
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#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8
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#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9
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#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba
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#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb
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#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc
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#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd
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#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe
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#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf
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#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0
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#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1
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#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2
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#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
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#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
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#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
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#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
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#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
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#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8
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#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9
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#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca
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#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb
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#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc
62
+
#define MAX77759_CHGR_REG_CHG_INT 0xb0
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#define MAX77759_CHGR_REG_CHG_INT_AICL BIT(7)
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#define MAX77759_CHGR_REG_CHG_INT_CHGIN BIT(6)
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#define MAX77759_CHGR_REG_CHG_INT_WCIN BIT(5)
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#define MAX77759_CHGR_REG_CHG_INT_CHG BIT(4)
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#define MAX77759_CHGR_REG_CHG_INT_BAT BIT(3)
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#define MAX77759_CHGR_REG_CHG_INT_INLIM BIT(2)
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#define MAX77759_CHGR_REG_CHG_INT_THM2 BIT(1)
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#define MAX77759_CHGR_REG_CHG_INT_BYP BIT(0)
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#define MAX77759_CHGR_REG_CHG_INT2 0xb1
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#define MAX77759_CHGR_REG_CHG_INT2_INSEL BIT(7)
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#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1 BIT(6)
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#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2 BIT(5)
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#define MAX77759_CHGR_REG_CHG_INT2_BAT_OILO BIT(4)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC BIT(3)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV BIT(2)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO BIT(1)
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#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE BIT(0)
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#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2
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#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3
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#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4
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#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5
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#define MAX77759_CHGR_REG_CHG_DETAILS_00_CHGIN_DTLS GENMASK(6, 5)
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#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6
86
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#define MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS GENMASK(6, 4)
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#define MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS GENMASK(3, 0)
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#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7
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#define MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS BIT(5)
90
+
#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8
91
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#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9
92
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#define MAX77759_CHGR_REG_CHG_CNFG_00_MODE GENMASK(3, 0)
93
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#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba
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#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb
95
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#define MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC GENMASK(5, 0)
96
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#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc
97
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#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd
98
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#define MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM GENMASK(5, 0)
99
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#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe
100
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#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf
101
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#define MAX77759_CHGR_REG_CHG_CNFG_06_CHGPROT GENMASK(3, 2)
102
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#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0
103
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#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1
104
+
#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2
105
+
#define MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM GENMASK(6, 0)
106
+
#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
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+
#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
108
+
#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
109
+
/* Wireless Charging input channel select */
110
+
#define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6)
111
+
/* CHGIN/USB input channel select */
112
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#define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5)
113
+
#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
114
+
#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
115
+
#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8
116
+
#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9
117
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#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca
118
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#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb
119
+
#define MAX77759_CHGR_REG_CHG_CNFG_18_WDTEN BIT(0)
120
+
#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc
91
121
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/* MaxQ opcodes for max77759_maxq_command() */
93
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#define MAX77759_MAXQ_OPCODE_MAXLENGTH (MAX77759_MAXQ_REG_AP_DATAOUT32 - \
···
130
100
#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE 0x24
131
101
#define MAX77759_MAXQ_OPCODE_USER_SPACE_READ 0x81
132
102
#define MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE 0x82
103
+
104
+
/*
105
+
* enum max77759_chgr_chgin_dtls_status - Charger Input Status
106
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE:
107
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* Charger input voltage (Vchgin) < Under Voltage Threshold (Vuvlo)
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE: Vchgin > Vuvlo and
109
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* Vchgin < (Battery Voltage (Vbatt) + system voltage (Vsys))
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE:
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* Vchgin > Over Voltage threshold (Vovlo)
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* @MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID:
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* Vchgin > Vuvlo, Vchgin < Vovlo and Vchgin > (Vsys + Vbatt)
114
+
*/
115
+
enum max77759_chgr_chgin_dtls_status {
116
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE,
117
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE,
118
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE,
119
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID,
120
+
};
121
+
122
+
/*
123
+
* enum max77759_chgr_bat_dtls_states - Battery Details
124
+
* @MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP: No battery and the charger suspended
125
+
* @MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY: Vbatt < Vtrickle
126
+
* @MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT: Charging suspended due to timer fault
127
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* @MAX77759_CHGR_BAT_DTLS_BAT_OKAY: Battery okay and Vbatt > Min Sys Voltage (Vsysmin)
128
+
* @MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE: Battery is okay. Vtrickle < Vbatt < Vsysmin
129
+
* @MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE: Battery voltage > Overvoltage threshold
130
+
* @MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT: Battery current exceeds overcurrent threshold
131
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* @MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE: Battery only mode and battery level not available
132
+
*/
133
+
enum max77759_chgr_bat_dtls_states {
134
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MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP,
135
+
MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY,
136
+
MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT,
137
+
MAX77759_CHGR_BAT_DTLS_BAT_OKAY,
138
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MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE,
139
+
MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE,
140
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MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT,
141
+
MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE,
142
+
};
143
+
144
+
/*
145
+
* enum max77759_chgr_chg_dtls_states - Charger Details
146
+
* @MAX77759_CHGR_CHG_DTLS_PREQUAL: Charger in prequalification mode
147
+
* @MAX77759_CHGR_CHG_DTLS_CC: Charger in fast charge const curr mode
148
+
* @MAX77759_CHGR_CHG_DTLS_CV: Charger in fast charge const voltage mode
149
+
* @MAX77759_CHGR_CHG_DTLS_TO: Charger is in top off mode
150
+
* @MAX77759_CHGR_CHG_DTLS_DONE: Charger is done
151
+
* @MAX77759_CHGR_CHG_DTLS_RSVD_1: Reserved
152
+
* @MAX77759_CHGR_CHG_DTLS_TIMER_FAULT: Charger is in timer fault mode
153
+
* @MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM: Charger is suspended as battery removal detected
154
+
* @MAX77759_CHGR_CHG_DTLS_OFF: Charger is off. Input invalid or charger disabled
155
+
* @MAX77759_CHGR_CHG_DTLS_RSVD_2: Reserved
156
+
* @MAX77759_CHGR_CHG_DTLS_RSVD_3: Reserved
157
+
* @MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER: Charger is off as watchdog timer expired
158
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* @MAX77759_CHGR_CHG_DTLS_SUSP_JEITA: Charger is in JEITA control mode
159
+
*/
160
+
enum max77759_chgr_chg_dtls_states {
161
+
MAX77759_CHGR_CHG_DTLS_PREQUAL,
162
+
MAX77759_CHGR_CHG_DTLS_CC,
163
+
MAX77759_CHGR_CHG_DTLS_CV,
164
+
MAX77759_CHGR_CHG_DTLS_TO,
165
+
MAX77759_CHGR_CHG_DTLS_DONE,
166
+
MAX77759_CHGR_CHG_DTLS_RSVD_1,
167
+
MAX77759_CHGR_CHG_DTLS_TIMER_FAULT,
168
+
MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM,
169
+
MAX77759_CHGR_CHG_DTLS_OFF,
170
+
MAX77759_CHGR_CHG_DTLS_RSVD_2,
171
+
MAX77759_CHGR_CHG_DTLS_RSVD_3,
172
+
MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER,
173
+
MAX77759_CHGR_CHG_DTLS_SUSP_JEITA,
174
+
};
175
+
176
+
enum max77759_chgr_mode {
177
+
MAX77759_CHGR_MODE_OFF,
178
+
MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5,
179
+
MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA,
180
+
};
133
181
134
182
/**
135
183
* struct max77759 - core max77759 internal data structure