Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration
Torrent PHY can have separate input reference clocks for PLL0 and PLL1.
Add support for dual reference clock multilink configurations.
Add register sequences for PCIe(100MHz) + USXGMII(156.25MHz) multilink
configuration. PCIe uses PLL0 and USXGMII uses PLL1.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Swapnil Jakhade
and committed by
Vinod Koul
b426146a
088de129
+200
-9
+200
-9
drivers/phy/cadence/phy-cadence-torrent.c
+200
-9
drivers/phy/cadence/phy-cadence-torrent.c
···
355
355
struct reset_control *apb_rst;
356
356
struct device *dev;
357
357
struct clk *clk;
358
+
struct clk *clk1;
358
359
enum cdns_torrent_ref_clk ref_clk_rate;
360
+
enum cdns_torrent_ref_clk ref_clk1_rate;
359
361
struct cdns_torrent_inst phys[MAX_NUM_LANES];
360
362
int nsubnodes;
361
363
const struct cdns_torrent_data *init_data;
···
2462
2460
{
2463
2461
const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2464
2462
struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2463
+
enum cdns_torrent_ref_clk ref_clk1 = cdns_phy->ref_clk1_rate;
2465
2464
enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2466
2465
struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2467
2466
enum cdns_torrent_phy_type phy_t1, phy_t2;
2467
+
struct cdns_torrent_vals *phy_pma_cmn_vals;
2468
2468
struct cdns_torrent_vals *pcs_cmn_vals;
2469
2469
int i, j, node, mlane, num_lanes, ret;
2470
2470
struct cdns_reg_pairs *reg_pairs;
···
2493
2489
* Get the array values as [phy_t2][phy_t1][ssc].
2494
2490
*/
2495
2491
swap(phy_t1, phy_t2);
2492
+
swap(ref_clk, ref_clk1);
2496
2493
}
2497
2494
2498
2495
mlane = cdns_phy->phys[node].mlane;
···
2557
2552
reg_pairs[i].val);
2558
2553
}
2559
2554
2555
+
/* PHY PMA common registers configurations */
2556
+
phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,
2557
+
CLK_ANY, CLK_ANY,
2558
+
phy_t1, phy_t2, ANY_SSC);
2559
+
if (phy_pma_cmn_vals) {
2560
+
reg_pairs = phy_pma_cmn_vals->reg_pairs;
2561
+
num_regs = phy_pma_cmn_vals->num_regs;
2562
+
regmap = cdns_phy->regmap_phy_pma_common_cdb;
2563
+
for (i = 0; i < num_regs; i++)
2564
+
regmap_write(regmap, reg_pairs[i].off,
2565
+
reg_pairs[i].val);
2566
+
}
2567
+
2560
2568
/* PMA common registers configurations */
2561
2569
cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,
2562
-
ref_clk, ref_clk,
2570
+
ref_clk, ref_clk1,
2563
2571
phy_t1, phy_t2, ssc);
2564
2572
if (cmn_vals) {
2565
2573
reg_pairs = cmn_vals->reg_pairs;
···
2585
2567
2586
2568
/* PMA TX lane registers configurations */
2587
2569
tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,
2588
-
ref_clk, ref_clk,
2570
+
ref_clk, ref_clk1,
2589
2571
phy_t1, phy_t2, ssc);
2590
2572
if (tx_ln_vals) {
2591
2573
reg_pairs = tx_ln_vals->reg_pairs;
···
2600
2582
2601
2583
/* PMA RX lane registers configurations */
2602
2584
rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,
2603
-
ref_clk, ref_clk,
2585
+
ref_clk, ref_clk1,
2604
2586
phy_t1, phy_t2, ssc);
2605
2587
if (rx_ln_vals) {
2606
2588
reg_pairs = rx_ln_vals->reg_pairs;
···
2702
2684
static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2703
2685
{
2704
2686
struct device *dev = cdns_phy->dev;
2687
+
unsigned long ref_clk1_rate;
2705
2688
unsigned long ref_clk_rate;
2706
2689
int ret;
2707
2690
2691
+
/* refclk: Input reference clock for PLL0 */
2708
2692
cdns_phy->clk = devm_clk_get(dev, "refclk");
2709
2693
if (IS_ERR(cdns_phy->clk)) {
2710
2694
dev_err(dev, "phy ref clock not found\n");
···
2715
2695
2716
2696
ret = clk_prepare_enable(cdns_phy->clk);
2717
2697
if (ret) {
2718
-
dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2698
+
dev_err(cdns_phy->dev, "Failed to prepare ref clock: %d\n", ret);
2719
2699
return ret;
2720
2700
}
2721
2701
2722
2702
ref_clk_rate = clk_get_rate(cdns_phy->clk);
2723
2703
if (!ref_clk_rate) {
2724
2704
dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2725
-
clk_disable_unprepare(cdns_phy->clk);
2726
-
return -EINVAL;
2705
+
ret = -EINVAL;
2706
+
goto disable_clk;
2727
2707
}
2728
2708
2729
2709
switch (ref_clk_rate) {
···
2740
2720
cdns_phy->ref_clk_rate = CLK_156_25_MHZ;
2741
2721
break;
2742
2722
default:
2743
-
dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2744
-
clk_disable_unprepare(cdns_phy->clk);
2745
-
return -EINVAL;
2723
+
dev_err(cdns_phy->dev, "Invalid ref clock rate\n");
2724
+
ret = -EINVAL;
2725
+
goto disable_clk;
2726
+
}
2727
+
2728
+
/* refclk1: Input reference clock for PLL1 */
2729
+
cdns_phy->clk1 = devm_clk_get_optional(dev, "pll1_refclk");
2730
+
if (IS_ERR(cdns_phy->clk1)) {
2731
+
dev_err(dev, "phy PLL1 ref clock not found\n");
2732
+
ret = PTR_ERR(cdns_phy->clk1);
2733
+
goto disable_clk;
2734
+
}
2735
+
2736
+
if (cdns_phy->clk1) {
2737
+
ret = clk_prepare_enable(cdns_phy->clk1);
2738
+
if (ret) {
2739
+
dev_err(cdns_phy->dev, "Failed to prepare PLL1 ref clock: %d\n", ret);
2740
+
goto disable_clk;
2741
+
}
2742
+
2743
+
ref_clk1_rate = clk_get_rate(cdns_phy->clk1);
2744
+
if (!ref_clk1_rate) {
2745
+
dev_err(cdns_phy->dev, "Failed to get PLL1 ref clock rate\n");
2746
+
ret = -EINVAL;
2747
+
goto disable_clk1;
2748
+
}
2749
+
2750
+
switch (ref_clk1_rate) {
2751
+
case REF_CLK_19_2MHZ:
2752
+
cdns_phy->ref_clk1_rate = CLK_19_2_MHZ;
2753
+
break;
2754
+
case REF_CLK_25MHZ:
2755
+
cdns_phy->ref_clk1_rate = CLK_25_MHZ;
2756
+
break;
2757
+
case REF_CLK_100MHZ:
2758
+
cdns_phy->ref_clk1_rate = CLK_100_MHZ;
2759
+
break;
2760
+
case REF_CLK_156_25MHZ:
2761
+
cdns_phy->ref_clk1_rate = CLK_156_25_MHZ;
2762
+
break;
2763
+
default:
2764
+
dev_err(cdns_phy->dev, "Invalid PLL1 ref clock rate\n");
2765
+
ret = -EINVAL;
2766
+
goto disable_clk1;
2767
+
}
2768
+
} else {
2769
+
cdns_phy->ref_clk1_rate = cdns_phy->ref_clk_rate;
2746
2770
}
2747
2771
2748
2772
return 0;
2773
+
2774
+
disable_clk1:
2775
+
clk_disable_unprepare(cdns_phy->clk1);
2776
+
disable_clk:
2777
+
clk_disable_unprepare(cdns_phy->clk);
2778
+
return ret;
2749
2779
}
2750
2780
2751
2781
static int cdns_torrent_phy_probe(struct platform_device *pdev)
···
3050
2980
reset_control_put(cdns_phy->phys[i].lnk_rst);
3051
2981
of_node_put(child);
3052
2982
reset_control_assert(cdns_phy->apb_rst);
2983
+
clk_disable_unprepare(cdns_phy->clk1);
3053
2984
clk_disable_unprepare(cdns_phy->clk);
3054
2985
clk_cleanup:
3055
2986
cdns_torrent_clk_cleanup(cdns_phy);
···
3069
2998
reset_control_put(cdns_phy->phys[i].lnk_rst);
3070
2999
}
3071
3000
3001
+
clk_disable_unprepare(cdns_phy->clk1);
3072
3002
clk_disable_unprepare(cdns_phy->clk);
3073
3003
cdns_torrent_clk_cleanup(cdns_phy);
3074
3004
}
···
3104
3032
static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = {
3105
3033
.reg_pairs = dp_usb_xcvr_diag_ln_regs,
3106
3034
.num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs),
3035
+
};
3036
+
3037
+
/* PCIe and USXGMII link configuration */
3038
+
static struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = {
3039
+
{0x0003, PHY_PLL_CFG},
3040
+
{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3041
+
{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3042
+
{0x0400, CMN_PDIAG_PLL1_CLK_SEL_M0}
3043
+
};
3044
+
3045
+
static struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = {
3046
+
{0x0000, XCVR_DIAG_HSCLK_SEL},
3047
+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3048
+
{0x0012, XCVR_DIAG_PLLDRC_CTRL}
3049
+
};
3050
+
3051
+
static struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = {
3052
+
{0x0011, XCVR_DIAG_HSCLK_SEL},
3053
+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3054
+
{0x0089, XCVR_DIAG_PLLDRC_CTRL}
3055
+
};
3056
+
3057
+
static struct cdns_torrent_vals pcie_usxgmii_link_cmn_vals = {
3058
+
.reg_pairs = pcie_usxgmii_link_cmn_regs,
3059
+
.num_regs = ARRAY_SIZE(pcie_usxgmii_link_cmn_regs),
3060
+
};
3061
+
3062
+
static struct cdns_torrent_vals pcie_usxgmii_xcvr_diag_ln_vals = {
3063
+
.reg_pairs = pcie_usxgmii_xcvr_diag_ln_regs,
3064
+
.num_regs = ARRAY_SIZE(pcie_usxgmii_xcvr_diag_ln_regs),
3065
+
};
3066
+
3067
+
static struct cdns_torrent_vals usxgmii_pcie_xcvr_diag_ln_vals = {
3068
+
.reg_pairs = usxgmii_pcie_xcvr_diag_ln_regs,
3069
+
.num_regs = ARRAY_SIZE(usxgmii_pcie_xcvr_diag_ln_regs),
3070
+
};
3071
+
3072
+
/*
3073
+
* Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC
3074
+
*/
3075
+
static struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = {
3076
+
{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3077
+
{0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},
3078
+
{0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},
3079
+
{0x061B, CMN_PLL1_VCOCAL_INIT_TMR},
3080
+
{0x0019, CMN_PLL1_VCOCAL_ITER_TMR},
3081
+
{0x1354, CMN_PLL1_VCOCAL_REFTIM_START},
3082
+
{0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},
3083
+
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
3084
+
{0x0138, CMN_PLL1_LOCK_REFCNT_START},
3085
+
{0x0138, CMN_PLL1_LOCK_PLLCNT_START},
3086
+
{0x007F, CMN_TXPUCAL_TUNE},
3087
+
{0x007F, CMN_TXPDCAL_TUNE}
3088
+
};
3089
+
3090
+
static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = {
3091
+
{0x00F3, TX_PSC_A0},
3092
+
{0x04A2, TX_PSC_A2},
3093
+
{0x04A2, TX_PSC_A3 },
3094
+
{0x0000, TX_TXCC_CPOST_MULT_00},
3095
+
{0x0000, XCVR_DIAG_PSC_OVRD}
3096
+
};
3097
+
3098
+
static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = {
3099
+
{0x091D, RX_PSC_A0},
3100
+
{0x0900, RX_PSC_A2},
3101
+
{0x0100, RX_PSC_A3},
3102
+
{0x0030, RX_REE_SMGM_CTRL1},
3103
+
{0x03C7, RX_REE_GCSM1_EQENM_PH1},
3104
+
{0x01C7, RX_REE_GCSM1_EQENM_PH2},
3105
+
{0x0000, RX_DIAG_DFE_CTRL},
3106
+
{0x0019, RX_REE_TAP1_CLIP},
3107
+
{0x0019, RX_REE_TAP2TON_CLIP},
3108
+
{0x00B9, RX_DIAG_NQST_CTRL},
3109
+
{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3110
+
{0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3111
+
{0x0033, RX_DIAG_PI_RATE},
3112
+
{0x0001, RX_DIAG_ACYA},
3113
+
{0x018C, RX_CDRLF_CNFG}
3114
+
};
3115
+
3116
+
static struct cdns_torrent_vals ml_usxgmii_pll1_156_25_no_ssc_cmn_vals = {
3117
+
.reg_pairs = ml_usxgmii_pll1_156_25_no_ssc_cmn_regs,
3118
+
.num_regs = ARRAY_SIZE(ml_usxgmii_pll1_156_25_no_ssc_cmn_regs),
3119
+
};
3120
+
3121
+
static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_tx_ln_vals = {
3122
+
.reg_pairs = ml_usxgmii_156_25_no_ssc_tx_ln_regs,
3123
+
.num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_tx_ln_regs),
3124
+
};
3125
+
3126
+
static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_rx_ln_vals = {
3127
+
.reg_pairs = ml_usxgmii_156_25_no_ssc_rx_ln_regs,
3128
+
.num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_rx_ln_regs),
3107
3129
};
3108
3130
3109
3131
/* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */
···
4332
4166
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
4333
4167
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
4334
4168
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
4169
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},
4335
4170
4336
4171
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4337
4172
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
···
4349
4182
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},
4350
4183
4351
4184
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals},
4185
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &pcie_usxgmii_link_cmn_vals},
4352
4186
};
4353
4187
4354
4188
static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
···
4362
4194
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4363
4195
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
4364
4196
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
4197
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},
4365
4198
4366
4199
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4367
4200
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
···
4379
4210
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},
4380
4211
4381
4212
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals},
4213
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &usxgmii_pcie_xcvr_diag_ln_vals},
4382
4214
};
4383
4215
4384
4216
static struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
···
4455
4285
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
4456
4286
4457
4287
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
4288
+
4289
+
/* Dual refclk */
4290
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4291
+
4292
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},
4458
4293
};
4459
4294
4460
4295
static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
···
4527
4352
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4528
4353
4529
4354
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4355
+
4356
+
/* Dual refclk */
4357
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4358
+
4359
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4530
4360
};
4531
4361
4532
4362
static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
···
4599
4419
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4600
4420
4601
4421
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4422
+
4423
+
/* Dual refclk */
4424
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4425
+
4426
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4602
4427
};
4603
4428
4604
4429
static const struct cdns_torrent_data cdns_map_torrent = {
···
4637
4452
4638
4453
static struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = {
4639
4454
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals},
4455
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &ti_usxgmii_phy_pma_cmn_vals},
4640
4456
};
4641
4457
4642
4458
static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
···
4705
4519
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4706
4520
4707
4521
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4522
+
4523
+
/* Dual refclk */
4524
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4525
+
4526
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4708
4527
};
4709
4528
4710
4529
static const struct cdns_torrent_data ti_j721e_map_torrent = {