soc: qcom: geni-se: Cleanup register defines and update copyright

Refactor register macros for consistency and clarity and remove redundant
definitions and update naming for better alignment.
Update copyright to include Qualcomm Technologies, Inc.

Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250911043256.3523057-3-viken.dadhaniya@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Viken Dadhaniya and committed by

Bjorn Andersson 8 months ago b44a593f 9bc71308

+16 -16

1 changed file

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drivers

soc

qcom

qcom-geni-se.c

+16 -16

drivers/soc/qcom/qcom-geni-se.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 - // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 2 + /* 3 + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 + */ 3 6 4 7 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 8 #define __DISABLE_TRACE_MMIO__ ··· 113 110 static const char * const icc_path_names[] = {"qup-core", "qup-config", 114 111 "qup-memory"}; 115 112 116 - #define QUP_HW_VER_REG 0x4 113 + /* Common QUPV3 registers */ 114 + #define QUPV3_HW_VER_REG 0x4 117 115 118 116 /* Common SE registers */ 119 - #define GENI_INIT_CFG_REVISION 0x0 120 - #define GENI_S_INIT_CFG_REVISION 0x4 121 - #define GENI_OUTPUT_CTRL 0x24 122 - #define GENI_CGC_CTRL 0x28 123 - #define GENI_CLK_CTRL_RO 0x60 124 - #define GENI_FW_S_REVISION_RO 0x6c 117 + #define SE_GENI_INIT_CFG_REVISION 0x0 118 + #define SE_GENI_S_INIT_CFG_REVISION 0x4 119 + #define SE_GENI_CGC_CTRL 0x28 120 + #define SE_GENI_CLK_CTRL_RO 0x60 121 + #define SE_GENI_FW_S_REVISION_RO 0x6c 125 122 #define SE_GENI_BYTE_GRAN 0x254 126 123 #define SE_GENI_TX_PACKING_CFG0 0x260 127 124 #define SE_GENI_TX_PACKING_CFG1 0x264 128 125 #define SE_GENI_RX_PACKING_CFG0 0x284 129 126 #define SE_GENI_RX_PACKING_CFG1 0x288 130 - #define SE_GENI_M_GP_LENGTH 0x910 131 - #define SE_GENI_S_GP_LENGTH 0x914 132 127 #define SE_DMA_TX_PTR_L 0xc30 133 128 #define SE_DMA_TX_PTR_H 0xc34 134 129 #define SE_DMA_TX_ATTR 0xc38 ··· 143 142 #define SE_DMA_RX_IRQ_EN 0xd48 144 143 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 145 144 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 146 - #define SE_DMA_RX_LEN_IN 0xd54 147 145 #define SE_DMA_RX_MAX_BURST 0xd5c 148 146 #define SE_DMA_RX_FLUSH 0xd60 149 147 #define SE_GSI_EVENT_EN 0xe18 ··· 179 179 /* SE_DMA_GENERAL_CFG */ 180 180 #define DMA_RX_CLK_CGC_ON BIT(0) 181 181 #define DMA_TX_CLK_CGC_ON BIT(1) 182 - #define DMA_AHB_SLV_CFG_ON BIT(2) 182 + #define DMA_AHB_SLV_CLK_CGC_ON BIT(2) 183 183 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 184 184 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 185 185 #define RX_DMA_ZERO_PADDING_EN BIT(5) ··· 196 196 { 197 197 struct geni_wrapper *wrapper = se->wrapper; 198 198 199 - return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 199 + return readl_relaxed(wrapper->base + QUPV3_HW_VER_REG); 200 200 } 201 201 EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version); 202 202 ··· 220 220 { 221 221 u32 val; 222 222 223 - val = readl_relaxed(base + GENI_CGC_CTRL); 223 + val = readl_relaxed(base + SE_GENI_CGC_CTRL); 224 224 val |= DEFAULT_CGC_EN; 225 - writel_relaxed(val, base + GENI_CGC_CTRL); 225 + writel_relaxed(val, base + SE_GENI_CGC_CTRL); 226 226 227 227 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 228 - val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 228 + val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON; 229 229 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 230 230 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 231 231

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