crypto: hisilicon - add device load query functionality to debugfs

+7

Documentation/ABI/testing/debugfs-hisi-hpre

··· 50 50 Available for PF and VF in host. VF in guest currently only 51 51 has one debug register. 52 52 53 + What: /sys/kernel/debug/hisi_hpre/<bdf>/dev_usage 54 + Date: Mar 2026 55 + Contact: linux-crypto@vger.kernel.org 56 + Description: Query the real-time bandwidth usage of device. 57 + Returns the bandwidth usage of each channel on the device. 58 + The returned number is in percentage. 59 + 53 60 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/current_q 54 61 Date: Sep 2019 55 62 Contact: linux-crypto@vger.kernel.org

+7

Documentation/ABI/testing/debugfs-hisi-sec

··· 24 24 1/1000~1000/1000 of total QoS. The driver reading alg_qos to 25 25 get related QoS in the host and VM, Such as "cat alg_qos". 26 26 27 + What: /sys/kernel/debug/hisi_sec2/<bdf>/dev_usage 28 + Date: Mar 2026 29 + Contact: linux-crypto@vger.kernel.org 30 + Description: Query the real-time bandwidth usage of device. 31 + Returns the bandwidth usage of each channel on the device. 32 + The returned number is in percentage. 33 + 27 34 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_regs 28 35 Date: Oct 2019 29 36 Contact: linux-crypto@vger.kernel.org

+7

Documentation/ABI/testing/debugfs-hisi-zip

··· 36 36 1/1000~1000/1000 of total QoS. The driver reading alg_qos to 37 37 get related QoS in the host and VM, Such as "cat alg_qos". 38 38 39 + What: /sys/kernel/debug/hisi_zip/<bdf>/dev_usage 40 + Date: Mar 2026 41 + Contact: linux-crypto@vger.kernel.org 42 + Description: Query the real-time bandwidth usage of device. 43 + Returns the bandwidth usage of each channel on the device. 44 + The returned number is in percentage. 45 + 39 46 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/regs 40 47 Date: Nov 2018 41 48 Contact: linux-crypto@vger.kernel.org

+54

drivers/crypto/hisilicon/debugfs.c

··· 1040 1040 } 1041 1041 } 1042 1042 1043 + static int qm_usage_percent(struct hisi_qm *qm, int chan_num) 1044 + { 1045 + u32 val, used_bw, total_bw; 1046 + 1047 + val = readl(qm->io_base + QM_CHANNEL_USAGE_OFFSET + 1048 + chan_num * QM_CHANNEL_ADDR_INTRVL); 1049 + used_bw = lower_16_bits(val); 1050 + total_bw = upper_16_bits(val); 1051 + if (!total_bw) 1052 + return -EIO; 1053 + 1054 + if (total_bw <= used_bw) 1055 + return QM_MAX_DEV_USAGE; 1056 + 1057 + return (used_bw * QM_DEV_USAGE_RATE) / total_bw; 1058 + } 1059 + 1060 + static int qm_usage_show(struct seq_file *s, void *unused) 1061 + { 1062 + struct hisi_qm *qm = s->private; 1063 + bool dev_is_active = true; 1064 + int i, ret; 1065 + 1066 + /* If device is in suspended, usage is 0. */ 1067 + ret = hisi_qm_get_dfx_access(qm); 1068 + if (ret == -EAGAIN) { 1069 + dev_is_active = false; 1070 + } else if (ret) { 1071 + dev_err(&qm->pdev->dev, "failed to get dfx access for usage_show!\n"); 1072 + return ret; 1073 + } 1074 + 1075 + ret = 0; 1076 + for (i = 0; i < qm->channel_data.channel_num; i++) { 1077 + if (dev_is_active) { 1078 + ret = qm_usage_percent(qm, i); 1079 + if (ret < 0) { 1080 + hisi_qm_put_dfx_access(qm); 1081 + return ret; 1082 + } 1083 + } 1084 + seq_printf(s, "%s: %d\n", qm->channel_data.channel_name[i], ret); 1085 + } 1086 + 1087 + if (dev_is_active) 1088 + hisi_qm_put_dfx_access(qm); 1089 + 1090 + return 0; 1091 + } 1092 + DEFINE_SHOW_ATTRIBUTE(qm_usage); 1093 + 1043 1094 static int qm_diff_regs_show(struct seq_file *s, void *unused) 1044 1095 { 1045 1096 struct hisi_qm *qm = s->private; ··· 1209 1158 if (qm_regs) 1210 1159 debugfs_create_file("diff_regs", 0444, qm->debug.qm_d, 1211 1160 qm, &qm_diff_regs_fops); 1161 + 1162 + if (qm->ver >= QM_HW_V5) 1163 + debugfs_create_file("dev_usage", 0444, qm->debug.debug_root, qm, &qm_usage_fops); 1212 1164 1213 1165 debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops); 1214 1166

+18

drivers/crypto/hisilicon/hpre/hpre_main.c

··· 121 121 #define HPRE_DFX_COMMON2_LEN 0xE 122 122 #define HPRE_DFX_CORE_LEN 0x43 123 123 124 + #define HPRE_MAX_CHANNEL_NUM 2 125 + 124 126 static const char hpre_name[] = "hisi_hpre"; 125 127 static struct dentry *hpre_debugfs_root; 126 128 static const struct pci_device_id hpre_dev_ids[] = { ··· 370 368 .reg_offset = HPRE_DFX_CORE, 371 369 .reg_len = HPRE_DFX_CORE_LEN, 372 370 }, 371 + }; 372 + 373 + static const char *hpre_channel_name[HPRE_MAX_CHANNEL_NUM] = { 374 + "RSA", 375 + "ECC", 373 376 }; 374 377 375 378 static const struct hisi_qm_err_ini hpre_err_ini; ··· 1241 1234 return 0; 1242 1235 } 1243 1236 1237 + static void hpre_set_channels(struct hisi_qm *qm) 1238 + { 1239 + struct qm_channel *channel_data = &qm->channel_data; 1240 + int i; 1241 + 1242 + channel_data->channel_num = HPRE_MAX_CHANNEL_NUM; 1243 + for (i = 0; i < HPRE_MAX_CHANNEL_NUM; i++) 1244 + channel_data->channel_name[i] = hpre_channel_name[i]; 1245 + } 1246 + 1244 1247 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1245 1248 { 1246 1249 u64 alg_msk; ··· 1284 1267 return ret; 1285 1268 } 1286 1269 1270 + hpre_set_channels(qm); 1287 1271 /* Fetch and save the value of capability registers */ 1288 1272 ret = hpre_pre_store_cap_reg(qm); 1289 1273 if (ret) {

+11

drivers/crypto/hisilicon/sec2/sec_main.c

··· 133 133 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ 134 134 GENMASK_ULL(45, 43)) 135 135 136 + #define SEC_MAX_CHANNEL_NUM 1 137 + 136 138 struct sec_hw_error { 137 139 u32 int_msk; 138 140 const char *msg; ··· 1290 1288 return 0; 1291 1289 } 1292 1290 1291 + static void sec_set_channels(struct hisi_qm *qm) 1292 + { 1293 + struct qm_channel *channel_data = &qm->channel_data; 1294 + 1295 + channel_data->channel_num = SEC_MAX_CHANNEL_NUM; 1296 + channel_data->channel_name[0] = "SEC"; 1297 + } 1298 + 1293 1299 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1294 1300 { 1295 1301 u64 alg_msk; ··· 1335 1325 return ret; 1336 1326 } 1337 1327 1328 + sec_set_channels(qm); 1338 1329 /* Fetch and save the value of capability registers */ 1339 1330 ret = sec_pre_store_cap_reg(qm); 1340 1331 if (ret) {

+19

drivers/crypto/hisilicon/zip/zip_main.c

··· 122 122 #define HZIP_LIT_LEN_EN_OFFSET 0x301204 123 123 #define HZIP_LIT_LEN_EN_EN BIT(4) 124 124 125 + #define HZIP_MAX_CHANNEL_NUM 3 126 + 125 127 enum { 126 128 HZIP_HIGH_COMP_RATE, 127 129 HZIP_HIGH_COMP_PERF, ··· 359 357 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 360 358 .reg_len = HZIP_CORE_REGS_DFX_LEN, 361 359 }, 360 + }; 361 + 362 + static const char *zip_channel_name[HZIP_MAX_CHANNEL_NUM] = { 363 + "COMPRESS", 364 + "DECOMPRESS", 365 + "DAE" 362 366 }; 363 367 364 368 static int hzip_diff_regs_show(struct seq_file *s, void *unused) ··· 1408 1400 return 0; 1409 1401 } 1410 1402 1403 + static void zip_set_channels(struct hisi_qm *qm) 1404 + { 1405 + struct qm_channel *channel_data = &qm->channel_data; 1406 + int i; 1407 + 1408 + channel_data->channel_num = HZIP_MAX_CHANNEL_NUM; 1409 + for (i = 0; i < HZIP_MAX_CHANNEL_NUM; i++) 1410 + channel_data->channel_name[i] = zip_channel_name[i]; 1411 + } 1412 + 1411 1413 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1412 1414 { 1413 1415 u64 alg_msk; ··· 1456 1438 return ret; 1457 1439 } 1458 1440 1441 + zip_set_channels(qm); 1459 1442 /* Fetch and save the value of capability registers */ 1460 1443 ret = zip_pre_store_cap_reg(qm); 1461 1444 if (ret) {

+12

include/linux/hisi_acc_qm.h

··· 102 102 #define QM_MIG_REGION_SEL 0x100198 103 103 #define QM_MIG_REGION_EN BIT(0) 104 104 105 + #define QM_MAX_CHANNEL_NUM 8 106 + #define QM_CHANNEL_USAGE_OFFSET 0x1100 107 + #define QM_MAX_DEV_USAGE 100 108 + #define QM_DEV_USAGE_RATE 100 109 + #define QM_CHANNEL_ADDR_INTRVL 0x4 110 + 105 111 /* uacce mode of the driver */ 106 112 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */ 107 113 #define UACCE_MODE_SVA 1 /* use uacce sva mode */ ··· 365 359 struct qm_dma qcdma; 366 360 }; 367 361 362 + struct qm_channel { 363 + int channel_num; 364 + const char *channel_name[QM_MAX_CHANNEL_NUM]; 365 + }; 366 + 368 367 struct hisi_qm { 369 368 enum qm_hw_ver ver; 370 369 enum qm_fun_type fun_type; ··· 444 433 struct qm_err_isolate isolate_data; 445 434 446 435 struct hisi_qm_cap_tables cap_tables; 436 + struct qm_channel channel_data; 447 437 }; 448 438 449 439 struct hisi_qp_status {

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