Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: spi_amd: Performance Optimization Patch Series
Merge series from Raju Rangoju <Raju.Rangoju@amd.com>:
AMD SPI controller’s index mode performance is constrained by the
hardware limitation of the FIFO queue length. This patch series introduces
optimizations to the spi_amd driver, aiming to maximize throughput and
enhance overall performance. The changes includes,
- Enable SPI dual and quad I/O modes and update SPI-MEM support function to
reflect AMD SPI0 hardware capabilities.
- Utilize efficient kernel APIs to streamline SPI I/O operations for
enhanced performance.
- Refine the set tx/rx count functions to optimize SPI I/O throughput.
- Minimize the number of data read calls by efficiently retrieving data
from FIFO queues, improving SPI I/O efficiency.
- Add changes to support AMD HID2 SPI controller and update SPI-MEM support
function to reflect AMD HID2 hardware capabilities.
- Add changes to set SPI controller address mode before initiating the
commands
- Add changes to implement HIDDMA read operation support for HID2 SPI
controller
+295
-30
+295
-30
drivers/spi/spi-amd.c
+295
-30
drivers/spi/spi-amd.c
···
7
7
// Author: Sanjay R Mehta <sanju.mehta@amd.com>
8
8
9
9
#include <linux/acpi.h>
10
+
#include <linux/delay.h>
11
+
#include <linux/dma-mapping.h>
10
12
#include <linux/init.h>
13
+
#include <linux/io-64-nonatomic-lo-hi.h>
14
+
#include <linux/iopoll.h>
11
15
#include <linux/module.h>
12
16
#include <linux/platform_device.h>
13
-
#include <linux/delay.h>
14
17
#include <linux/spi/spi.h>
15
-
#include <linux/iopoll.h>
16
18
#include <linux/spi/spi-mem.h>
17
19
18
20
#define AMD_SPI_CTRL0_REG 0x00
···
35
33
#define AMD_SPI_TX_COUNT_REG 0x48
36
34
#define AMD_SPI_RX_COUNT_REG 0x4B
37
35
#define AMD_SPI_STATUS_REG 0x4C
36
+
#define AMD_SPI_ADDR32CTRL_REG 0x50
38
37
39
38
#define AMD_SPI_FIFO_SIZE 70
40
39
#define AMD_SPI_MEM_SIZE 200
41
40
#define AMD_SPI_MAX_DATA 64
41
+
#define AMD_SPI_HID2_DMA_SIZE 4096
42
42
43
43
#define AMD_SPI_ENA_REG 0x20
44
44
#define AMD_SPI_ALT_SPD_SHIFT 20
···
51
47
#define AMD_SPI_SPD7_SHIFT 8
52
48
#define AMD_SPI_SPD7_MASK GENMASK(13, AMD_SPI_SPD7_SHIFT)
53
49
50
+
#define AMD_SPI_HID2_INPUT_RING_BUF0 0X100
51
+
#define AMD_SPI_HID2_CNTRL 0x150
52
+
#define AMD_SPI_HID2_INT_STATUS 0x154
53
+
#define AMD_SPI_HID2_CMD_START 0x156
54
+
#define AMD_SPI_HID2_INT_MASK 0x158
55
+
#define AMD_SPI_HID2_READ_CNTRL0 0x170
56
+
#define AMD_SPI_HID2_READ_CNTRL1 0x174
57
+
#define AMD_SPI_HID2_READ_CNTRL2 0x180
58
+
54
59
#define AMD_SPI_MAX_HZ 100000000
55
60
#define AMD_SPI_MIN_HZ 800000
61
+
62
+
#define AMD_SPI_IO_SLEEP_US 20
63
+
#define AMD_SPI_IO_TIMEOUT_US 2000000
64
+
65
+
/* SPI read command opcodes */
66
+
#define AMD_SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
67
+
#define AMD_SPI_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
68
+
#define AMD_SPI_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
69
+
#define AMD_SPI_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
70
+
#define AMD_SPI_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
71
+
#define AMD_SPI_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
72
+
73
+
/* SPI read command opcodes - 4B address */
74
+
#define AMD_SPI_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
75
+
#define AMD_SPI_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
76
+
#define AMD_SPI_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
77
+
#define AMD_SPI_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
78
+
#define AMD_SPI_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
56
79
57
80
/**
58
81
* enum amd_spi_versions - SPI controller versions
59
82
* @AMD_SPI_V1: AMDI0061 hardware version
60
83
* @AMD_SPI_V2: AMDI0062 hardware version
84
+
* @AMD_HID2_SPI: AMDI0063 hardware version
61
85
*/
62
86
enum amd_spi_versions {
63
87
AMD_SPI_V1 = 1,
64
88
AMD_SPI_V2,
89
+
AMD_HID2_SPI,
65
90
};
66
91
67
92
enum amd_spi_speed {
···
121
88
/**
122
89
* struct amd_spi - SPI driver instance
123
90
* @io_remap_addr: Start address of the SPI controller registers
91
+
* @phy_dma_buf: Physical address of DMA buffer
92
+
* @dma_virt_addr: Virtual address of DMA buffer
124
93
* @version: SPI controller hardware version
125
94
* @speed_hz: Device frequency
126
95
*/
127
96
struct amd_spi {
128
97
void __iomem *io_remap_addr;
98
+
dma_addr_t phy_dma_buf;
99
+
void *dma_virt_addr;
129
100
enum amd_spi_versions version;
130
101
unsigned int speed_hz;
131
102
};
132
103
133
104
static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
134
105
{
135
-
return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
106
+
return readb((u8 __iomem *)amd_spi->io_remap_addr + idx);
136
107
}
137
108
138
109
static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
139
110
{
140
-
iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
111
+
writeb(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
141
112
}
142
113
143
114
static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
···
152
115
amd_spi_writereg8(amd_spi, idx, tmp);
153
116
}
154
117
118
+
static inline u16 amd_spi_readreg16(struct amd_spi *amd_spi, int idx)
119
+
{
120
+
return readw((u8 __iomem *)amd_spi->io_remap_addr + idx);
121
+
}
122
+
123
+
static inline void amd_spi_writereg16(struct amd_spi *amd_spi, int idx, u16 val)
124
+
{
125
+
writew(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
126
+
}
127
+
155
128
static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
156
129
{
157
-
return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
130
+
return readl((u8 __iomem *)amd_spi->io_remap_addr + idx);
158
131
}
159
132
160
133
static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
161
134
{
162
-
iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
135
+
writel(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
136
+
}
137
+
138
+
static inline u64 amd_spi_readreg64(struct amd_spi *amd_spi, int idx)
139
+
{
140
+
return readq((u8 __iomem *)amd_spi->io_remap_addr + idx);
141
+
}
142
+
143
+
static inline void amd_spi_writereg64(struct amd_spi *amd_spi, int idx, u64 val)
144
+
{
145
+
writeq(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
163
146
}
164
147
165
148
static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
···
213
156
AMD_SPI_OPCODE_MASK);
214
157
return 0;
215
158
case AMD_SPI_V2:
159
+
case AMD_HID2_SPI:
216
160
amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
217
161
return 0;
218
162
default:
···
223
165
224
166
static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
225
167
{
226
-
amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
168
+
amd_spi_writereg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count);
227
169
}
228
170
229
171
static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
230
172
{
231
-
amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
173
+
amd_spi_writereg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count);
232
174
}
233
175
234
176
static int amd_spi_busy_wait(struct amd_spi *amd_spi)
···
241
183
reg = AMD_SPI_CTRL0_REG;
242
184
break;
243
185
case AMD_SPI_V2:
186
+
case AMD_HID2_SPI:
244
187
reg = AMD_SPI_STATUS_REG;
245
188
break;
246
189
default:
···
267
208
AMD_SPI_EXEC_CMD);
268
209
return 0;
269
210
case AMD_SPI_V2:
211
+
case AMD_HID2_SPI:
270
212
/* Trigger the command execution */
271
213
amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
272
214
AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
···
409
349
case AMD_SPI_V1:
410
350
break;
411
351
case AMD_SPI_V2:
352
+
case AMD_HID2_SPI:
412
353
amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
413
354
break;
414
355
default:
···
421
360
return message->status;
422
361
}
423
362
363
+
static inline bool amd_is_spi_read_cmd_4b(const u16 op)
364
+
{
365
+
switch (op) {
366
+
case AMD_SPI_OP_READ_FAST_4B:
367
+
case AMD_SPI_OP_READ_1_1_2_4B:
368
+
case AMD_SPI_OP_READ_1_2_2_4B:
369
+
case AMD_SPI_OP_READ_1_1_4_4B:
370
+
case AMD_SPI_OP_READ_1_4_4_4B:
371
+
return true;
372
+
default:
373
+
return false;
374
+
}
375
+
}
376
+
377
+
static inline bool amd_is_spi_read_cmd(const u16 op)
378
+
{
379
+
switch (op) {
380
+
case AMD_SPI_OP_READ:
381
+
case AMD_SPI_OP_READ_FAST:
382
+
case AMD_SPI_OP_READ_1_1_2:
383
+
case AMD_SPI_OP_READ_1_2_2:
384
+
case AMD_SPI_OP_READ_1_1_4:
385
+
case AMD_SPI_OP_READ_1_4_4:
386
+
return true;
387
+
default:
388
+
return amd_is_spi_read_cmd_4b(op);
389
+
}
390
+
}
391
+
424
392
static bool amd_spi_supports_op(struct spi_mem *mem,
425
393
const struct spi_mem_op *op)
426
394
{
395
+
struct amd_spi *amd_spi = spi_controller_get_devdata(mem->spi->controller);
396
+
427
397
/* bus width is number of IO lines used to transmit */
428
-
if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
429
-
op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
398
+
if (op->cmd.buswidth > 1 || op->addr.buswidth > 4)
430
399
return false;
400
+
401
+
/* AMD SPI controllers support quad mode only for read operations */
402
+
if (amd_is_spi_read_cmd(op->cmd.opcode)) {
403
+
if (op->data.buswidth > 4)
404
+
return false;
405
+
406
+
/*
407
+
* HID2 SPI controller supports DMA read up to 4K bytes and
408
+
* doesn't support 4-byte address commands.
409
+
*/
410
+
if (amd_spi->version == AMD_HID2_SPI) {
411
+
if (amd_is_spi_read_cmd_4b(op->cmd.opcode) ||
412
+
op->data.nbytes > AMD_SPI_HID2_DMA_SIZE)
413
+
return false;
414
+
} else if (op->data.nbytes > AMD_SPI_MAX_DATA) {
415
+
return false;
416
+
}
417
+
} else if (op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA) {
418
+
return false;
419
+
}
431
420
432
421
return spi_mem_default_supports_op(mem, op);
433
422
}
434
423
435
424
static int amd_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
436
425
{
437
-
op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_MAX_DATA);
426
+
struct amd_spi *amd_spi = spi_controller_get_devdata(mem->spi->controller);
427
+
428
+
/*
429
+
* HID2 SPI controller DMA read mode supports reading up to 4k
430
+
* bytes in single transaction, where as SPI0 and HID2 SPI
431
+
* controller index mode supports maximum of 64 bytes in a single
432
+
* transaction.
433
+
*/
434
+
if (amd_spi->version == AMD_HID2_SPI && amd_is_spi_read_cmd(op->cmd.opcode))
435
+
op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_HID2_DMA_SIZE);
436
+
else
437
+
op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_MAX_DATA);
438
+
438
439
return 0;
439
440
}
440
441
···
520
397
const struct spi_mem_op *op)
521
398
{
522
399
int base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes;
523
-
u8 *buf = (u8 *)op->data.buf.out;
400
+
u64 *buf_64 = (u64 *)op->data.buf.out;
524
401
u32 nbytes = op->data.nbytes;
402
+
u32 left_data = nbytes;
403
+
u8 *buf;
525
404
int i;
526
405
527
406
amd_spi_set_opcode(amd_spi, op->cmd.opcode);
528
407
amd_spi_set_addr(amd_spi, op);
529
408
530
-
for (i = 0; i < nbytes; i++)
531
-
amd_spi_writereg8(amd_spi, (base_addr + i), buf[i]);
409
+
for (i = 0; left_data >= 8; i++, left_data -= 8)
410
+
amd_spi_writereg64(amd_spi, base_addr + op->dummy.nbytes + (i * 8), *buf_64++);
411
+
412
+
buf = (u8 *)buf_64;
413
+
for (i = 0; i < left_data; i++) {
414
+
amd_spi_writereg8(amd_spi, base_addr + op->dummy.nbytes + nbytes + i - left_data,
415
+
buf[i]);
416
+
}
532
417
533
418
amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->data.nbytes);
534
419
amd_spi_set_rx_count(amd_spi, 0);
···
544
413
amd_spi_execute_opcode(amd_spi);
545
414
}
546
415
416
+
static void amd_spi_hiddma_read(struct amd_spi *amd_spi, const struct spi_mem_op *op)
417
+
{
418
+
u16 hid_cmd_start, val;
419
+
u32 hid_regval;
420
+
421
+
/* Set the opcode in hid2_read_control0 register */
422
+
hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL0);
423
+
hid_regval = (hid_regval & ~GENMASK(7, 0)) | op->cmd.opcode;
424
+
425
+
/*
426
+
* Program the address in the hid2_read_control0 register [8:31]. The address should
427
+
* be written starting from the 8th bit of the register, requiring an 8-bit shift.
428
+
* Additionally, to convert a 2-byte spinand address to a 3-byte address, another
429
+
* 8-bit shift is needed. Therefore, a total shift of 16 bits is required.
430
+
*/
431
+
hid_regval = (hid_regval & ~GENMASK(31, 8)) | (op->addr.val << 16);
432
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL0, hid_regval);
433
+
434
+
/* Configure dummy clock cycles for fast read, dual, quad I/O commands */
435
+
hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL2);
436
+
/* Fast read dummy cycle */
437
+
hid_regval &= ~GENMASK(4, 0);
438
+
439
+
/* Fast read Dual I/O dummy cycle */
440
+
hid_regval &= ~GENMASK(12, 8);
441
+
442
+
/* Fast read Quad I/O dummy cycle */
443
+
hid_regval = (hid_regval & ~GENMASK(20, 16)) | BIT(17);
444
+
445
+
/* Set no of preamble bytecount */
446
+
hid_regval &= ~GENMASK(27, 24);
447
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL2, hid_regval);
448
+
449
+
/*
450
+
* Program the HID2 Input Ring Buffer0. 4k aligned buf_memory_addr[31:12],
451
+
* buf_size[4:0], end_input_ring[5].
452
+
*/
453
+
hid_regval = amd_spi->phy_dma_buf | BIT(5) | BIT(0);
454
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_INPUT_RING_BUF0, hid_regval);
455
+
456
+
/* Program max read length(no of DWs) in hid2_read_control1 register */
457
+
hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL1);
458
+
hid_regval = (hid_regval & ~GENMASK(15, 0)) | ((op->data.nbytes / 4) - 1);
459
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL1, hid_regval);
460
+
461
+
/* Set cmd start bit in hid2_cmd_start register to trigger HID basic read operation */
462
+
hid_cmd_start = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_CMD_START);
463
+
amd_spi_writereg16(amd_spi, AMD_SPI_HID2_CMD_START, (hid_cmd_start | BIT(3)));
464
+
465
+
/* Check interrupt status of HIDDMA basic read operation in hid2_int_status register */
466
+
readw_poll_timeout(amd_spi->io_remap_addr + AMD_SPI_HID2_INT_STATUS, val,
467
+
(val & BIT(3)), AMD_SPI_IO_SLEEP_US, AMD_SPI_IO_TIMEOUT_US);
468
+
469
+
/* Clear the interrupts by writing to hid2_int_status register */
470
+
val = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_INT_STATUS);
471
+
amd_spi_writereg16(amd_spi, AMD_SPI_HID2_INT_STATUS, val);
472
+
}
473
+
547
474
static void amd_spi_mem_data_in(struct amd_spi *amd_spi,
548
475
const struct spi_mem_op *op)
549
476
{
550
-
int offset = (op->addr.nbytes == 0) ? 0 : 1;
551
-
u8 *buf = (u8 *)op->data.buf.in;
477
+
int base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes;
478
+
u64 *buf_64 = (u64 *)op->data.buf.in;
552
479
u32 nbytes = op->data.nbytes;
553
-
int base_addr, i;
480
+
u32 left_data = nbytes;
481
+
u32 data;
482
+
u8 *buf;
483
+
int i;
554
484
555
-
base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes + offset;
485
+
/*
486
+
* Condition for using HID read mode. Only for reading complete page data, use HID read.
487
+
* Use index mode otherwise.
488
+
*/
489
+
if (amd_spi->version == AMD_HID2_SPI && amd_is_spi_read_cmd(op->cmd.opcode)) {
490
+
amd_spi_hiddma_read(amd_spi, op);
556
491
557
-
amd_spi_set_opcode(amd_spi, op->cmd.opcode);
558
-
amd_spi_set_addr(amd_spi, op);
559
-
amd_spi_set_tx_count(amd_spi, op->addr.nbytes);
560
-
amd_spi_set_rx_count(amd_spi, op->data.nbytes + 1);
561
-
amd_spi_clear_fifo_ptr(amd_spi);
562
-
amd_spi_execute_opcode(amd_spi);
563
-
amd_spi_busy_wait(amd_spi);
492
+
for (i = 0; left_data >= 8; i++, left_data -= 8)
493
+
*buf_64++ = readq((u8 __iomem *)amd_spi->dma_virt_addr + (i * 8));
564
494
565
-
for (i = 0; i < nbytes; i++)
566
-
buf[i] = amd_spi_readreg8(amd_spi, base_addr + i);
495
+
buf = (u8 *)buf_64;
496
+
for (i = 0; i < left_data; i++)
497
+
buf[i] = readb((u8 __iomem *)amd_spi->dma_virt_addr +
498
+
(nbytes - left_data + i));
499
+
500
+
/* Reset HID RX memory logic */
501
+
data = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_CNTRL);
502
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, data | BIT(5));
503
+
} else {
504
+
/* Index mode */
505
+
amd_spi_set_opcode(amd_spi, op->cmd.opcode);
506
+
amd_spi_set_addr(amd_spi, op);
507
+
amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->dummy.nbytes);
508
+
509
+
for (i = 0; i < op->dummy.nbytes; i++)
510
+
amd_spi_writereg8(amd_spi, (base_addr + i), 0xff);
511
+
512
+
amd_spi_set_rx_count(amd_spi, op->data.nbytes);
513
+
amd_spi_clear_fifo_ptr(amd_spi);
514
+
amd_spi_execute_opcode(amd_spi);
515
+
amd_spi_busy_wait(amd_spi);
516
+
517
+
for (i = 0; left_data >= 8; i++, left_data -= 8)
518
+
*buf_64++ = amd_spi_readreg64(amd_spi, base_addr + op->dummy.nbytes +
519
+
(i * 8));
520
+
521
+
buf = (u8 *)buf_64;
522
+
for (i = 0; i < left_data; i++)
523
+
buf[i] = amd_spi_readreg8(amd_spi, base_addr + op->dummy.nbytes +
524
+
nbytes + i - left_data);
525
+
}
526
+
527
+
}
528
+
529
+
static void amd_set_spi_addr_mode(struct amd_spi *amd_spi,
530
+
const struct spi_mem_op *op)
531
+
{
532
+
u32 val = amd_spi_readreg32(amd_spi, AMD_SPI_ADDR32CTRL_REG);
533
+
534
+
if (amd_is_spi_read_cmd_4b(op->cmd.opcode))
535
+
amd_spi_writereg32(amd_spi, AMD_SPI_ADDR32CTRL_REG, val | BIT(0));
536
+
else
537
+
amd_spi_writereg32(amd_spi, AMD_SPI_ADDR32CTRL_REG, val & ~BIT(0));
567
538
}
568
539
569
540
static int amd_spi_exec_mem_op(struct spi_mem *mem,
···
679
446
ret = amd_set_spi_freq(amd_spi, mem->spi->max_speed_hz);
680
447
if (ret)
681
448
return ret;
449
+
450
+
if (amd_spi->version == AMD_SPI_V2)
451
+
amd_set_spi_addr_mode(amd_spi, op);
682
452
683
453
switch (op->data.dir) {
684
454
case SPI_MEM_DATA_IN:
···
725
489
return AMD_SPI_FIFO_SIZE;
726
490
}
727
491
492
+
static int amd_spi_setup_hiddma(struct amd_spi *amd_spi, struct device *dev)
493
+
{
494
+
u32 hid_regval;
495
+
496
+
/* Allocate DMA buffer to use for HID basic read operation */
497
+
amd_spi->dma_virt_addr = dma_alloc_coherent(dev, AMD_SPI_HID2_DMA_SIZE,
498
+
&amd_spi->phy_dma_buf, GFP_KERNEL);
499
+
if (!amd_spi->dma_virt_addr)
500
+
return -ENOMEM;
501
+
502
+
/*
503
+
* Enable interrupts and set mask bits in hid2_int_mask register to generate interrupt
504
+
* properly for HIDDMA basic read operations.
505
+
*/
506
+
hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_INT_MASK);
507
+
hid_regval = (hid_regval & GENMASK(31, 8)) | BIT(19);
508
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_INT_MASK, hid_regval);
509
+
510
+
/* Configure buffer unit(4k) in hid2_control register */
511
+
hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_CNTRL);
512
+
amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, hid_regval & ~BIT(3));
513
+
514
+
return 0;
515
+
}
516
+
728
517
static int amd_spi_probe(struct platform_device *pdev)
729
518
{
730
519
struct device *dev = &pdev->dev;
···
773
512
amd_spi->version = (uintptr_t) device_get_match_data(dev);
774
513
775
514
/* Initialize the spi_controller fields */
776
-
host->bus_num = 0;
515
+
host->bus_num = (amd_spi->version == AMD_HID2_SPI) ? 2 : 0;
777
516
host->num_chipselect = 4;
778
-
host->mode_bits = 0;
517
+
host->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD;
779
518
host->flags = SPI_CONTROLLER_HALF_DUPLEX;
780
519
host->max_speed_hz = AMD_SPI_MAX_HZ;
781
520
host->min_speed_hz = AMD_SPI_MIN_HZ;
···
790
529
if (err)
791
530
return dev_err_probe(dev, err, "error registering SPI controller\n");
792
531
793
-
return 0;
532
+
if (amd_spi->version == AMD_HID2_SPI)
533
+
err = amd_spi_setup_hiddma(amd_spi, dev);
534
+
535
+
return err;
794
536
}
795
537
796
538
#ifdef CONFIG_ACPI
797
539
static const struct acpi_device_id spi_acpi_match[] = {
798
540
{ "AMDI0061", AMD_SPI_V1 },
799
541
{ "AMDI0062", AMD_SPI_V2 },
542
+
{ "AMDI0063", AMD_HID2_SPI },
800
543
{},
801
544
};
802
545
MODULE_DEVICE_TABLE(acpi, spi_acpi_match);