Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx

+1

MAINTAINERS

··· 2126 2126 F: fs/dlm/ 2127 2127 2128 2128 DMA GENERIC OFFLOAD ENGINE SUBSYSTEM 2129 + M: Vinod Koul <vinod.koul@intel.com> 2129 2130 M: Dan Williams <dan.j.williams@intel.com> 2130 2131 S: Supported 2131 2132 F: drivers/dma/

+33 -20

drivers/dma/amba-pl08x.c

··· 79 79 #include <linux/module.h> 80 80 #include <linux/interrupt.h> 81 81 #include <linux/slab.h> 82 + #include <linux/delay.h> 82 83 #include <linux/dmapool.h> 83 84 #include <linux/dmaengine.h> 84 85 #include <linux/amba/bus.h> ··· 236 235 } 237 236 238 237 /* 239 - * Overall DMAC remains enabled always. 238 + * Pause the channel by setting the HALT bit. 240 239 * 241 - * Disabling individual channels could lose data. 240 + * For M->P transfers, pause the DMAC first and then stop the peripheral - 241 + * the FIFO can only drain if the peripheral is still requesting data. 242 + * (note: this can still timeout if the DMAC FIFO never drains of data.) 242 243 * 243 - * Disable the peripheral DMA after disabling the DMAC in order to allow 244 - * the DMAC FIFO to drain, and hence allow the channel to show inactive 244 + * For P->M transfers, disable the peripheral first to stop it filling 245 + * the DMAC FIFO, and then pause the DMAC. 245 246 */ 246 247 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) 247 248 { 248 249 u32 val; 250 + int timeout; 249 251 250 252 /* Set the HALT bit and wait for the FIFO to drain */ 251 253 val = readl(ch->base + PL080_CH_CONFIG); ··· 256 252 writel(val, ch->base + PL080_CH_CONFIG); 257 253 258 254 /* Wait for channel inactive */ 259 - while (pl08x_phy_channel_busy(ch)) 260 - cpu_relax(); 255 + for (timeout = 1000; timeout; timeout--) { 256 + if (!pl08x_phy_channel_busy(ch)) 257 + break; 258 + udelay(1); 259 + } 260 + if (pl08x_phy_channel_busy(ch)) 261 + pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); 261 262 } 262 263 263 264 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) ··· 276 267 } 277 268 278 269 279 - /* Stops the channel */ 280 - static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch) 270 + /* 271 + * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and 272 + * clears any pending interrupt status. This should not be used for 273 + * an on-going transfer, but as a method of shutting down a channel 274 + * (eg, when it's no longer used) or terminating a transfer. 275 + */ 276 + static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, 277 + struct pl08x_phy_chan *ch) 281 278 { 282 - u32 val; 279 + u32 val = readl(ch->base + PL080_CH_CONFIG); 283 280 284 - pl08x_pause_phy_chan(ch); 281 + val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | 282 + PL080_CONFIG_TC_IRQ_MASK); 285 283 286 - /* Disable channel */ 287 - val = readl(ch->base + PL080_CH_CONFIG); 288 - val &= ~PL080_CONFIG_ENABLE; 289 - val &= ~PL080_CONFIG_ERR_IRQ_MASK; 290 - val &= ~PL080_CONFIG_TC_IRQ_MASK; 291 284 writel(val, ch->base + PL080_CH_CONFIG); 285 + 286 + writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); 287 + writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); 292 288 } 293 289 294 290 static inline u32 get_bytes_in_cctl(u32 cctl) ··· 418 404 { 419 405 unsigned long flags; 420 406 407 + spin_lock_irqsave(&ch->lock, flags); 408 + 421 409 /* Stop the channel and clear its interrupts */ 422 - pl08x_stop_phy_chan(ch); 423 - writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR); 424 - writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR); 410 + pl08x_terminate_phy_chan(pl08x, ch); 425 411 426 412 /* Mark it as free */ 427 - spin_lock_irqsave(&ch->lock, flags); 428 413 ch->serving = NULL; 429 414 spin_unlock_irqrestore(&ch->lock, flags); 430 415 } ··· 1462 1449 plchan->state = PL08X_CHAN_IDLE; 1463 1450 1464 1451 if (plchan->phychan) { 1465 - pl08x_stop_phy_chan(plchan->phychan); 1452 + pl08x_terminate_phy_chan(pl08x, plchan->phychan); 1466 1453 1467 1454 /* 1468 1455 * Mark physical channel as free and free any slave

+22 -4

drivers/dma/imx-dma.c

··· 49 49 50 50 struct imxdma_engine { 51 51 struct device *dev; 52 + struct device_dma_parameters dma_parms; 52 53 struct dma_device dma_device; 53 54 struct imxdma_channel channel[MAX_DMA_CHANNELS]; 54 55 }; ··· 243 242 else 244 243 dmamode = DMA_MODE_WRITE; 245 244 245 + switch (imxdmac->word_size) { 246 + case DMA_SLAVE_BUSWIDTH_4_BYTES: 247 + if (sgl->length & 3 || sgl->dma_address & 3) 248 + return NULL; 249 + break; 250 + case DMA_SLAVE_BUSWIDTH_2_BYTES: 251 + if (sgl->length & 1 || sgl->dma_address & 1) 252 + return NULL; 253 + break; 254 + case DMA_SLAVE_BUSWIDTH_1_BYTE: 255 + break; 256 + default: 257 + return NULL; 258 + } 259 + 246 260 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len, 247 261 dma_length, imxdmac->per_address, dmamode); 248 262 if (ret) ··· 345 329 346 330 INIT_LIST_HEAD(&imxdma->dma_device.channels); 347 331 332 + dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); 333 + dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); 334 + 348 335 /* Initialize channel parameters */ 349 336 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 350 337 struct imxdma_channel *imxdmac = &imxdma->channel[i]; ··· 365 346 imxdmac->imxdma = imxdma; 366 347 spin_lock_init(&imxdmac->lock); 367 348 368 - dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); 369 - dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); 370 - 371 349 imxdmac->chan.device = &imxdma->dma_device; 372 - imxdmac->chan.chan_id = i; 373 350 imxdmac->channel = i; 374 351 375 352 /* Add the channel to the DMAC list */ ··· 384 369 imxdma->dma_device.device_issue_pending = imxdma_issue_pending; 385 370 386 371 platform_set_drvdata(pdev, imxdma); 372 + 373 + imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; 374 + dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); 387 375 388 376 ret = dma_async_device_register(&imxdma->dma_device); 389 377 if (ret) {

+47 -41

drivers/dma/imx-sdma.c

··· 230 230 * struct sdma_channel - housekeeping for a SDMA channel 231 231 * 232 232 * @sdma pointer to the SDMA engine for this channel 233 - * @channel the channel number, matches dmaengine chan_id 233 + * @channel the channel number, matches dmaengine chan_id + 1 234 234 * @direction transfer type. Needed for setting SDMA script 235 235 * @peripheral_type Peripheral type. Needed for setting SDMA script 236 236 * @event_id0 aka dma request line ··· 301 301 302 302 struct sdma_engine { 303 303 struct device *dev; 304 + struct device_dma_parameters dma_parms; 304 305 struct sdma_channel channel[MAX_DMA_CHANNELS]; 305 306 struct sdma_channel_control *channel_control; 306 307 void __iomem *regs; ··· 450 449 if (bd->mode.status & BD_RROR) 451 450 sdmac->status = DMA_ERROR; 452 451 else 453 - sdmac->status = DMA_SUCCESS; 452 + sdmac->status = DMA_IN_PROGRESS; 454 453 455 454 bd->mode.status |= BD_DONE; 456 455 sdmac->buf_tail++; ··· 771 770 __raw_writel(1 << channel, sdma->regs + SDMA_H_START); 772 771 } 773 772 774 - static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdma) 773 + static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac) 775 774 { 776 - dma_cookie_t cookie = sdma->chan.cookie; 775 + dma_cookie_t cookie = sdmac->chan.cookie; 777 776 778 777 if (++cookie < 0) 779 778 cookie = 1; 780 779 781 - sdma->chan.cookie = cookie; 782 - sdma->desc.cookie = cookie; 780 + sdmac->chan.cookie = cookie; 781 + sdmac->desc.cookie = cookie; 783 782 784 783 return cookie; 785 784 } ··· 799 798 800 799 cookie = sdma_assign_cookie(sdmac); 801 800 802 - sdma_enable_channel(sdma, tx->chan->chan_id); 801 + sdma_enable_channel(sdma, sdmac->channel); 803 802 804 803 spin_unlock_irq(&sdmac->lock); 805 804 ··· 811 810 struct sdma_channel *sdmac = to_sdma_chan(chan); 812 811 struct imx_dma_data *data = chan->private; 813 812 int prio, ret; 814 - 815 - /* No need to execute this for internal channel 0 */ 816 - if (chan->chan_id == 0) 817 - return 0; 818 813 819 814 if (!data) 820 815 return -EINVAL; ··· 876 879 struct sdma_channel *sdmac = to_sdma_chan(chan); 877 880 struct sdma_engine *sdma = sdmac->sdma; 878 881 int ret, i, count; 879 - int channel = chan->chan_id; 882 + int channel = sdmac->channel; 880 883 struct scatterlist *sg; 881 884 882 885 if (sdmac->status == DMA_IN_PROGRESS) ··· 921 924 ret = -EINVAL; 922 925 goto err_out; 923 926 } 924 - if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 927 + 928 + switch (sdmac->word_size) { 929 + case DMA_SLAVE_BUSWIDTH_4_BYTES: 925 930 bd->mode.command = 0; 926 - else 927 - bd->mode.command = sdmac->word_size; 931 + if (count & 3 || sg->dma_address & 3) 932 + return NULL; 933 + break; 934 + case DMA_SLAVE_BUSWIDTH_2_BYTES: 935 + bd->mode.command = 2; 936 + if (count & 1 || sg->dma_address & 1) 937 + return NULL; 938 + break; 939 + case DMA_SLAVE_BUSWIDTH_1_BYTE: 940 + bd->mode.command = 1; 941 + break; 942 + default: 943 + return NULL; 944 + } 928 945 929 946 param = BD_DONE | BD_EXTD | BD_CONT; 930 947 931 - if (sdmac->flags & IMX_DMA_SG_LOOP) { 948 + if (i + 1 == sg_len) { 932 949 param |= BD_INTR; 933 - if (i + 1 == sg_len) 934 - param |= BD_WRAP; 950 + param |= BD_LAST; 951 + param &= ~BD_CONT; 935 952 } 936 - 937 - if (i + 1 == sg_len) 938 - param |= BD_INTR; 939 953 940 954 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n", 941 955 i, count, sg->dma_address, ··· 961 953 962 954 return &sdmac->desc; 963 955 err_out: 956 + sdmac->status = DMA_ERROR; 964 957 return NULL; 965 958 } 966 959 ··· 972 963 struct sdma_channel *sdmac = to_sdma_chan(chan); 973 964 struct sdma_engine *sdma = sdmac->sdma; 974 965 int num_periods = buf_len / period_len; 975 - int channel = chan->chan_id; 966 + int channel = sdmac->channel; 976 967 int ret, i = 0, buf = 0; 977 968 978 969 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); ··· 1075 1066 { 1076 1067 struct sdma_channel *sdmac = to_sdma_chan(chan); 1077 1068 dma_cookie_t last_used; 1078 - enum dma_status ret; 1079 1069 1080 1070 last_used = chan->cookie; 1081 1071 1082 - ret = dma_async_is_complete(cookie, sdmac->last_completed, last_used); 1083 1072 dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0); 1084 1073 1085 - return ret; 1074 + return sdmac->status; 1086 1075 } 1087 1076 1088 1077 static void sdma_issue_pending(struct dma_chan *chan) ··· 1142 1135 /* download the RAM image for SDMA */ 1143 1136 sdma_load_script(sdma, ram_code, 1144 1137 header->ram_code_size, 1145 - sdma->script_addrs->ram_code_start_addr); 1138 + addr->ram_code_start_addr); 1146 1139 clk_disable(sdma->clk); 1147 1140 1148 1141 sdma_add_scripts(sdma, addr); ··· 1244 1237 struct resource *iores; 1245 1238 struct sdma_platform_data *pdata = pdev->dev.platform_data; 1246 1239 int i; 1247 - dma_cap_mask_t mask; 1248 1240 struct sdma_engine *sdma; 1249 1241 1250 1242 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); ··· 1286 1280 1287 1281 sdma->version = pdata->sdma_version; 1288 1282 1283 + dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1284 + dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1285 + 1289 1286 INIT_LIST_HEAD(&sdma->dma_device.channels); 1290 1287 /* Initialize channel parameters */ 1291 1288 for (i = 0; i < MAX_DMA_CHANNELS; i++) { ··· 1297 1288 sdmac->sdma = sdma; 1298 1289 spin_lock_init(&sdmac->lock); 1299 1290 1300 - dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1301 - dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1302 - 1303 1291 sdmac->chan.device = &sdma->dma_device; 1304 - sdmac->chan.chan_id = i; 1305 1292 sdmac->channel = i; 1306 1293 1307 - /* Add the channel to the DMAC list */ 1308 - list_add_tail(&sdmac->chan.device_node, &sdma->dma_device.channels); 1294 + /* 1295 + * Add the channel to the DMAC list. Do not add channel 0 though 1296 + * because we need it internally in the SDMA driver. This also means 1297 + * that channel 0 in dmaengine counting matches sdma channel 1. 1298 + */ 1299 + if (i) 1300 + list_add_tail(&sdmac->chan.device_node, 1301 + &sdma->dma_device.channels); 1309 1302 } 1310 1303 1311 1304 ret = sdma_init(sdma); ··· 1328 1317 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 1329 1318 sdma->dma_device.device_control = sdma_control; 1330 1319 sdma->dma_device.device_issue_pending = sdma_issue_pending; 1320 + sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1321 + dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1331 1322 1332 1323 ret = dma_async_device_register(&sdma->dma_device); 1333 1324 if (ret) { 1334 1325 dev_err(&pdev->dev, "unable to register\n"); 1335 1326 goto err_init; 1336 1327 } 1337 - 1338 - /* request channel 0. This is an internal control channel 1339 - * to the SDMA engine and not available to clients. 1340 - */ 1341 - dma_cap_zero(mask); 1342 - dma_cap_set(DMA_SLAVE, mask); 1343 - dma_request_channel(mask, NULL, NULL); 1344 1328 1345 1329 dev_info(sdma->dev, "initialized\n"); 1346 1330 ··· 1354 1348 err_request_region: 1355 1349 err_irq: 1356 1350 kfree(sdma); 1357 - return 0; 1351 + return ret; 1358 1352 } 1359 1353 1360 1354 static int __exit sdma_remove(struct platform_device *pdev)

-50

drivers/dma/ipu/ipu_idmac.c

··· 1145 1145 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN); 1146 1146 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN); 1147 1147 1148 - /* 1149 - * Problem (observed with channel DMAIC_7): after enabling the channel 1150 - * and initialising buffers, there comes an interrupt with current still 1151 - * pointing at buffer 0, whereas it should use buffer 0 first and only 1152 - * generate an interrupt when it is done, then current should already 1153 - * point to buffer 1. This spurious interrupt also comes on channel 1154 - * DMASDC_0. With DMAIC_7 normally, is we just leave the ISR after the 1155 - * first interrupt, there comes the second with current correctly 1156 - * pointing to buffer 1 this time. But sometimes this second interrupt 1157 - * doesn't come and the channel hangs. Clearing BUFx_RDY when disabling 1158 - * the channel seems to prevent the channel from hanging, but it doesn't 1159 - * prevent the spurious interrupt. This might also be unsafe. Think 1160 - * about the IDMAC controller trying to switch to a buffer, when we 1161 - * clear the ready bit, and re-enable it a moment later. 1162 - */ 1163 - reg = idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY); 1164 - idmac_write_ipureg(ipu, 0, IPU_CHA_BUF0_RDY); 1165 - idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF0_RDY); 1166 - 1167 - reg = idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY); 1168 - idmac_write_ipureg(ipu, 0, IPU_CHA_BUF1_RDY); 1169 - idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF1_RDY); 1170 - 1171 1148 spin_unlock_irqrestore(&ipu->lock, flags); 1172 1149 1173 1150 return 0; ··· 1223 1246 1224 1247 /* Other interrupts do not interfere with this channel */ 1225 1248 spin_lock(&ichan->lock); 1226 - if (unlikely(chan_id != IDMAC_SDC_0 && chan_id != IDMAC_SDC_1 && 1227 - ((curbuf >> chan_id) & 1) == ichan->active_buffer && 1228 - !list_is_last(ichan->queue.next, &ichan->queue))) { 1229 - int i = 100; 1230 - 1231 - /* This doesn't help. See comment in ipu_disable_channel() */ 1232 - while (--i) { 1233 - curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF); 1234 - if (((curbuf >> chan_id) & 1) != ichan->active_buffer) 1235 - break; 1236 - cpu_relax(); 1237 - } 1238 - 1239 - if (!i) { 1240 - spin_unlock(&ichan->lock); 1241 - dev_dbg(dev, 1242 - "IRQ on active buffer on channel %x, active " 1243 - "%d, ready %x, %x, current %x!\n", chan_id, 1244 - ichan->active_buffer, ready0, ready1, curbuf); 1245 - return IRQ_NONE; 1246 - } else 1247 - dev_dbg(dev, 1248 - "Buffer deactivated on channel %x, active " 1249 - "%d, ready %x, %x, current %x, rest %d!\n", chan_id, 1250 - ichan->active_buffer, ready0, ready1, curbuf, i); 1251 - } 1252 - 1253 1249 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) || 1254 1250 (!ichan->active_buffer && (ready0 >> chan_id) & 1) 1255 1251 )) {

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