tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ES8316 audio codec fixes on Rock5B

Merge series from Cristian Ciocaltea <cristian.ciocaltea@collabora.com>:

This patch series handles a few issues related to the ES8316 audio
codec, discovered while doing some testing on the Rock 5B board.

Mark Brown b48aa6a3 f2d4aa7e

+3742 -1865
+5
.mailmap
··· 364 364 Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de> 365 365 Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.com> 366 366 Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> 367 + Nikolay Aleksandrov <razor@blackwall.org> <naleksan@redhat.com> 368 + Nikolay Aleksandrov <razor@blackwall.org> <nikolay@redhat.com> 369 + Nikolay Aleksandrov <razor@blackwall.org> <nikolay@cumulusnetworks.com> 370 + Nikolay Aleksandrov <razor@blackwall.org> <nikolay@nvidia.com> 371 + Nikolay Aleksandrov <razor@blackwall.org> <nikolay@isovalent.com> 367 372 Oleksandr Natalenko <oleksandr@natalenko.name> <oleksandr@redhat.com> 368 373 Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net> 369 374 Oleksij Rempel <linux@rempel-privat.de> <external.Oleksij.Rempel@de.bosch.com>
+4
CREDITS
··· 1706 1706 S: D-69126 Heidelberg 1707 1707 S: Germany 1708 1708 1709 + N: Neil Horman 1710 + M: nhorman@tuxdriver.com 1711 + D: SCTP protocol maintainer. 1712 + 1709 1713 N: Simon Horman 1710 1714 M: horms@verge.net.au 1711 1715 D: Renesas ARM/ARM64 SoC maintainer
+27 -22
Documentation/admin-guide/quickly-build-trimmed-linux.rst
··· 215 215 reduce the compile time enormously, especially if you are running an 216 216 universal kernel from a commodity Linux distribution. 217 217 218 - There is a catch: the make target 'localmodconfig' will disable kernel 219 - features you have not directly or indirectly through some program utilized 220 - since you booted the system. You can reduce or nearly eliminate that risk by 221 - using tricks outlined in the reference section; for quick testing purposes 222 - that risk is often negligible, but it is an aspect you want to keep in mind 223 - in case your kernel behaves oddly. 218 + There is a catch: 'localmodconfig' is likely to disable kernel features you 219 + did not use since you booted your Linux -- like drivers for currently 220 + disconnected peripherals or a virtualization software not haven't used yet. 221 + You can reduce or nearly eliminate that risk with tricks the reference 222 + section outlines; but when building a kernel just for quick testing purposes 223 + it is often negligible if such features are missing. But you should keep that 224 + aspect in mind when using a kernel built with this make target, as it might 225 + be the reason why something you only use occasionally stopped working. 224 226 225 227 [:ref:`details<configuration>`] 226 228 ··· 273 271 does nothing at all; in that case you have to manually install your kernel, 274 272 as outlined in the reference section. 275 273 274 + If you are running a immutable Linux distribution, check its documentation 275 + and the web to find out how to install your own kernel there. 276 + 276 277 [:ref:`details<install>`] 277 278 278 279 .. _another_sbs: ··· 296 291 version you care about, as git otherwise might retrieve the entire commit 297 292 history:: 298 293 299 - git fetch --shallow-exclude=v6.1 origin 294 + git fetch --shallow-exclude=v6.0 origin 300 295 301 - If you modified the sources (for example by applying a patch), you now need 302 - to discard those modifications; that's because git otherwise will not be able 303 - to switch to the sources of another version due to potential conflicting 304 - changes:: 296 + Now switch to the version you are interested in -- but be aware the command 297 + used here will discard any modifications you performed, as they would 298 + conflict with the sources you want to checkout:: 305 299 306 - git reset --hard 307 - 308 - Now checkout the version you are interested in, as explained above:: 309 - 310 - git checkout --detach origin/master 300 + git checkout --force --detach origin/master 311 301 312 302 At this point you might want to patch the sources again or set/modify a build 313 - tag, as explained earlier; afterwards adjust the build configuration to the 314 - new codebase and build your next kernel:: 303 + tag, as explained earlier. Afterwards adjust the build configuration to the 304 + new codebase using olddefconfig, which will now adjust the configuration file 305 + you prepared earlier using localmodconfig (~/linux/.config) for your next 306 + kernel:: 315 307 316 308 # reminder: if you want to apply patches, do it at this point 317 309 # reminder: you might want to update your build tag at this point 318 310 make olddefconfig 311 + 312 + Now build your kernel:: 313 + 319 314 make -j $(nproc --all) 320 315 321 - Install the kernel as outlined above:: 316 + Afterwards install the kernel as outlined above:: 322 317 323 318 command -v installkernel && sudo make modules_install install 324 319 ··· 589 584 curl -L \ 590 585 https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/clone.bundle \ 591 586 -o linux-stable.git.bundle 592 - git clone clone.bundle ~/linux/ 587 + git clone linux-stable.git.bundle ~/linux/ 593 588 rm linux-stable.git.bundle 594 589 cd ~/linux/ 595 - git remote set-url origin 596 - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git 590 + git remote set-url origin \ 591 + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git 597 592 git fetch origin 598 593 git checkout --detach origin/master 599 594
+3 -3
Documentation/cdrom/index.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 2 3 - ===== 4 - cdrom 5 - ===== 3 + ====== 4 + CD-ROM 5 + ====== 6 6 7 7 .. toctree:: 8 8 :maxdepth: 1
+1 -1
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
··· 32 32 maxItems: 1 33 33 34 34 iommus: 35 - maxItems: 1 35 + maxItems: 4 36 36 37 37 power-domains: 38 38 maxItems: 1
+12
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
··· 82 82 Indicates if the DSI controller is driving a panel which needs 83 83 2 DSI links. 84 84 85 + qcom,master-dsi: 86 + type: boolean 87 + description: | 88 + Indicates if the DSI controller is the master DSI controller when 89 + qcom,dual-dsi-mode enabled. 90 + 91 + qcom,sync-dual-dsi: 92 + type: boolean 93 + description: | 94 + Indicates if the DSI controller needs to sync the other DSI controller 95 + with MIPI DCS commands when qcom,dual-dsi-mode enabled. 96 + 85 97 assigned-clocks: 86 98 minItems: 2 87 99 maxItems: 4
+15 -4
Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml
··· 21 21 22 22 st,can-primary: 23 23 description: 24 - Primary and secondary mode of the bxCAN peripheral is only relevant 25 - if the chip has two CAN peripherals. In that case they share some 26 - of the required logic. 24 + Primary mode of the bxCAN peripheral is only relevant if the chip has 25 + two CAN peripherals in dual CAN configuration. In that case they share 26 + some of the required logic. 27 + Not to be used if the peripheral is in single CAN configuration. 27 28 To avoid misunderstandings, it should be noted that ST documentation 28 - uses the terms master/slave instead of primary/secondary. 29 + uses the terms master instead of primary. 30 + type: boolean 31 + 32 + st,can-secondary: 33 + description: 34 + Secondary mode of the bxCAN peripheral is only relevant if the chip 35 + has two CAN peripherals in dual CAN configuration. In that case they 36 + share some of the required logic. 37 + Not to be used if the peripheral is in single CAN configuration. 38 + To avoid misunderstandings, it should be noted that ST documentation 39 + uses the terms slave instead of secondary. 29 40 type: boolean 30 41 31 42 reg:
+1 -2
Documentation/filesystems/ramfs-rootfs-initramfs.rst
··· 6 6 7 7 October 17, 2005 8 8 9 - Rob Landley <rob@landley.net> 10 - ============================= 9 + :Author: Rob Landley <rob@landley.net> 11 10 12 11 What is ramfs? 13 12 --------------
+4
Documentation/filesystems/sharedsubtree.rst
··· 147 147 148 148 149 149 3) Setting mount states 150 + ----------------------- 150 151 151 152 The mount command (util-linux package) can be used to set mount 152 153 states:: ··· 613 612 614 613 615 614 6) Quiz 615 + ------- 616 616 617 617 A. What is the result of the following command sequence? 618 618 ··· 675 673 /mnt/1/test be? 676 674 677 675 7) FAQ 676 + ------ 678 677 679 678 Q1. Why is bind mount needed? How is it different from symbolic links? 680 679 symbolic links can get stale if the destination mount gets ··· 844 841 tmp usr tmp usr tmp usr 845 842 846 843 8) Implementation 844 + ----------------- 847 845 848 846 8A) Datastructure 849 847
+1 -1
Documentation/fpga/index.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 2 3 3 ==== 4 - fpga 4 + FPGA 5 5 ==== 6 6 7 7 .. toctree::
+1 -1
Documentation/locking/index.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 2 3 3 ======= 4 - locking 4 + Locking 5 5 ======= 6 6 7 7 .. toctree::
+1 -1
Documentation/pcmcia/index.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 2 3 3 ====== 4 - pcmcia 4 + PCMCIA 5 5 ====== 6 6 7 7 .. toctree::
-1
Documentation/s390/vfio-ap.rst
··· 551 551 * IOMMU_SUPPORT 552 552 * S390 553 553 * ZCRYPT 554 - * S390_AP_IOMMU 555 554 * VFIO 556 555 * KVM 557 556
+1 -1
Documentation/staging/crc32.rst
··· 1 1 ================================= 2 - brief tutorial on CRC computation 2 + Brief tutorial on CRC computation 3 3 ================================= 4 4 5 5 A CRC is a long-division remainder. You add the CRC to the message,
+1 -1
Documentation/timers/index.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 2 3 3 ====== 4 - timers 4 + Timers 5 5 ====== 6 6 7 7 .. toctree::
+7 -11
MAINTAINERS
··· 1677 1677 F: drivers/soc/versatile/ 1678 1678 1679 1679 ARM KOMEDA DRM-KMS DRIVER 1680 - M: James (Qian) Wang <james.qian.wang@arm.com> 1681 1680 M: Liviu Dudau <liviu.dudau@arm.com> 1682 - M: Mihail Atanassov <mihail.atanassov@arm.com> 1683 - L: Mali DP Maintainers <malidp@foss.arm.com> 1684 1681 S: Supported 1685 1682 T: git git://anongit.freedesktop.org/drm/drm-misc 1686 1683 F: Documentation/devicetree/bindings/display/arm,komeda.yaml ··· 1698 1701 1699 1702 ARM MALI-DP DRM DRIVER 1700 1703 M: Liviu Dudau <liviu.dudau@arm.com> 1701 - M: Brian Starkey <brian.starkey@arm.com> 1702 - L: Mali DP Maintainers <malidp@foss.arm.com> 1703 1704 S: Supported 1704 1705 T: git git://anongit.freedesktop.org/drm/drm-misc 1705 1706 F: Documentation/devicetree/bindings/display/arm,malidp.yaml ··· 4909 4914 CIRRUS LOGIC AUDIO CODEC DRIVERS 4910 4915 M: James Schulman <james.schulman@cirrus.com> 4911 4916 M: David Rhodes <david.rhodes@cirrus.com> 4912 - M: Lucas Tanure <tanureal@opensource.cirrus.com> 4913 4917 M: Richard Fitzgerald <rf@opensource.cirrus.com> 4914 4918 L: alsa-devel@alsa-project.org (moderated for non-subscribers) 4915 4919 L: patches@opensource.cirrus.com ··· 6006 6012 F: Documentation/devicetree/bindings/input/da90??-onkey.txt 6007 6013 F: Documentation/devicetree/bindings/input/dlg,da72??.txt 6008 6014 F: Documentation/devicetree/bindings/mfd/da90*.txt 6009 - F: Documentation/devicetree/bindings/mfd/da90*.yaml 6015 + F: Documentation/devicetree/bindings/mfd/dlg,da90*.yaml 6010 6016 F: Documentation/devicetree/bindings/regulator/da92*.txt 6011 6017 F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml 6012 6018 F: Documentation/devicetree/bindings/regulator/slg51000.txt ··· 6205 6211 X: Documentation/driver-api/media/ 6206 6212 X: Documentation/firmware-guide/acpi/ 6207 6213 X: Documentation/i2c/ 6214 + X: Documentation/netlink/ 6208 6215 X: Documentation/power/ 6209 6216 X: Documentation/spi/ 6210 6217 X: Documentation/userspace-api/media/ ··· 14561 14566 F: Documentation/devicetree/bindings/net/ 14562 14567 F: drivers/connector/ 14563 14568 F: drivers/net/ 14569 + X: drivers/net/wireless/ 14564 14570 F: include/dt-bindings/net/ 14565 14571 F: include/linux/etherdevice.h 14566 14572 F: include/linux/fcdevice.h ··· 14611 14615 T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git 14612 14616 T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git 14613 14617 F: Documentation/core-api/netlink.rst 14618 + F: Documentation/netlink/ 14614 14619 F: Documentation/networking/ 14615 14620 F: Documentation/process/maintainer-netdev.rst 14616 14621 F: Documentation/userspace-api/netlink/ ··· 14626 14629 F: lib/net_utils.c 14627 14630 F: lib/random32.c 14628 14631 F: net/ 14632 + X: net/bluetooth/ 14629 14633 F: tools/net/ 14630 14634 F: tools/testing/selftests/net/ 14631 14635 ··· 18573 18575 F: security/safesetid/ 18574 18576 18575 18577 SAMSUNG AUDIO (ASoC) DRIVERS 18576 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 18577 18578 M: Sylwester Nawrocki <s.nawrocki@samsung.com> 18578 18579 L: alsa-devel@alsa-project.org (moderated for non-subscribers) 18579 - S: Supported 18580 + S: Maintained 18580 18581 B: mailto:linux-samsung-soc@vger.kernel.org 18581 18582 F: Documentation/devicetree/bindings/sound/samsung* 18582 18583 F: sound/soc/samsung/ ··· 18839 18842 F: include/target/ 18840 18843 18841 18844 SCTP PROTOCOL 18842 - M: Neil Horman <nhorman@tuxdriver.com> 18843 18845 M: Marcelo Ricardo Leitner <marcelo.leitner@gmail.com> 18844 18846 M: Xin Long <lucien.xin@gmail.com> 18845 18847 L: linux-sctp@vger.kernel.org 18846 18848 S: Maintained 18847 - W: http://lksctp.sourceforge.net 18849 + W: https://github.com/sctp/lksctp-tools/wiki 18848 18850 F: Documentation/networking/sctp.rst 18849 18851 F: include/linux/sctp.h 18850 18852 F: include/net/sctp/
+1 -1
Makefile
··· 2 2 VERSION = 6 3 3 PATCHLEVEL = 4 4 4 SUBLEVEL = 0 5 - EXTRAVERSION = -rc2 5 + EXTRAVERSION = -rc3 6 6 NAME = Hurr durr I'ma ninja sloth 7 7 8 8 # *DOCUMENTATION*
+1
arch/arm/boot/dts/stm32f429.dtsi
··· 387 387 interrupt-names = "tx", "rx0", "rx1", "sce"; 388 388 resets = <&rcc STM32F4_APB1_RESET(CAN2)>; 389 389 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; 390 + st,can-secondary; 390 391 st,gcan = <&gcan>; 391 392 status = "disabled"; 392 393 };
+82
arch/arm/boot/dts/stm32f7-pinctrl.dtsi
··· 283 283 slew-rate = <2>; 284 284 }; 285 285 }; 286 + 287 + can1_pins_a: can1-0 { 288 + pins1 { 289 + pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ 290 + }; 291 + pins2 { 292 + pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ 293 + bias-pull-up; 294 + }; 295 + }; 296 + 297 + can1_pins_b: can1-1 { 298 + pins1 { 299 + pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */ 300 + }; 301 + pins2 { 302 + pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */ 303 + bias-pull-up; 304 + }; 305 + }; 306 + 307 + can1_pins_c: can1-2 { 308 + pins1 { 309 + pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */ 310 + }; 311 + pins2 { 312 + pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ 313 + bias-pull-up; 314 + 315 + }; 316 + }; 317 + 318 + can1_pins_d: can1-3 { 319 + pins1 { 320 + pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 321 + }; 322 + pins2 { 323 + pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ 324 + bias-pull-up; 325 + 326 + }; 327 + }; 328 + 329 + can2_pins_a: can2-0 { 330 + pins1 { 331 + pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */ 332 + }; 333 + pins2 { 334 + pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 335 + bias-pull-up; 336 + }; 337 + }; 338 + 339 + can2_pins_b: can2-1 { 340 + pins1 { 341 + pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 342 + }; 343 + pins2 { 344 + pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */ 345 + bias-pull-up; 346 + }; 347 + }; 348 + 349 + can3_pins_a: can3-0 { 350 + pins1 { 351 + pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */ 352 + }; 353 + pins2 { 354 + pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */ 355 + bias-pull-up; 356 + }; 357 + }; 358 + 359 + can3_pins_b: can3-1 { 360 + pins1 { 361 + pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */ 362 + }; 363 + pins2 { 364 + pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */ 365 + bias-pull-up; 366 + }; 367 + }; 286 368 }; 287 369 }; 288 370 };
+3 -3
arch/arm/include/asm/arm_pmuv3.h
··· 92 92 93 93 #define RETURN_READ_PMEVCNTRN(n) \ 94 94 return read_sysreg(PMEVCNTR##n) 95 - static unsigned long read_pmevcntrn(int n) 95 + static inline unsigned long read_pmevcntrn(int n) 96 96 { 97 97 PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN); 98 98 return 0; ··· 100 100 101 101 #define WRITE_PMEVCNTRN(n) \ 102 102 write_sysreg(val, PMEVCNTR##n) 103 - static void write_pmevcntrn(int n, unsigned long val) 103 + static inline void write_pmevcntrn(int n, unsigned long val) 104 104 { 105 105 PMEVN_SWITCH(n, WRITE_PMEVCNTRN); 106 106 } 107 107 108 108 #define WRITE_PMEVTYPERN(n) \ 109 109 write_sysreg(val, PMEVTYPER##n) 110 - static void write_pmevtypern(int n, unsigned long val) 110 + static inline void write_pmevtypern(int n, unsigned long val) 111 111 { 112 112 PMEVN_SWITCH(n, WRITE_PMEVTYPERN); 113 113 }
+3 -3
arch/arm64/include/asm/arm_pmuv3.h
··· 13 13 14 14 #define RETURN_READ_PMEVCNTRN(n) \ 15 15 return read_sysreg(pmevcntr##n##_el0) 16 - static unsigned long read_pmevcntrn(int n) 16 + static inline unsigned long read_pmevcntrn(int n) 17 17 { 18 18 PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN); 19 19 return 0; ··· 21 21 22 22 #define WRITE_PMEVCNTRN(n) \ 23 23 write_sysreg(val, pmevcntr##n##_el0) 24 - static void write_pmevcntrn(int n, unsigned long val) 24 + static inline void write_pmevcntrn(int n, unsigned long val) 25 25 { 26 26 PMEVN_SWITCH(n, WRITE_PMEVCNTRN); 27 27 } 28 28 29 29 #define WRITE_PMEVTYPERN(n) \ 30 30 write_sysreg(val, pmevtyper##n##_el0) 31 - static void write_pmevtypern(int n, unsigned long val) 31 + static inline void write_pmevtypern(int n, unsigned long val) 32 32 { 33 33 PMEVN_SWITCH(n, WRITE_PMEVTYPERN); 34 34 }
+8
arch/arm64/include/asm/cputype.h
··· 126 126 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 127 127 #define APPLE_CPU_PART_M2_BLIZZARD 0x032 128 128 #define APPLE_CPU_PART_M2_AVALANCHE 0x033 129 + #define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 130 + #define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 131 + #define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 132 + #define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 129 133 130 134 #define AMPERE_CPU_PART_AMPERE1 0xAC3 131 135 ··· 185 181 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) 186 182 #define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD) 187 183 #define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE) 184 + #define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO) 185 + #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO) 186 + #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) 187 + #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) 188 188 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) 189 189 190 190 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
+1
arch/arm64/include/asm/kvm_pgtable.h
··· 209 209 kvm_pte_t old; 210 210 void *arg; 211 211 struct kvm_pgtable_mm_ops *mm_ops; 212 + u64 start; 212 213 u64 addr; 213 214 u64 end; 214 215 u32 level;
+2 -5
arch/arm64/kernel/mte.c
··· 66 66 return; 67 67 68 68 /* if PG_mte_tagged is set, tags have already been initialised */ 69 - for (i = 0; i < nr_pages; i++, page++) { 70 - if (!page_mte_tagged(page)) { 69 + for (i = 0; i < nr_pages; i++, page++) 70 + if (!page_mte_tagged(page)) 71 71 mte_sync_page_tags(page, old_pte, check_swap, 72 72 pte_is_tagged); 73 - set_page_mte_tagged(page); 74 - } 75 - } 76 73 77 74 /* ensure the tags are visible before the PTE is set */ 78 75 smp_wmb();
+1 -1
arch/arm64/kernel/vdso.c
··· 288 288 289 289 memcpy((void *)(vdso_page + 0x1000 - kuser_sz), __kuser_helper_start, 290 290 kuser_sz); 291 - aarch32_vectors_page = virt_to_page(vdso_page); 291 + aarch32_vectors_page = virt_to_page((void *)vdso_page); 292 292 return 0; 293 293 } 294 294
+17 -9
arch/arm64/kvm/fpsimd.c
··· 81 81 82 82 fpsimd_kvm_prepare(); 83 83 84 + /* 85 + * We will check TIF_FOREIGN_FPSTATE just before entering the 86 + * guest in kvm_arch_vcpu_ctxflush_fp() and override this to 87 + * FP_STATE_FREE if the flag set. 88 + */ 84 89 vcpu->arch.fp_state = FP_STATE_HOST_OWNED; 85 90 86 91 vcpu_clear_flag(vcpu, HOST_SVE_ENABLED); 87 92 if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN) 88 93 vcpu_set_flag(vcpu, HOST_SVE_ENABLED); 89 94 90 - /* 91 - * We don't currently support SME guests but if we leave 92 - * things in streaming mode then when the guest starts running 93 - * FPSIMD or SVE code it may generate SME traps so as a 94 - * special case if we are in streaming mode we force the host 95 - * state to be saved now and exit streaming mode so that we 96 - * don't have to handle any SME traps for valid guest 97 - * operations. Do this for ZA as well for now for simplicity. 98 - */ 99 95 if (system_supports_sme()) { 100 96 vcpu_clear_flag(vcpu, HOST_SME_ENABLED); 101 97 if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN) 102 98 vcpu_set_flag(vcpu, HOST_SME_ENABLED); 103 99 100 + /* 101 + * If PSTATE.SM is enabled then save any pending FP 102 + * state and disable PSTATE.SM. If we leave PSTATE.SM 103 + * enabled and the guest does not enable SME via 104 + * CPACR_EL1.SMEN then operations that should be valid 105 + * may generate SME traps from EL1 to EL1 which we 106 + * can't intercept and which would confuse the guest. 107 + * 108 + * Do the same for PSTATE.ZA in the case where there 109 + * is state in the registers which has not already 110 + * been saved, this is very unlikely to happen. 111 + */ 104 112 if (read_sysreg_s(SYS_SVCR) & (SVCR_SM_MASK | SVCR_ZA_MASK)) { 105 113 vcpu->arch.fp_state = FP_STATE_FREE; 106 114 fpsimd_save_and_flush_cpu_state();
+10 -2
arch/arm64/kvm/hyp/include/hyp/switch.h
··· 177 177 sve_guest = vcpu_has_sve(vcpu); 178 178 esr_ec = kvm_vcpu_trap_get_class(vcpu); 179 179 180 - /* Don't handle SVE traps for non-SVE vcpus here: */ 181 - if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD) 180 + /* Only handle traps the vCPU can support here: */ 181 + switch (esr_ec) { 182 + case ESR_ELx_EC_FP_ASIMD: 183 + break; 184 + case ESR_ELx_EC_SVE: 185 + if (!sve_guest) 186 + return false; 187 + break; 188 + default: 182 189 return false; 190 + } 183 191 184 192 /* Valid trap. Switch the context: */ 185 193
+32 -9
arch/arm64/kvm/hyp/pgtable.c
··· 58 58 struct kvm_pgtable_walk_data { 59 59 struct kvm_pgtable_walker *walker; 60 60 61 + const u64 start; 61 62 u64 addr; 62 - u64 end; 63 + const u64 end; 63 64 }; 64 65 65 66 static bool kvm_phys_is_valid(u64 phys) ··· 202 201 .old = READ_ONCE(*ptep), 203 202 .arg = data->walker->arg, 204 203 .mm_ops = mm_ops, 204 + .start = data->start, 205 205 .addr = data->addr, 206 206 .end = data->end, 207 207 .level = level, ··· 295 293 struct kvm_pgtable_walker *walker) 296 294 { 297 295 struct kvm_pgtable_walk_data walk_data = { 296 + .start = ALIGN_DOWN(addr, PAGE_SIZE), 298 297 .addr = ALIGN_DOWN(addr, PAGE_SIZE), 299 298 .end = PAGE_ALIGN(walk_data.addr + size), 300 299 .walker = walker, ··· 352 349 } 353 350 354 351 struct hyp_map_data { 355 - u64 phys; 352 + const u64 phys; 356 353 kvm_pte_t attr; 357 354 }; 358 355 ··· 410 407 static bool hyp_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx, 411 408 struct hyp_map_data *data) 412 409 { 410 + u64 phys = data->phys + (ctx->addr - ctx->start); 413 411 kvm_pte_t new; 414 - u64 granule = kvm_granule_size(ctx->level), phys = data->phys; 415 412 416 413 if (!kvm_block_mapping_supported(ctx, phys)) 417 414 return false; 418 415 419 - data->phys += granule; 420 416 new = kvm_init_valid_leaf_pte(phys, data->attr, ctx->level); 421 417 if (ctx->old == new) 422 418 return true; ··· 578 576 } 579 577 580 578 struct stage2_map_data { 581 - u64 phys; 579 + const u64 phys; 582 580 kvm_pte_t attr; 583 581 u8 owner_id; 584 582 ··· 796 794 return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN); 797 795 } 798 796 797 + static u64 stage2_map_walker_phys_addr(const struct kvm_pgtable_visit_ctx *ctx, 798 + const struct stage2_map_data *data) 799 + { 800 + u64 phys = data->phys; 801 + 802 + /* 803 + * Stage-2 walks to update ownership data are communicated to the map 804 + * walker using an invalid PA. Avoid offsetting an already invalid PA, 805 + * which could overflow and make the address valid again. 806 + */ 807 + if (!kvm_phys_is_valid(phys)) 808 + return phys; 809 + 810 + /* 811 + * Otherwise, work out the correct PA based on how far the walk has 812 + * gotten. 813 + */ 814 + return phys + (ctx->addr - ctx->start); 815 + } 816 + 799 817 static bool stage2_leaf_mapping_allowed(const struct kvm_pgtable_visit_ctx *ctx, 800 818 struct stage2_map_data *data) 801 819 { 820 + u64 phys = stage2_map_walker_phys_addr(ctx, data); 821 + 802 822 if (data->force_pte && (ctx->level < (KVM_PGTABLE_MAX_LEVELS - 1))) 803 823 return false; 804 824 805 - return kvm_block_mapping_supported(ctx, data->phys); 825 + return kvm_block_mapping_supported(ctx, phys); 806 826 } 807 827 808 828 static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx, 809 829 struct stage2_map_data *data) 810 830 { 811 831 kvm_pte_t new; 812 - u64 granule = kvm_granule_size(ctx->level), phys = data->phys; 832 + u64 phys = stage2_map_walker_phys_addr(ctx, data); 833 + u64 granule = kvm_granule_size(ctx->level); 813 834 struct kvm_pgtable *pgt = data->mmu->pgt; 814 835 struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; 815 836 ··· 866 841 867 842 stage2_make_pte(ctx, new); 868 843 869 - if (kvm_phys_is_valid(phys)) 870 - data->phys += granule; 871 844 return 0; 872 845 } 873 846
+1 -1
arch/arm64/kvm/inject_fault.c
··· 204 204 * Size Fault at level 0, as if exceeding PARange. 205 205 * 206 206 * Non-LPAE guests will only get the external abort, as there 207 - * is no way to to describe the ASF. 207 + * is no way to describe the ASF. 208 208 */ 209 209 if (vcpu_el1_is_32bit(vcpu) && 210 210 !(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
+4
arch/arm64/kvm/vgic/vgic-v3.c
··· 616 616 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 617 617 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 618 618 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 619 + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 620 + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 621 + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 622 + MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 619 623 {}, 620 624 }; 621 625
+3 -4
arch/arm64/kvm/vmid.c
··· 47 47 int cpu; 48 48 u64 vmid; 49 49 50 - bitmap_clear(vmid_map, 0, NUM_USER_VMIDS); 50 + bitmap_zero(vmid_map, NUM_USER_VMIDS); 51 51 52 52 for_each_possible_cpu(cpu) { 53 53 vmid = atomic64_xchg_relaxed(&per_cpu(active_vmids, cpu), 0); ··· 182 182 */ 183 183 WARN_ON(NUM_USER_VMIDS - 1 <= num_possible_cpus()); 184 184 atomic64_set(&vmid_generation, VMID_FIRST_VERSION); 185 - vmid_map = kcalloc(BITS_TO_LONGS(NUM_USER_VMIDS), 186 - sizeof(*vmid_map), GFP_KERNEL); 185 + vmid_map = bitmap_zalloc(NUM_USER_VMIDS, GFP_KERNEL); 187 186 if (!vmid_map) 188 187 return -ENOMEM; 189 188 ··· 191 192 192 193 void __init kvm_arm_vmid_alloc_free(void) 193 194 { 194 - kfree(vmid_map); 195 + bitmap_free(vmid_map); 195 196 }
+3 -2
arch/arm64/mm/copypage.c
··· 21 21 22 22 copy_page(kto, kfrom); 23 23 24 + if (kasan_hw_tags_enabled()) 25 + page_kasan_tag_reset(to); 26 + 24 27 if (system_supports_mte() && page_mte_tagged(from)) { 25 - if (kasan_hw_tags_enabled()) 26 - page_kasan_tag_reset(to); 27 28 /* It's a new page, shouldn't have been tagged yet */ 28 29 WARN_ON_ONCE(!try_page_mte_tagging(to)); 29 30 mte_copy_page_tags(kto, kfrom);
+2 -2
arch/arm64/mm/fault.c
··· 480 480 } 481 481 } 482 482 483 - #define VM_FAULT_BADMAP 0x010000 484 - #define VM_FAULT_BADACCESS 0x020000 483 + #define VM_FAULT_BADMAP ((__force vm_fault_t)0x010000) 484 + #define VM_FAULT_BADACCESS ((__force vm_fault_t)0x020000) 485 485 486 486 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, 487 487 unsigned int mm_flags, unsigned long vm_flags,
+4 -2
arch/powerpc/boot/Makefile
··· 34 34 35 35 BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ 36 36 -fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \ 37 - $(call cc-option,-mno-prefixed) $(call cc-option,-mno-pcrel) \ 38 - $(call cc-option,-mno-mma) \ 39 37 $(call cc-option,-mno-spe) $(call cc-option,-mspe=no) \ 40 38 -pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \ 41 39 $(LINUXINCLUDE) ··· 68 70 BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -nostdinc 69 71 70 72 BOOTARFLAGS := -crD 73 + 74 + BOOTCFLAGS += $(call cc-option,-mno-prefixed) \ 75 + $(call cc-option,-mno-pcrel) \ 76 + $(call cc-option,-mno-mma) 71 77 72 78 ifdef CONFIG_CC_IS_CLANG 73 79 BOOTCFLAGS += $(CLANG_FLAGS)
+1 -1
arch/powerpc/crypto/Kconfig
··· 96 96 97 97 config CRYPTO_AES_GCM_P10 98 98 tristate "Stitched AES/GCM acceleration support on P10 or later CPU (PPC)" 99 - depends on PPC64 && CPU_LITTLE_ENDIAN 99 + depends on PPC64 && CPU_LITTLE_ENDIAN && VSX 100 100 select CRYPTO_LIB_AES 101 101 select CRYPTO_ALGAPI 102 102 select CRYPTO_AEAD
-5
arch/powerpc/include/asm/iommu.h
··· 205 205 int pci_domain_number, unsigned long pe_num); 206 206 extern int iommu_add_device(struct iommu_table_group *table_group, 207 207 struct device *dev); 208 - extern void iommu_del_device(struct device *dev); 209 208 extern long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl, 210 209 unsigned long entry, unsigned long *hpa, 211 210 enum dma_data_direction *direction); ··· 227 228 struct device *dev) 228 229 { 229 230 return 0; 230 - } 231 - 232 - static inline void iommu_del_device(struct device *dev) 233 - { 234 231 } 235 232 #endif /* !CONFIG_IOMMU_API */ 236 233
+3 -1
arch/powerpc/kernel/dma-iommu.c
··· 144 144 /* We support DMA to/from any memory page via the iommu */ 145 145 int dma_iommu_dma_supported(struct device *dev, u64 mask) 146 146 { 147 - struct iommu_table *tbl = get_iommu_table_base(dev); 147 + struct iommu_table *tbl; 148 148 149 149 if (dev_is_pci(dev) && dma_iommu_bypass_supported(dev, mask)) { 150 150 /* ··· 161 161 dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n"); 162 162 return 1; 163 163 } 164 + 165 + tbl = get_iommu_table_base(dev); 164 166 165 167 if (!tbl) { 166 168 dev_err(dev, "Warning: IOMMU dma not supported: mask 0x%08llx, table unavailable\n", mask);
+7 -21
arch/powerpc/kernel/iommu.c
··· 518 518 /* Convert entry to a dma_addr_t */ 519 519 entry += tbl->it_offset; 520 520 dma_addr = entry << tbl->it_page_shift; 521 - dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl)); 521 + dma_addr |= (vaddr & ~IOMMU_PAGE_MASK(tbl)); 522 522 523 523 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n", 524 524 npages, entry, dma_addr); ··· 905 905 unsigned int order; 906 906 unsigned int nio_pages, io_order; 907 907 struct page *page; 908 + int tcesize = (1 << tbl->it_page_shift); 908 909 909 910 size = PAGE_ALIGN(size); 910 911 order = get_order(size); ··· 932 931 memset(ret, 0, size); 933 932 934 933 /* Set up tces to cover the allocated range */ 935 - nio_pages = size >> tbl->it_page_shift; 934 + nio_pages = IOMMU_PAGE_ALIGN(size, tbl) >> tbl->it_page_shift; 935 + 936 936 io_order = get_iommu_order(size, tbl); 937 937 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL, 938 938 mask >> tbl->it_page_shift, io_order, 0); ··· 941 939 free_pages((unsigned long)ret, order); 942 940 return NULL; 943 941 } 944 - *dma_handle = mapping; 942 + 943 + *dma_handle = mapping | ((u64)ret & (tcesize - 1)); 945 944 return ret; 946 945 } 947 946 ··· 953 950 unsigned int nio_pages; 954 951 955 952 size = PAGE_ALIGN(size); 956 - nio_pages = size >> tbl->it_page_shift; 953 + nio_pages = IOMMU_PAGE_ALIGN(size, tbl) >> tbl->it_page_shift; 957 954 iommu_free(tbl, dma_handle, nio_pages); 958 955 size = PAGE_ALIGN(size); 959 956 free_pages((unsigned long)vaddr, get_order(size)); ··· 1170 1167 return iommu_probe_device(dev); 1171 1168 } 1172 1169 EXPORT_SYMBOL_GPL(iommu_add_device); 1173 - 1174 - void iommu_del_device(struct device *dev) 1175 - { 1176 - /* 1177 - * Some devices might not have IOMMU table and group 1178 - * and we needn't detach them from the associated 1179 - * IOMMU groups 1180 - */ 1181 - if (!device_iommu_mapped(dev)) { 1182 - pr_debug("iommu_tce: skipping device %s with no tbl\n", 1183 - dev_name(dev)); 1184 - return; 1185 - } 1186 - 1187 - iommu_group_remove_device(dev); 1188 - } 1189 - EXPORT_SYMBOL_GPL(iommu_del_device); 1190 1170 1191 1171 /* 1192 1172 * A simple iommu_table_group_ops which only allows reusing the existing
+3 -2
arch/powerpc/kernel/isa-bridge.c
··· 93 93 } 94 94 95 95 inval_range: 96 - if (!phb_io_base_phys) { 96 + if (phb_io_base_phys) { 97 97 pr_err("no ISA IO ranges or unexpected isa range, mapping 64k\n"); 98 98 remap_isa_base(phb_io_base_phys, 0x10000); 99 + return 0; 99 100 } 100 - return 0; 101 + return -EINVAL; 101 102 } 102 103 103 104
+2 -2
arch/powerpc/mm/book3s64/radix_pgtable.c
··· 1040 1040 pte_t entry, unsigned long address, int psize) 1041 1041 { 1042 1042 struct mm_struct *mm = vma->vm_mm; 1043 - unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | 1044 - _PAGE_RW | _PAGE_EXEC); 1043 + unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY | 1044 + _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 1045 1045 1046 1046 unsigned long change = pte_val(entry) ^ pte_val(*ptep); 1047 1047 /*
+2
arch/powerpc/net/bpf_jit_comp.c
··· 101 101 bpf_hdr = jit_data->header; 102 102 proglen = jit_data->proglen; 103 103 extra_pass = true; 104 + /* During extra pass, ensure index is reset before repopulating extable entries */ 105 + cgctx.exentry_idx = 0; 104 106 goto skip_init_ctx; 105 107 } 106 108
+1
arch/powerpc/platforms/Kconfig
··· 265 265 config FSL_ULI1575 266 266 bool "ULI1575 PCIe south bridge support" 267 267 depends on FSL_SOC_BOOKE || PPC_86xx 268 + depends on PCI 268 269 select FSL_PCI 269 270 select GENERIC_ISA_DMA 270 271 help
-25
arch/powerpc/platforms/powernv/pci.c
··· 865 865 /* Configure IOMMU DMA hooks */ 866 866 set_pci_dma_ops(&dma_iommu_ops); 867 867 } 868 - 869 - static int pnv_tce_iommu_bus_notifier(struct notifier_block *nb, 870 - unsigned long action, void *data) 871 - { 872 - struct device *dev = data; 873 - 874 - switch (action) { 875 - case BUS_NOTIFY_DEL_DEVICE: 876 - iommu_del_device(dev); 877 - return 0; 878 - default: 879 - return 0; 880 - } 881 - } 882 - 883 - static struct notifier_block pnv_tce_iommu_bus_nb = { 884 - .notifier_call = pnv_tce_iommu_bus_notifier, 885 - }; 886 - 887 - static int __init pnv_tce_iommu_bus_notifier_init(void) 888 - { 889 - bus_register_notifier(&pci_bus_type, &pnv_tce_iommu_bus_nb); 890 - return 0; 891 - } 892 - machine_subsys_initcall_sync(powernv, pnv_tce_iommu_bus_notifier_init);
+9 -29
arch/powerpc/platforms/pseries/iommu.c
··· 91 91 static void iommu_pseries_free_group(struct iommu_table_group *table_group, 92 92 const char *node_name) 93 93 { 94 - struct iommu_table *tbl; 95 - 96 94 if (!table_group) 97 95 return; 98 96 99 - tbl = table_group->tables[0]; 100 97 #ifdef CONFIG_IOMMU_API 101 98 if (table_group->group) { 102 99 iommu_group_put(table_group->group); 103 100 BUG_ON(table_group->group); 104 101 } 105 102 #endif 106 - iommu_tce_table_put(tbl); 103 + 104 + /* Default DMA window table is at index 0, while DDW at 1. SR-IOV 105 + * adapters only have table on index 1. 106 + */ 107 + if (table_group->tables[0]) 108 + iommu_tce_table_put(table_group->tables[0]); 109 + 110 + if (table_group->tables[1]) 111 + iommu_tce_table_put(table_group->tables[1]); 107 112 108 113 kfree(table_group); 109 114 } ··· 1699 1694 } 1700 1695 1701 1696 __setup("multitce=", disable_multitce); 1702 - 1703 - static int tce_iommu_bus_notifier(struct notifier_block *nb, 1704 - unsigned long action, void *data) 1705 - { 1706 - struct device *dev = data; 1707 - 1708 - switch (action) { 1709 - case BUS_NOTIFY_DEL_DEVICE: 1710 - iommu_del_device(dev); 1711 - return 0; 1712 - default: 1713 - return 0; 1714 - } 1715 - } 1716 - 1717 - static struct notifier_block tce_iommu_bus_nb = { 1718 - .notifier_call = tce_iommu_bus_notifier, 1719 - }; 1720 - 1721 - static int __init tce_iommu_bus_notifier_init(void) 1722 - { 1723 - bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb); 1724 - return 0; 1725 - } 1726 - machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init); 1727 1697 1728 1698 #ifdef CONFIG_SPAPR_TCE_IOMMU 1729 1699 struct iommu_group *pSeries_pci_device_group(struct pci_controller *hose,
+2
arch/riscv/kernel/probes/Makefile
··· 4 4 obj-$(CONFIG_KPROBES_ON_FTRACE) += ftrace.o 5 5 obj-$(CONFIG_UPROBES) += uprobes.o decode-insn.o simulate-insn.o 6 6 CFLAGS_REMOVE_simulate-insn.o = $(CC_FLAGS_FTRACE) 7 + CFLAGS_REMOVE_rethook.o = $(CC_FLAGS_FTRACE) 8 + CFLAGS_REMOVE_rethook_trampoline.o = $(CC_FLAGS_FTRACE)
+1 -10
arch/s390/Kconfig
··· 469 469 config SCHED_MC 470 470 def_bool n 471 471 472 - config SCHED_BOOK 473 - def_bool n 474 - 475 - config SCHED_DRAWER 476 - def_bool n 477 - 478 472 config SCHED_TOPOLOGY 479 473 def_bool y 480 474 prompt "Topology scheduler support" 481 475 select SCHED_SMT 482 476 select SCHED_MC 483 - select SCHED_BOOK 484 - select SCHED_DRAWER 485 477 help 486 478 Topology scheduler support improves the CPU scheduler's decision 487 479 making when dealing with machines that have multi-threading, ··· 708 716 config VFIO_CCW 709 717 def_tristate n 710 718 prompt "Support for VFIO-CCW subchannels" 711 - depends on S390_CCW_IOMMU 712 719 depends on VFIO 713 720 select VFIO_MDEV 714 721 help ··· 719 728 config VFIO_AP 720 729 def_tristate n 721 730 prompt "VFIO support for AP devices" 722 - depends on S390_AP_IOMMU && KVM 731 + depends on KVM 723 732 depends on VFIO 724 733 depends on ZCRYPT 725 734 select VFIO_MDEV
+1 -2
arch/s390/configs/debug_defconfig
··· 591 591 CONFIG_VIRTIO_INPUT=y 592 592 CONFIG_VHOST_NET=m 593 593 CONFIG_VHOST_VSOCK=m 594 - CONFIG_S390_CCW_IOMMU=y 595 - CONFIG_S390_AP_IOMMU=y 596 594 CONFIG_EXT4_FS=y 597 595 CONFIG_EXT4_FS_POSIX_ACL=y 598 596 CONFIG_EXT4_FS_SECURITY=y ··· 701 703 CONFIG_IMA_WRITE_POLICY=y 702 704 CONFIG_IMA_APPRAISE=y 703 705 CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" 706 + CONFIG_INIT_STACK_NONE=y 704 707 CONFIG_CRYPTO_USER=m 705 708 # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set 706 709 CONFIG_CRYPTO_PCRYPT=m
+1 -2
arch/s390/configs/defconfig
··· 580 580 CONFIG_VIRTIO_INPUT=y 581 581 CONFIG_VHOST_NET=m 582 582 CONFIG_VHOST_VSOCK=m 583 - CONFIG_S390_CCW_IOMMU=y 584 - CONFIG_S390_AP_IOMMU=y 585 583 CONFIG_EXT4_FS=y 586 584 CONFIG_EXT4_FS_POSIX_ACL=y 587 585 CONFIG_EXT4_FS_SECURITY=y ··· 684 686 CONFIG_IMA_WRITE_POLICY=y 685 687 CONFIG_IMA_APPRAISE=y 686 688 CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" 689 + CONFIG_INIT_STACK_NONE=y 687 690 CONFIG_CRYPTO_FIPS=y 688 691 CONFIG_CRYPTO_USER=m 689 692 # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+1
arch/s390/configs/zfcpdump_defconfig
··· 67 67 # CONFIG_MISC_FILESYSTEMS is not set 68 68 # CONFIG_NETWORK_FILESYSTEMS is not set 69 69 CONFIG_LSM="yama,loadpin,safesetid,integrity" 70 + CONFIG_INIT_STACK_NONE=y 70 71 # CONFIG_ZLIB_DFLTCC is not set 71 72 CONFIG_XZ_DEC_MICROLZMA=y 72 73 CONFIG_PRINTK_TIME=y
+1 -1
arch/s390/crypto/chacha-glue.c
··· 82 82 * it cannot handle a block of data or less, but otherwise 83 83 * it can handle data of arbitrary size 84 84 */ 85 - if (bytes <= CHACHA_BLOCK_SIZE || nrounds != 20) 85 + if (bytes <= CHACHA_BLOCK_SIZE || nrounds != 20 || !MACHINE_HAS_VX) 86 86 chacha_crypt_generic(state, dst, src, bytes, nrounds); 87 87 else 88 88 chacha20_crypt_s390(state, dst, src, bytes,
+1 -1
arch/s390/include/asm/compat.h
··· 112 112 u32 f_namelen; 113 113 u32 f_frsize; 114 114 u32 f_flags; 115 - u32 f_spare[4]; 115 + u32 f_spare[5]; 116 116 }; 117 117 118 118 /*
+2 -2
arch/s390/include/uapi/asm/statfs.h
··· 30 30 unsigned int f_namelen; 31 31 unsigned int f_frsize; 32 32 unsigned int f_flags; 33 - unsigned int f_spare[4]; 33 + unsigned int f_spare[5]; 34 34 }; 35 35 36 36 struct statfs64 { ··· 45 45 unsigned int f_namelen; 46 46 unsigned int f_frsize; 47 47 unsigned int f_flags; 48 - unsigned int f_spare[4]; 48 + unsigned int f_spare[5]; 49 49 }; 50 50 51 51 #endif
+1
arch/s390/kernel/Makefile
··· 10 10 11 11 # Do not trace early setup code 12 12 CFLAGS_REMOVE_early.o = $(CC_FLAGS_FTRACE) 13 + CFLAGS_REMOVE_rethook.o = $(CC_FLAGS_FTRACE) 13 14 14 15 endif 15 16
+1 -2
arch/s390/kernel/ipl.c
··· 1935 1935 1936 1936 static void dump_reipl_run(struct shutdown_trigger *trigger) 1937 1937 { 1938 - unsigned long ipib = (unsigned long) reipl_block_actual; 1939 1938 struct lowcore *abs_lc; 1940 1939 unsigned int csum; 1941 1940 1942 1941 csum = (__force unsigned int) 1943 1942 csum_partial(reipl_block_actual, reipl_block_actual->hdr.len, 0); 1944 1943 abs_lc = get_abs_lowcore(); 1945 - abs_lc->ipib = ipib; 1944 + abs_lc->ipib = __pa(reipl_block_actual); 1946 1945 abs_lc->ipib_checksum = csum; 1947 1946 put_abs_lowcore(abs_lc); 1948 1947 dump_run(trigger);
+17 -15
arch/s390/kernel/topology.c
··· 95 95 static void cpu_thread_map(cpumask_t *dst, unsigned int cpu) 96 96 { 97 97 static cpumask_t mask; 98 - int i; 98 + unsigned int max_cpu; 99 99 100 100 cpumask_clear(&mask); 101 101 if (!cpumask_test_cpu(cpu, &cpu_setup_mask)) ··· 104 104 if (topology_mode != TOPOLOGY_MODE_HW) 105 105 goto out; 106 106 cpu -= cpu % (smp_cpu_mtid + 1); 107 - for (i = 0; i <= smp_cpu_mtid; i++) { 108 - if (cpumask_test_cpu(cpu + i, &cpu_setup_mask)) 109 - cpumask_set_cpu(cpu + i, &mask); 107 + max_cpu = min(cpu + smp_cpu_mtid, nr_cpu_ids - 1); 108 + for (; cpu <= max_cpu; cpu++) { 109 + if (cpumask_test_cpu(cpu, &cpu_setup_mask)) 110 + cpumask_set_cpu(cpu, &mask); 110 111 } 111 112 out: 112 113 cpumask_copy(dst, &mask); ··· 124 123 unsigned int core; 125 124 126 125 for_each_set_bit(core, &tl_core->mask, TOPOLOGY_CORE_BITS) { 127 - unsigned int rcore; 128 - int lcpu, i; 126 + unsigned int max_cpu, rcore; 127 + int cpu; 129 128 130 129 rcore = TOPOLOGY_CORE_BITS - 1 - core + tl_core->origin; 131 - lcpu = smp_find_processor_id(rcore << smp_cpu_mt_shift); 132 - if (lcpu < 0) 130 + cpu = smp_find_processor_id(rcore << smp_cpu_mt_shift); 131 + if (cpu < 0) 133 132 continue; 134 - for (i = 0; i <= smp_cpu_mtid; i++) { 135 - topo = &cpu_topology[lcpu + i]; 133 + max_cpu = min(cpu + smp_cpu_mtid, nr_cpu_ids - 1); 134 + for (; cpu <= max_cpu; cpu++) { 135 + topo = &cpu_topology[cpu]; 136 136 topo->drawer_id = drawer->id; 137 137 topo->book_id = book->id; 138 138 topo->socket_id = socket->id; 139 139 topo->core_id = rcore; 140 - topo->thread_id = lcpu + i; 140 + topo->thread_id = cpu; 141 141 topo->dedicated = tl_core->d; 142 - cpumask_set_cpu(lcpu + i, &drawer->mask); 143 - cpumask_set_cpu(lcpu + i, &book->mask); 144 - cpumask_set_cpu(lcpu + i, &socket->mask); 145 - smp_cpu_set_polarization(lcpu + i, tl_core->pp); 142 + cpumask_set_cpu(cpu, &drawer->mask); 143 + cpumask_set_cpu(cpu, &book->mask); 144 + cpumask_set_cpu(cpu, &socket->mask); 145 + smp_cpu_set_polarization(cpu, tl_core->pp); 146 146 } 147 147 } 148 148 }
+3 -1
arch/um/drivers/Makefile
··· 16 16 hostaudio-objs := hostaudio_kern.o 17 17 ubd-objs := ubd_kern.o ubd_user.o 18 18 port-objs := port_kern.o port_user.o 19 - harddog-objs := harddog_kern.o harddog_user.o 19 + harddog-objs := harddog_kern.o 20 + harddog-builtin-$(CONFIG_UML_WATCHDOG) := harddog_user.o harddog_user_exp.o 20 21 rtc-objs := rtc_kern.o rtc_user.o 21 22 22 23 LDFLAGS_pcap.o = $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libpcap.a) ··· 61 60 obj-$(CONFIG_TTY_CHAN) += tty.o 62 61 obj-$(CONFIG_XTERM_CHAN) += xterm.o xterm_kern.o 63 62 obj-$(CONFIG_UML_WATCHDOG) += harddog.o 63 + obj-y += $(harddog-builtin-y) $(harddog-builtin-m) 64 64 obj-$(CONFIG_BLK_DEV_COW_COMMON) += cow_user.o 65 65 obj-$(CONFIG_UML_RANDOM) += random.o 66 66 obj-$(CONFIG_VIRTIO_UML) += virtio_uml.o
+9
arch/um/drivers/harddog.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #ifndef UM_WATCHDOG_H 3 + #define UM_WATCHDOG_H 4 + 5 + int start_watchdog(int *in_fd_ret, int *out_fd_ret, char *sock); 6 + void stop_watchdog(int in_fd, int out_fd); 7 + int ping_watchdog(int fd); 8 + 9 + #endif /* UM_WATCHDOG_H */
+1 -6
arch/um/drivers/harddog_kern.c
··· 47 47 #include <linux/spinlock.h> 48 48 #include <linux/uaccess.h> 49 49 #include "mconsole.h" 50 + #include "harddog.h" 50 51 51 52 MODULE_LICENSE("GPL"); 52 53 ··· 60 59 /* 61 60 * Allow only one person to hold it open 62 61 */ 63 - 64 - extern int start_watchdog(int *in_fd_ret, int *out_fd_ret, char *sock); 65 62 66 63 static int harddog_open(struct inode *inode, struct file *file) 67 64 { ··· 91 92 return err; 92 93 } 93 94 94 - extern void stop_watchdog(int in_fd, int out_fd); 95 - 96 95 static int harddog_release(struct inode *inode, struct file *file) 97 96 { 98 97 /* ··· 108 111 109 112 return 0; 110 113 } 111 - 112 - extern int ping_watchdog(int fd); 113 114 114 115 static ssize_t harddog_write(struct file *file, const char __user *data, size_t len, 115 116 loff_t *ppos)
+1
arch/um/drivers/harddog_user.c
··· 7 7 #include <unistd.h> 8 8 #include <errno.h> 9 9 #include <os.h> 10 + #include "harddog.h" 10 11 11 12 struct dog_data { 12 13 int stdin_fd;
+9
arch/um/drivers/harddog_user_exp.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + #include <linux/export.h> 3 + #include "harddog.h" 4 + 5 + #if IS_MODULE(CONFIG_UML_WATCHDOG) 6 + EXPORT_SYMBOL(start_watchdog); 7 + EXPORT_SYMBOL(stop_watchdog); 8 + EXPORT_SYMBOL(ping_watchdog); 9 + #endif
+2
arch/x86/include/asm/vmx.h
··· 13 13 14 14 15 15 #include <linux/bitops.h> 16 + #include <linux/bug.h> 16 17 #include <linux/types.h> 18 + 17 19 #include <uapi/asm/vmx.h> 18 20 #include <asm/vmxfeatures.h> 19 21
+1
arch/x86/kernel/Makefile
··· 17 17 CFLAGS_REMOVE_early_printk.o = -pg 18 18 CFLAGS_REMOVE_head64.o = -pg 19 19 CFLAGS_REMOVE_sev.o = -pg 20 + CFLAGS_REMOVE_rethook.o = -pg 20 21 endif 21 22 22 23 KASAN_SANITIZE_head$(BITS).o := n
-16
arch/x86/kvm/cpuid.c
··· 253 253 int nent) 254 254 { 255 255 struct kvm_cpuid_entry2 *best; 256 - u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent); 257 256 258 257 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 259 258 if (best) { ··· 290 291 cpuid_entry_change(best, X86_FEATURE_MWAIT, 291 292 vcpu->arch.ia32_misc_enable_msr & 292 293 MSR_IA32_MISC_ENABLE_MWAIT); 293 - } 294 - 295 - /* 296 - * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 297 - * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 298 - * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 299 - * at the time of EENTER, thus adjust the allowed XFRM by the guest's 300 - * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 301 - * '1' even on CPUs that don't support XSAVE. 302 - */ 303 - best = cpuid_entry2_find(entries, nent, 0x12, 0x1); 304 - if (best) { 305 - best->ecx &= guest_supported_xcr0 & 0xffffffff; 306 - best->edx &= guest_supported_xcr0 >> 32; 307 - best->ecx |= XFEATURE_MASK_FPSSE; 308 294 } 309 295 } 310 296
+9 -2
arch/x86/kvm/vmx/sgx.c
··· 170 170 return 1; 171 171 } 172 172 173 - /* Enforce CPUID restrictions on MISCSELECT, ATTRIBUTES and XFRM. */ 173 + /* 174 + * Enforce CPUID restrictions on MISCSELECT, ATTRIBUTES and XFRM. Note 175 + * that the allowed XFRM (XFeature Request Mask) isn't strictly bound 176 + * by the supported XCR0. FP+SSE *must* be set in XFRM, even if XSAVE 177 + * is unsupported, i.e. even if XCR0 itself is completely unsupported. 178 + */ 174 179 if ((u32)miscselect & ~sgx_12_0->ebx || 175 180 (u32)attributes & ~sgx_12_1->eax || 176 181 (u32)(attributes >> 32) & ~sgx_12_1->ebx || 177 182 (u32)xfrm & ~sgx_12_1->ecx || 178 - (u32)(xfrm >> 32) & ~sgx_12_1->edx) { 183 + (u32)(xfrm >> 32) & ~sgx_12_1->edx || 184 + xfrm & ~(vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE) || 185 + (xfrm & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) { 179 186 kvm_inject_gp(vcpu, 0); 180 187 return 1; 181 188 }
+5 -1
arch/x86/kvm/x86.c
··· 1446 1446 #endif 1447 1447 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1448 1448 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1449 - MSR_IA32_SPEC_CTRL, 1449 + MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL, 1450 1450 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1451 1451 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1452 1452 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, ··· 7153 7153 case MSR_IA32_XFD: 7154 7154 case MSR_IA32_XFD_ERR: 7155 7155 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 7156 + return; 7157 + break; 7158 + case MSR_IA32_TSX_CTRL: 7159 + if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) 7156 7160 return; 7157 7161 break; 7158 7162 default:
+11 -1
block/fops.c
··· 678 678 return error; 679 679 } 680 680 681 + static int blkdev_mmap(struct file *file, struct vm_area_struct *vma) 682 + { 683 + struct inode *bd_inode = bdev_file_inode(file); 684 + 685 + if (bdev_read_only(I_BDEV(bd_inode))) 686 + return generic_file_readonly_mmap(file, vma); 687 + 688 + return generic_file_mmap(file, vma); 689 + } 690 + 681 691 const struct file_operations def_blk_fops = { 682 692 .open = blkdev_open, 683 693 .release = blkdev_close, ··· 695 685 .read_iter = blkdev_read_iter, 696 686 .write_iter = blkdev_write_iter, 697 687 .iopoll = iocb_bio_iopoll, 698 - .mmap = generic_file_mmap, 688 + .mmap = blkdev_mmap, 699 689 .fsync = blkdev_fsync, 700 690 .unlocked_ioctl = blkdev_ioctl, 701 691 #ifdef CONFIG_COMPAT
+12
drivers/acpi/resource.c
··· 516 516 { } 517 517 }; 518 518 519 + static const struct dmi_system_id lg_laptop[] = { 520 + { 521 + .ident = "LG Electronics 17U70P", 522 + .matches = { 523 + DMI_MATCH(DMI_SYS_VENDOR, "LG Electronics"), 524 + DMI_MATCH(DMI_BOARD_NAME, "17U70P"), 525 + }, 526 + }, 527 + { } 528 + }; 529 + 519 530 struct irq_override_cmp { 520 531 const struct dmi_system_id *system; 521 532 unsigned char irq; ··· 543 532 { lenovo_laptop, 10, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true }, 544 533 { tongfang_gm_rg, 1, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW, 1, true }, 545 534 { maingear_laptop, 1, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW, 1, true }, 535 + { lg_laptop, 1, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, false }, 546 536 }; 547 537 548 538 static bool acpi_dev_irq_override(u32 gsi, u8 triggering, u8 polarity,
+2
drivers/base/class.c
··· 320 320 start_knode = &start->p->knode_class; 321 321 klist_iter_init_node(&sp->klist_devices, &iter->ki, start_knode); 322 322 iter->type = type; 323 + iter->sp = sp; 323 324 } 324 325 EXPORT_SYMBOL_GPL(class_dev_iter_init); 325 326 ··· 362 361 void class_dev_iter_exit(struct class_dev_iter *iter) 363 362 { 364 363 klist_iter_exit(&iter->ki); 364 + subsys_put(iter->sp); 365 365 } 366 366 EXPORT_SYMBOL_GPL(class_dev_iter_exit); 367 367
+7 -2
drivers/block/ublk_drv.c
··· 1120 1120 return ubq->nr_io_ready == ubq->q_depth; 1121 1121 } 1122 1122 1123 + static void ublk_cmd_cancel_cb(struct io_uring_cmd *cmd, unsigned issue_flags) 1124 + { 1125 + io_uring_cmd_done(cmd, UBLK_IO_RES_ABORT, 0, issue_flags); 1126 + } 1127 + 1123 1128 static void ublk_cancel_queue(struct ublk_queue *ubq) 1124 1129 { 1125 1130 int i; ··· 1136 1131 struct ublk_io *io = &ubq->ios[i]; 1137 1132 1138 1133 if (io->flags & UBLK_IO_FLAG_ACTIVE) 1139 - io_uring_cmd_done(io->cmd, UBLK_IO_RES_ABORT, 0, 1140 - IO_URING_F_UNLOCKED); 1134 + io_uring_cmd_complete_in_task(io->cmd, 1135 + ublk_cmd_cancel_cb); 1141 1136 } 1142 1137 1143 1138 /* all io commands are canceled */
+4
drivers/char/tpm/tpm-chip.c
··· 571 571 { 572 572 struct tpm_chip *chip = container_of(rng, struct tpm_chip, hwrng); 573 573 574 + /* Give back zero bytes, as TPM chip has not yet fully resumed: */ 575 + if (chip->flags & TPM_CHIP_FLAG_SUSPENDED) 576 + return 0; 577 + 574 578 return tpm_get_random(chip, data, max); 575 579 } 576 580
+10
drivers/char/tpm/tpm-interface.c
··· 412 412 } 413 413 414 414 suspended: 415 + chip->flags |= TPM_CHIP_FLAG_SUSPENDED; 416 + 415 417 if (rc) 416 418 dev_err(dev, "Ignoring error %d while suspending\n", rc); 417 419 return 0; ··· 430 428 431 429 if (chip == NULL) 432 430 return -ENODEV; 431 + 432 + chip->flags &= ~TPM_CHIP_FLAG_SUSPENDED; 433 + 434 + /* 435 + * Guarantee that SUSPENDED is written last, so that hwrng does not 436 + * activate before the chip has been fully resumed. 437 + */ 438 + wmb(); 433 439 434 440 return 0; 435 441 }
+16
drivers/char/tpm/tpm_tis.c
··· 122 122 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T490s"), 123 123 }, 124 124 }, 125 + { 126 + .callback = tpm_tis_disable_irq, 127 + .ident = "ThinkStation P360 Tiny", 128 + .matches = { 129 + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 130 + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkStation P360 Tiny"), 131 + }, 132 + }, 133 + { 134 + .callback = tpm_tis_disable_irq, 135 + .ident = "ThinkPad L490", 136 + .matches = { 137 + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 138 + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L490"), 139 + }, 140 + }, 125 141 {} 126 142 }; 127 143
+19 -24
drivers/char/tpm/tpm_tis_core.c
··· 1209 1209 u32 intmask; 1210 1210 int rc; 1211 1211 1212 - if (chip->ops->clk_enable != NULL) 1213 - chip->ops->clk_enable(chip, true); 1214 - 1215 - /* reenable interrupts that device may have lost or 1216 - * BIOS/firmware may have disabled 1212 + /* 1213 + * Re-enable interrupts that device may have lost or BIOS/firmware may 1214 + * have disabled. 1217 1215 */ 1218 1216 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), priv->irq); 1219 - if (rc < 0) 1220 - goto out; 1217 + if (rc < 0) { 1218 + dev_err(&chip->dev, "Setting IRQ failed.\n"); 1219 + return; 1220 + } 1221 1221 1222 1222 intmask = priv->int_mask | TPM_GLOBAL_INT_ENABLE; 1223 - 1224 - tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask); 1225 - 1226 - out: 1227 - if (chip->ops->clk_enable != NULL) 1228 - chip->ops->clk_enable(chip, false); 1229 - 1230 - return; 1223 + rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask); 1224 + if (rc < 0) 1225 + dev_err(&chip->dev, "Enabling interrupts failed.\n"); 1231 1226 } 1232 1227 1233 1228 int tpm_tis_resume(struct device *dev) ··· 1230 1235 struct tpm_chip *chip = dev_get_drvdata(dev); 1231 1236 int ret; 1232 1237 1233 - ret = tpm_tis_request_locality(chip, 0); 1234 - if (ret < 0) 1238 + ret = tpm_chip_start(chip); 1239 + if (ret) 1235 1240 return ret; 1236 1241 1237 1242 if (chip->flags & TPM_CHIP_FLAG_IRQ) 1238 1243 tpm_tis_reenable_interrupts(chip); 1239 - 1240 - ret = tpm_pm_resume(dev); 1241 - if (ret) 1242 - goto out; 1243 1244 1244 1245 /* 1245 1246 * TPM 1.2 requires self-test on resume. This function actually returns ··· 1243 1252 */ 1244 1253 if (!(chip->flags & TPM_CHIP_FLAG_TPM2)) 1245 1254 tpm1_do_selftest(chip); 1246 - out: 1247 - tpm_tis_relinquish_locality(chip, 0); 1248 1255 1249 - return ret; 1256 + tpm_chip_stop(chip); 1257 + 1258 + ret = tpm_pm_resume(dev); 1259 + if (ret) 1260 + return ret; 1261 + 1262 + return 0; 1250 1263 } 1251 1264 EXPORT_SYMBOL_GPL(tpm_tis_resume); 1252 1265 #endif
+1 -1
drivers/cpufreq/acpi-cpufreq.c
··· 975 975 976 976 /* don't keep reloading if cpufreq_driver exists */ 977 977 if (cpufreq_get_current_driver()) 978 - return -EEXIST; 978 + return -ENODEV; 979 979 980 980 pr_debug("%s\n", __func__); 981 981
+1 -1
drivers/cpufreq/pcc-cpufreq.c
··· 583 583 584 584 /* Skip initialization if another cpufreq driver is there. */ 585 585 if (cpufreq_get_current_driver()) 586 - return -EEXIST; 586 + return -ENODEV; 587 587 588 588 if (acpi_disabled) 589 589 return -ENODEV;
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 582 582 if (r) 583 583 amdgpu_fence_driver_force_completion(ring); 584 584 585 - if (ring->fence_drv.irq_src) 585 + if (!drm_dev_is_unplugged(adev_to_drm(adev)) && 586 + ring->fence_drv.irq_src) 586 587 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 587 588 ring->fence_drv.irq_type); 588 589
+7 -1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 8152 8152 case IP_VERSION(10, 3, 3): 8153 8153 case IP_VERSION(10, 3, 6): 8154 8154 case IP_VERSION(10, 3, 7): 8155 + if (!enable) 8156 + amdgpu_gfx_off_ctrl(adev, false); 8157 + 8155 8158 gfx_v10_cntl_pg(adev, enable); 8156 - amdgpu_gfx_off_ctrl(adev, enable); 8159 + 8160 + if (enable) 8161 + amdgpu_gfx_off_ctrl(adev, true); 8162 + 8157 8163 break; 8158 8164 default: 8159 8165 break;
+14 -5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 4667 4667 uint64_t clock; 4668 4668 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4669 4669 4670 - amdgpu_gfx_off_ctrl(adev, false); 4671 - mutex_lock(&adev->gfx.gpu_clock_mutex); 4672 4670 if (amdgpu_sriov_vf(adev)) { 4671 + amdgpu_gfx_off_ctrl(adev, false); 4672 + mutex_lock(&adev->gfx.gpu_clock_mutex); 4673 4673 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4674 4674 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4675 4675 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4676 4676 if (clock_counter_hi_pre != clock_counter_hi_after) 4677 4677 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4678 + mutex_unlock(&adev->gfx.gpu_clock_mutex); 4679 + amdgpu_gfx_off_ctrl(adev, true); 4678 4680 } else { 4681 + preempt_disable(); 4679 4682 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4680 4683 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4681 4684 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4682 4685 if (clock_counter_hi_pre != clock_counter_hi_after) 4683 4686 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4687 + preempt_enable(); 4684 4688 } 4685 4689 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4686 - mutex_unlock(&adev->gfx.gpu_clock_mutex); 4687 - amdgpu_gfx_off_ctrl(adev, true); 4690 + 4688 4691 return clock; 4689 4692 } 4690 4693 ··· 5153 5150 break; 5154 5151 case IP_VERSION(11, 0, 1): 5155 5152 case IP_VERSION(11, 0, 4): 5153 + if (!enable) 5154 + amdgpu_gfx_off_ctrl(adev, false); 5155 + 5156 5156 gfx_v11_cntl_pg(adev, enable); 5157 - amdgpu_gfx_off_ctrl(adev, enable); 5157 + 5158 + if (enable) 5159 + amdgpu_gfx_off_ctrl(adev, true); 5160 + 5158 5161 break; 5159 5162 default: 5160 5163 break;
+16 -21
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 4003 4003 clock = clock_lo | (clock_hi << 32ULL); 4004 4004 break; 4005 4005 case IP_VERSION(9, 1, 0): 4006 - preempt_disable(); 4007 - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4008 - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4009 - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4010 - /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4011 - * roughly every 42 seconds. 4012 - */ 4013 - if (hi_check != clock_hi) { 4014 - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4015 - clock_hi = hi_check; 4016 - } 4017 - preempt_enable(); 4018 - clock = clock_lo | (clock_hi << 32ULL); 4019 - break; 4020 4006 case IP_VERSION(9, 2, 2): 4021 4007 preempt_disable(); 4022 - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4023 - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4024 - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4025 - /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4026 - * roughly every 42 seconds. 4027 - */ 4028 - if (hi_check != clock_hi) { 4008 + if (adev->rev_id >= 0x8) { 4009 + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4029 4010 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4011 + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4012 + } else { 4013 + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4014 + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4015 + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4016 + } 4017 + /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4018 + * roughly every 42 seconds. 4019 + */ 4020 + if (hi_check != clock_hi) { 4021 + if (adev->rev_id >= 0x8) 4022 + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4023 + else 4024 + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4030 4025 clock_hi = hi_check; 4031 4026 } 4032 4027 preempt_enable();
+20 -1
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
··· 31 31 #include "umc_v8_10.h" 32 32 #include "athub/athub_3_0_0_sh_mask.h" 33 33 #include "athub/athub_3_0_0_offset.h" 34 + #include "dcn/dcn_3_2_0_offset.h" 35 + #include "dcn/dcn_3_2_0_sh_mask.h" 34 36 #include "oss/osssys_6_0_0_offset.h" 35 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 38 #include "navi10_enum.h" ··· 548 546 549 547 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 550 548 { 551 - return 0; 549 + u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 550 + unsigned size; 551 + 552 + if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 553 + size = AMDGPU_VBIOS_VGA_ALLOCATION; 554 + } else { 555 + u32 viewport; 556 + u32 pitch; 557 + 558 + viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 559 + pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 560 + size = (REG_GET_FIELD(viewport, 561 + HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 562 + REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 563 + 4); 564 + } 565 + 566 + return size; 552 567 } 553 568 554 569 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
+18
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 733 733 return ret; 734 734 } 735 735 736 + /* 737 + * Explicitly notify PMFW the power mode the system in. Since 738 + * the PMFW may boot the ASIC with a different mode. 739 + * For those supporting ACDC switch via gpio, PMFW will 740 + * handle the switch automatically. Driver involvement 741 + * is unnecessary. 742 + */ 743 + if (!smu->dc_controlled_by_gpio) { 744 + ret = smu_set_power_source(smu, 745 + adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 746 + SMU_POWER_SOURCE_DC); 747 + if (ret) { 748 + dev_err(adev->dev, "Failed to switch to %s mode!\n", 749 + adev->pm.ac_power ? "AC" : "DC"); 750 + return ret; 751 + } 752 + } 753 + 736 754 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 737 755 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 738 756 return 0;
+1 -19
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
··· 3413 3413 return 0; 3414 3414 3415 3415 ret = navi10_run_umc_cdr_workaround(smu); 3416 - if (ret) { 3416 + if (ret) 3417 3417 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3418 - return ret; 3419 - } 3420 - 3421 - if (!smu->dc_controlled_by_gpio) { 3422 - /* 3423 - * For Navi1X, manually switch it to AC mode as PMFW 3424 - * may boot it with DC mode. 3425 - */ 3426 - ret = smu_v11_0_set_power_source(smu, 3427 - adev->pm.ac_power ? 3428 - SMU_POWER_SOURCE_AC : 3429 - SMU_POWER_SOURCE_DC); 3430 - if (ret) { 3431 - dev_err(adev->dev, "Failed to switch to %s mode!\n", 3432 - adev->pm.ac_power ? "AC" : "DC"); 3433 - return ret; 3434 - } 3435 - } 3436 3418 3437 3419 return ret; 3438 3420 }
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
··· 1770 1770 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost, 1771 1771 .get_power_limit = smu_v13_0_7_get_power_limit, 1772 1772 .set_power_limit = smu_v13_0_set_power_limit, 1773 + .set_power_source = smu_v13_0_set_power_source, 1773 1774 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode, 1774 1775 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode, 1775 1776 .set_tool_table_location = smu_v13_0_set_tool_table_location,
+2 -2
drivers/gpu/drm/exynos/exynos_drm_g2d.h
··· 34 34 return -ENODEV; 35 35 } 36 36 37 - int g2d_open(struct drm_device *drm_dev, struct drm_file *file) 37 + static inline int g2d_open(struct drm_device *drm_dev, struct drm_file *file) 38 38 { 39 39 return 0; 40 40 } 41 41 42 - void g2d_close(struct drm_device *drm_dev, struct drm_file *file) 42 + static inline void g2d_close(struct drm_device *drm_dev, struct drm_file *file) 43 43 { } 44 44 #endif
+6 -4
drivers/gpu/drm/i915/display/intel_hdcp.c
··· 204 204 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 205 205 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 206 206 struct intel_hdcp *hdcp = &connector->hdcp; 207 - struct intel_gt *gt = dev_priv->media_gt; 208 - struct intel_gsc_uc *gsc = &gt->uc.gsc; 209 207 bool capable = false; 210 208 211 209 /* I915 support for HDCP2.2 */ ··· 211 213 return false; 212 214 213 215 /* If MTL+ make sure gsc is loaded and proxy is setup */ 214 - if (intel_hdcp_gsc_cs_required(dev_priv)) 215 - if (!intel_uc_fw_is_running(&gsc->fw)) 216 + if (intel_hdcp_gsc_cs_required(dev_priv)) { 217 + struct intel_gt *gt = dev_priv->media_gt; 218 + struct intel_gsc_uc *gsc = gt ? &gt->uc.gsc : NULL; 219 + 220 + if (!gsc || !intel_uc_fw_is_running(&gsc->fw)) 216 221 return false; 222 + } 217 223 218 224 /* MEI/GSC interface is solid depending on which is used */ 219 225 mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+8 -8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
··· 98 98 99 99 static const struct dpu_lm_cfg msm8998_lm[] = { 100 100 LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, 101 - &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), 101 + &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 102 102 LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, 103 - &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), 103 + &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 104 104 LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, 105 - &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), 105 + &msm8998_lm_sblk, PINGPONG_2, LM_5, 0), 106 106 LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, 107 107 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 108 108 LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, 109 109 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 110 110 LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, 111 - &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), 111 + &msm8998_lm_sblk, PINGPONG_3, LM_2, 0), 112 112 }; 113 113 114 114 static const struct dpu_pingpong_cfg msm8998_pp[] = { ··· 134 134 }; 135 135 136 136 static const struct dpu_intf_cfg msm8998_intf[] = { 137 - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 138 - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 139 - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 140 - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 137 + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 138 + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 139 + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 140 + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 141 141 }; 142 142 143 143 static const struct dpu_perf_cfg msm8998_perf_data = {
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 128 128 }; 129 129 130 130 static const struct dpu_pingpong_cfg sm8150_pp[] = { 131 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 131 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 132 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 134 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 134 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 135 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 137 137 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 116 116 }; 117 117 118 118 static const struct dpu_pingpong_cfg sc8180x_pp[] = { 119 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 119 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 120 120 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 121 121 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 122 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 122 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 123 123 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 124 124 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 125 125 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 129 129 }; 130 130 131 131 static const struct dpu_pingpong_cfg sm8250_pp[] = { 132 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 132 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 133 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 134 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 135 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 135 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 137 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 138 138 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+2 -2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
··· 80 80 }; 81 81 82 82 static const struct dpu_pingpong_cfg sc7180_pp[] = { 83 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), 84 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), 83 + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, -1, -1), 84 + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk, -1, -1), 85 85 }; 86 86 87 87 static const struct dpu_intf_cfg sc7180_intf[] = {
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
··· 122 122 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 123 123 BIT(MDP_SSPP_TOP0_INTR2) | \ 124 124 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 125 - BIT(MDP_INTF0_INTR) | \ 126 125 BIT(MDP_INTF1_INTR), 127 126 }; 128 127
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
··· 112 112 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 113 113 BIT(MDP_SSPP_TOP0_INTR2) | \ 114 114 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 115 - BIT(MDP_INTF0_INTR) | \ 116 115 BIT(MDP_INTF1_INTR), 117 116 }; 118 117
+6 -6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
··· 127 127 }; 128 128 129 129 static const struct dpu_pingpong_cfg sm8350_pp[] = { 130 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 130 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 131 131 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 132 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 133 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 133 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 134 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 135 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 136 - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, 136 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 137 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 138 138 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 139 - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, 139 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 140 140 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 141 141 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 142 - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, 142 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 143 143 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 144 144 -1), 145 - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, 145 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 146 146 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 147 147 -1), 148 148 };
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
··· 87 87 }; 88 88 89 89 static const struct dpu_pingpong_cfg sc7280_pp[] = { 90 - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 91 - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 92 - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 93 - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 90 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 91 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 92 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 93 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 94 94 }; 95 95 96 96 static const struct dpu_intf_cfg sc7280_intf[] = {
+12 -12
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
··· 121 121 }; 122 122 123 123 static const struct dpu_pingpong_cfg sc8280xp_pp[] = { 124 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 125 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), 126 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 127 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), 128 - PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te, 129 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), 130 - PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te, 131 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), 132 - PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te, 133 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), 134 - PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te, 135 - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), 124 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 125 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), 126 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 127 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), 128 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 129 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), 130 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 131 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), 132 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 133 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), 134 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 135 + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), 136 136 }; 137 137 138 138 static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
+8 -8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
··· 128 128 }; 129 129 /* FIXME: interrupts */ 130 130 static const struct dpu_pingpong_cfg sm8450_pp[] = { 131 - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 131 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 132 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 134 - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 134 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 135 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 137 - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, 137 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 138 138 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 139 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 140 - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, 140 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 141 141 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 142 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 143 - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, 143 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 144 144 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 145 145 -1), 146 - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, 146 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 147 147 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 148 148 -1), 149 - PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, 149 + PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk, 150 150 -1, 151 151 -1), 152 - PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, 152 + PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk, 153 153 -1, 154 154 -1), 155 155 };
+8 -8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
··· 132 132 &sm8150_dspp_sblk), 133 133 }; 134 134 static const struct dpu_pingpong_cfg sm8550_pp[] = { 135 - PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 135 + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 136 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 137 137 -1), 138 - PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 138 + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 139 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 140 140 -1), 141 - PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 141 + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 142 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 143 143 -1), 144 - PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 144 + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 145 145 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 146 146 -1), 147 - PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 147 + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 148 148 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 149 149 -1), 150 - PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 150 + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 151 151 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 152 152 -1), 153 - PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 153 + PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 154 154 -1, 155 155 -1), 156 - PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 156 + PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 157 157 -1, 158 158 -1), 159 159 };
+6 -11
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 491 491 .len = 0x20, .version = 0x20000}, 492 492 }; 493 493 494 - #define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 494 + #define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 495 495 {\ 496 496 .name = _name, .id = _id, \ 497 497 .base = _base, .len = 0, \ ··· 587 587 588 588 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 589 589 { 590 - .pps = 1088 * 1920 * 30, 590 + .pps = 1920 * 1080 * 30, 591 591 .ot_limit = 2, 592 592 }, 593 593 { 594 - .pps = 1088 * 1920 * 60, 595 - .ot_limit = 6, 594 + .pps = 1920 * 1080 * 60, 595 + .ot_limit = 4, 596 596 }, 597 597 { 598 598 .pps = 3840 * 2160 * 30, ··· 705 705 {.fl = 10, .lut = 0x1555b}, 706 706 {.fl = 11, .lut = 0x5555b}, 707 707 {.fl = 12, .lut = 0x15555b}, 708 - {.fl = 13, .lut = 0x55555b}, 709 - {.fl = 14, .lut = 0}, 710 - {.fl = 1, .lut = 0x1b}, 711 - {.fl = 0, .lut = 0} 708 + {.fl = 0, .lut = 0x55555b} 712 709 }; 713 710 714 711 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { ··· 727 730 {.fl = 10, .lut = 0x1aaff}, 728 731 {.fl = 11, .lut = 0x5aaff}, 729 732 {.fl = 12, .lut = 0x15aaff}, 730 - {.fl = 13, .lut = 0x55aaff}, 731 - {.fl = 1, .lut = 0x1aaff}, 732 - {.fl = 0, .lut = 0}, 733 + {.fl = 0, .lut = 0x55aaff}, 733 734 }; 734 735 735 736 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
+13 -10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
··· 15 15 16 16 /* 17 17 * Register offsets in MDSS register file for the interrupt registers 18 - * w.r.t. to the MDP base 18 + * w.r.t. the MDP base 19 19 */ 20 20 #define MDP_SSPP_TOP0_OFF 0x0 21 21 #define MDP_INTF_0_OFF 0x6A000 ··· 24 24 #define MDP_INTF_3_OFF 0x6B800 25 25 #define MDP_INTF_4_OFF 0x6C000 26 26 #define MDP_INTF_5_OFF 0x6C800 27 + #define INTF_INTR_EN 0x1c0 28 + #define INTF_INTR_STATUS 0x1c4 29 + #define INTF_INTR_CLEAR 0x1c8 27 30 #define MDP_AD4_0_OFF 0x7C000 28 31 #define MDP_AD4_1_OFF 0x7D000 29 32 #define MDP_AD4_INTR_EN_OFF 0x41c 30 33 #define MDP_AD4_INTR_CLEAR_OFF 0x424 31 34 #define MDP_AD4_INTR_STATUS_OFF 0x420 32 - #define MDP_INTF_0_OFF_REV_7xxx 0x34000 33 - #define MDP_INTF_1_OFF_REV_7xxx 0x35000 34 - #define MDP_INTF_2_OFF_REV_7xxx 0x36000 35 - #define MDP_INTF_3_OFF_REV_7xxx 0x37000 36 - #define MDP_INTF_4_OFF_REV_7xxx 0x38000 37 - #define MDP_INTF_5_OFF_REV_7xxx 0x39000 38 - #define MDP_INTF_6_OFF_REV_7xxx 0x3a000 39 - #define MDP_INTF_7_OFF_REV_7xxx 0x3b000 40 - #define MDP_INTF_8_OFF_REV_7xxx 0x3c000 35 + #define MDP_INTF_0_OFF_REV_7xxx 0x34000 36 + #define MDP_INTF_1_OFF_REV_7xxx 0x35000 37 + #define MDP_INTF_2_OFF_REV_7xxx 0x36000 38 + #define MDP_INTF_3_OFF_REV_7xxx 0x37000 39 + #define MDP_INTF_4_OFF_REV_7xxx 0x38000 40 + #define MDP_INTF_5_OFF_REV_7xxx 0x39000 41 + #define MDP_INTF_6_OFF_REV_7xxx 0x3a000 42 + #define MDP_INTF_7_OFF_REV_7xxx 0x3b000 43 + #define MDP_INTF_8_OFF_REV_7xxx 0x3c000 41 44 42 45 /** 43 46 * struct dpu_intr_reg - array of DPU register sets
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
··· 56 56 #define INTF_TPG_RGB_MAPPING 0x11C 57 57 #define INTF_PROG_FETCH_START 0x170 58 58 #define INTF_PROG_ROT_START 0x174 59 - 60 - #define INTF_FRAME_LINE_COUNT_EN 0x0A8 61 - #define INTF_FRAME_COUNT 0x0AC 62 - #define INTF_LINE_COUNT 0x0B0 63 - 64 59 #define INTF_MUX 0x25C 65 60 #define INTF_STATUS 0x26C 66 61
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
··· 61 61 for (i = 0; i < m->wb_count; i++) { 62 62 if (wb == m->wb[i].id) { 63 63 b->blk_addr = addr + m->wb[i].base; 64 + b->log_mask = DPU_DBG_MASK_WB; 64 65 return &m->wb[i]; 65 66 } 66 67 }
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
··· 21 21 #define HIST_INTR_EN 0x01c 22 22 #define HIST_INTR_STATUS 0x020 23 23 #define HIST_INTR_CLEAR 0x024 24 - #define INTF_INTR_EN 0x1C0 25 - #define INTF_INTR_STATUS 0x1C4 26 - #define INTF_INTR_CLEAR 0x1C8 27 24 #define SPLIT_DISPLAY_EN 0x2F4 28 25 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 29 26 #define DSPP_IGC_COLOR0_RAM_LUTN 0x300
+12
drivers/gpu/drm/msm/dp/dp_audio.c
··· 593 593 .i2s = 1, 594 594 }; 595 595 596 + void dp_unregister_audio_driver(struct device *dev, struct dp_audio *dp_audio) 597 + { 598 + struct dp_audio_private *audio_priv; 599 + 600 + audio_priv = container_of(dp_audio, struct dp_audio_private, dp_audio); 601 + 602 + if (audio_priv->audio_pdev) { 603 + platform_device_unregister(audio_priv->audio_pdev); 604 + audio_priv->audio_pdev = NULL; 605 + } 606 + } 607 + 596 608 int dp_register_audio_driver(struct device *dev, 597 609 struct dp_audio *dp_audio) 598 610 {
+2
drivers/gpu/drm/msm/dp/dp_audio.h
··· 53 53 int dp_register_audio_driver(struct device *dev, 54 54 struct dp_audio *dp_audio); 55 55 56 + void dp_unregister_audio_driver(struct device *dev, struct dp_audio *dp_audio); 57 + 56 58 /** 57 59 * dp_audio_put() 58 60 *
+1
drivers/gpu/drm/msm/dp/dp_display.c
··· 326 326 kthread_stop(dp->ev_tsk); 327 327 328 328 dp_power_client_deinit(dp->power); 329 + dp_unregister_audio_driver(dev, dp->audio); 329 330 dp_aux_unregister(dp->aux); 330 331 dp->drm_dev = NULL; 331 332 dp->aux->drm_dev = NULL;
+2
drivers/gpu/drm/msm/msm_atomic.c
··· 155 155 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 156 156 if (drm_atomic_crtc_needs_modeset(crtc_state)) 157 157 return false; 158 + if (!crtc_state->active) 159 + return false; 158 160 if (++num_crtcs > 1) 159 161 return false; 160 162 *async_crtc = crtc;
+8 -14
drivers/gpu/drm/msm/msm_gem.c
··· 219 219 } 220 220 } 221 221 222 - static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj) 222 + static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj, 223 + unsigned madv) 223 224 { 224 225 struct msm_drm_private *priv = obj->dev->dev_private; 225 226 struct msm_gem_object *msm_obj = to_msm_bo(obj); ··· 228 227 229 228 msm_gem_assert_locked(obj); 230 229 231 - if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) { 230 + if (GEM_WARN_ON(msm_obj->madv > madv)) { 231 + DRM_DEV_ERROR(obj->dev->dev, "Invalid madv state: %u vs %u\n", 232 + msm_obj->madv, madv); 232 233 return ERR_PTR(-EBUSY); 233 234 } 234 235 ··· 251 248 struct page **p; 252 249 253 250 msm_gem_lock(obj); 254 - p = msm_gem_pin_pages_locked(obj); 251 + p = msm_gem_pin_pages_locked(obj, MSM_MADV_WILLNEED); 255 252 msm_gem_unlock(obj); 256 253 257 254 return p; ··· 476 473 477 474 msm_gem_assert_locked(obj); 478 475 479 - if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) 480 - return -EBUSY; 481 - 482 - pages = msm_gem_pin_pages_locked(obj); 476 + pages = msm_gem_pin_pages_locked(obj, MSM_MADV_WILLNEED); 483 477 if (IS_ERR(pages)) 484 478 return PTR_ERR(pages); 485 479 ··· 699 699 if (obj->import_attach) 700 700 return ERR_PTR(-ENODEV); 701 701 702 - if (GEM_WARN_ON(msm_obj->madv > madv)) { 703 - DRM_DEV_ERROR(obj->dev->dev, "Invalid madv state: %u vs %u\n", 704 - msm_obj->madv, madv); 705 - return ERR_PTR(-EBUSY); 706 - } 707 - 708 - pages = msm_gem_pin_pages_locked(obj); 702 + pages = msm_gem_pin_pages_locked(obj, madv); 709 703 if (IS_ERR(pages)) 710 704 return ERR_CAST(pages); 711 705
+18 -7
drivers/gpu/drm/msm/msm_gem_submit.c
··· 722 722 struct msm_drm_private *priv = dev->dev_private; 723 723 struct drm_msm_gem_submit *args = data; 724 724 struct msm_file_private *ctx = file->driver_priv; 725 - struct msm_gem_submit *submit; 725 + struct msm_gem_submit *submit = NULL; 726 726 struct msm_gpu *gpu = priv->gpu; 727 727 struct msm_gpu_submitqueue *queue; 728 728 struct msm_ringbuffer *ring; ··· 769 769 out_fence_fd = get_unused_fd_flags(O_CLOEXEC); 770 770 if (out_fence_fd < 0) { 771 771 ret = out_fence_fd; 772 - return ret; 772 + goto out_post_unlock; 773 773 } 774 774 } 775 775 776 776 submit = submit_create(dev, gpu, queue, args->nr_bos, args->nr_cmds); 777 - if (IS_ERR(submit)) 778 - return PTR_ERR(submit); 777 + if (IS_ERR(submit)) { 778 + ret = PTR_ERR(submit); 779 + goto out_post_unlock; 780 + } 779 781 780 782 trace_msm_gpu_submit(pid_nr(submit->pid), ring->id, submit->ident, 781 783 args->nr_bos, args->nr_cmds); ··· 964 962 if (has_ww_ticket) 965 963 ww_acquire_fini(&submit->ticket); 966 964 out_unlock: 967 - if (ret && (out_fence_fd >= 0)) 968 - put_unused_fd(out_fence_fd); 969 965 mutex_unlock(&queue->lock); 970 966 out_post_unlock: 971 - msm_gem_submit_put(submit); 967 + if (ret && (out_fence_fd >= 0)) 968 + put_unused_fd(out_fence_fd); 969 + 970 + if (!IS_ERR_OR_NULL(submit)) { 971 + msm_gem_submit_put(submit); 972 + } else { 973 + /* 974 + * If the submit hasn't yet taken ownership of the queue 975 + * then we need to drop the reference ourself: 976 + */ 977 + msm_submitqueue_put(queue); 978 + } 972 979 if (!IS_ERR_OR_NULL(post_deps)) { 973 980 for (i = 0; i < args->nr_out_syncobjs; ++i) { 974 981 kfree(post_deps[i].chain);
+7 -2
drivers/gpu/drm/msm/msm_iommu.c
··· 234 234 /* Get the pagetable configuration from the domain */ 235 235 if (adreno_smmu->cookie) 236 236 ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); 237 - if (!ttbr1_cfg) 237 + 238 + /* 239 + * If you hit this WARN_ONCE() you are probably missing an entry in 240 + * qcom_smmu_impl_of_match[] in arm-smmu-qcom.c 241 + */ 242 + if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables")) 238 243 return ERR_PTR(-ENODEV); 239 244 240 245 pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); ··· 415 410 struct msm_mmu *mmu; 416 411 417 412 mmu = msm_iommu_new(dev, quirks); 418 - if (IS_ERR(mmu)) 413 + if (IS_ERR_OR_NULL(mmu)) 419 414 return mmu; 420 415 421 416 iommu = to_msm_iommu(mmu);
-16
drivers/iommu/Kconfig
··· 417 417 help 418 418 Support for the IOMMU API for s390 PCI devices. 419 419 420 - config S390_CCW_IOMMU 421 - bool "S390 CCW IOMMU Support" 422 - depends on S390 && CCW || COMPILE_TEST 423 - select IOMMU_API 424 - help 425 - Enables bits of IOMMU API required by VFIO. The iommu_ops 426 - is not implemented as it is not necessary for VFIO. 427 - 428 - config S390_AP_IOMMU 429 - bool "S390 AP IOMMU Support" 430 - depends on S390 && ZCRYPT || COMPILE_TEST 431 - select IOMMU_API 432 - help 433 - Enables bits of IOMMU API required by VFIO. The iommu_ops 434 - is not implemented as it is not necessary for VFIO. 435 - 436 420 config MTK_IOMMU 437 421 tristate "MediaTek IOMMU Support" 438 422 depends on ARCH_MEDIATEK || COMPILE_TEST
+10
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
··· 517 517 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data }, 518 518 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, 519 519 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, 520 + { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, 520 521 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, 521 522 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, 522 523 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, ··· 561 560 match = of_match_node(qcom_smmu_impl_of_match, np); 562 561 if (match) 563 562 return qcom_smmu_create(smmu, match->data); 563 + 564 + /* 565 + * If you hit this WARN_ON() you are missing an entry in the 566 + * qcom_smmu_impl_of_match[] table, and GPU per-process page- 567 + * tables will be broken. 568 + */ 569 + WARN(of_device_is_compatible(np, "qcom,adreno-smmu"), 570 + "Missing qcom_smmu_impl_of_match entry for: %s", 571 + dev_name(smmu->dev)); 564 572 565 573 return smmu; 566 574 }
+43 -6
drivers/media/dvb-core/dvb_ca_en50221.c
··· 151 151 152 152 /* mutex serializing ioctls */ 153 153 struct mutex ioctl_mutex; 154 + 155 + /* A mutex used when a device is disconnected */ 156 + struct mutex remove_mutex; 157 + 158 + /* Whether the device is disconnected */ 159 + int exit; 154 160 }; 155 161 156 162 static void dvb_ca_private_free(struct dvb_ca_private *ca) ··· 193 187 static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, 194 188 u8 *ebuf, int ecount); 195 189 static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, 196 - u8 *ebuf, int ecount); 190 + u8 *ebuf, int ecount, int size_write_flag); 197 191 198 192 /** 199 193 * findstr - Safely find needle in haystack. ··· 376 370 ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_FR, HZ / 10); 377 371 if (ret) 378 372 return ret; 379 - ret = dvb_ca_en50221_write_data(ca, slot, buf, 2); 373 + ret = dvb_ca_en50221_write_data(ca, slot, buf, 2, CMDREG_SW); 380 374 if (ret != 2) 381 375 return -EIO; 382 376 ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN); ··· 784 778 * @buf: The data in this buffer is treated as a complete link-level packet to 785 779 * be written. 786 780 * @bytes_write: Size of ebuf. 781 + * @size_write_flag: A flag on Command Register which says whether the link size 782 + * information will be writen or not. 787 783 * 788 784 * return: Number of bytes written, or < 0 on error. 789 785 */ 790 786 static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, 791 - u8 *buf, int bytes_write) 787 + u8 *buf, int bytes_write, int size_write_flag) 792 788 { 793 789 struct dvb_ca_slot *sl = &ca->slot_info[slot]; 794 790 int status; ··· 825 817 826 818 /* OK, set HC bit */ 827 819 status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, 828 - IRQEN | CMDREG_HC); 820 + IRQEN | CMDREG_HC | size_write_flag); 829 821 if (status) 830 822 goto exit; 831 823 ··· 1516 1508 1517 1509 mutex_lock(&sl->slot_lock); 1518 1510 status = dvb_ca_en50221_write_data(ca, slot, fragbuf, 1519 - fraglen + 2); 1511 + fraglen + 2, 0); 1520 1512 mutex_unlock(&sl->slot_lock); 1521 1513 if (status == (fraglen + 2)) { 1522 1514 written = 1; ··· 1717 1709 1718 1710 dprintk("%s\n", __func__); 1719 1711 1720 - if (!try_module_get(ca->pub->owner)) 1712 + mutex_lock(&ca->remove_mutex); 1713 + 1714 + if (ca->exit) { 1715 + mutex_unlock(&ca->remove_mutex); 1716 + return -ENODEV; 1717 + } 1718 + 1719 + if (!try_module_get(ca->pub->owner)) { 1720 + mutex_unlock(&ca->remove_mutex); 1721 1721 return -EIO; 1722 + } 1722 1723 1723 1724 err = dvb_generic_open(inode, file); 1724 1725 if (err < 0) { 1725 1726 module_put(ca->pub->owner); 1727 + mutex_unlock(&ca->remove_mutex); 1726 1728 return err; 1727 1729 } 1728 1730 ··· 1757 1739 1758 1740 dvb_ca_private_get(ca); 1759 1741 1742 + mutex_unlock(&ca->remove_mutex); 1760 1743 return 0; 1761 1744 } 1762 1745 ··· 1777 1758 1778 1759 dprintk("%s\n", __func__); 1779 1760 1761 + mutex_lock(&ca->remove_mutex); 1762 + 1780 1763 /* mark the CA device as closed */ 1781 1764 ca->open = 0; 1782 1765 dvb_ca_en50221_thread_update_delay(ca); ··· 1788 1767 module_put(ca->pub->owner); 1789 1768 1790 1769 dvb_ca_private_put(ca); 1770 + 1771 + if (dvbdev->users == 1 && ca->exit == 1) { 1772 + mutex_unlock(&ca->remove_mutex); 1773 + wake_up(&dvbdev->wait_queue); 1774 + } else { 1775 + mutex_unlock(&ca->remove_mutex); 1776 + } 1791 1777 1792 1778 return err; 1793 1779 } ··· 1919 1891 } 1920 1892 1921 1893 mutex_init(&ca->ioctl_mutex); 1894 + mutex_init(&ca->remove_mutex); 1922 1895 1923 1896 if (signal_pending(current)) { 1924 1897 ret = -EINTR; ··· 1961 1932 int i; 1962 1933 1963 1934 dprintk("%s\n", __func__); 1935 + 1936 + mutex_lock(&ca->remove_mutex); 1937 + ca->exit = 1; 1938 + mutex_unlock(&ca->remove_mutex); 1939 + 1940 + if (ca->dvbdev->users < 1) 1941 + wait_event(ca->dvbdev->wait_queue, 1942 + ca->dvbdev->users == 1); 1964 1943 1965 1944 /* shutdown the thread if there was one */ 1966 1945 kthread_stop(ca->thread);
+2 -2
drivers/media/dvb-core/dvb_demux.c
··· 115 115 116 116 cc = buf[3] & 0x0f; 117 117 ccok = ((feed->cc + 1) & 0x0f) == cc; 118 - feed->cc = cc; 119 118 if (!ccok) { 120 119 set_buf_flags(feed, DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED); 121 120 dprintk_sect_loss("missed packet: %d instead of %d!\n", 122 121 cc, (feed->cc + 1) & 0x0f); 123 122 } 123 + feed->cc = cc; 124 124 125 125 if (buf[1] & 0x40) // PUSI ? 126 126 feed->peslen = 0xfffa; ··· 300 300 301 301 cc = buf[3] & 0x0f; 302 302 ccok = ((feed->cc + 1) & 0x0f) == cc; 303 - feed->cc = cc; 304 303 305 304 if (buf[3] & 0x20) { 306 305 /* adaption field present, check for discontinuity_indicator */ ··· 335 336 feed->pusi_seen = false; 336 337 dvb_dmx_swfilter_section_new(feed); 337 338 } 339 + feed->cc = cc; 338 340 339 341 if (buf[1] & 0x40) { 340 342 /* PUSI=1 (is set), section boundary is here */
+56 -13
drivers/media/dvb-core/dvb_frontend.c
··· 293 293 } 294 294 295 295 if (events->eventw == events->eventr) { 296 - int ret; 296 + struct wait_queue_entry wait; 297 + int ret = 0; 297 298 298 299 if (flags & O_NONBLOCK) 299 300 return -EWOULDBLOCK; 300 301 301 - ret = wait_event_interruptible(events->wait_queue, 302 - dvb_frontend_test_event(fepriv, events)); 303 - 302 + init_waitqueue_entry(&wait, current); 303 + add_wait_queue(&events->wait_queue, &wait); 304 + while (!dvb_frontend_test_event(fepriv, events)) { 305 + wait_woken(&wait, TASK_INTERRUPTIBLE, 0); 306 + if (signal_pending(current)) { 307 + ret = -ERESTARTSYS; 308 + break; 309 + } 310 + } 311 + remove_wait_queue(&events->wait_queue, &wait); 304 312 if (ret < 0) 305 313 return ret; 306 314 } ··· 817 809 818 810 dev_dbg(fe->dvb->device, "%s:\n", __func__); 819 811 812 + mutex_lock(&fe->remove_mutex); 813 + 820 814 if (fe->exit != DVB_FE_DEVICE_REMOVED) 821 815 fe->exit = DVB_FE_NORMAL_EXIT; 822 816 mb(); 823 817 824 - if (!fepriv->thread) 818 + if (!fepriv->thread) { 819 + mutex_unlock(&fe->remove_mutex); 825 820 return; 821 + } 826 822 827 823 kthread_stop(fepriv->thread); 824 + 825 + mutex_unlock(&fe->remove_mutex); 826 + 827 + if (fepriv->dvbdev->users < -1) { 828 + wait_event(fepriv->dvbdev->wait_queue, 829 + fepriv->dvbdev->users == -1); 830 + } 828 831 829 832 sema_init(&fepriv->sem, 1); 830 833 fepriv->state = FESTATE_IDLE; ··· 2780 2761 struct dvb_adapter *adapter = fe->dvb; 2781 2762 int ret; 2782 2763 2764 + mutex_lock(&fe->remove_mutex); 2765 + 2783 2766 dev_dbg(fe->dvb->device, "%s:\n", __func__); 2784 - if (fe->exit == DVB_FE_DEVICE_REMOVED) 2785 - return -ENODEV; 2767 + if (fe->exit == DVB_FE_DEVICE_REMOVED) { 2768 + ret = -ENODEV; 2769 + goto err_remove_mutex; 2770 + } 2786 2771 2787 2772 if (adapter->mfe_shared == 2) { 2788 2773 mutex_lock(&adapter->mfe_lock); ··· 2794 2771 if (adapter->mfe_dvbdev && 2795 2772 !adapter->mfe_dvbdev->writers) { 2796 2773 mutex_unlock(&adapter->mfe_lock); 2797 - return -EBUSY; 2774 + ret = -EBUSY; 2775 + goto err_remove_mutex; 2798 2776 } 2799 2777 adapter->mfe_dvbdev = dvbdev; 2800 2778 } ··· 2818 2794 while (mferetry-- && (mfedev->users != -1 || 2819 2795 mfepriv->thread)) { 2820 2796 if (msleep_interruptible(500)) { 2821 - if (signal_pending(current)) 2822 - return -EINTR; 2797 + if (signal_pending(current)) { 2798 + ret = -EINTR; 2799 + goto err_remove_mutex; 2800 + } 2823 2801 } 2824 2802 } 2825 2803 ··· 2833 2807 if (mfedev->users != -1 || 2834 2808 mfepriv->thread) { 2835 2809 mutex_unlock(&adapter->mfe_lock); 2836 - return -EBUSY; 2810 + ret = -EBUSY; 2811 + goto err_remove_mutex; 2837 2812 } 2838 2813 adapter->mfe_dvbdev = dvbdev; 2839 2814 } ··· 2893 2866 2894 2867 if (adapter->mfe_shared) 2895 2868 mutex_unlock(&adapter->mfe_lock); 2869 + 2870 + mutex_unlock(&fe->remove_mutex); 2896 2871 return ret; 2897 2872 2898 2873 err3: ··· 2916 2887 err0: 2917 2888 if (adapter->mfe_shared) 2918 2889 mutex_unlock(&adapter->mfe_lock); 2890 + 2891 + err_remove_mutex: 2892 + mutex_unlock(&fe->remove_mutex); 2919 2893 return ret; 2920 2894 } 2921 2895 ··· 2928 2896 struct dvb_frontend *fe = dvbdev->priv; 2929 2897 struct dvb_frontend_private *fepriv = fe->frontend_priv; 2930 2898 int ret; 2899 + 2900 + mutex_lock(&fe->remove_mutex); 2931 2901 2932 2902 dev_dbg(fe->dvb->device, "%s:\n", __func__); 2933 2903 ··· 2952 2918 } 2953 2919 mutex_unlock(&fe->dvb->mdev_lock); 2954 2920 #endif 2955 - if (fe->exit != DVB_FE_NO_EXIT) 2956 - wake_up(&dvbdev->wait_queue); 2957 2921 if (fe->ops.ts_bus_ctrl) 2958 2922 fe->ops.ts_bus_ctrl(fe, 0); 2923 + 2924 + if (fe->exit != DVB_FE_NO_EXIT) { 2925 + mutex_unlock(&fe->remove_mutex); 2926 + wake_up(&dvbdev->wait_queue); 2927 + } else { 2928 + mutex_unlock(&fe->remove_mutex); 2929 + } 2930 + 2931 + } else { 2932 + mutex_unlock(&fe->remove_mutex); 2959 2933 } 2960 2934 2961 2935 dvb_frontend_put(fe); ··· 3064 3022 fepriv = fe->frontend_priv; 3065 3023 3066 3024 kref_init(&fe->refcount); 3025 + mutex_init(&fe->remove_mutex); 3067 3026 3068 3027 /* 3069 3028 * After initialization, there need to be two references: one
+35 -3
drivers/media/dvb-core/dvb_net.c
··· 1564 1564 return dvb_usercopy(file, cmd, arg, dvb_net_do_ioctl); 1565 1565 } 1566 1566 1567 + static int locked_dvb_net_open(struct inode *inode, struct file *file) 1568 + { 1569 + struct dvb_device *dvbdev = file->private_data; 1570 + struct dvb_net *dvbnet = dvbdev->priv; 1571 + int ret; 1572 + 1573 + if (mutex_lock_interruptible(&dvbnet->remove_mutex)) 1574 + return -ERESTARTSYS; 1575 + 1576 + if (dvbnet->exit) { 1577 + mutex_unlock(&dvbnet->remove_mutex); 1578 + return -ENODEV; 1579 + } 1580 + 1581 + ret = dvb_generic_open(inode, file); 1582 + 1583 + mutex_unlock(&dvbnet->remove_mutex); 1584 + 1585 + return ret; 1586 + } 1587 + 1567 1588 static int dvb_net_close(struct inode *inode, struct file *file) 1568 1589 { 1569 1590 struct dvb_device *dvbdev = file->private_data; 1570 1591 struct dvb_net *dvbnet = dvbdev->priv; 1571 1592 1593 + mutex_lock(&dvbnet->remove_mutex); 1594 + 1572 1595 dvb_generic_release(inode, file); 1573 1596 1574 - if(dvbdev->users == 1 && dvbnet->exit == 1) 1597 + if (dvbdev->users == 1 && dvbnet->exit == 1) { 1598 + mutex_unlock(&dvbnet->remove_mutex); 1575 1599 wake_up(&dvbdev->wait_queue); 1600 + } else { 1601 + mutex_unlock(&dvbnet->remove_mutex); 1602 + } 1603 + 1576 1604 return 0; 1577 1605 } 1578 1606 ··· 1608 1580 static const struct file_operations dvb_net_fops = { 1609 1581 .owner = THIS_MODULE, 1610 1582 .unlocked_ioctl = dvb_net_ioctl, 1611 - .open = dvb_generic_open, 1583 + .open = locked_dvb_net_open, 1612 1584 .release = dvb_net_close, 1613 1585 .llseek = noop_llseek, 1614 1586 }; ··· 1627 1599 { 1628 1600 int i; 1629 1601 1602 + mutex_lock(&dvbnet->remove_mutex); 1630 1603 dvbnet->exit = 1; 1604 + mutex_unlock(&dvbnet->remove_mutex); 1605 + 1631 1606 if (dvbnet->dvbdev->users < 1) 1632 1607 wait_event(dvbnet->dvbdev->wait_queue, 1633 - dvbnet->dvbdev->users==1); 1608 + dvbnet->dvbdev->users == 1); 1634 1609 1635 1610 dvb_unregister_device(dvbnet->dvbdev); 1636 1611 ··· 1652 1621 int i; 1653 1622 1654 1623 mutex_init(&dvbnet->ioctl_mutex); 1624 + mutex_init(&dvbnet->remove_mutex); 1655 1625 dvbnet->demux = dmx; 1656 1626 1657 1627 for (i=0; i<DVB_NET_DEVICES_MAX; i++)
+63 -21
drivers/media/dvb-core/dvbdev.c
··· 27 27 #include <media/tuner.h> 28 28 29 29 static DEFINE_MUTEX(dvbdev_mutex); 30 + static LIST_HEAD(dvbdevfops_list); 30 31 static int dvbdev_debug; 31 32 32 33 module_param(dvbdev_debug, int, 0644); ··· 454 453 enum dvb_device_type type, int demux_sink_pads) 455 454 { 456 455 struct dvb_device *dvbdev; 457 - struct file_operations *dvbdevfops; 456 + struct file_operations *dvbdevfops = NULL; 457 + struct dvbdevfops_node *node = NULL, *new_node = NULL; 458 458 struct device *clsdev; 459 459 int minor; 460 460 int id, ret; 461 461 462 462 mutex_lock(&dvbdev_register_lock); 463 463 464 - if ((id = dvbdev_get_free_id (adap, type)) < 0){ 464 + if ((id = dvbdev_get_free_id (adap, type)) < 0) { 465 465 mutex_unlock(&dvbdev_register_lock); 466 466 *pdvbdev = NULL; 467 467 pr_err("%s: couldn't find free device id\n", __func__); ··· 470 468 } 471 469 472 470 *pdvbdev = dvbdev = kzalloc(sizeof(*dvbdev), GFP_KERNEL); 473 - 474 471 if (!dvbdev){ 475 472 mutex_unlock(&dvbdev_register_lock); 476 473 return -ENOMEM; 477 474 } 478 475 479 - dvbdevfops = kmemdup(template->fops, sizeof(*dvbdevfops), GFP_KERNEL); 476 + /* 477 + * When a device of the same type is probe()d more than once, 478 + * the first allocated fops are used. This prevents memory leaks 479 + * that can occur when the same device is probe()d repeatedly. 480 + */ 481 + list_for_each_entry(node, &dvbdevfops_list, list_head) { 482 + if (node->fops->owner == adap->module && 483 + node->type == type && 484 + node->template == template) { 485 + dvbdevfops = node->fops; 486 + break; 487 + } 488 + } 480 489 481 - if (!dvbdevfops){ 482 - kfree (dvbdev); 483 - mutex_unlock(&dvbdev_register_lock); 484 - return -ENOMEM; 490 + if (dvbdevfops == NULL) { 491 + dvbdevfops = kmemdup(template->fops, sizeof(*dvbdevfops), GFP_KERNEL); 492 + if (!dvbdevfops) { 493 + kfree(dvbdev); 494 + mutex_unlock(&dvbdev_register_lock); 495 + return -ENOMEM; 496 + } 497 + 498 + new_node = kzalloc(sizeof(struct dvbdevfops_node), GFP_KERNEL); 499 + if (!new_node) { 500 + kfree(dvbdevfops); 501 + kfree(dvbdev); 502 + mutex_unlock(&dvbdev_register_lock); 503 + return -ENOMEM; 504 + } 505 + 506 + new_node->fops = dvbdevfops; 507 + new_node->type = type; 508 + new_node->template = template; 509 + list_add_tail (&new_node->list_head, &dvbdevfops_list); 485 510 } 486 511 487 512 memcpy(dvbdev, template, sizeof(struct dvb_device)); ··· 519 490 dvbdev->priv = priv; 520 491 dvbdev->fops = dvbdevfops; 521 492 init_waitqueue_head (&dvbdev->wait_queue); 522 - 523 493 dvbdevfops->owner = adap->module; 524 - 525 494 list_add_tail (&dvbdev->list_head, &adap->device_list); 526 - 527 495 down_write(&minor_rwsem); 528 496 #ifdef CONFIG_DVB_DYNAMIC_MINORS 529 497 for (minor = 0; minor < MAX_DVB_MINORS; minor++) 530 498 if (dvb_minors[minor] == NULL) 531 499 break; 532 - 533 500 if (minor == MAX_DVB_MINORS) { 501 + if (new_node) { 502 + list_del (&new_node->list_head); 503 + kfree(dvbdevfops); 504 + kfree(new_node); 505 + } 534 506 list_del (&dvbdev->list_head); 535 - kfree(dvbdevfops); 536 507 kfree(dvbdev); 537 508 up_write(&minor_rwsem); 538 509 mutex_unlock(&dvbdev_register_lock); ··· 541 512 #else 542 513 minor = nums2minor(adap->num, type, id); 543 514 #endif 544 - 545 515 dvbdev->minor = minor; 546 516 dvb_minors[minor] = dvb_device_get(dvbdev); 547 517 up_write(&minor_rwsem); 548 - 549 518 ret = dvb_register_media_device(dvbdev, type, minor, demux_sink_pads); 550 519 if (ret) { 551 520 pr_err("%s: dvb_register_media_device failed to create the mediagraph\n", 552 521 __func__); 553 - 522 + if (new_node) { 523 + list_del (&new_node->list_head); 524 + kfree(dvbdevfops); 525 + kfree(new_node); 526 + } 554 527 dvb_media_device_free(dvbdev); 555 528 list_del (&dvbdev->list_head); 556 - kfree(dvbdevfops); 557 529 kfree(dvbdev); 558 530 mutex_unlock(&dvbdev_register_lock); 559 531 return ret; 560 532 } 561 - 562 - mutex_unlock(&dvbdev_register_lock); 563 533 564 534 clsdev = device_create(dvb_class, adap->device, 565 535 MKDEV(DVB_MAJOR, minor), ··· 566 538 if (IS_ERR(clsdev)) { 567 539 pr_err("%s: failed to create device dvb%d.%s%d (%ld)\n", 568 540 __func__, adap->num, dnames[type], id, PTR_ERR(clsdev)); 541 + if (new_node) { 542 + list_del (&new_node->list_head); 543 + kfree(dvbdevfops); 544 + kfree(new_node); 545 + } 569 546 dvb_media_device_free(dvbdev); 570 547 list_del (&dvbdev->list_head); 571 - kfree(dvbdevfops); 572 548 kfree(dvbdev); 549 + mutex_unlock(&dvbdev_register_lock); 573 550 return PTR_ERR(clsdev); 574 551 } 552 + 575 553 dprintk("DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n", 576 554 adap->num, dnames[type], id, minor, minor); 577 555 556 + mutex_unlock(&dvbdev_register_lock); 578 557 return 0; 579 558 } 580 559 EXPORT_SYMBOL(dvb_register_device); ··· 610 575 { 611 576 struct dvb_device *dvbdev = container_of(ref, struct dvb_device, ref); 612 577 613 - kfree (dvbdev->fops); 614 578 kfree (dvbdev); 615 579 } 616 580 ··· 1115 1081 1116 1082 static void __exit exit_dvbdev(void) 1117 1083 { 1084 + struct dvbdevfops_node *node, *next; 1085 + 1118 1086 class_destroy(dvb_class); 1119 1087 cdev_del(&dvb_device_cdev); 1120 1088 unregister_chrdev_region(MKDEV(DVB_MAJOR, 0), MAX_DVB_MINORS); 1089 + 1090 + list_for_each_entry_safe(node, next, &dvbdevfops_list, list_head) { 1091 + list_del (&node->list_head); 1092 + kfree(node->fops); 1093 + kfree(node); 1094 + } 1121 1095 } 1122 1096 1123 1097 subsys_initcall(init_dvbdev);
+1 -1
drivers/media/dvb-frontends/mn88443x.c
··· 798 798 static struct i2c_driver mn88443x_driver = { 799 799 .driver = { 800 800 .name = "mn88443x", 801 - .of_match_table = of_match_ptr(mn88443x_of_match), 801 + .of_match_table = mn88443x_of_match, 802 802 }, 803 803 .probe_new = mn88443x_probe, 804 804 .remove = mn88443x_remove,
+10 -9
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
··· 697 697 netup_unidvb_dma_enable(dma, 0); 698 698 msleep(50); 699 699 cancel_work_sync(&dma->work); 700 - del_timer(&dma->timeout); 700 + del_timer_sync(&dma->timeout); 701 701 } 702 702 703 703 static int netup_unidvb_dma_setup(struct netup_unidvb_dev *ndev) ··· 887 887 ndev->lmmio0, (u32)pci_resource_len(pci_dev, 0), 888 888 ndev->lmmio1, (u32)pci_resource_len(pci_dev, 1), 889 889 pci_dev->irq); 890 - if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED, 891 - "netup_unidvb", pci_dev) < 0) { 892 - dev_err(&pci_dev->dev, 893 - "%s(): can't get IRQ %d\n", __func__, pci_dev->irq); 894 - goto irq_request_err; 895 - } 890 + 896 891 ndev->dma_size = 2 * 188 * 897 892 NETUP_DMA_BLOCKS_COUNT * NETUP_DMA_PACKETS_COUNT; 898 893 ndev->dma_virt = dma_alloc_coherent(&pci_dev->dev, ··· 928 933 dev_err(&pci_dev->dev, "netup_unidvb: DMA setup failed\n"); 929 934 goto dma_setup_err; 930 935 } 936 + 937 + if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED, 938 + "netup_unidvb", pci_dev) < 0) { 939 + dev_err(&pci_dev->dev, 940 + "%s(): can't get IRQ %d\n", __func__, pci_dev->irq); 941 + goto dma_setup_err; 942 + } 943 + 931 944 dev_info(&pci_dev->dev, 932 945 "netup_unidvb: device has been initialized\n"); 933 946 return 0; ··· 954 951 dma_free_coherent(&pci_dev->dev, ndev->dma_size, 955 952 ndev->dma_virt, ndev->dma_phys); 956 953 dma_alloc_err: 957 - free_irq(pci_dev->irq, pci_dev); 958 - irq_request_err: 959 954 iounmap(ndev->lmmio1); 960 955 pci_bar1_error: 961 956 iounmap(ndev->lmmio0);
+8
drivers/media/usb/dvb-usb-v2/ce6230.c
··· 101 101 if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { 102 102 if (msg[i].addr == 103 103 ce6230_zl10353_config.demod_address) { 104 + if (msg[i].len < 1) { 105 + i = -EOPNOTSUPP; 106 + break; 107 + } 104 108 req.cmd = DEMOD_READ; 105 109 req.value = msg[i].addr >> 1; 106 110 req.index = msg[i].buf[0]; ··· 121 117 } else { 122 118 if (msg[i].addr == 123 119 ce6230_zl10353_config.demod_address) { 120 + if (msg[i].len < 1) { 121 + i = -EOPNOTSUPP; 122 + break; 123 + } 124 124 req.cmd = DEMOD_WRITE; 125 125 req.value = msg[i].addr >> 1; 126 126 req.index = msg[i].buf[0];
+12
drivers/media/usb/dvb-usb-v2/ec168.c
··· 115 115 while (i < num) { 116 116 if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { 117 117 if (msg[i].addr == ec168_ec100_config.demod_address) { 118 + if (msg[i].len < 1) { 119 + i = -EOPNOTSUPP; 120 + break; 121 + } 118 122 req.cmd = READ_DEMOD; 119 123 req.value = 0; 120 124 req.index = 0xff00 + msg[i].buf[0]; /* reg */ ··· 135 131 } 136 132 } else { 137 133 if (msg[i].addr == ec168_ec100_config.demod_address) { 134 + if (msg[i].len < 1) { 135 + i = -EOPNOTSUPP; 136 + break; 137 + } 138 138 req.cmd = WRITE_DEMOD; 139 139 req.value = msg[i].buf[1]; /* val */ 140 140 req.index = 0xff00 + msg[i].buf[0]; /* reg */ ··· 147 139 ret = ec168_ctrl_msg(d, &req); 148 140 i += 1; 149 141 } else { 142 + if (msg[i].len < 1) { 143 + i = -EOPNOTSUPP; 144 + break; 145 + } 150 146 req.cmd = WRITE_I2C; 151 147 req.value = msg[i].buf[0]; /* val */ 152 148 req.index = 0x0100 + msg[i].addr; /* I2C addr */
+20
drivers/media/usb/dvb-usb-v2/rtl28xxu.c
··· 176 176 ret = -EOPNOTSUPP; 177 177 goto err_mutex_unlock; 178 178 } else if (msg[0].addr == 0x10) { 179 + if (msg[0].len < 1 || msg[1].len < 1) { 180 + ret = -EOPNOTSUPP; 181 + goto err_mutex_unlock; 182 + } 179 183 /* method 1 - integrated demod */ 180 184 if (msg[0].buf[0] == 0x00) { 181 185 /* return demod page from driver cache */ ··· 193 189 ret = rtl28xxu_ctrl_msg(d, &req); 194 190 } 195 191 } else if (msg[0].len < 2) { 192 + if (msg[0].len < 1) { 193 + ret = -EOPNOTSUPP; 194 + goto err_mutex_unlock; 195 + } 196 196 /* method 2 - old I2C */ 197 197 req.value = (msg[0].buf[0] << 8) | (msg[0].addr << 1); 198 198 req.index = CMD_I2C_RD; ··· 225 217 ret = -EOPNOTSUPP; 226 218 goto err_mutex_unlock; 227 219 } else if (msg[0].addr == 0x10) { 220 + if (msg[0].len < 1) { 221 + ret = -EOPNOTSUPP; 222 + goto err_mutex_unlock; 223 + } 228 224 /* method 1 - integrated demod */ 229 225 if (msg[0].buf[0] == 0x00) { 226 + if (msg[0].len < 2) { 227 + ret = -EOPNOTSUPP; 228 + goto err_mutex_unlock; 229 + } 230 230 /* save demod page for later demod access */ 231 231 dev->page = msg[0].buf[1]; 232 232 ret = 0; ··· 247 231 ret = rtl28xxu_ctrl_msg(d, &req); 248 232 } 249 233 } else if ((msg[0].len < 23) && (!dev->new_i2c_write)) { 234 + if (msg[0].len < 1) { 235 + ret = -EOPNOTSUPP; 236 + goto err_mutex_unlock; 237 + } 250 238 /* method 2 - old I2C */ 251 239 req.value = (msg[0].buf[0] << 8) | (msg[0].addr << 1); 252 240 req.index = CMD_I2C_WR;
+12
drivers/media/usb/dvb-usb/az6027.c
··· 988 988 /* write/read request */ 989 989 if (i + 1 < num && (msg[i + 1].flags & I2C_M_RD)) { 990 990 req = 0xB9; 991 + if (msg[i].len < 1) { 992 + i = -EOPNOTSUPP; 993 + break; 994 + } 991 995 index = (((msg[i].buf[0] << 8) & 0xff00) | (msg[i].buf[1] & 0x00ff)); 992 996 value = msg[i].addr + (msg[i].len << 8); 993 997 length = msg[i + 1].len + 6; ··· 1005 1001 1006 1002 /* demod 16bit addr */ 1007 1003 req = 0xBD; 1004 + if (msg[i].len < 1) { 1005 + i = -EOPNOTSUPP; 1006 + break; 1007 + } 1008 1008 index = (((msg[i].buf[0] << 8) & 0xff00) | (msg[i].buf[1] & 0x00ff)); 1009 1009 value = msg[i].addr + (2 << 8); 1010 1010 length = msg[i].len - 2; ··· 1034 1026 } else { 1035 1027 1036 1028 req = 0xBD; 1029 + if (msg[i].len < 1) { 1030 + i = -EOPNOTSUPP; 1031 + break; 1032 + } 1037 1033 index = msg[i].buf[0] & 0x00FF; 1038 1034 value = msg[i].addr + (1 << 8); 1039 1035 length = msg[i].len - 1;
+4
drivers/media/usb/dvb-usb/digitv.c
··· 63 63 warn("more than 2 i2c messages at a time is not handled yet. TODO."); 64 64 65 65 for (i = 0; i < num; i++) { 66 + if (msg[i].len < 1) { 67 + i = -EOPNOTSUPP; 68 + break; 69 + } 66 70 /* write/read request */ 67 71 if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) { 68 72 if (digitv_ctrl_msg(d, USB_READ_COFDM, msg[i].buf[0], NULL, 0,
+1 -1
drivers/media/usb/dvb-usb/dw2102.c
··· 946 946 for (i = 0; i < 6; i++) { 947 947 obuf[1] = 0xf0 + i; 948 948 if (i2c_transfer(&d->i2c_adap, msg, 2) != 2) 949 - break; 949 + return -1; 950 950 else 951 951 mac[i] = ibuf[0]; 952 952 }
+1
drivers/media/usb/pvrusb2/Kconfig
··· 37 37 bool "pvrusb2 ATSC/DVB support" 38 38 default y 39 39 depends on VIDEO_PVRUSB2 && DVB_CORE 40 + depends on VIDEO_PVRUSB2=m || DVB_CORE=y 40 41 select DVB_LGDT330X if MEDIA_SUBDRV_AUTOSELECT 41 42 select DVB_S5H1409 if MEDIA_SUBDRV_AUTOSELECT 42 43 select DVB_S5H1411 if MEDIA_SUBDRV_AUTOSELECT
+1 -2
drivers/media/usb/ttusb-dec/ttusb_dec.c
··· 1544 1544 dvb_dmx_release(&dec->demux); 1545 1545 if (dec->fe) { 1546 1546 dvb_unregister_frontend(dec->fe); 1547 - if (dec->fe->ops.release) 1548 - dec->fe->ops.release(dec->fe); 1547 + dvb_frontend_detach(dec->fe); 1549 1548 } 1550 1549 dvb_unregister_adapter(&dec->adapter); 1551 1550 }
+1 -1
drivers/net/can/Kconfig
··· 95 95 96 96 config CAN_BXCAN 97 97 tristate "STM32 Basic Extended CAN (bxCAN) devices" 98 - depends on OF || ARCH_STM32 || COMPILE_TEST 98 + depends on ARCH_STM32 || COMPILE_TEST 99 99 depends on HAS_IOMEM 100 100 select CAN_RX_OFFLOAD 101 101 help
+23 -11
drivers/net/can/bxcan.c
··· 118 118 #define BXCAN_FiR1_REG(b) (0x40 + (b) * 8) 119 119 #define BXCAN_FiR2_REG(b) (0x44 + (b) * 8) 120 120 121 - #define BXCAN_FILTER_ID(primary) (primary ? 0 : 14) 121 + #define BXCAN_FILTER_ID(cfg) ((cfg) == BXCAN_CFG_DUAL_SECONDARY ? 14 : 0) 122 122 123 123 /* Filter primary register (FMR) bits */ 124 124 #define BXCAN_FMR_CANSB_MASK GENMASK(13, 8) ··· 133 133 BXCAN_LEC_BIT0_ERROR, 134 134 BXCAN_LEC_CRC_ERROR, 135 135 BXCAN_LEC_UNUSED 136 + }; 137 + 138 + enum bxcan_cfg { 139 + BXCAN_CFG_SINGLE = 0, 140 + BXCAN_CFG_DUAL_PRIMARY, 141 + BXCAN_CFG_DUAL_SECONDARY 136 142 }; 137 143 138 144 /* Structure of the message buffer */ ··· 173 167 struct regmap *gcan; 174 168 int tx_irq; 175 169 int sce_irq; 176 - bool primary; 170 + enum bxcan_cfg cfg; 177 171 struct clk *clk; 178 172 spinlock_t rmw_lock; /* lock for read-modify-write operations */ 179 173 unsigned int tx_head; ··· 208 202 spin_unlock_irqrestore(&priv->rmw_lock, flags); 209 203 } 210 204 211 - static void bxcan_disable_filters(struct bxcan_priv *priv, bool primary) 205 + static void bxcan_disable_filters(struct bxcan_priv *priv, enum bxcan_cfg cfg) 212 206 { 213 - unsigned int fid = BXCAN_FILTER_ID(primary); 207 + unsigned int fid = BXCAN_FILTER_ID(cfg); 214 208 u32 fmask = BIT(fid); 215 209 216 210 regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, 0); 217 211 } 218 212 219 - static void bxcan_enable_filters(struct bxcan_priv *priv, bool primary) 213 + static void bxcan_enable_filters(struct bxcan_priv *priv, enum bxcan_cfg cfg) 220 214 { 221 - unsigned int fid = BXCAN_FILTER_ID(primary); 215 + unsigned int fid = BXCAN_FILTER_ID(cfg); 222 216 u32 fmask = BIT(fid); 223 217 224 218 /* Filter settings: ··· 686 680 BXCAN_BTR_BRP_MASK | BXCAN_BTR_TS1_MASK | BXCAN_BTR_TS2_MASK | 687 681 BXCAN_BTR_SJW_MASK, set); 688 682 689 - bxcan_enable_filters(priv, priv->primary); 683 + bxcan_enable_filters(priv, priv->cfg); 690 684 691 685 /* Clear all internal status */ 692 686 priv->tx_head = 0; ··· 812 806 BXCAN_IER_EPVIE | BXCAN_IER_EWGIE | BXCAN_IER_FOVIE1 | 813 807 BXCAN_IER_FFIE1 | BXCAN_IER_FMPIE1 | BXCAN_IER_FOVIE0 | 814 808 BXCAN_IER_FFIE0 | BXCAN_IER_FMPIE0 | BXCAN_IER_TMEIE, 0); 815 - bxcan_disable_filters(priv, priv->primary); 809 + bxcan_disable_filters(priv, priv->cfg); 816 810 bxcan_enter_sleep_mode(priv); 817 811 priv->can.state = CAN_STATE_STOPPED; 818 812 } ··· 937 931 struct clk *clk = NULL; 938 932 void __iomem *regs; 939 933 struct regmap *gcan; 940 - bool primary; 934 + enum bxcan_cfg cfg; 941 935 int err, rx_irq, tx_irq, sce_irq; 942 936 943 937 regs = devm_platform_ioremap_resource(pdev, 0); ··· 952 946 return PTR_ERR(gcan); 953 947 } 954 948 955 - primary = of_property_read_bool(np, "st,can-primary"); 949 + if (of_property_read_bool(np, "st,can-primary")) 950 + cfg = BXCAN_CFG_DUAL_PRIMARY; 951 + else if (of_property_read_bool(np, "st,can-secondary")) 952 + cfg = BXCAN_CFG_DUAL_SECONDARY; 953 + else 954 + cfg = BXCAN_CFG_SINGLE; 955 + 956 956 clk = devm_clk_get(dev, NULL); 957 957 if (IS_ERR(clk)) { 958 958 dev_err(dev, "failed to get clock\n"); ··· 1004 992 priv->clk = clk; 1005 993 priv->tx_irq = tx_irq; 1006 994 priv->sce_irq = sce_irq; 1007 - priv->primary = primary; 995 + priv->cfg = cfg; 1008 996 priv->can.clock.freq = clk_get_rate(clk); 1009 997 spin_lock_init(&priv->rmw_lock); 1010 998 priv->tx_head = 0;
+2 -1
drivers/net/can/dev/skb.c
··· 54 54 /* check flag whether this packet has to be looped back */ 55 55 if (!(dev->flags & IFF_ECHO) || 56 56 (skb->protocol != htons(ETH_P_CAN) && 57 - skb->protocol != htons(ETH_P_CANFD))) { 57 + skb->protocol != htons(ETH_P_CANFD) && 58 + skb->protocol != htons(ETH_P_CANXL))) { 58 59 kfree_skb(skb); 59 60 return 0; 60 61 }
+29 -22
drivers/net/can/kvaser_pciefd.c
··· 71 71 #define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14) 72 72 /* Shared receive buffer registers */ 73 73 #define KVASER_PCIEFD_SRB_BASE 0x1f200 74 + #define KVASER_PCIEFD_SRB_FIFO_LAST_REG (KVASER_PCIEFD_SRB_BASE + 0x1f4) 74 75 #define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200) 75 76 #define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204) 76 77 #define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c) 77 78 #define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210) 79 + #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214) 78 80 #define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218) 79 81 /* EPCS flash controller registers */ 80 82 #define KVASER_PCIEFD_SPI_BASE 0x1fc00 ··· 112 110 #define KVASER_PCIEFD_SRB_STAT_DI BIT(15) 113 111 /* DMA support */ 114 112 #define KVASER_PCIEFD_SRB_STAT_DMA BIT(24) 113 + 114 + /* SRB current packet level */ 115 + #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff 115 116 116 117 /* DMA Enable */ 117 118 #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0) ··· 531 526 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD | 532 527 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL | 533 528 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP | 534 - KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD; 529 + KVASER_PCIEFD_KCAN_IRQ_TAR; 535 530 536 531 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 537 532 ··· 559 554 560 555 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 561 556 mode |= KVASER_PCIEFD_KCAN_MODE_LOM; 557 + else 558 + mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM; 562 559 563 560 mode |= KVASER_PCIEFD_KCAN_MODE_EEN; 564 561 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN; ··· 579 572 580 573 spin_lock_irqsave(&can->lock, irq); 581 574 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 582 - iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD, 575 + iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD, 583 576 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 584 577 585 578 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); ··· 622 615 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 623 616 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 624 617 625 - iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD, 618 + iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD, 626 619 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 627 620 628 621 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); ··· 726 719 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 727 720 del_timer(&can->bec_poll_timer); 728 721 } 722 + can->can.state = CAN_STATE_STOPPED; 729 723 close_candev(netdev); 730 724 731 725 return ret; ··· 1015 1007 SET_NETDEV_DEV(netdev, &pcie->pci->dev); 1016 1008 1017 1009 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1018 - iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | 1019 - KVASER_PCIEFD_KCAN_IRQ_TFD, 1010 + iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD, 1020 1011 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1021 1012 1022 1013 pcie->can[i] = can; ··· 1065 1058 { 1066 1059 int i; 1067 1060 u32 srb_status; 1061 + u32 srb_packet_count; 1068 1062 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT]; 1069 1063 1070 1064 /* Disable the DMA */ ··· 1092 1084 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 | 1093 1085 KVASER_PCIEFD_SRB_CMD_RDB1, 1094 1086 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1087 + 1088 + /* Empty Rx FIFO */ 1089 + srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) & 1090 + KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK; 1091 + while (srb_packet_count) { 1092 + /* Drop current packet in FIFO */ 1093 + ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG); 1094 + srb_packet_count--; 1095 + } 1095 1096 1096 1097 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); 1097 1098 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) { ··· 1442 1425 cmd = KVASER_PCIEFD_KCAN_CMD_AT; 1443 1426 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 1444 1427 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 1445 - 1446 - iowrite32(KVASER_PCIEFD_KCAN_IRQ_TFD, 1447 - can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1448 1428 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET && 1449 1429 p->header[0] & KVASER_PCIEFD_SPACK_IRM && 1450 1430 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) && ··· 1728 1714 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF) 1729 1715 netdev_err(can->can.dev, "Tx FIFO overflow\n"); 1730 1716 1731 - if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD) { 1732 - u8 count = ioread32(can->reg_base + 1733 - KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1734 - 1735 - if (count == 0) 1736 - iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1737 - can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1738 - } 1739 - 1740 1717 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP) 1741 1718 netdev_err(can->can.dev, 1742 1719 "Fail to change bittiming, when not in reset mode\n"); ··· 1829 1824 if (err) 1830 1825 goto err_teardown_can_ctrls; 1831 1826 1827 + err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler, 1828 + IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie); 1829 + if (err) 1830 + goto err_teardown_can_ctrls; 1831 + 1832 1832 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1, 1833 1833 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1834 1834 ··· 1854 1844 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1, 1855 1845 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1856 1846 1857 - err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler, 1858 - IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie); 1859 - if (err) 1860 - goto err_teardown_can_ctrls; 1861 - 1862 1847 err = kvaser_pciefd_reg_candev(pcie); 1863 1848 if (err) 1864 1849 goto err_free_irq; ··· 1861 1856 return 0; 1862 1857 1863 1858 err_free_irq: 1859 + /* Disable PCI interrupts */ 1860 + iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG); 1864 1861 free_irq(pcie->pci->irq, pcie); 1865 1862 1866 1863 err_teardown_can_ctrls:
+1 -1
drivers/net/dsa/mv88e6xxx/port.h
··· 276 276 /* Offset 0x10: Extended Port Control Command */ 277 277 #define MV88E6393X_PORT_EPC_CMD 0x10 278 278 #define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 279 - #define MV88E6393X_PORT_EPC_CMD_WRITE 0x0300 279 + #define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000 280 280 #define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 281 281 282 282 /* Offset 0x11: Extended Port Control Data */
+65 -18
drivers/net/dsa/rzn1_a5psw.c
··· 120 120 a5psw_port_pattern_set(a5psw, port, A5PSW_PATTERN_MGMTFWD, enable); 121 121 } 122 122 123 + static void a5psw_port_tx_enable(struct a5psw *a5psw, int port, bool enable) 124 + { 125 + u32 mask = A5PSW_PORT_ENA_TX(port); 126 + u32 reg = enable ? mask : 0; 127 + 128 + /* Even though the port TX is disabled through TXENA bit in the 129 + * PORT_ENA register, it can still send BPDUs. This depends on the tag 130 + * configuration added when sending packets from the CPU port to the 131 + * switch port. Indeed, when using forced forwarding without filtering, 132 + * even disabled ports will be able to send packets that are tagged. 133 + * This allows to implement STP support when ports are in a state where 134 + * forwarding traffic should be stopped but BPDUs should still be sent. 135 + */ 136 + a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, mask, reg); 137 + } 138 + 123 139 static void a5psw_port_enable_set(struct a5psw *a5psw, int port, bool enable) 124 140 { 125 141 u32 port_ena = 0; ··· 308 292 return 0; 309 293 } 310 294 295 + static void a5psw_port_learning_set(struct a5psw *a5psw, int port, bool learn) 296 + { 297 + u32 mask = A5PSW_INPUT_LEARN_DIS(port); 298 + u32 reg = !learn ? mask : 0; 299 + 300 + a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg); 301 + } 302 + 303 + static void a5psw_port_rx_block_set(struct a5psw *a5psw, int port, bool block) 304 + { 305 + u32 mask = A5PSW_INPUT_LEARN_BLOCK(port); 306 + u32 reg = block ? mask : 0; 307 + 308 + a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg); 309 + } 310 + 311 311 static void a5psw_flooding_set_resolution(struct a5psw *a5psw, int port, 312 312 bool set) 313 313 { ··· 338 306 339 307 for (i = 0; i < ARRAY_SIZE(offsets); i++) 340 308 a5psw_reg_writel(a5psw, offsets[i], a5psw->bridged_ports); 309 + } 310 + 311 + static void a5psw_port_set_standalone(struct a5psw *a5psw, int port, 312 + bool standalone) 313 + { 314 + a5psw_port_learning_set(a5psw, port, !standalone); 315 + a5psw_flooding_set_resolution(a5psw, port, !standalone); 316 + a5psw_port_mgmtfwd_set(a5psw, port, standalone); 341 317 } 342 318 343 319 static int a5psw_port_bridge_join(struct dsa_switch *ds, int port, ··· 363 323 } 364 324 365 325 a5psw->br_dev = bridge.dev; 366 - a5psw_flooding_set_resolution(a5psw, port, true); 367 - a5psw_port_mgmtfwd_set(a5psw, port, false); 326 + a5psw_port_set_standalone(a5psw, port, false); 368 327 369 328 return 0; 370 329 } ··· 373 334 { 374 335 struct a5psw *a5psw = ds->priv; 375 336 376 - a5psw_flooding_set_resolution(a5psw, port, false); 377 - a5psw_port_mgmtfwd_set(a5psw, port, true); 337 + a5psw_port_set_standalone(a5psw, port, true); 378 338 379 339 /* No more ports bridged */ 380 340 if (a5psw->bridged_ports == BIT(A5PSW_CPU_PORT)) ··· 382 344 383 345 static void a5psw_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 384 346 { 385 - u32 mask = A5PSW_INPUT_LEARN_DIS(port) | A5PSW_INPUT_LEARN_BLOCK(port); 347 + bool learning_enabled, rx_enabled, tx_enabled; 386 348 struct a5psw *a5psw = ds->priv; 387 - u32 reg = 0; 388 349 389 350 switch (state) { 390 351 case BR_STATE_DISABLED: 391 352 case BR_STATE_BLOCKING: 392 - reg |= A5PSW_INPUT_LEARN_DIS(port); 393 - reg |= A5PSW_INPUT_LEARN_BLOCK(port); 394 - break; 395 353 case BR_STATE_LISTENING: 396 - reg |= A5PSW_INPUT_LEARN_DIS(port); 354 + rx_enabled = false; 355 + tx_enabled = false; 356 + learning_enabled = false; 397 357 break; 398 358 case BR_STATE_LEARNING: 399 - reg |= A5PSW_INPUT_LEARN_BLOCK(port); 359 + rx_enabled = false; 360 + tx_enabled = false; 361 + learning_enabled = true; 400 362 break; 401 363 case BR_STATE_FORWARDING: 402 - default: 364 + rx_enabled = true; 365 + tx_enabled = true; 366 + learning_enabled = true; 403 367 break; 368 + default: 369 + dev_err(ds->dev, "invalid STP state: %d\n", state); 370 + return; 404 371 } 405 372 406 - a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg); 373 + a5psw_port_learning_set(a5psw, port, learning_enabled); 374 + a5psw_port_rx_block_set(a5psw, port, !rx_enabled); 375 + a5psw_port_tx_enable(a5psw, port, tx_enabled); 407 376 } 408 377 409 378 static void a5psw_port_fast_age(struct dsa_switch *ds, int port) ··· 718 673 } 719 674 720 675 /* Configure management port */ 721 - reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_DISCARD; 676 + reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_ENABLE; 722 677 a5psw_reg_writel(a5psw, A5PSW_MGMT_CFG, reg); 723 678 724 679 /* Set pattern 0 to forward all frame to mgmt port */ ··· 767 722 if (dsa_port_is_unused(dp)) 768 723 continue; 769 724 770 - /* Enable egress flooding for CPU port */ 771 - if (dsa_port_is_cpu(dp)) 725 + /* Enable egress flooding and learning for CPU port */ 726 + if (dsa_port_is_cpu(dp)) { 772 727 a5psw_flooding_set_resolution(a5psw, port, true); 728 + a5psw_port_learning_set(a5psw, port, true); 729 + } 773 730 774 - /* Enable management forward only for user ports */ 731 + /* Enable standalone mode for user ports */ 775 732 if (dsa_port_is_user(dp)) 776 - a5psw_port_mgmtfwd_set(a5psw, port, true); 733 + a5psw_port_set_standalone(a5psw, port, true); 777 734 } 778 735 779 736 return 0;
+2 -1
drivers/net/dsa/rzn1_a5psw.h
··· 19 19 #define A5PSW_PORT_OFFSET(port) (0x400 * (port)) 20 20 21 21 #define A5PSW_PORT_ENA 0x8 22 + #define A5PSW_PORT_ENA_TX(port) BIT(port) 22 23 #define A5PSW_PORT_ENA_RX_SHIFT 16 23 24 #define A5PSW_PORT_ENA_TX_RX(port) (BIT((port) + A5PSW_PORT_ENA_RX_SHIFT) | \ 24 25 BIT(port)) ··· 37 36 #define A5PSW_INPUT_LEARN_BLOCK(p) BIT(p) 38 37 39 38 #define A5PSW_MGMT_CFG 0x20 40 - #define A5PSW_MGMT_CFG_DISCARD BIT(7) 39 + #define A5PSW_MGMT_CFG_ENABLE BIT(6) 41 40 42 41 #define A5PSW_MODE_CFG 0x24 43 42 #define A5PSW_MODE_STATS_RESET BIT(31)
+3 -1
drivers/net/ethernet/3com/3c515.c
··· 66 66 #include <linux/timer.h> 67 67 #include <linux/ethtool.h> 68 68 #include <linux/bitops.h> 69 - 70 69 #include <linux/uaccess.h> 70 + 71 + #include <net/Space.h> 72 + 71 73 #include <asm/io.h> 72 74 #include <asm/dma.h> 73 75
+1
drivers/net/ethernet/8390/ne.c
··· 52 52 #include <linux/etherdevice.h> 53 53 #include <linux/jiffies.h> 54 54 #include <linux/platform_device.h> 55 + #include <net/Space.h> 55 56 56 57 #include <asm/io.h> 57 58
+1
drivers/net/ethernet/8390/smc-ultra.c
··· 66 66 #include <linux/isapnp.h> 67 67 #include <linux/netdevice.h> 68 68 #include <linux/etherdevice.h> 69 + #include <net/Space.h> 69 70 70 71 #include <asm/io.h> 71 72 #include <asm/irq.h>
+1
drivers/net/ethernet/8390/wd.c
··· 37 37 #include <linux/delay.h> 38 38 #include <linux/netdevice.h> 39 39 #include <linux/etherdevice.h> 40 + #include <net/Space.h> 40 41 41 42 #include <asm/io.h> 42 43
+1
drivers/net/ethernet/amd/lance.c
··· 59 59 #include <linux/skbuff.h> 60 60 #include <linux/mm.h> 61 61 #include <linux/bitops.h> 62 + #include <net/Space.h> 62 63 63 64 #include <asm/io.h> 64 65 #include <asm/dma.h>
+5 -3
drivers/net/ethernet/broadcom/genet/bcmgenet.c
··· 3450 3450 return ret; 3451 3451 } 3452 3452 3453 - static void bcmgenet_netif_stop(struct net_device *dev) 3453 + static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) 3454 3454 { 3455 3455 struct bcmgenet_priv *priv = netdev_priv(dev); 3456 3456 ··· 3465 3465 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3466 3466 umac_enable_set(priv, CMD_TX_EN, false); 3467 3467 3468 + if (stop_phy) 3469 + phy_stop(dev->phydev); 3468 3470 bcmgenet_disable_rx_napi(priv); 3469 3471 bcmgenet_intr_disable(priv); 3470 3472 ··· 3487 3485 3488 3486 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3489 3487 3490 - bcmgenet_netif_stop(dev); 3488 + bcmgenet_netif_stop(dev, false); 3491 3489 3492 3490 /* Really kill the PHY state machine and disconnect from it */ 3493 3491 phy_disconnect(dev->phydev); ··· 4305 4303 4306 4304 netif_device_detach(dev); 4307 4305 4308 - bcmgenet_netif_stop(dev); 4306 + bcmgenet_netif_stop(dev, true); 4309 4307 4310 4308 if (!device_may_wakeup(d)) 4311 4309 phy_suspend(dev->phydev);
+2
drivers/net/ethernet/cirrus/cs89x0.c
··· 72 72 #include <linux/gfp.h> 73 73 #include <linux/io.h> 74 74 75 + #include <net/Space.h> 76 + 75 77 #include <asm/irq.h> 76 78 #include <linux/atomic.h> 77 79 #if ALLOW_DMA
+11 -5
drivers/net/ethernet/freescale/fec_main.c
··· 3798 3798 entries_free = fec_enet_get_free_txdesc_num(txq); 3799 3799 if (entries_free < MAX_SKB_FRAGS + 1) { 3800 3800 netdev_err(fep->netdev, "NOT enough BD for SG!\n"); 3801 - xdp_return_frame(frame); 3802 3801 return NETDEV_TX_BUSY; 3803 3802 } 3804 3803 ··· 4477 4478 struct device_node *np = pdev->dev.of_node; 4478 4479 int ret; 4479 4480 4480 - ret = pm_runtime_resume_and_get(&pdev->dev); 4481 + ret = pm_runtime_get_sync(&pdev->dev); 4481 4482 if (ret < 0) 4482 - return ret; 4483 + dev_err(&pdev->dev, 4484 + "Failed to resume device in remove callback (%pe)\n", 4485 + ERR_PTR(ret)); 4483 4486 4484 4487 cancel_work_sync(&fep->tx_timeout_work); 4485 4488 fec_ptp_stop(pdev); ··· 4494 4493 of_phy_deregister_fixed_link(np); 4495 4494 of_node_put(fep->phy_node); 4496 4495 4497 - clk_disable_unprepare(fep->clk_ahb); 4498 - clk_disable_unprepare(fep->clk_ipg); 4496 + /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4497 + * disabling them again. 4498 + */ 4499 + if (ret >= 0) { 4500 + clk_disable_unprepare(fep->clk_ahb); 4501 + clk_disable_unprepare(fep->clk_ipg); 4502 + } 4499 4503 pm_runtime_put_noidle(&pdev->dev); 4500 4504 pm_runtime_disable(&pdev->dev); 4501 4505
+21 -4
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
··· 331 331 return head == hw->cmq.csq.next_to_use; 332 332 } 333 333 334 - static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, 334 + static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 335 + { 336 + static const struct hclge_cmdq_tx_timeout_map cmdq_tx_timeout_map[] = { 337 + {HCLGE_OPC_CFG_RST_TRIGGER, HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS}, 338 + }; 339 + u32 i; 340 + 341 + for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout_map); i++) 342 + if (cmdq_tx_timeout_map[i].opcode == opcode) 343 + return cmdq_tx_timeout_map[i].tx_timeout; 344 + 345 + return tx_timeout; 346 + } 347 + 348 + static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, u16 opcode, 335 349 bool *is_completed) 336 350 { 351 + u32 cmdq_tx_timeout = hclge_get_cmdq_tx_timeout(opcode, 352 + hw->cmq.tx_timeout); 337 353 u32 timeout = 0; 338 354 339 355 do { ··· 359 343 } 360 344 udelay(1); 361 345 timeout++; 362 - } while (timeout < hw->cmq.tx_timeout); 346 + } while (timeout < cmdq_tx_timeout); 363 347 } 364 348 365 349 static int hclge_comm_cmd_convert_err_code(u16 desc_ret) ··· 423 407 * if multi descriptors to be sent, use the first one to check 424 408 */ 425 409 if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 426 - hclge_comm_wait_for_resp(hw, &is_completed); 410 + hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode), 411 + &is_completed); 427 412 428 413 if (!is_completed) 429 414 ret = -EBADE; ··· 546 529 cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM; 547 530 548 531 /* Setup Tx write back timeout */ 549 - cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT; 532 + cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT; 550 533 551 534 /* Setup queue rings */ 552 535 ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);
+7 -1
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
··· 54 54 #define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B) 55 55 #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 3 56 56 #define HCLGE_COMM_NIC_CMQ_DESC_NUM 1024 57 - #define HCLGE_COMM_CMDQ_TX_TIMEOUT 30000 57 + #define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT 30000 58 + #define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS 500000 58 59 59 60 enum hclge_opcode_type { 60 61 /* Generic commands */ ··· 359 358 struct hclge_comm_caps_bit_map { 360 359 u16 imp_bit; 361 360 u16 local_bit; 361 + }; 362 + 363 + struct hclge_cmdq_tx_timeout_map { 364 + u32 opcode; 365 + u32 tx_timeout; 362 366 }; 363 367 364 368 struct hclge_comm_firmware_compat_cmd {
+1 -1
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
··· 130 130 .name = "tx_bd_queue", 131 131 .cmd = HNAE3_DBG_CMD_TX_BD, 132 132 .dentry = HNS3_DBG_DENTRY_TX_BD, 133 - .buf_len = HNS3_DBG_READ_LEN_4MB, 133 + .buf_len = HNS3_DBG_READ_LEN_5MB, 134 134 .init = hns3_dbg_bd_file_init, 135 135 }, 136 136 {
+1
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
··· 10 10 #define HNS3_DBG_READ_LEN_128KB 0x20000 11 11 #define HNS3_DBG_READ_LEN_1MB 0x100000 12 12 #define HNS3_DBG_READ_LEN_4MB 0x400000 13 + #define HNS3_DBG_READ_LEN_5MB 0x500000 13 14 #define HNS3_DBG_WRITE_LEN 1024 14 15 15 16 #define HNS3_DBG_DATA_STR_LEN 32
+9 -6
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
··· 8053 8053 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8054 8054 * so it only need to stop phy here. 8055 8055 */ 8056 - if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && 8057 - hdev->reset_type != HNAE3_FUNC_RESET && 8058 - hdev->reset_type != HNAE3_FLR_RESET) { 8059 - hclge_mac_stop_phy(hdev); 8060 - hclge_update_link_status(hdev); 8061 - return; 8056 + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8057 + hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8058 + HCLGE_PFC_DISABLE); 8059 + if (hdev->reset_type != HNAE3_FUNC_RESET && 8060 + hdev->reset_type != HNAE3_FLR_RESET) { 8061 + hclge_mac_stop_phy(hdev); 8062 + hclge_update_link_status(hdev); 8063 + return; 8064 + } 8062 8065 } 8063 8066 8064 8067 hclge_reset_tqp(handle);
+2 -2
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
··· 171 171 return hclge_cmd_send(&hdev->hw, &desc, 1); 172 172 } 173 173 174 - static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 175 - u8 pfc_bitmap) 174 + int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 175 + u8 pfc_bitmap) 176 176 { 177 177 struct hclge_desc desc; 178 178 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
+5
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
··· 164 164 u32 rsvd1; 165 165 }; 166 166 167 + #define HCLGE_PFC_DISABLE 0 168 + #define HCLGE_PFC_TX_RX_DISABLE 0 169 + 167 170 struct hclge_pfc_en_cmd { 168 171 u8 tx_rx_en_bitmap; 169 172 u8 pri_en_bitmap; ··· 238 235 void hclge_tm_pfc_info_update(struct hclge_dev *hdev); 239 236 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); 240 237 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init); 238 + int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 239 + u8 pfc_bitmap); 241 240 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); 242 241 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); 243 242 void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
+4 -1
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
··· 1436 1436 * might happen in case reset assertion was made by PF. Yes, this also 1437 1437 * means we might end up waiting bit more even for VF reset. 1438 1438 */ 1439 - msleep(5000); 1439 + if (hdev->reset_type == HNAE3_VF_FULL_RESET) 1440 + msleep(5000); 1441 + else 1442 + msleep(500); 1440 1443 1441 1444 return 0; 1442 1445 }
-5
drivers/net/ethernet/intel/iavf/iavf_virtchnl.c
··· 2238 2238 iavf_process_config(adapter); 2239 2239 adapter->flags |= IAVF_FLAG_SETUP_NETDEV_FEATURES; 2240 2240 2241 - /* Request VLAN offload settings */ 2242 - if (VLAN_V2_ALLOWED(adapter)) 2243 - iavf_set_vlan_offload_features(adapter, 0, 2244 - netdev->features); 2245 - 2246 2241 iavf_set_queue_vlan_tag_loc(adapter); 2247 2242 2248 2243 was_mac_changed = !ether_addr_equal(netdev->dev_addr,
+2 -3
drivers/net/ethernet/intel/ice/ice_dcb_lib.c
··· 932 932 if ((first->tx_flags & ICE_TX_FLAGS_HW_VLAN || 933 933 first->tx_flags & ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN) || 934 934 skb->priority != TC_PRIO_CONTROL) { 935 - first->tx_flags &= ~ICE_TX_FLAGS_VLAN_PR_M; 935 + first->vid &= ~VLAN_PRIO_MASK; 936 936 /* Mask the lower 3 bits to set the 802.1p priority */ 937 - first->tx_flags |= (skb->priority & 0x7) << 938 - ICE_TX_FLAGS_VLAN_PR_S; 937 + first->vid |= (skb->priority << VLAN_PRIO_SHIFT) & VLAN_PRIO_MASK; 939 938 /* if this is not already set it means a VLAN 0 + priority needs 940 939 * to be offloaded 941 940 */
+5
drivers/net/ethernet/intel/ice/ice_lib.c
··· 2745 2745 goto unroll_vector_base; 2746 2746 2747 2747 ice_vsi_map_rings_to_vectors(vsi); 2748 + vsi->stat_offsets_loaded = false; 2749 + 2748 2750 if (ice_is_xdp_ena_vsi(vsi)) { 2749 2751 ret = ice_vsi_determine_xdp_res(vsi); 2750 2752 if (ret) ··· 2795 2793 ret = ice_vsi_alloc_ring_stats(vsi); 2796 2794 if (ret) 2797 2795 goto unroll_vector_base; 2796 + 2797 + vsi->stat_offsets_loaded = false; 2798 + 2798 2799 /* Do not exit if configuring RSS had an issue, at least 2799 2800 * receive traffic on first queue. Hence no need to capture 2800 2801 * return value
+4 -4
drivers/net/ethernet/intel/ice/ice_sriov.c
··· 1171 1171 if (!vf) 1172 1172 return -EINVAL; 1173 1173 1174 - ret = ice_check_vf_ready_for_cfg(vf); 1174 + ret = ice_check_vf_ready_for_reset(vf); 1175 1175 if (ret) 1176 1176 goto out_put_vf; 1177 1177 ··· 1286 1286 goto out_put_vf; 1287 1287 } 1288 1288 1289 - ret = ice_check_vf_ready_for_cfg(vf); 1289 + ret = ice_check_vf_ready_for_reset(vf); 1290 1290 if (ret) 1291 1291 goto out_put_vf; 1292 1292 ··· 1340 1340 return -EOPNOTSUPP; 1341 1341 } 1342 1342 1343 - ret = ice_check_vf_ready_for_cfg(vf); 1343 + ret = ice_check_vf_ready_for_reset(vf); 1344 1344 if (ret) 1345 1345 goto out_put_vf; 1346 1346 ··· 1653 1653 if (!vf) 1654 1654 return -EINVAL; 1655 1655 1656 - ret = ice_check_vf_ready_for_cfg(vf); 1656 + ret = ice_check_vf_ready_for_reset(vf); 1657 1657 if (ret) 1658 1658 goto out_put_vf; 1659 1659
+3 -5
drivers/net/ethernet/intel/ice/ice_txrx.c
··· 1664 1664 1665 1665 if (first->tx_flags & ICE_TX_FLAGS_HW_VLAN) { 1666 1666 td_cmd |= (u64)ICE_TX_DESC_CMD_IL2TAG1; 1667 - td_tag = (first->tx_flags & ICE_TX_FLAGS_VLAN_M) >> 1668 - ICE_TX_FLAGS_VLAN_S; 1667 + td_tag = first->vid; 1669 1668 } 1670 1669 1671 1670 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); ··· 1997 1998 * VLAN offloads exclusively so we only care about the VLAN ID here 1998 1999 */ 1999 2000 if (skb_vlan_tag_present(skb)) { 2000 - first->tx_flags |= skb_vlan_tag_get(skb) << ICE_TX_FLAGS_VLAN_S; 2001 + first->vid = skb_vlan_tag_get(skb); 2001 2002 if (tx_ring->flags & ICE_TX_FLAGS_RING_VLAN_L2TAG2) 2002 2003 first->tx_flags |= ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN; 2003 2004 else ··· 2387 2388 offload.cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX | 2388 2389 (ICE_TX_CTX_DESC_IL2TAG2 << 2389 2390 ICE_TXD_CTX_QW1_CMD_S)); 2390 - offload.cd_l2tag2 = (first->tx_flags & ICE_TX_FLAGS_VLAN_M) >> 2391 - ICE_TX_FLAGS_VLAN_S; 2391 + offload.cd_l2tag2 = first->vid; 2392 2392 } 2393 2393 2394 2394 /* set up TSO offload */
+3 -6
drivers/net/ethernet/intel/ice/ice_txrx.h
··· 127 127 #define ICE_TX_FLAGS_IPV6 BIT(6) 128 128 #define ICE_TX_FLAGS_TUNNEL BIT(7) 129 129 #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8) 130 - #define ICE_TX_FLAGS_VLAN_M 0xffff0000 131 - #define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000 132 - #define ICE_TX_FLAGS_VLAN_PR_S 29 133 - #define ICE_TX_FLAGS_VLAN_S 16 134 130 135 131 #define ICE_XDP_PASS 0 136 132 #define ICE_XDP_CONSUMED BIT(0) ··· 178 182 unsigned int gso_segs; 179 183 unsigned int nr_frags; /* used for mbuf XDP */ 180 184 }; 181 - u32 type:16; /* &ice_tx_buf_type */ 182 - u32 tx_flags:16; 185 + u32 tx_flags:12; 186 + u32 type:4; /* &ice_tx_buf_type */ 187 + u32 vid:16; 183 188 DEFINE_DMA_UNMAP_LEN(len); 184 189 DEFINE_DMA_UNMAP_ADDR(dma); 185 190 };
+19
drivers/net/ethernet/intel/ice/ice_vf_lib.c
··· 186 186 } 187 187 188 188 /** 189 + * ice_check_vf_ready_for_reset - check if VF is ready to be reset 190 + * @vf: VF to check if it's ready to be reset 191 + * 192 + * The purpose of this function is to ensure that the VF is not in reset, 193 + * disabled, and is both initialized and active, thus enabling us to safely 194 + * initialize another reset. 195 + */ 196 + int ice_check_vf_ready_for_reset(struct ice_vf *vf) 197 + { 198 + int ret; 199 + 200 + ret = ice_check_vf_ready_for_cfg(vf); 201 + if (!ret && !test_bit(ICE_VF_STATE_ACTIVE, vf->vf_states)) 202 + ret = -EAGAIN; 203 + 204 + return ret; 205 + } 206 + 207 + /** 189 208 * ice_trigger_vf_reset - Reset a VF on HW 190 209 * @vf: pointer to the VF structure 191 210 * @is_vflr: true if VFLR was issued, false if not
+1
drivers/net/ethernet/intel/ice/ice_vf_lib.h
··· 215 215 struct ice_vsi *ice_get_vf_vsi(struct ice_vf *vf); 216 216 bool ice_is_vf_disabled(struct ice_vf *vf); 217 217 int ice_check_vf_ready_for_cfg(struct ice_vf *vf); 218 + int ice_check_vf_ready_for_reset(struct ice_vf *vf); 218 219 void ice_set_vf_state_dis(struct ice_vf *vf); 219 220 bool ice_is_any_vf_in_unicast_promisc(struct ice_pf *pf); 220 221 void
+1
drivers/net/ethernet/intel/ice/ice_virtchnl.c
··· 3955 3955 ice_vc_notify_vf_link_state(vf); 3956 3956 break; 3957 3957 case VIRTCHNL_OP_RESET_VF: 3958 + clear_bit(ICE_VF_STATE_ACTIVE, vf->vf_states); 3958 3959 ops->reset_vf(vf); 3959 3960 break; 3960 3961 case VIRTCHNL_OP_ADD_ETH_ADDR:
+2 -2
drivers/net/ethernet/intel/igb/e1000_mac.c
··· 426 426 static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 427 427 { 428 428 u32 hash_value, hash_mask; 429 - u8 bit_shift = 0; 429 + u8 bit_shift = 1; 430 430 431 431 /* Register count multiplied by bits per register */ 432 432 hash_mask = (hw->mac.mta_reg_count * 32) - 1; ··· 434 434 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 435 435 * where 0xFF would still fall within the hash mask. 436 436 */ 437 - while (hash_mask >> bit_shift != 0xFF) 437 + while (hash_mask >> bit_shift != 0xFF && bit_shift < 4) 438 438 bit_shift++; 439 439 440 440 /* The portion of the address that is used for the hash table
+1 -1
drivers/net/ethernet/netronome/nfp/nic/main.h
··· 8 8 9 9 #ifdef CONFIG_DCB 10 10 /* DCB feature definitions */ 11 - #define NFP_NET_MAX_DSCP 4 11 + #define NFP_NET_MAX_DSCP 64 12 12 #define NFP_NET_MAX_TC IEEE_8021QAZ_MAX_TCS 13 13 #define NFP_NET_MAX_PRIO 8 14 14 #define NFP_DCB_CFG_STRIDE 256
+3 -1
drivers/net/ethernet/sfc/ef100_netdev.c
··· 378 378 efx->net_dev = net_dev; 379 379 SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); 380 380 381 - net_dev->features |= efx->type->offload_features; 381 + /* enable all supported features except rx-fcs and rx-all */ 382 + net_dev->features |= efx->type->offload_features & 383 + ~(NETIF_F_RXFCS | NETIF_F_RXALL); 382 384 net_dev->hw_features |= efx->type->offload_features; 383 385 net_dev->hw_enc_features |= efx->type->offload_features; 384 386 net_dev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_SG |
+2
drivers/net/ethernet/sun/cassini.c
··· 5077 5077 cas_shutdown(cp); 5078 5078 mutex_unlock(&cp->pm_mutex); 5079 5079 5080 + vfree(cp->fw_data); 5081 + 5080 5082 pci_iounmap(pdev, cp->regs); 5081 5083 5082 5084
+8 -7
drivers/net/mdio/mdio-i2c.c
··· 291 291 return i2c_transfer_rollball(i2c, msgs, ARRAY_SIZE(msgs)); 292 292 } 293 293 294 - static int i2c_mii_read_rollball(struct mii_bus *bus, int phy_id, int reg) 294 + static int i2c_mii_read_rollball(struct mii_bus *bus, int phy_id, int devad, 295 + int reg) 295 296 { 296 297 u8 buf[4], res[6]; 297 298 int bus_addr, ret; ··· 303 302 return 0xffff; 304 303 305 304 buf[0] = ROLLBALL_DATA_ADDR; 306 - buf[1] = (reg >> 16) & 0x1f; 305 + buf[1] = devad; 307 306 buf[2] = (reg >> 8) & 0xff; 308 307 buf[3] = reg & 0xff; 309 308 ··· 323 322 return val; 324 323 } 325 324 326 - static int i2c_mii_write_rollball(struct mii_bus *bus, int phy_id, int reg, 327 - u16 val) 325 + static int i2c_mii_write_rollball(struct mii_bus *bus, int phy_id, int devad, 326 + int reg, u16 val) 328 327 { 329 328 int bus_addr, ret; 330 329 u8 buf[6]; ··· 334 333 return 0; 335 334 336 335 buf[0] = ROLLBALL_DATA_ADDR; 337 - buf[1] = (reg >> 16) & 0x1f; 336 + buf[1] = devad; 338 337 buf[2] = (reg >> 8) & 0xff; 339 338 buf[3] = reg & 0xff; 340 339 buf[4] = val >> 8; ··· 406 405 return ERR_PTR(ret); 407 406 } 408 407 409 - mii->read = i2c_mii_read_rollball; 410 - mii->write = i2c_mii_write_rollball; 408 + mii->read_c45 = i2c_mii_read_rollball; 409 + mii->write_c45 = i2c_mii_write_rollball; 411 410 break; 412 411 default: 413 412 mii->read = i2c_mii_read_default_c22;
+1 -1
drivers/net/pcs/pcs-xpcs.c
··· 873 873 874 874 switch (compat->an_mode) { 875 875 case DW_AN_C73: 876 - if (phylink_autoneg_inband(mode)) { 876 + if (test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) { 877 877 ret = xpcs_config_aneg_c73(xpcs, compat); 878 878 if (ret) 879 879 return ret;
+21 -1
drivers/net/phy/dp83867.c
··· 44 44 #define DP83867_STRAP_STS1 0x006E 45 45 #define DP83867_STRAP_STS2 0x006f 46 46 #define DP83867_RGMIIDCTL 0x0086 47 + #define DP83867_DSP_FFE_CFG 0x012c 47 48 #define DP83867_RXFCFG 0x0134 48 49 #define DP83867_RXFPMD1 0x0136 49 50 #define DP83867_RXFPMD2 0x0137 ··· 942 941 943 942 usleep_range(10, 20); 944 943 945 - return phy_modify(phydev, MII_DP83867_PHYCTRL, 944 + err = phy_modify(phydev, MII_DP83867_PHYCTRL, 946 945 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 946 + if (err < 0) 947 + return err; 948 + 949 + /* Configure the DSP Feedforward Equalizer Configuration register to 950 + * improve short cable (< 1 meter) performance. This will not affect 951 + * long cable performance. 952 + */ 953 + err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG, 954 + 0x0e81); 955 + if (err < 0) 956 + return err; 957 + 958 + err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); 959 + if (err < 0) 960 + return err; 961 + 962 + usleep_range(10, 20); 963 + 964 + return 0; 947 965 } 948 966 949 967 static void dp83867_link_change_notify(struct phy_device *phydev)
+4 -4
drivers/net/phy/phylink.c
··· 2225 2225 2226 2226 ASSERT_RTNL(); 2227 2227 2228 + /* Mask out unsupported advertisements */ 2229 + linkmode_and(config.advertising, kset->link_modes.advertising, 2230 + pl->supported); 2231 + 2228 2232 if (pl->phydev) { 2229 2233 /* We can rely on phylib for this update; we also do not need 2230 2234 * to update the pl->link_config settings: ··· 2252 2248 } 2253 2249 2254 2250 config = pl->link_config; 2255 - 2256 - /* Mask out unsupported advertisements */ 2257 - linkmode_and(config.advertising, kset->link_modes.advertising, 2258 - pl->supported); 2259 2251 2260 2252 /* FIXME: should we reject autoneg if phy/mac does not support it? */ 2261 2253 switch (kset->base.autoneg) {
+15
drivers/net/tun.c
··· 1977 1977 int queue_len; 1978 1978 1979 1979 spin_lock_bh(&queue->lock); 1980 + 1981 + if (unlikely(tfile->detached)) { 1982 + spin_unlock_bh(&queue->lock); 1983 + rcu_read_unlock(); 1984 + err = -EBUSY; 1985 + goto free_skb; 1986 + } 1987 + 1980 1988 __skb_queue_tail(queue, skb); 1981 1989 queue_len = skb_queue_len(queue); 1982 1990 spin_unlock(&queue->lock); ··· 2520 2512 if (tfile->napi_enabled) { 2521 2513 queue = &tfile->sk.sk_write_queue; 2522 2514 spin_lock(&queue->lock); 2515 + 2516 + if (unlikely(tfile->detached)) { 2517 + spin_unlock(&queue->lock); 2518 + kfree_skb(skb); 2519 + return -EBUSY; 2520 + } 2521 + 2523 2522 __skb_queue_tail(queue, skb); 2524 2523 spin_unlock(&queue->lock); 2525 2524 ret = 1;
+44 -17
drivers/net/virtio_net.c
··· 1868 1868 return received; 1869 1869 } 1870 1870 1871 + static void virtnet_disable_queue_pair(struct virtnet_info *vi, int qp_index) 1872 + { 1873 + virtnet_napi_tx_disable(&vi->sq[qp_index].napi); 1874 + napi_disable(&vi->rq[qp_index].napi); 1875 + xdp_rxq_info_unreg(&vi->rq[qp_index].xdp_rxq); 1876 + } 1877 + 1878 + static int virtnet_enable_queue_pair(struct virtnet_info *vi, int qp_index) 1879 + { 1880 + struct net_device *dev = vi->dev; 1881 + int err; 1882 + 1883 + err = xdp_rxq_info_reg(&vi->rq[qp_index].xdp_rxq, dev, qp_index, 1884 + vi->rq[qp_index].napi.napi_id); 1885 + if (err < 0) 1886 + return err; 1887 + 1888 + err = xdp_rxq_info_reg_mem_model(&vi->rq[qp_index].xdp_rxq, 1889 + MEM_TYPE_PAGE_SHARED, NULL); 1890 + if (err < 0) 1891 + goto err_xdp_reg_mem_model; 1892 + 1893 + virtnet_napi_enable(vi->rq[qp_index].vq, &vi->rq[qp_index].napi); 1894 + virtnet_napi_tx_enable(vi, vi->sq[qp_index].vq, &vi->sq[qp_index].napi); 1895 + 1896 + return 0; 1897 + 1898 + err_xdp_reg_mem_model: 1899 + xdp_rxq_info_unreg(&vi->rq[qp_index].xdp_rxq); 1900 + return err; 1901 + } 1902 + 1871 1903 static int virtnet_open(struct net_device *dev) 1872 1904 { 1873 1905 struct virtnet_info *vi = netdev_priv(dev); ··· 1913 1881 if (!try_fill_recv(vi, &vi->rq[i], GFP_KERNEL)) 1914 1882 schedule_delayed_work(&vi->refill, 0); 1915 1883 1916 - err = xdp_rxq_info_reg(&vi->rq[i].xdp_rxq, dev, i, vi->rq[i].napi.napi_id); 1884 + err = virtnet_enable_queue_pair(vi, i); 1917 1885 if (err < 0) 1918 - return err; 1919 - 1920 - err = xdp_rxq_info_reg_mem_model(&vi->rq[i].xdp_rxq, 1921 - MEM_TYPE_PAGE_SHARED, NULL); 1922 - if (err < 0) { 1923 - xdp_rxq_info_unreg(&vi->rq[i].xdp_rxq); 1924 - return err; 1925 - } 1926 - 1927 - virtnet_napi_enable(vi->rq[i].vq, &vi->rq[i].napi); 1928 - virtnet_napi_tx_enable(vi, vi->sq[i].vq, &vi->sq[i].napi); 1886 + goto err_enable_qp; 1929 1887 } 1930 1888 1931 1889 return 0; 1890 + 1891 + err_enable_qp: 1892 + disable_delayed_refill(vi); 1893 + cancel_delayed_work_sync(&vi->refill); 1894 + 1895 + for (i--; i >= 0; i--) 1896 + virtnet_disable_queue_pair(vi, i); 1897 + return err; 1932 1898 } 1933 1899 1934 1900 static int virtnet_poll_tx(struct napi_struct *napi, int budget) ··· 2335 2305 /* Make sure refill_work doesn't re-enable napi! */ 2336 2306 cancel_delayed_work_sync(&vi->refill); 2337 2307 2338 - for (i = 0; i < vi->max_queue_pairs; i++) { 2339 - virtnet_napi_tx_disable(&vi->sq[i].napi); 2340 - napi_disable(&vi->rq[i].napi); 2341 - xdp_rxq_info_unreg(&vi->rq[i].xdp_rxq); 2342 - } 2308 + for (i = 0; i < vi->max_queue_pairs; i++) 2309 + virtnet_disable_queue_pair(vi, i); 2343 2310 2344 2311 return 0; 2345 2312 }
+1 -1
drivers/net/wireless/broadcom/b43/b43.h
··· 651 651 union { 652 652 __be16 d16; 653 653 __be32 d32; 654 - } data __packed; 654 + } __packed data; 655 655 } __packed; 656 656 657 657
+1 -1
drivers/net/wireless/broadcom/b43legacy/b43legacy.h
··· 379 379 union { 380 380 __be16 d16; 381 381 __be32 d32; 382 - } data __packed; 382 + } __packed data; 383 383 } __packed; 384 384 385 385 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
+5
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
··· 1039 1039 struct brcmf_sdio_dev *sdiodev; 1040 1040 struct brcmf_bus *bus_if; 1041 1041 1042 + if (!id) { 1043 + dev_err(&func->dev, "Error no sdio_device_id passed for %x:%x\n", func->vendor, func->device); 1044 + return -ENODEV; 1045 + } 1046 + 1042 1047 brcmf_dbg(SDIO, "Enter\n"); 1043 1048 brcmf_dbg(SDIO, "Class=%x\n", func->class); 1044 1049 brcmf_dbg(SDIO, "sdio vendor ID: 0x%04x\n", func->vendor);
+11
drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
··· 2394 2394 } 2395 2395 #endif 2396 2396 2397 + /* Forward declaration for pci_match_id() call */ 2398 + static const struct pci_device_id brcmf_pcie_devid_table[]; 2399 + 2397 2400 static int 2398 2401 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2399 2402 { ··· 2406 2403 struct brcmf_pciedev *pcie_bus_dev; 2407 2404 struct brcmf_core *core; 2408 2405 struct brcmf_bus *bus; 2406 + 2407 + if (!id) { 2408 + id = pci_match_id(brcmf_pcie_devid_table, pdev); 2409 + if (!id) { 2410 + pci_err(pdev, "Error could not find pci_device_id for %x:%x\n", pdev->vendor, pdev->device); 2411 + return -ENODEV; 2412 + } 2413 + } 2409 2414 2410 2415 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 2411 2416
+11
drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c
··· 1331 1331 brcmf_usb_detach(devinfo); 1332 1332 } 1333 1333 1334 + /* Forward declaration for usb_match_id() call */ 1335 + static const struct usb_device_id brcmf_usb_devid_table[]; 1336 + 1334 1337 static int 1335 1338 brcmf_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) 1336 1339 { ··· 1344 1341 int ret = 0; 1345 1342 u32 num_of_eps; 1346 1343 u8 endpoint_num, ep; 1344 + 1345 + if (!id) { 1346 + id = usb_match_id(intf, brcmf_usb_devid_table); 1347 + if (!id) { 1348 + dev_err(&intf->dev, "Error could not find matching usb_device_id\n"); 1349 + return -ENODEV; 1350 + } 1351 + } 1347 1352 1348 1353 brcmf_dbg(USB, "Enter 0x%04x:0x%04x\n", id->idVendor, id->idProduct); 1349 1354
+1 -1
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
··· 38 38 }, 39 39 { .ident = "ASUS", 40 40 .matches = { 41 - DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek COMPUTER INC."), 41 + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 42 42 }, 43 43 }, 44 44 {}
+11 -8
drivers/net/wireless/intel/iwlwifi/fw/dbg.c
··· 1664 1664 } 1665 1665 1666 1666 static void * 1667 - iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1668 - struct iwl_dump_ini_region_data *reg_data, 1667 + iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1669 1668 struct iwl_fw_ini_monitor_dump *data, 1670 1669 const struct iwl_fw_mon_regs *addrs) 1671 1670 { 1672 - struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1673 - u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1674 - 1675 1671 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1676 1672 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1677 1673 return NULL; ··· 1698 1702 void *data, u32 data_len) 1699 1703 { 1700 1704 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1705 + struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1706 + u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1701 1707 1702 - return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1708 + return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1703 1709 &fwrt->trans->cfg->mon_dram_regs); 1704 1710 } 1705 1711 ··· 1711 1713 void *data, u32 data_len) 1712 1714 { 1713 1715 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1716 + struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1717 + u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1714 1718 1715 - return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1719 + return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1716 1720 &fwrt->trans->cfg->mon_smem_regs); 1717 1721 } 1718 1722 ··· 1725 1725 { 1726 1726 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1727 1727 1728 - return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1728 + return iwl_dump_ini_mon_fill_header(fwrt, 1729 + /* no offset calculation later */ 1730 + IWL_FW_INI_ALLOCATION_ID_DBGC1, 1731 + mon_dump, 1729 1732 &fwrt->trans->cfg->mon_dbgi_regs); 1730 1733 } 1731 1734
+5
drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
··· 526 526 rcu_read_lock(); 527 527 528 528 sta = rcu_dereference(mvm->fw_id_to_mac_id[mvmvif->deflink.ap_sta_id]); 529 + if (WARN_ON_ONCE(IS_ERR_OR_NULL(sta))) { 530 + rcu_read_unlock(); 531 + return PTR_ERR_OR_ZERO(sta); 532 + } 533 + 529 534 if (sta->mfp && (peer->ftm.trigger_based || peer->ftm.non_trigger_based)) 530 535 FTM_PUT_FLAG(PMF); 531 536
+2 -3
drivers/net/wireless/intel/iwlwifi/mvm/fw.c
··· 1091 1091 }, 1092 1092 { .ident = "LENOVO", 1093 1093 .matches = { 1094 - DMI_MATCH(DMI_SYS_VENDOR, "Lenovo"), 1094 + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1095 1095 }, 1096 1096 }, 1097 1097 { .ident = "DELL", ··· 1727 1727 iwl_mvm_tas_init(mvm); 1728 1728 iwl_mvm_leds_sync(mvm); 1729 1729 1730 - if (fw_has_capa(&mvm->fw->ucode_capa, 1731 - IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) { 1730 + if (iwl_rfi_supported(mvm)) { 1732 1731 if (iwl_mvm_eval_dsm_rfi(mvm) == DSM_VALUE_RFI_ENABLE) 1733 1732 iwl_rfi_send_config_cmd(mvm, NULL); 1734 1733 }
+7 -5
drivers/net/wireless/intel/iwlwifi/mvm/link.c
··· 123 123 if (mvmvif->link[i]->phy_ctxt) 124 124 count++; 125 125 126 - /* FIXME: IWL_MVM_FW_MAX_ACTIVE_LINKS_NUM should be 127 - * defined per HW 128 - */ 129 - if (count >= IWL_MVM_FW_MAX_ACTIVE_LINKS_NUM) 130 - return -EINVAL; 126 + if (vif->type == NL80211_IFTYPE_AP) { 127 + if (count > mvm->fw->ucode_capa.num_beacons) 128 + return -EOPNOTSUPP; 129 + /* this should be per HW or such */ 130 + } else if (count >= IWL_MVM_FW_MAX_ACTIVE_LINKS_NUM) { 131 + return -EOPNOTSUPP; 132 + } 131 133 } 132 134 133 135 /* Catch early if driver tries to activate or deactivate a link
+25 -30
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 - * Copyright (C) 2012-2014, 2018-2022 Intel Corporation 3 + * Copyright (C) 2012-2014, 2018-2023 Intel Corporation 4 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 6 */ ··· 3607 3607 struct ieee80211_vif *vif, 3608 3608 struct ieee80211_sta *sta) 3609 3609 { 3610 - unsigned int i; 3610 + struct ieee80211_link_sta *link_sta; 3611 + unsigned int link_id; 3611 3612 3612 3613 /* Beacon interval check - firmware will crash if the beacon 3613 3614 * interval is less than 16. We can't avoid connecting at all, ··· 3617 3616 * wpa_s will blocklist the AP... 3618 3617 */ 3619 3618 3620 - for_each_set_bit(i, (unsigned long *)&sta->valid_links, 3621 - IEEE80211_MLD_MAX_NUM_LINKS) { 3622 - struct ieee80211_link_sta *link_sta = 3623 - link_sta_dereference_protected(sta, i); 3619 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 3624 3620 struct ieee80211_bss_conf *link_conf = 3625 - link_conf_dereference_protected(vif, i); 3621 + link_conf_dereference_protected(vif, link_id); 3626 3622 3627 - if (!link_conf || !link_sta) 3623 + if (!link_conf) 3628 3624 continue; 3629 3625 3630 3626 if (link_conf->beacon_int < IWL_MVM_MIN_BEACON_INTERVAL_TU) { ··· 3643 3645 bool is_sta) 3644 3646 { 3645 3647 struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif); 3646 - unsigned int i; 3648 + struct ieee80211_link_sta *link_sta; 3649 + unsigned int link_id; 3647 3650 3648 - for_each_set_bit(i, (unsigned long *)&sta->valid_links, 3649 - IEEE80211_MLD_MAX_NUM_LINKS) { 3650 - struct ieee80211_link_sta *link_sta = 3651 - link_sta_dereference_protected(sta, i); 3651 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 3652 3652 struct ieee80211_bss_conf *link_conf = 3653 - link_conf_dereference_protected(vif, i); 3653 + link_conf_dereference_protected(vif, link_id); 3654 3654 3655 - if (!link_conf || !link_sta || !mvmvif->link[i]) 3655 + if (!link_conf || !mvmvif->link[link_id]) 3656 3656 continue; 3657 3657 3658 3658 link_conf->he_support = link_sta->he_cap.has_he; 3659 3659 3660 3660 if (is_sta) { 3661 - mvmvif->link[i]->he_ru_2mhz_block = false; 3661 + mvmvif->link[link_id]->he_ru_2mhz_block = false; 3662 3662 if (link_sta->he_cap.has_he) 3663 - iwl_mvm_check_he_obss_narrow_bw_ru(hw, vif, i, 3663 + iwl_mvm_check_he_obss_narrow_bw_ru(hw, vif, 3664 + link_id, 3664 3665 link_conf); 3665 3666 } 3666 3667 } ··· 3672 3675 struct iwl_mvm_sta_state_ops *callbacks) 3673 3676 { 3674 3677 struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif); 3678 + struct ieee80211_link_sta *link_sta; 3675 3679 unsigned int i; 3676 3680 int ret; 3677 3681 ··· 3697 3699 NL80211_TDLS_SETUP); 3698 3700 } 3699 3701 3700 - for (i = 0; i < ARRAY_SIZE(sta->link); i++) { 3701 - struct ieee80211_link_sta *link_sta; 3702 - 3703 - link_sta = link_sta_dereference_protected(sta, i); 3704 - if (!link_sta) 3705 - continue; 3706 - 3702 + for_each_sta_active_link(vif, sta, link_sta, i) 3707 3703 link_sta->agg.max_rc_amsdu_len = 1; 3708 - } 3704 + 3709 3705 ieee80211_sta_recalc_aggregates(sta); 3710 3706 3711 3707 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) ··· 3717 3725 { 3718 3726 struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif); 3719 3727 struct iwl_mvm_sta *mvm_sta = iwl_mvm_sta_from_mac80211(sta); 3720 - unsigned int i; 3728 + struct ieee80211_link_sta *link_sta; 3729 + unsigned int link_id; 3721 3730 3722 3731 lockdep_assert_held(&mvm->mutex); 3723 3732 ··· 3744 3751 if (!mvm->mld_api_is_used) 3745 3752 goto out; 3746 3753 3747 - for_each_set_bit(i, (unsigned long *)&sta->valid_links, 3748 - IEEE80211_MLD_MAX_NUM_LINKS) { 3754 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 3749 3755 struct ieee80211_bss_conf *link_conf = 3750 - link_conf_dereference_protected(vif, i); 3756 + link_conf_dereference_protected(vif, link_id); 3751 3757 3752 3758 if (WARN_ON(!link_conf)) 3753 3759 return -EINVAL; 3754 - if (!mvmvif->link[i]) 3760 + if (!mvmvif->link[link_id]) 3755 3761 continue; 3756 3762 3757 3763 iwl_mvm_link_changed(mvm, vif, link_conf, ··· 3881 3889 * from the AP now. 3882 3890 */ 3883 3891 iwl_mvm_reset_cca_40mhz_workaround(mvm, vif); 3892 + 3893 + /* Also free dup data just in case any assertions below fail */ 3894 + kfree(mvm_sta->dup_data); 3884 3895 } 3885 3896 3886 3897 mutex_lock(&mvm->mutex);
+5 -4
drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c
··· 906 906 n_active++; 907 907 } 908 908 909 - if (vif->type == NL80211_IFTYPE_AP && 910 - n_active > mvm->fw->ucode_capa.num_beacons) 909 + if (vif->type == NL80211_IFTYPE_AP) { 910 + if (n_active > mvm->fw->ucode_capa.num_beacons) 911 + return -EOPNOTSUPP; 912 + } else if (n_active > 1) { 911 913 return -EOPNOTSUPP; 912 - else if (n_active > 1) 913 - return -EOPNOTSUPP; 914 + } 914 915 } 915 916 916 917 for (i = 0; i < IEEE80211_MLD_MAX_NUM_LINKS; i++) {
+6 -8
drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c
··· 667 667 ret = iwl_mvm_mld_alloc_sta_links(mvm, vif, sta); 668 668 if (ret) 669 669 return ret; 670 - } 671 670 672 - spin_lock_init(&mvm_sta->lock); 671 + spin_lock_init(&mvm_sta->lock); 673 672 674 - if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) 675 - ret = iwl_mvm_alloc_sta_after_restart(mvm, vif, sta); 676 - else 677 673 ret = iwl_mvm_sta_init(mvm, vif, sta, IWL_MVM_INVALID_STA, 678 674 STATION_TYPE_PEER); 675 + } else { 676 + ret = iwl_mvm_alloc_sta_after_restart(mvm, vif, sta); 677 + } 678 + 679 679 if (ret) 680 680 goto err; 681 681 ··· 728 728 struct iwl_mvm_sta *mvm_sta = iwl_mvm_sta_from_mac80211(sta); 729 729 struct ieee80211_link_sta *link_sta; 730 730 unsigned int link_id; 731 - int ret = 0; 731 + int ret = -EINVAL; 732 732 733 733 lockdep_assert_held(&mvm->mutex); 734 734 ··· 790 790 int ret; 791 791 792 792 lockdep_assert_held(&mvm->mutex); 793 - 794 - kfree(mvm_sta->dup_data); 795 793 796 794 /* flush its queues here since we are freeing mvm_sta */ 797 795 for_each_sta_active_link(vif, sta, link_sta, link_id) {
+1
drivers/net/wireless/intel/iwlwifi/mvm/mvm.h
··· 2347 2347 u32 old_sta_mask, 2348 2348 u32 new_sta_mask); 2349 2349 2350 + bool iwl_rfi_supported(struct iwl_mvm *mvm); 2350 2351 int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm, 2351 2352 struct iwl_rfi_lut_entry *rfi_table); 2352 2353 struct iwl_rfi_freq_table_resp_cmd *iwl_rfi_get_freq_table(struct iwl_mvm *mvm);
+10
drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
··· 445 445 struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data; 446 446 447 447 n_channels = __le32_to_cpu(mcc_resp->n_channels); 448 + if (iwl_rx_packet_payload_len(pkt) != 449 + struct_size(mcc_resp, channels, n_channels)) { 450 + resp_cp = ERR_PTR(-EINVAL); 451 + goto exit; 452 + } 448 453 resp_len = sizeof(struct iwl_mcc_update_resp) + 449 454 n_channels * sizeof(__le32); 450 455 resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); ··· 461 456 struct iwl_mcc_update_resp_v3 *mcc_resp_v3 = (void *)pkt->data; 462 457 463 458 n_channels = __le32_to_cpu(mcc_resp_v3->n_channels); 459 + if (iwl_rx_packet_payload_len(pkt) != 460 + struct_size(mcc_resp_v3, channels, n_channels)) { 461 + resp_cp = ERR_PTR(-EINVAL); 462 + goto exit; 463 + } 464 464 resp_len = sizeof(struct iwl_mcc_update_resp) + 465 465 n_channels * sizeof(__le32); 466 466 resp_cp = kzalloc(resp_len, GFP_KERNEL);
+13 -3
drivers/net/wireless/intel/iwlwifi/mvm/rfi.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 2 /* 3 - * Copyright (C) 2020 - 2021 Intel Corporation 3 + * Copyright (C) 2020 - 2022 Intel Corporation 4 4 */ 5 5 6 6 #include "mvm.h" ··· 70 70 PHY_BAND_6, PHY_BAND_6,}}, 71 71 }; 72 72 73 + bool iwl_rfi_supported(struct iwl_mvm *mvm) 74 + { 75 + /* The feature depends on a platform bugfix, so for now 76 + * it's always disabled. 77 + * When the platform support detection is implemented we should 78 + * check FW TLV and platform support instead. 79 + */ 80 + return false; 81 + } 82 + 73 83 int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm, struct iwl_rfi_lut_entry *rfi_table) 74 84 { 75 85 int ret; ··· 91 81 .len[0] = sizeof(cmd), 92 82 }; 93 83 94 - if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) 84 + if (!iwl_rfi_supported(mvm)) 95 85 return -EOPNOTSUPP; 96 86 97 87 lockdep_assert_held(&mvm->mutex); ··· 123 113 .flags = CMD_WANT_SKB, 124 114 }; 125 115 126 - if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_RFIM_SUPPORT)) 116 + if (!iwl_rfi_supported(mvm)) 127 117 return ERR_PTR(-EOPNOTSUPP); 128 118 129 119 mutex_lock(&mvm->mutex);
+3
drivers/net/wireless/intel/iwlwifi/mvm/rs.c
··· 2691 2691 return; 2692 2692 2693 2693 lq_sta = mvm_sta; 2694 + 2695 + spin_lock(&lq_sta->pers.lock); 2694 2696 iwl_mvm_hwrate_to_tx_rate_v1(lq_sta->last_rate_n_flags, 2695 2697 info->band, &info->control.rates[0]); 2696 2698 info->control.rates[0].count = 1; ··· 2707 2705 iwl_mvm_hwrate_to_tx_rate_v1(last_ucode_rate, info->band, 2708 2706 &txrc->reported_rate); 2709 2707 } 2708 + spin_unlock(&lq_sta->pers.lock); 2710 2709 } 2711 2710 2712 2711 static void *rs_drv_alloc_sta(void *mvm_rate, struct ieee80211_sta *sta,
+8 -1
drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c
··· 691 691 692 692 rcu_read_lock(); 693 693 sta = rcu_dereference(buf->mvm->fw_id_to_mac_id[sta_id]); 694 + if (WARN_ON_ONCE(IS_ERR_OR_NULL(sta))) { 695 + rcu_read_unlock(); 696 + goto out; 697 + } 698 + 694 699 mvmsta = iwl_mvm_sta_from_mac80211(sta); 695 700 696 701 /* SN is set to the last expired frame + 1 */ ··· 717 712 entries[index].e.reorder_time + 718 713 1 + RX_REORDER_BUF_TIMEOUT_MQ); 719 714 } 715 + 716 + out: 720 717 spin_unlock(&buf->lock); 721 718 } 722 719 ··· 2519 2512 RCU_INIT_POINTER(mvm->csa_tx_blocked_vif, NULL); 2520 2513 /* Unblock BCAST / MCAST station */ 2521 2514 iwl_mvm_modify_all_sta_disable_tx(mvm, mvmvif, false); 2522 - cancel_delayed_work_sync(&mvm->cs_tx_unblock_dwork); 2515 + cancel_delayed_work(&mvm->cs_tx_unblock_dwork); 2523 2516 } 2524 2517 } 2525 2518
+9 -4
drivers/net/wireless/intel/iwlwifi/mvm/sta.c
··· 281 281 * A-MDPU and hence the timer continues to run. Then, the 282 282 * timer expires and sta is NULL. 283 283 */ 284 - if (!sta) 284 + if (IS_ERR_OR_NULL(sta)) 285 285 goto unlock; 286 286 287 287 mvm_sta = iwl_mvm_sta_from_mac80211(sta); ··· 2089 2089 2090 2090 lockdep_assert_held(&mvm->mutex); 2091 2091 2092 - if (iwl_mvm_has_new_rx_api(mvm)) 2093 - kfree(mvm_sta->dup_data); 2094 - 2095 2092 ret = iwl_mvm_drain_sta(mvm, mvm_sta, true); 2096 2093 if (ret) 2097 2094 return ret; ··· 3782 3785 u8 sta_id = mvmvif->deflink.ap_sta_id; 3783 3786 sta = rcu_dereference_protected(mvm->fw_id_to_mac_id[sta_id], 3784 3787 lockdep_is_held(&mvm->mutex)); 3788 + if (WARN_ON_ONCE(IS_ERR_OR_NULL(sta))) 3789 + return NULL; 3790 + 3785 3791 return sta->addr; 3786 3792 } 3787 3793 ··· 3822 3822 3823 3823 if (keyconf->cipher == WLAN_CIPHER_SUITE_TKIP) { 3824 3824 addr = iwl_mvm_get_mac_addr(mvm, vif, sta); 3825 + if (!addr) { 3826 + IWL_ERR(mvm, "Failed to find mac address\n"); 3827 + return -EINVAL; 3828 + } 3829 + 3825 3830 /* get phase 1 key from mac80211 */ 3826 3831 ieee80211_get_key_rx_seq(keyconf, 0, &seq); 3827 3832 ieee80211_get_tkip_rx_p1k(keyconf, addr, seq.tkip.iv32, p1k);
+1 -1
drivers/net/wireless/intel/iwlwifi/mvm/tx.c
··· 1875 1875 mvmsta = iwl_mvm_sta_from_staid_rcu(mvm, sta_id); 1876 1876 1877 1877 sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_id]); 1878 - if (WARN_ON_ONCE(!sta || !sta->wme)) { 1878 + if (WARN_ON_ONCE(IS_ERR_OR_NULL(sta) || !sta->wme)) { 1879 1879 rcu_read_unlock(); 1880 1880 return; 1881 1881 }
+1 -1
drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h
··· 173 173 #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23) 174 174 175 175 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23) 176 - 176 + #define MT_TXS7_MPDU_RETRY_BYTE GENMASK(22, 0) 177 177 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23) 178 178 179 179 /* RXD DW0 */
+2 -1
drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c
··· 608 608 /* PPDU based reporting */ 609 609 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) { 610 610 stats->tx_bytes += 611 - le32_get_bits(txs_data[5], MT_TXS5_MPDU_TX_BYTE); 611 + le32_get_bits(txs_data[5], MT_TXS5_MPDU_TX_BYTE) - 612 + le32_get_bits(txs_data[7], MT_TXS7_MPDU_RETRY_BYTE); 612 613 stats->tx_packets += 613 614 le32_get_bits(txs_data[5], MT_TXS5_MPDU_TX_CNT); 614 615 stats->tx_failed +=
+1 -1
drivers/net/wireless/mediatek/mt76/mt7996/mac.c
··· 1088 1088 else if (beacon && mvif->beacon_rates_idx) 1089 1089 idx = mvif->beacon_rates_idx; 1090 1090 1091 - txwi[6] |= FIELD_PREP(MT_TXD6_TX_RATE, idx); 1091 + txwi[6] |= cpu_to_le32(FIELD_PREP(MT_TXD6_TX_RATE, idx)); 1092 1092 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1093 1093 } 1094 1094 }
+1
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
··· 1803 1803 u32 rege9c; 1804 1804 u32 regeb4; 1805 1805 u32 regebc; 1806 + u32 regrcr; 1806 1807 int next_mbox; 1807 1808 int nr_out_eps; 1808 1809
+3 -1
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
··· 4171 4171 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4172 4172 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4173 4173 rtl8xxxu_write32(priv, REG_RCR, val32); 4174 + priv->regrcr = val32; 4174 4175 4175 4176 if (fops->init_reg_rxfltmap) { 4176 4177 /* Accept all data frames */ ··· 6502 6501 unsigned int *total_flags, u64 multicast) 6503 6502 { 6504 6503 struct rtl8xxxu_priv *priv = hw->priv; 6505 - u32 rcr = rtl8xxxu_read32(priv, REG_RCR); 6504 + u32 rcr = priv->regrcr; 6506 6505 6507 6506 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 6508 6507 __func__, changed_flags, *total_flags); ··· 6548 6547 */ 6549 6548 6550 6549 rtl8xxxu_write32(priv, REG_RCR, rcr); 6550 + priv->regrcr = rcr; 6551 6551 6552 6552 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 6553 6553 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
+1 -1
drivers/net/wireless/realtek/rtw88/mac80211.c
··· 918 918 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 919 919 920 920 if (changed & IEEE80211_RC_BW_CHANGED) 921 - rtw_update_sta_info(rtwdev, si, true); 921 + ieee80211_queue_work(rtwdev->hw, &si->rc_work); 922 922 } 923 923 924 924 const struct ieee80211_ops rtw_ops = {
+15
drivers/net/wireless/realtek/rtw88/main.c
··· 319 319 return mac_id; 320 320 } 321 321 322 + static void rtw_sta_rc_work(struct work_struct *work) 323 + { 324 + struct rtw_sta_info *si = container_of(work, struct rtw_sta_info, 325 + rc_work); 326 + struct rtw_dev *rtwdev = si->rtwdev; 327 + 328 + mutex_lock(&rtwdev->mutex); 329 + rtw_update_sta_info(rtwdev, si, true); 330 + mutex_unlock(&rtwdev->mutex); 331 + } 332 + 322 333 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 323 334 struct ieee80211_vif *vif) 324 335 { ··· 340 329 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 341 330 return -ENOSPC; 342 331 332 + si->rtwdev = rtwdev; 343 333 si->sta = sta; 344 334 si->vif = vif; 345 335 si->init_ra_lv = 1; 346 336 ewma_rssi_init(&si->avg_rssi); 347 337 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 348 338 rtw_txq_init(rtwdev, sta->txq[i]); 339 + INIT_WORK(&si->rc_work, rtw_sta_rc_work); 349 340 350 341 rtw_update_sta_info(rtwdev, si, true); 351 342 rtw_fw_media_status_report(rtwdev, si->mac_id, true); ··· 365 352 { 366 353 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 367 354 int i; 355 + 356 + cancel_work_sync(&si->rc_work); 368 357 369 358 rtw_release_macid(rtwdev, si->mac_id); 370 359 if (fw_exist)
+3
drivers/net/wireless/realtek/rtw88/main.h
··· 743 743 DECLARE_EWMA(rssi, 10, 16); 744 744 745 745 struct rtw_sta_info { 746 + struct rtw_dev *rtwdev; 746 747 struct ieee80211_sta *sta; 747 748 struct ieee80211_vif *vif; 748 749 ··· 768 767 769 768 bool use_cfg_mask; 770 769 struct cfg80211_bitrate_mask *mask; 770 + 771 + struct work_struct rc_work; 771 772 }; 772 773 773 774 enum rtw_bfee_role {
-8
drivers/net/wireless/realtek/rtw88/sdio.c
··· 87 87 u8 buf[2]; 88 88 int i; 89 89 90 - if (rtw_sdio_use_memcpy_io(rtwdev, addr, 2)) { 91 - sdio_writew(rtwsdio->sdio_func, val, addr, err_ret); 92 - return; 93 - } 94 - 95 90 *(__le16 *)buf = cpu_to_le16(val); 96 91 97 92 for (i = 0; i < 2; i++) { ··· 119 124 struct rtw_sdio *rtwsdio = (struct rtw_sdio *)rtwdev->priv; 120 125 u8 buf[2]; 121 126 int i; 122 - 123 - if (rtw_sdio_use_memcpy_io(rtwdev, addr, 2)) 124 - return sdio_readw(rtwsdio->sdio_func, addr, err_ret); 125 127 126 128 for (i = 0; i < 2; i++) { 127 129 buf[i] = sdio_readb(rtwsdio->sdio_func, addr + i, err_ret);
+1 -1
drivers/net/wireless/realtek/rtw88/usb.h
··· 78 78 u8 pipe_interrupt; 79 79 u8 pipe_in; 80 80 u8 out_ep[RTW_USB_EP_MAX]; 81 - u8 qsel_to_ep[TX_DESC_QSEL_MAX]; 81 + int qsel_to_ep[TX_DESC_QSEL_MAX]; 82 82 u8 usb_txagg_num; 83 83 84 84 struct workqueue_struct *txwq, *rxwq;
+4
drivers/net/wireless/realtek/rtw89/mac.c
··· 1425 1425 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1426 1426 /* PCIE 64 */ 1427 1427 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1428 + /* 8852B PCIE SCC */ 1429 + .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1428 1430 /* DLFW */ 1429 1431 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1430 1432 /* 8852C DLFW */ ··· 1451 1449 .wde_qt4 = {0, 0, 0, 0,}, 1452 1450 /* PCIE 64 */ 1453 1451 .wde_qt6 = {448, 48, 0, 16,}, 1452 + /* 8852B PCIE SCC */ 1453 + .wde_qt7 = {446, 48, 0, 16,}, 1454 1454 /* 8852C DLFW */ 1455 1455 .wde_qt17 = {0, 0, 0, 0,}, 1456 1456 /* 8852C PCIE SCC */
+2
drivers/net/wireless/realtek/rtw89/mac.h
··· 792 792 const struct rtw89_dle_size wde_size0; 793 793 const struct rtw89_dle_size wde_size4; 794 794 const struct rtw89_dle_size wde_size6; 795 + const struct rtw89_dle_size wde_size7; 795 796 const struct rtw89_dle_size wde_size9; 796 797 const struct rtw89_dle_size wde_size18; 797 798 const struct rtw89_dle_size wde_size19; ··· 805 804 const struct rtw89_wde_quota wde_qt0; 806 805 const struct rtw89_wde_quota wde_qt4; 807 806 const struct rtw89_wde_quota wde_qt6; 807 + const struct rtw89_wde_quota wde_qt7; 808 808 const struct rtw89_wde_quota wde_qt17; 809 809 const struct rtw89_wde_quota wde_qt18; 810 810 const struct rtw89_ple_quota ple_qt4;
+14 -14
drivers/net/wireless/realtek/rtw89/rtw8852b.c
··· 18 18 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" 19 19 20 20 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { 21 - {5, 343, grp_0}, /* ACH 0 */ 22 - {5, 343, grp_0}, /* ACH 1 */ 23 - {5, 343, grp_0}, /* ACH 2 */ 24 - {5, 343, grp_0}, /* ACH 3 */ 21 + {5, 341, grp_0}, /* ACH 0 */ 22 + {5, 341, grp_0}, /* ACH 1 */ 23 + {4, 342, grp_0}, /* ACH 2 */ 24 + {4, 342, grp_0}, /* ACH 3 */ 25 25 {0, 0, grp_0}, /* ACH 4 */ 26 26 {0, 0, grp_0}, /* ACH 5 */ 27 27 {0, 0, grp_0}, /* ACH 6 */ 28 28 {0, 0, grp_0}, /* ACH 7 */ 29 - {4, 344, grp_0}, /* B0MGQ */ 30 - {4, 344, grp_0}, /* B0HIQ */ 29 + {4, 342, grp_0}, /* B0MGQ */ 30 + {4, 342, grp_0}, /* B0HIQ */ 31 31 {0, 0, grp_0}, /* B1MGQ */ 32 32 {0, 0, grp_0}, /* B1HIQ */ 33 33 {40, 0, 0} /* FWCMDQ */ 34 34 }; 35 35 36 36 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { 37 - 448, /* Group 0 */ 37 + 446, /* Group 0 */ 38 38 0, /* Group 1 */ 39 - 448, /* Public Max */ 39 + 446, /* Public Max */ 40 40 0 /* WP threshold */ 41 41 }; 42 42 ··· 49 49 }; 50 50 51 51 static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { 52 - [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6, 53 - &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 54 - &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 52 + [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7, 53 + &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 54 + &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 55 55 &rtw89_mac_size.ple_qt58}, 56 - [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6, 57 - &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 58 - &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 56 + [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7, 57 + &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 58 + &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 59 59 &rtw89_mac_size.ple_qt_52b_wow}, 60 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 61 61 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
+2 -1
drivers/net/wireless/virtual/mac80211_hwsim.c
··· 5964 5964 ret = -ENOMEM; 5965 5965 goto out_free; 5966 5966 } 5967 + param.pmsr_capa = pmsr_capa; 5968 + 5967 5969 ret = parse_pmsr_capa(info->attrs[HWSIM_ATTR_PMSR_SUPPORT], pmsr_capa, info); 5968 5970 if (ret) 5969 5971 goto out_free; 5970 - param.pmsr_capa = pmsr_capa; 5971 5972 } 5972 5973 5973 5974 ret = mac80211_hwsim_new_radio(info, &param);
+21 -6
drivers/net/wwan/iosm/iosm_ipc_imem.c
··· 565 565 struct ipc_mux_config mux_cfg; 566 566 struct iosm_imem *ipc_imem; 567 567 u8 ctrl_chl_idx = 0; 568 + int ret; 568 569 569 570 ipc_imem = container_of(instance, struct iosm_imem, run_state_worker); 570 571 571 572 if (ipc_imem->phase != IPC_P_RUN) { 572 573 dev_err(ipc_imem->dev, 573 574 "Modem link down. Exit run state worker."); 574 - return; 575 + goto err_out; 575 576 } 576 577 577 578 if (test_and_clear_bit(IOSM_DEVLINK_INIT, &ipc_imem->flag)) 578 579 ipc_devlink_deinit(ipc_imem->ipc_devlink); 579 580 580 - if (!ipc_imem_setup_cp_mux_cap_init(ipc_imem, &mux_cfg)) 581 - ipc_imem->mux = ipc_mux_init(&mux_cfg, ipc_imem); 581 + ret = ipc_imem_setup_cp_mux_cap_init(ipc_imem, &mux_cfg); 582 + if (ret < 0) 583 + goto err_out; 582 584 583 - ipc_imem_wwan_channel_init(ipc_imem, mux_cfg.protocol); 584 - if (ipc_imem->mux) 585 - ipc_imem->mux->wwan = ipc_imem->wwan; 585 + ipc_imem->mux = ipc_mux_init(&mux_cfg, ipc_imem); 586 + if (!ipc_imem->mux) 587 + goto err_out; 588 + 589 + ret = ipc_imem_wwan_channel_init(ipc_imem, mux_cfg.protocol); 590 + if (ret < 0) 591 + goto err_ipc_mux_deinit; 592 + 593 + ipc_imem->mux->wwan = ipc_imem->wwan; 586 594 587 595 while (ctrl_chl_idx < IPC_MEM_MAX_CHANNELS) { 588 596 if (!ipc_chnl_cfg_get(&chnl_cfg_port, ctrl_chl_idx)) { ··· 630 622 631 623 /* Complete all memory stores after setting bit */ 632 624 smp_mb__after_atomic(); 625 + 626 + return; 627 + 628 + err_ipc_mux_deinit: 629 + ipc_mux_deinit(ipc_imem->mux); 630 + err_out: 631 + ipc_uevent_send(ipc_imem->dev, UEVENT_CD_READY_LINK_DOWN); 633 632 } 634 633 635 634 static void ipc_imem_handle_irq(struct iosm_imem *ipc_imem, int irq)
+8 -4
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
··· 77 77 } 78 78 79 79 /* Initialize wwan channel */ 80 - void ipc_imem_wwan_channel_init(struct iosm_imem *ipc_imem, 81 - enum ipc_mux_protocol mux_type) 80 + int ipc_imem_wwan_channel_init(struct iosm_imem *ipc_imem, 81 + enum ipc_mux_protocol mux_type) 82 82 { 83 83 struct ipc_chnl_cfg chnl_cfg = { 0 }; 84 84 ··· 87 87 /* If modem version is invalid (0xffffffff), do not initialize WWAN. */ 88 88 if (ipc_imem->cp_version == -1) { 89 89 dev_err(ipc_imem->dev, "invalid CP version"); 90 - return; 90 + return -EIO; 91 91 } 92 92 93 93 ipc_chnl_cfg_get(&chnl_cfg, ipc_imem->nr_of_channels); ··· 104 104 105 105 /* WWAN registration. */ 106 106 ipc_imem->wwan = ipc_wwan_init(ipc_imem, ipc_imem->dev); 107 - if (!ipc_imem->wwan) 107 + if (!ipc_imem->wwan) { 108 108 dev_err(ipc_imem->dev, 109 109 "failed to register the ipc_wwan interfaces"); 110 + return -ENOMEM; 111 + } 112 + 113 + return 0; 110 114 } 111 115 112 116 /* Map SKB to DMA for transfer */
+4 -2
drivers/net/wwan/iosm/iosm_ipc_imem_ops.h
··· 91 91 * MUX. 92 92 * @ipc_imem: Pointer to iosm_imem struct. 93 93 * @mux_type: Type of mux protocol. 94 + * 95 + * Return: 0 on success and failure value on error 94 96 */ 95 - void ipc_imem_wwan_channel_init(struct iosm_imem *ipc_imem, 96 - enum ipc_mux_protocol mux_type); 97 + int ipc_imem_wwan_channel_init(struct iosm_imem *ipc_imem, 98 + enum ipc_mux_protocol mux_type); 97 99 98 100 /** 99 101 * ipc_imem_sys_devlink_open - Open a Flash/CD Channel link to CP
+18
drivers/net/wwan/t7xx/t7xx_pci.c
··· 45 45 #define T7XX_PCI_IREG_BASE 0 46 46 #define T7XX_PCI_EREG_BASE 2 47 47 48 + #define T7XX_INIT_TIMEOUT 20 48 49 #define PM_SLEEP_DIS_TIMEOUT_MS 20 49 50 #define PM_ACK_TIMEOUT_MS 1500 50 51 #define PM_AUTOSUSPEND_MS 20000 ··· 97 96 spin_lock_init(&t7xx_dev->md_pm_lock); 98 97 init_completion(&t7xx_dev->sleep_lock_acquire); 99 98 init_completion(&t7xx_dev->pm_sr_ack); 99 + init_completion(&t7xx_dev->init_done); 100 100 atomic_set(&t7xx_dev->md_pm_state, MTK_PM_INIT); 101 101 102 102 device_init_wakeup(&pdev->dev, true); ··· 126 124 pm_runtime_mark_last_busy(&t7xx_dev->pdev->dev); 127 125 pm_runtime_allow(&t7xx_dev->pdev->dev); 128 126 pm_runtime_put_noidle(&t7xx_dev->pdev->dev); 127 + complete_all(&t7xx_dev->init_done); 129 128 } 130 129 131 130 static int t7xx_pci_pm_reinit(struct t7xx_pci_dev *t7xx_dev) ··· 532 529 __t7xx_pci_pm_suspend(pdev); 533 530 } 534 531 532 + static int t7xx_pci_pm_prepare(struct device *dev) 533 + { 534 + struct pci_dev *pdev = to_pci_dev(dev); 535 + struct t7xx_pci_dev *t7xx_dev; 536 + 537 + t7xx_dev = pci_get_drvdata(pdev); 538 + if (!wait_for_completion_timeout(&t7xx_dev->init_done, T7XX_INIT_TIMEOUT * HZ)) { 539 + dev_warn(dev, "Not ready for system sleep.\n"); 540 + return -ETIMEDOUT; 541 + } 542 + 543 + return 0; 544 + } 545 + 535 546 static int t7xx_pci_pm_suspend(struct device *dev) 536 547 { 537 548 return __t7xx_pci_pm_suspend(to_pci_dev(dev)); ··· 572 555 } 573 556 574 557 static const struct dev_pm_ops t7xx_pci_pm_ops = { 558 + .prepare = t7xx_pci_pm_prepare, 575 559 .suspend = t7xx_pci_pm_suspend, 576 560 .resume = t7xx_pci_pm_resume, 577 561 .resume_noirq = t7xx_pci_pm_resume_noirq,
+1
drivers/net/wwan/t7xx/t7xx_pci.h
··· 69 69 struct t7xx_modem *md; 70 70 struct t7xx_ccmni_ctrl *ccmni_ctlb; 71 71 bool rgu_pci_irq_en; 72 + struct completion init_done; 72 73 73 74 /* Low Power Items */ 74 75 struct list_head md_pm_entities;
+5 -1
drivers/nvme/host/core.c
··· 3585 3585 { 3586 3586 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); 3587 3587 3588 + if (!test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags)) 3589 + return -EBUSY; 3590 + 3588 3591 if (device_remove_file_self(dev, attr)) 3589 3592 nvme_delete_ctrl_sync(ctrl); 3590 3593 return count; ··· 5048 5045 * that were missed. We identify persistent discovery controllers by 5049 5046 * checking that they started once before, hence are reconnecting back. 5050 5047 */ 5051 - if (test_and_set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) && 5048 + if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) && 5052 5049 nvme_discovery_ctrl(ctrl)) 5053 5050 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover"); 5054 5051 ··· 5059 5056 } 5060 5057 5061 5058 nvme_change_uevent(ctrl, "NVME_EVENT=connected"); 5059 + set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags); 5062 5060 } 5063 5061 EXPORT_SYMBOL_GPL(nvme_start_ctrl); 5064 5062
+3 -1
drivers/nvme/host/hwmon.c
··· 163 163 case hwmon_temp_max: 164 164 case hwmon_temp_min: 165 165 if ((!channel && data->ctrl->wctemp) || 166 - (channel && data->log->temp_sensor[channel - 1])) { 166 + (channel && data->log->temp_sensor[channel - 1] && 167 + !(data->ctrl->quirks & 168 + NVME_QUIRK_NO_SECONDARY_TEMP_THRESH))) { 167 169 if (data->ctrl->quirks & 168 170 NVME_QUIRK_NO_TEMP_THRESH_CHANGE) 169 171 return 0444;
-1
drivers/nvme/host/multipath.c
··· 884 884 { 885 885 if (!head->disk) 886 886 return; 887 - blk_mark_disk_dead(head->disk); 888 887 /* make sure all pending bios are cleaned up */ 889 888 kblockd_schedule_work(&head->requeue_work); 890 889 flush_work(&head->requeue_work);
+5
drivers/nvme/host/nvme.h
··· 149 149 * Reports garbage in the namespace identifiers (eui64, nguid, uuid). 150 150 */ 151 151 NVME_QUIRK_BOGUS_NID = (1 << 18), 152 + 153 + /* 154 + * No temperature thresholds for channels other than 0 (Composite). 155 + */ 156 + NVME_QUIRK_NO_SECONDARY_TEMP_THRESH = (1 << 19), 152 157 }; 153 158 154 159 /*
+7 -1
drivers/nvme/host/pci.c
··· 2956 2956 * over a single page. 2957 2957 */ 2958 2958 dev->ctrl.max_hw_sectors = min_t(u32, 2959 - NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 2959 + NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9); 2960 2960 dev->ctrl.max_segments = NVME_MAX_SEGS; 2961 2961 2962 2962 /* ··· 3402 3402 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3403 3403 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3404 3404 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3405 + { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */ 3406 + .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, }, 3405 3407 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3406 3408 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3407 3409 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ ··· 3442 3440 .driver_data = NVME_QUIRK_BOGUS_NID | 3443 3441 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3444 3442 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */ 3443 + .driver_data = NVME_QUIRK_BOGUS_NID, }, 3444 + { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */ 3445 + .driver_data = NVME_QUIRK_BOGUS_NID, }, 3446 + { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */ 3445 3447 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3446 3448 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3447 3449 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
+31 -2
drivers/s390/block/dasd_eckd.c
··· 127 127 struct dasd_device *, struct dasd_device *, 128 128 unsigned int, int, unsigned int, unsigned int, 129 129 unsigned int, unsigned int); 130 + static int dasd_eckd_query_pprc_status(struct dasd_device *, 131 + struct dasd_pprc_data_sc4 *); 130 132 131 133 /* initial attempt at a probe function. this can be simplified once 132 134 * the other detection code is gone */ ··· 3735 3733 return count; 3736 3734 } 3737 3735 3736 + static int dasd_in_copy_relation(struct dasd_device *device) 3737 + { 3738 + struct dasd_pprc_data_sc4 *temp; 3739 + int rc; 3740 + 3741 + if (!dasd_eckd_pprc_enabled(device)) 3742 + return 0; 3743 + 3744 + temp = kzalloc(sizeof(*temp), GFP_KERNEL); 3745 + if (!temp) 3746 + return -ENOMEM; 3747 + 3748 + rc = dasd_eckd_query_pprc_status(device, temp); 3749 + if (!rc) 3750 + rc = temp->dev_info[0].state; 3751 + 3752 + kfree(temp); 3753 + return rc; 3754 + } 3755 + 3738 3756 /* 3739 3757 * Release allocated space for a given range or an entire volume. 3740 3758 */ ··· 3771 3749 int cur_to_trk, cur_from_trk; 3772 3750 struct dasd_ccw_req *cqr; 3773 3751 u32 beg_cyl, end_cyl; 3752 + int copy_relation; 3774 3753 struct ccw1 *ccw; 3775 3754 int trks_per_ext; 3776 3755 size_t ras_size; ··· 3782 3759 3783 3760 if (dasd_eckd_ras_sanity_checks(device, first_trk, last_trk)) 3784 3761 return ERR_PTR(-EINVAL); 3762 + 3763 + copy_relation = dasd_in_copy_relation(device); 3764 + if (copy_relation < 0) 3765 + return ERR_PTR(copy_relation); 3785 3766 3786 3767 rq = req ? blk_mq_rq_to_pdu(req) : NULL; 3787 3768 ··· 3815 3788 /* 3816 3789 * This bit guarantees initialisation of tracks within an extent that is 3817 3790 * not fully specified, but is only supported with a certain feature 3818 - * subset. 3791 + * subset and for devices not in a copy relation. 3819 3792 */ 3820 - ras_data->op_flags.guarantee_init = !!(features->feature[56] & 0x01); 3793 + if (features->feature[56] & 0x01 && !copy_relation) 3794 + ras_data->op_flags.guarantee_init = 1; 3795 + 3821 3796 ras_data->lss = private->conf.ned->ID; 3822 3797 ras_data->dev_addr = private->conf.ned->unit_addr; 3823 3798 ras_data->nr_exts = nr_exts;
+2
drivers/s390/cio/device.c
··· 1111 1111 cdev = sch_get_cdev(sch); 1112 1112 if (cdev) 1113 1113 dev_fsm_event(cdev, DEV_EVENT_VERIFY); 1114 + else 1115 + css_schedule_eval(sch->schid); 1114 1116 } 1115 1117 1116 1118 static void io_subchannel_terminate_path(struct subchannel *sch, u8 mask)
+1 -1
drivers/s390/cio/qdio.h
··· 95 95 " lgr 1,%[token]\n" 96 96 " .insn rsy,0xeb000000008a,%[qs],%[ccq],0(%[state])" 97 97 : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart) 98 - : [state] "d" ((unsigned long)state), [token] "d" (token) 98 + : [state] "a" ((unsigned long)state), [token] "d" (token) 99 99 : "memory", "cc", "1"); 100 100 *count = _ccq & 0xff; 101 101 *start = _queuestart & 0xff;
+3
drivers/s390/crypto/pkey_api.c
··· 1293 1293 return PTR_ERR(kkey); 1294 1294 rc = pkey_keyblob2pkey(kkey, ktp.keylen, &ktp.protkey); 1295 1295 DEBUG_DBG("%s pkey_keyblob2pkey()=%d\n", __func__, rc); 1296 + memzero_explicit(kkey, ktp.keylen); 1296 1297 kfree(kkey); 1297 1298 if (rc) 1298 1299 break; ··· 1427 1426 kkey, ktp.keylen, &ktp.protkey); 1428 1427 DEBUG_DBG("%s pkey_keyblob2pkey2()=%d\n", __func__, rc); 1429 1428 kfree(apqns); 1429 + memzero_explicit(kkey, ktp.keylen); 1430 1430 kfree(kkey); 1431 1431 if (rc) 1432 1432 break; ··· 1554 1552 protkey, &protkeylen); 1555 1553 DEBUG_DBG("%s pkey_keyblob2pkey3()=%d\n", __func__, rc); 1556 1554 kfree(apqns); 1555 + memzero_explicit(kkey, ktp.keylen); 1557 1556 kfree(kkey); 1558 1557 if (rc) { 1559 1558 kfree(protkey);
+4 -1
drivers/scsi/scsi_lib.c
··· 1463 1463 struct Scsi_Host *host = cmd->device->host; 1464 1464 int rtn = 0; 1465 1465 1466 + atomic_inc(&cmd->device->iorequest_cnt); 1467 + 1466 1468 /* check if the device is still usable */ 1467 1469 if (unlikely(cmd->device->sdev_state == SDEV_DEL)) { 1468 1470 /* in SDEV_DEL we error all commands. DID_NO_CONNECT ··· 1485 1483 */ 1486 1484 SCSI_LOG_MLQUEUE(3, scmd_printk(KERN_INFO, cmd, 1487 1485 "queuecommand : device blocked\n")); 1486 + atomic_dec(&cmd->device->iorequest_cnt); 1488 1487 return SCSI_MLQUEUE_DEVICE_BUSY; 1489 1488 } 1490 1489 ··· 1518 1515 trace_scsi_dispatch_cmd_start(cmd); 1519 1516 rtn = host->hostt->queuecommand(host, cmd); 1520 1517 if (rtn) { 1518 + atomic_dec(&cmd->device->iorequest_cnt); 1521 1519 trace_scsi_dispatch_cmd_error(cmd, rtn); 1522 1520 if (rtn != SCSI_MLQUEUE_DEVICE_BUSY && 1523 1521 rtn != SCSI_MLQUEUE_TARGET_BUSY) ··· 1765 1761 goto out_dec_host_busy; 1766 1762 } 1767 1763 1768 - atomic_inc(&cmd->device->iorequest_cnt); 1769 1764 return BLK_STS_OK; 1770 1765 1771 1766 out_dec_host_busy:
+4 -4
drivers/scsi/storvsc_drv.c
··· 1780 1780 1781 1781 length = scsi_bufflen(scmnd); 1782 1782 payload = (struct vmbus_packet_mpb_array *)&cmd_request->mpb; 1783 - payload_sz = sizeof(cmd_request->mpb); 1783 + payload_sz = 0; 1784 1784 1785 1785 if (scsi_sg_count(scmnd)) { 1786 1786 unsigned long offset_in_hvpg = offset_in_hvpage(sgl->offset); ··· 1789 1789 unsigned long hvpfn, hvpfns_to_add; 1790 1790 int j, i = 0, sg_count; 1791 1791 1792 - if (hvpg_count > MAX_PAGE_BUFFER_COUNT) { 1792 + payload_sz = (hvpg_count * sizeof(u64) + 1793 + sizeof(struct vmbus_packet_mpb_array)); 1793 1794 1794 - payload_sz = (hvpg_count * sizeof(u64) + 1795 - sizeof(struct vmbus_packet_mpb_array)); 1795 + if (hvpg_count > MAX_PAGE_BUFFER_COUNT) { 1796 1796 payload = kzalloc(payload_sz, GFP_ATOMIC); 1797 1797 if (!payload) 1798 1798 return SCSI_MLQUEUE_DEVICE_BUSY;
+24 -5
drivers/thunderbolt/nhi.c
··· 54 54 return bit; 55 55 } 56 56 57 + static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring) 58 + { 59 + if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) 60 + return; 61 + iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); 62 + } 63 + 64 + static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring) 65 + { 66 + if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) 67 + ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring); 68 + else 69 + iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring); 70 + } 71 + 57 72 /* 58 73 * ring_interrupt_active() - activate/deactivate interrupts for a single ring 59 74 * ··· 76 61 */ 77 62 static void ring_interrupt_active(struct tb_ring *ring, bool active) 78 63 { 79 - int reg = REG_RING_INTERRUPT_BASE + 80 - ring_interrupt_index(ring) / 32 * 4; 64 + int index = ring_interrupt_index(ring) / 32 * 4; 65 + int reg = REG_RING_INTERRUPT_BASE + index; 81 66 int interrupt_bit = ring_interrupt_index(ring) & 31; 82 67 int mask = 1 << interrupt_bit; 83 68 u32 old, new; ··· 138 123 "interrupt for %s %d is already %s\n", 139 124 RING_TYPE(ring), ring->hop, 140 125 active ? "enabled" : "disabled"); 141 - iowrite32(new, ring->nhi->iobase + reg); 126 + 127 + if (active) 128 + iowrite32(new, ring->nhi->iobase + reg); 129 + else 130 + nhi_mask_interrupt(ring->nhi, mask, index); 142 131 } 143 132 144 133 /* ··· 155 136 int i = 0; 156 137 /* disable interrupts */ 157 138 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++) 158 - iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i); 139 + nhi_mask_interrupt(nhi, ~0, 4 * i); 159 140 160 141 /* clear interrupt status bits */ 161 142 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++) 162 - ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i); 143 + nhi_clear_interrupt(nhi, 4 * i); 163 144 } 164 145 165 146 /* ring helper methods */
+2
drivers/thunderbolt/nhi_regs.h
··· 93 93 #define REG_RING_INTERRUPT_BASE 0x38200 94 94 #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32) 95 95 96 + #define REG_RING_INTERRUPT_MASK_CLEAR_BASE 0x38208 97 + 96 98 #define REG_INT_THROTTLING_RATE 0x38c00 97 99 98 100 /* Interrupt Vector Allocation */
+5 -2
drivers/tty/serial/8250/8250_bcm7271.c
··· 1012 1012 of_property_read_u32(np, "clock-frequency", &clk_rate); 1013 1013 1014 1014 /* See if a Baud clock has been specified */ 1015 - baud_mux_clk = of_clk_get_by_name(np, "sw_baud"); 1015 + baud_mux_clk = devm_clk_get(dev, "sw_baud"); 1016 1016 if (IS_ERR(baud_mux_clk)) { 1017 1017 if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER) { 1018 1018 ret = -EPROBE_DEFER; ··· 1032 1032 if (clk_rate == 0) { 1033 1033 dev_err(dev, "clock-frequency or clk not defined\n"); 1034 1034 ret = -EINVAL; 1035 - goto release_dma; 1035 + goto err_clk_disable; 1036 1036 } 1037 1037 1038 1038 dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not "); ··· 1119 1119 serial8250_unregister_port(priv->line); 1120 1120 err: 1121 1121 brcmuart_free_bufs(dev, priv); 1122 + err_clk_disable: 1123 + clk_disable_unprepare(baud_mux_clk); 1122 1124 release_dma: 1123 1125 if (priv->dma_enabled) 1124 1126 brcmuart_arbitration(priv, 0); ··· 1135 1133 hrtimer_cancel(&priv->hrt); 1136 1134 serial8250_unregister_port(priv->line); 1137 1135 brcmuart_free_bufs(&pdev->dev, priv); 1136 + clk_disable_unprepare(priv->baud_mux_clk); 1138 1137 if (priv->dma_enabled) 1139 1138 brcmuart_arbitration(priv, 0); 1140 1139 return 0;
+17
drivers/tty/serial/8250/8250_exar.c
··· 40 40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 41 41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 42 42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 43 + 43 44 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 44 45 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 46 + 47 + #define PCI_SUBDEVICE_ID_USR_2980 0x0128 48 + #define PCI_SUBDEVICE_ID_USR_2981 0x0129 45 49 46 50 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001 47 51 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002 ··· 833 829 (kernel_ulong_t)&bd \ 834 830 } 835 831 832 + #define USR_DEVICE(devid, sdevid, bd) { \ 833 + PCI_DEVICE_SUB( \ 834 + PCI_VENDOR_ID_USR, \ 835 + PCI_DEVICE_ID_EXAR_##devid, \ 836 + PCI_VENDOR_ID_EXAR, \ 837 + PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \ 838 + (kernel_ulong_t)&bd \ 839 + } 840 + 836 841 static const struct pci_device_id exar_pci_tbl[] = { 837 842 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x), 838 843 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x), ··· 865 852 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), 866 853 867 854 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), 855 + 856 + /* USRobotics USR298x-OEM PCI Modems */ 857 + USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x), 858 + USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x), 868 859 869 860 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ 870 861 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
+5
drivers/tty/serial/8250/8250_pci.c
··· 1920 1920 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1921 1921 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1922 1922 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1923 + #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 1924 + #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 1923 1925 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1924 1926 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1925 1927 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 ··· 4087 4085 pciserial_resume_one); 4088 4086 4089 4087 static const struct pci_device_id serial_pci_tbl[] = { 4088 + { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4089 + PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4090 + pbn_b0_4_921600 }, 4090 4091 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4091 4092 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4092 4093 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
+1
drivers/tty/serial/8250/8250_port.c
··· 669 669 /** 670 670 * serial8250_em485_config() - generic ->rs485_config() callback 671 671 * @port: uart port 672 + * @termios: termios structure 672 673 * @rs485: rs485 settings 673 674 * 674 675 * Generic callback usable by 8250 uart drivers to activate rs485 settings
+4 -3
drivers/tty/serial/arc_uart.c
··· 606 606 } 607 607 uart->baud = val; 608 608 609 - port->membase = of_iomap(np, 0); 610 - if (!port->membase) 609 + port->membase = devm_platform_ioremap_resource(pdev, 0); 610 + if (IS_ERR(port->membase)) { 611 611 /* No point of dev_err since UART itself is hosed here */ 612 - return -ENXIO; 612 + return PTR_ERR(port->membase); 613 + } 613 614 614 615 port->irq = irq_of_parse_and_map(np, 0); 615 616
+4 -5
drivers/tty/serial/qcom_geni_serial.c
··· 1664 1664 uport->private_data = &port->private_data; 1665 1665 platform_set_drvdata(pdev, port); 1666 1666 1667 - ret = uart_add_one_port(drv, uport); 1668 - if (ret) 1669 - return ret; 1670 - 1671 1667 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1672 1668 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1673 1669 IRQF_TRIGGER_HIGH, port->name, uport); 1674 1670 if (ret) { 1675 1671 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1676 - uart_remove_one_port(drv, uport); 1677 1672 return ret; 1678 1673 } 1674 + 1675 + ret = uart_add_one_port(drv, uport); 1676 + if (ret) 1677 + return ret; 1679 1678 1680 1679 /* 1681 1680 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
+9 -2
drivers/tty/vt/vc_screen.c
··· 656 656 } 657 657 } 658 658 659 - /* The vcs_size might have changed while we slept to grab 660 - * the user buffer, so recheck. 659 + /* The vc might have been freed or vcs_size might have changed 660 + * while we slept to grab the user buffer, so recheck. 661 661 * Return data written up to now on failure. 662 662 */ 663 + vc = vcs_vc(inode, &viewed); 664 + if (!vc) { 665 + if (written) 666 + break; 667 + ret = -ENXIO; 668 + goto unlock_out; 669 + } 663 670 size = vcs_size(vc, attr, false); 664 671 if (size < 0) { 665 672 if (written)
+3 -2
drivers/ufs/core/ufs-mcq.c
··· 150 150 u32 hba_maxq, rem, tot_queues; 151 151 struct Scsi_Host *host = hba->host; 152 152 153 - hba_maxq = FIELD_GET(MAX_QUEUE_SUP, hba->mcq_capabilities); 153 + /* maxq is 0 based value */ 154 + hba_maxq = FIELD_GET(MAX_QUEUE_SUP, hba->mcq_capabilities) + 1; 154 155 155 156 tot_queues = UFS_MCQ_NUM_DEV_CMD_QUEUES + read_queues + poll_queues + 156 157 rw_queues; ··· 266 265 addr = (le64_to_cpu(cqe->command_desc_base_addr) & CQE_UCD_BA) - 267 266 hba->ucdl_dma_addr; 268 267 269 - return div_u64(addr, sizeof(struct utp_transfer_cmd_desc)); 268 + return div_u64(addr, ufshcd_get_ucd_size(hba)); 270 269 } 271 270 272 271 static void ufshcd_mcq_process_cqe(struct ufs_hba *hba,
+5 -5
drivers/ufs/core/ufshcd.c
··· 2849 2849 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2850 2850 { 2851 2851 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2852 - i * sizeof_utp_transfer_cmd_desc(hba); 2852 + i * ufshcd_get_ucd_size(hba); 2853 2853 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2854 2854 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2855 - i * sizeof_utp_transfer_cmd_desc(hba); 2855 + i * ufshcd_get_ucd_size(hba); 2856 2856 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2857 2857 response_upiu); 2858 2858 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); ··· 3761 3761 size_t utmrdl_size, utrdl_size, ucdl_size; 3762 3762 3763 3763 /* Allocate memory for UTP command descriptors */ 3764 - ucdl_size = sizeof_utp_transfer_cmd_desc(hba) * hba->nutrs; 3764 + ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3765 3765 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3766 3766 ucdl_size, 3767 3767 &hba->ucdl_dma_addr, ··· 3861 3861 prdt_offset = 3862 3862 offsetof(struct utp_transfer_cmd_desc, prd_table); 3863 3863 3864 - cmd_desc_size = sizeof_utp_transfer_cmd_desc(hba); 3864 + cmd_desc_size = ufshcd_get_ucd_size(hba); 3865 3865 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3866 3866 3867 3867 for (i = 0; i < hba->nutrs; i++) { ··· 8452 8452 { 8453 8453 size_t ucdl_size, utrdl_size; 8454 8454 8455 - ucdl_size = sizeof(struct utp_transfer_cmd_desc) * nutrs; 8455 + ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8456 8456 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8457 8457 hba->ucdl_dma_addr); 8458 8458
+2
drivers/usb/class/usbtmc.c
··· 1928 1928 1929 1929 if (request.req.wLength > USBTMC_BUFSIZE) 1930 1930 return -EMSGSIZE; 1931 + if (request.req.wLength == 0) /* Length-0 requests are never IN */ 1932 + request.req.bRequestType &= ~USB_DIR_IN; 1931 1933 1932 1934 is_in = request.req.bRequestType & USB_DIR_IN; 1933 1935
+1 -1
drivers/usb/dwc3/core.c
··· 1137 1137 1138 1138 dwc3_set_incr_burst_type(dwc); 1139 1139 1140 - dwc3_phy_power_on(dwc); 1140 + ret = dwc3_phy_power_on(dwc); 1141 1141 if (ret) 1142 1142 goto err_exit_phy; 1143 1143
+2
drivers/usb/dwc3/core.h
··· 1116 1116 * @dis_metastability_quirk: set to disable metastability quirk. 1117 1117 * @dis_split_quirk: set to disable split boundary. 1118 1118 * @wakeup_configured: set if the device is configured for remote wakeup. 1119 + * @suspended: set to track suspend event due to U3/L2. 1119 1120 * @imod_interval: set the interrupt moderation interval in 250ns 1120 1121 * increments or 0 to disable. 1121 1122 * @max_cfg_eps: current max number of IN eps used across all USB configs. ··· 1333 1332 unsigned dis_split_quirk:1; 1334 1333 unsigned async_callbacks:1; 1335 1334 unsigned wakeup_configured:1; 1335 + unsigned suspended:1; 1336 1336 1337 1337 u16 imod_interval; 1338 1338
+109
drivers/usb/dwc3/debugfs.c
··· 332 332 unsigned int current_mode; 333 333 unsigned long flags; 334 334 u32 reg; 335 + int ret; 336 + 337 + ret = pm_runtime_resume_and_get(dwc->dev); 338 + if (ret < 0) 339 + return ret; 335 340 336 341 spin_lock_irqsave(&dwc->lock, flags); 337 342 reg = dwc3_readl(dwc->regs, DWC3_GSTS); ··· 354 349 break; 355 350 } 356 351 spin_unlock_irqrestore(&dwc->lock, flags); 352 + 353 + pm_runtime_put_sync(dwc->dev); 357 354 358 355 return 0; 359 356 } ··· 402 395 struct dwc3 *dwc = s->private; 403 396 unsigned long flags; 404 397 u32 reg; 398 + int ret; 399 + 400 + ret = pm_runtime_resume_and_get(dwc->dev); 401 + if (ret < 0) 402 + return ret; 405 403 406 404 spin_lock_irqsave(&dwc->lock, flags); 407 405 reg = dwc3_readl(dwc->regs, DWC3_GCTL); ··· 425 413 default: 426 414 seq_printf(s, "UNKNOWN %08x\n", DWC3_GCTL_PRTCAP(reg)); 427 415 } 416 + 417 + pm_runtime_put_sync(dwc->dev); 428 418 429 419 return 0; 430 420 } ··· 477 463 struct dwc3 *dwc = s->private; 478 464 unsigned long flags; 479 465 u32 reg; 466 + int ret; 467 + 468 + ret = pm_runtime_resume_and_get(dwc->dev); 469 + if (ret < 0) 470 + return ret; 480 471 481 472 spin_lock_irqsave(&dwc->lock, flags); 482 473 reg = dwc3_readl(dwc->regs, DWC3_DCTL); ··· 512 493 seq_printf(s, "UNKNOWN %d\n", reg); 513 494 } 514 495 496 + pm_runtime_put_sync(dwc->dev); 497 + 515 498 return 0; 516 499 } 517 500 ··· 530 509 unsigned long flags; 531 510 u32 testmode = 0; 532 511 char buf[32]; 512 + int ret; 533 513 534 514 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) 535 515 return -EFAULT; ··· 548 526 else 549 527 testmode = 0; 550 528 529 + ret = pm_runtime_resume_and_get(dwc->dev); 530 + if (ret < 0) 531 + return ret; 532 + 551 533 spin_lock_irqsave(&dwc->lock, flags); 552 534 dwc3_gadget_set_test_mode(dwc, testmode); 553 535 spin_unlock_irqrestore(&dwc->lock, flags); 536 + 537 + pm_runtime_put_sync(dwc->dev); 554 538 555 539 return count; 556 540 } ··· 576 548 enum dwc3_link_state state; 577 549 u32 reg; 578 550 u8 speed; 551 + int ret; 552 + 553 + ret = pm_runtime_resume_and_get(dwc->dev); 554 + if (ret < 0) 555 + return ret; 579 556 580 557 spin_lock_irqsave(&dwc->lock, flags); 581 558 reg = dwc3_readl(dwc->regs, DWC3_GSTS); 582 559 if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) { 583 560 seq_puts(s, "Not available\n"); 584 561 spin_unlock_irqrestore(&dwc->lock, flags); 562 + pm_runtime_put_sync(dwc->dev); 585 563 return 0; 586 564 } 587 565 ··· 599 565 dwc3_gadget_link_string(state) : 600 566 dwc3_gadget_hs_link_string(state)); 601 567 spin_unlock_irqrestore(&dwc->lock, flags); 568 + 569 + pm_runtime_put_sync(dwc->dev); 602 570 603 571 return 0; 604 572 } ··· 620 584 char buf[32]; 621 585 u32 reg; 622 586 u8 speed; 587 + int ret; 623 588 624 589 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) 625 590 return -EFAULT; ··· 640 603 else 641 604 return -EINVAL; 642 605 606 + ret = pm_runtime_resume_and_get(dwc->dev); 607 + if (ret < 0) 608 + return ret; 609 + 643 610 spin_lock_irqsave(&dwc->lock, flags); 644 611 reg = dwc3_readl(dwc->regs, DWC3_GSTS); 645 612 if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) { 646 613 spin_unlock_irqrestore(&dwc->lock, flags); 614 + pm_runtime_put_sync(dwc->dev); 647 615 return -EINVAL; 648 616 } 649 617 ··· 658 616 if (speed < DWC3_DSTS_SUPERSPEED && 659 617 state != DWC3_LINK_STATE_RECOV) { 660 618 spin_unlock_irqrestore(&dwc->lock, flags); 619 + pm_runtime_put_sync(dwc->dev); 661 620 return -EINVAL; 662 621 } 663 622 664 623 dwc3_gadget_set_link_state(dwc, state); 665 624 spin_unlock_irqrestore(&dwc->lock, flags); 625 + 626 + pm_runtime_put_sync(dwc->dev); 666 627 667 628 return count; 668 629 } ··· 690 645 unsigned long flags; 691 646 u32 mdwidth; 692 647 u32 val; 648 + int ret; 649 + 650 + ret = pm_runtime_resume_and_get(dwc->dev); 651 + if (ret < 0) 652 + return ret; 693 653 694 654 spin_lock_irqsave(&dwc->lock, flags); 695 655 val = dwc3_core_fifo_space(dep, DWC3_TXFIFO); ··· 707 657 seq_printf(s, "%u\n", val); 708 658 spin_unlock_irqrestore(&dwc->lock, flags); 709 659 660 + pm_runtime_put_sync(dwc->dev); 661 + 710 662 return 0; 711 663 } 712 664 ··· 719 667 unsigned long flags; 720 668 u32 mdwidth; 721 669 u32 val; 670 + int ret; 671 + 672 + ret = pm_runtime_resume_and_get(dwc->dev); 673 + if (ret < 0) 674 + return ret; 722 675 723 676 spin_lock_irqsave(&dwc->lock, flags); 724 677 val = dwc3_core_fifo_space(dep, DWC3_RXFIFO); ··· 736 679 seq_printf(s, "%u\n", val); 737 680 spin_unlock_irqrestore(&dwc->lock, flags); 738 681 682 + pm_runtime_put_sync(dwc->dev); 683 + 739 684 return 0; 740 685 } 741 686 ··· 747 688 struct dwc3 *dwc = dep->dwc; 748 689 unsigned long flags; 749 690 u32 val; 691 + int ret; 692 + 693 + ret = pm_runtime_resume_and_get(dwc->dev); 694 + if (ret < 0) 695 + return ret; 750 696 751 697 spin_lock_irqsave(&dwc->lock, flags); 752 698 val = dwc3_core_fifo_space(dep, DWC3_TXREQQ); 753 699 seq_printf(s, "%u\n", val); 754 700 spin_unlock_irqrestore(&dwc->lock, flags); 701 + 702 + pm_runtime_put_sync(dwc->dev); 755 703 756 704 return 0; 757 705 } ··· 769 703 struct dwc3 *dwc = dep->dwc; 770 704 unsigned long flags; 771 705 u32 val; 706 + int ret; 707 + 708 + ret = pm_runtime_resume_and_get(dwc->dev); 709 + if (ret < 0) 710 + return ret; 772 711 773 712 spin_lock_irqsave(&dwc->lock, flags); 774 713 val = dwc3_core_fifo_space(dep, DWC3_RXREQQ); 775 714 seq_printf(s, "%u\n", val); 776 715 spin_unlock_irqrestore(&dwc->lock, flags); 716 + 717 + pm_runtime_put_sync(dwc->dev); 777 718 778 719 return 0; 779 720 } ··· 791 718 struct dwc3 *dwc = dep->dwc; 792 719 unsigned long flags; 793 720 u32 val; 721 + int ret; 722 + 723 + ret = pm_runtime_resume_and_get(dwc->dev); 724 + if (ret < 0) 725 + return ret; 794 726 795 727 spin_lock_irqsave(&dwc->lock, flags); 796 728 val = dwc3_core_fifo_space(dep, DWC3_RXINFOQ); 797 729 seq_printf(s, "%u\n", val); 798 730 spin_unlock_irqrestore(&dwc->lock, flags); 731 + 732 + pm_runtime_put_sync(dwc->dev); 799 733 800 734 return 0; 801 735 } ··· 813 733 struct dwc3 *dwc = dep->dwc; 814 734 unsigned long flags; 815 735 u32 val; 736 + int ret; 737 + 738 + ret = pm_runtime_resume_and_get(dwc->dev); 739 + if (ret < 0) 740 + return ret; 816 741 817 742 spin_lock_irqsave(&dwc->lock, flags); 818 743 val = dwc3_core_fifo_space(dep, DWC3_DESCFETCHQ); 819 744 seq_printf(s, "%u\n", val); 820 745 spin_unlock_irqrestore(&dwc->lock, flags); 746 + 747 + pm_runtime_put_sync(dwc->dev); 821 748 822 749 return 0; 823 750 } ··· 835 748 struct dwc3 *dwc = dep->dwc; 836 749 unsigned long flags; 837 750 u32 val; 751 + int ret; 752 + 753 + ret = pm_runtime_resume_and_get(dwc->dev); 754 + if (ret < 0) 755 + return ret; 838 756 839 757 spin_lock_irqsave(&dwc->lock, flags); 840 758 val = dwc3_core_fifo_space(dep, DWC3_EVENTQ); 841 759 seq_printf(s, "%u\n", val); 842 760 spin_unlock_irqrestore(&dwc->lock, flags); 761 + 762 + pm_runtime_put_sync(dwc->dev); 843 763 844 764 return 0; 845 765 } ··· 892 798 struct dwc3 *dwc = dep->dwc; 893 799 unsigned long flags; 894 800 int i; 801 + int ret; 802 + 803 + ret = pm_runtime_resume_and_get(dwc->dev); 804 + if (ret < 0) 805 + return ret; 895 806 896 807 spin_lock_irqsave(&dwc->lock, flags); 897 808 if (dep->number <= 1) { ··· 926 827 out: 927 828 spin_unlock_irqrestore(&dwc->lock, flags); 928 829 830 + pm_runtime_put_sync(dwc->dev); 831 + 929 832 return 0; 930 833 } 931 834 ··· 940 839 u32 lower_32_bits; 941 840 u32 upper_32_bits; 942 841 u32 reg; 842 + int ret; 843 + 844 + ret = pm_runtime_resume_and_get(dwc->dev); 845 + if (ret < 0) 846 + return ret; 943 847 944 848 spin_lock_irqsave(&dwc->lock, flags); 945 849 reg = DWC3_GDBGLSPMUX_EPSELECT(dep->number); ··· 956 850 ep_info = ((u64)upper_32_bits << 32) | lower_32_bits; 957 851 seq_printf(s, "0x%016llx\n", ep_info); 958 852 spin_unlock_irqrestore(&dwc->lock, flags); 853 + 854 + pm_runtime_put_sync(dwc->dev); 959 855 960 856 return 0; 961 857 } ··· 1018 910 dwc->regset->regs = dwc3_regs; 1019 911 dwc->regset->nregs = ARRAY_SIZE(dwc3_regs); 1020 912 dwc->regset->base = dwc->regs - DWC3_GLOBALS_REGS_START; 913 + dwc->regset->dev = dwc->dev; 1021 914 1022 915 root = debugfs_create_dir(dev_name(dwc->dev), usb_debug_root); 1023 916 dwc->debug_root = root;
+45 -34
drivers/usb/dwc3/gadget.c
··· 2440 2440 return -EINVAL; 2441 2441 } 2442 2442 dwc3_resume_gadget(dwc); 2443 + dwc->suspended = false; 2443 2444 dwc->link_state = DWC3_LINK_STATE_U0; 2444 2445 } 2445 2446 ··· 2700 2699 return ret; 2701 2700 } 2702 2701 2702 + static int dwc3_gadget_soft_connect(struct dwc3 *dwc) 2703 + { 2704 + /* 2705 + * In the Synopsys DWC_usb31 1.90a programming guide section 2706 + * 4.1.9, it specifies that for a reconnect after a 2707 + * device-initiated disconnect requires a core soft reset 2708 + * (DCTL.CSftRst) before enabling the run/stop bit. 2709 + */ 2710 + dwc3_core_soft_reset(dwc); 2711 + 2712 + dwc3_event_buffers_setup(dwc); 2713 + __dwc3_gadget_start(dwc); 2714 + return dwc3_gadget_run_stop(dwc, true); 2715 + } 2716 + 2703 2717 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 2704 2718 { 2705 2719 struct dwc3 *dwc = gadget_to_dwc(g); ··· 2753 2737 2754 2738 synchronize_irq(dwc->irq_gadget); 2755 2739 2756 - if (!is_on) { 2740 + if (!is_on) 2757 2741 ret = dwc3_gadget_soft_disconnect(dwc); 2758 - } else { 2759 - /* 2760 - * In the Synopsys DWC_usb31 1.90a programming guide section 2761 - * 4.1.9, it specifies that for a reconnect after a 2762 - * device-initiated disconnect requires a core soft reset 2763 - * (DCTL.CSftRst) before enabling the run/stop bit. 2764 - */ 2765 - dwc3_core_soft_reset(dwc); 2766 - 2767 - dwc3_event_buffers_setup(dwc); 2768 - __dwc3_gadget_start(dwc); 2769 - ret = dwc3_gadget_run_stop(dwc, true); 2770 - } 2742 + else 2743 + ret = dwc3_gadget_soft_connect(dwc); 2771 2744 2772 2745 pm_runtime_put(dwc->dev); 2773 2746 ··· 3943 3938 { 3944 3939 int reg; 3945 3940 3941 + dwc->suspended = false; 3942 + 3946 3943 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); 3947 3944 3948 3945 reg = dwc3_readl(dwc->regs, DWC3_DCTL); ··· 3968 3961 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 3969 3962 { 3970 3963 u32 reg; 3964 + 3965 + dwc->suspended = false; 3971 3966 3972 3967 /* 3973 3968 * Ideally, dwc3_reset_gadget() would trigger the function ··· 4189 4180 4190 4181 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo) 4191 4182 { 4183 + dwc->suspended = false; 4184 + 4192 4185 /* 4193 4186 * TODO take core out of low power mode when that's 4194 4187 * implemented. ··· 4288 4277 if (dwc->gadget->wakeup_armed) { 4289 4278 dwc3_gadget_enable_linksts_evts(dwc, false); 4290 4279 dwc3_resume_gadget(dwc); 4280 + dwc->suspended = false; 4291 4281 } 4292 4282 break; 4293 4283 case DWC3_LINK_STATE_U1: ··· 4315 4303 { 4316 4304 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 4317 4305 4318 - if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) 4306 + if (!dwc->suspended && next == DWC3_LINK_STATE_U3) { 4307 + dwc->suspended = true; 4319 4308 dwc3_suspend_gadget(dwc); 4309 + } 4320 4310 4321 4311 dwc->link_state = next; 4322 4312 } ··· 4669 4655 int dwc3_gadget_suspend(struct dwc3 *dwc) 4670 4656 { 4671 4657 unsigned long flags; 4658 + int ret; 4672 4659 4673 4660 if (!dwc->gadget_driver) 4674 4661 return 0; 4675 4662 4676 - dwc3_gadget_run_stop(dwc, false); 4663 + ret = dwc3_gadget_soft_disconnect(dwc); 4664 + if (ret) 4665 + goto err; 4677 4666 4678 4667 spin_lock_irqsave(&dwc->lock, flags); 4679 4668 dwc3_disconnect_gadget(dwc); 4680 - __dwc3_gadget_stop(dwc); 4681 4669 spin_unlock_irqrestore(&dwc->lock, flags); 4682 4670 4683 4671 return 0; 4672 + 4673 + err: 4674 + /* 4675 + * Attempt to reset the controller's state. Likely no 4676 + * communication can be established until the host 4677 + * performs a port reset. 4678 + */ 4679 + if (dwc->softconnect) 4680 + dwc3_gadget_soft_connect(dwc); 4681 + 4682 + return ret; 4684 4683 } 4685 4684 4686 4685 int dwc3_gadget_resume(struct dwc3 *dwc) 4687 4686 { 4688 - int ret; 4689 - 4690 4687 if (!dwc->gadget_driver || !dwc->softconnect) 4691 4688 return 0; 4692 4689 4693 - ret = __dwc3_gadget_start(dwc); 4694 - if (ret < 0) 4695 - goto err0; 4696 - 4697 - ret = dwc3_gadget_run_stop(dwc, true); 4698 - if (ret < 0) 4699 - goto err1; 4700 - 4701 - return 0; 4702 - 4703 - err1: 4704 - __dwc3_gadget_stop(dwc); 4705 - 4706 - err0: 4707 - return ret; 4690 + return dwc3_gadget_soft_connect(dwc); 4708 4691 } 4709 4692 4710 4693 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
+3
drivers/usb/gadget/function/u_ether.c
··· 17 17 #include <linux/etherdevice.h> 18 18 #include <linux/ethtool.h> 19 19 #include <linux/if_vlan.h> 20 + #include <linux/string_helpers.h> 20 21 #include <linux/usb/composite.h> 21 22 22 23 #include "u_ether.h" ··· 965 964 966 965 dev = netdev_priv(net); 967 966 snprintf(host_addr, len, "%pm", dev->host_mac); 967 + 968 + string_upper(host_addr, host_addr); 968 969 969 970 return strlen(host_addr); 970 971 }
+62 -125
drivers/usb/gadget/udc/core.c
··· 37 37 * @vbus: for udcs who care about vbus status, this value is real vbus status; 38 38 * for udcs who do not care about vbus status, this value is always true 39 39 * @started: the UDC's started state. True if the UDC had started. 40 - * @connect_lock: protects udc->vbus, udc->started, gadget->connect, gadget->deactivate related 41 - * functions. usb_gadget_connect_locked, usb_gadget_disconnect_locked, 42 - * usb_udc_connect_control_locked, usb_gadget_udc_start_locked, usb_gadget_udc_stop_locked are 43 - * called with this lock held. 44 40 * 45 41 * This represents the internal data structure which is used by the UDC-class 46 42 * to hold information about udc driver and gadget together. ··· 48 52 struct list_head list; 49 53 bool vbus; 50 54 bool started; 51 - struct mutex connect_lock; 52 55 }; 53 56 54 57 static struct class *udc_class; ··· 687 692 } 688 693 EXPORT_SYMBOL_GPL(usb_gadget_vbus_disconnect); 689 694 690 - /* Internal version of usb_gadget_connect needs to be called with connect_lock held. */ 691 - static int usb_gadget_connect_locked(struct usb_gadget *gadget) 692 - __must_hold(&gadget->udc->connect_lock) 695 + /** 696 + * usb_gadget_connect - software-controlled connect to USB host 697 + * @gadget:the peripheral being connected 698 + * 699 + * Enables the D+ (or potentially D-) pullup. The host will start 700 + * enumerating this gadget when the pullup is active and a VBUS session 701 + * is active (the link is powered). 702 + * 703 + * Returns zero on success, else negative errno. 704 + */ 705 + int usb_gadget_connect(struct usb_gadget *gadget) 693 706 { 694 707 int ret = 0; 695 708 ··· 706 703 goto out; 707 704 } 708 705 709 - if (gadget->connected) 710 - goto out; 711 - 712 - if (gadget->deactivated || !gadget->udc->started) { 706 + if (gadget->deactivated) { 713 707 /* 714 708 * If gadget is deactivated we only save new state. 715 709 * Gadget will be connected automatically after activation. 716 - * 717 - * udc first needs to be started before gadget can be pulled up. 718 710 */ 719 711 gadget->connected = true; 720 712 goto out; ··· 724 726 725 727 return ret; 726 728 } 727 - 728 - /** 729 - * usb_gadget_connect - software-controlled connect to USB host 730 - * @gadget:the peripheral being connected 731 - * 732 - * Enables the D+ (or potentially D-) pullup. The host will start 733 - * enumerating this gadget when the pullup is active and a VBUS session 734 - * is active (the link is powered). 735 - * 736 - * Returns zero on success, else negative errno. 737 - */ 738 - int usb_gadget_connect(struct usb_gadget *gadget) 739 - { 740 - int ret; 741 - 742 - mutex_lock(&gadget->udc->connect_lock); 743 - ret = usb_gadget_connect_locked(gadget); 744 - mutex_unlock(&gadget->udc->connect_lock); 745 - 746 - return ret; 747 - } 748 729 EXPORT_SYMBOL_GPL(usb_gadget_connect); 749 - 750 - /* Internal version of usb_gadget_disconnect needs to be called with connect_lock held. */ 751 - static int usb_gadget_disconnect_locked(struct usb_gadget *gadget) 752 - __must_hold(&gadget->udc->connect_lock) 753 - { 754 - int ret = 0; 755 - 756 - if (!gadget->ops->pullup) { 757 - ret = -EOPNOTSUPP; 758 - goto out; 759 - } 760 - 761 - if (!gadget->connected) 762 - goto out; 763 - 764 - if (gadget->deactivated || !gadget->udc->started) { 765 - /* 766 - * If gadget is deactivated we only save new state. 767 - * Gadget will stay disconnected after activation. 768 - * 769 - * udc should have been started before gadget being pulled down. 770 - */ 771 - gadget->connected = false; 772 - goto out; 773 - } 774 - 775 - ret = gadget->ops->pullup(gadget, 0); 776 - if (!ret) 777 - gadget->connected = 0; 778 - 779 - mutex_lock(&udc_lock); 780 - if (gadget->udc->driver) 781 - gadget->udc->driver->disconnect(gadget); 782 - mutex_unlock(&udc_lock); 783 - 784 - out: 785 - trace_usb_gadget_disconnect(gadget, ret); 786 - 787 - return ret; 788 - } 789 730 790 731 /** 791 732 * usb_gadget_disconnect - software-controlled disconnect from USB host ··· 741 804 */ 742 805 int usb_gadget_disconnect(struct usb_gadget *gadget) 743 806 { 744 - int ret; 807 + int ret = 0; 745 808 746 - mutex_lock(&gadget->udc->connect_lock); 747 - ret = usb_gadget_disconnect_locked(gadget); 748 - mutex_unlock(&gadget->udc->connect_lock); 809 + if (!gadget->ops->pullup) { 810 + ret = -EOPNOTSUPP; 811 + goto out; 812 + } 813 + 814 + if (!gadget->connected) 815 + goto out; 816 + 817 + if (gadget->deactivated) { 818 + /* 819 + * If gadget is deactivated we only save new state. 820 + * Gadget will stay disconnected after activation. 821 + */ 822 + gadget->connected = false; 823 + goto out; 824 + } 825 + 826 + ret = gadget->ops->pullup(gadget, 0); 827 + if (!ret) 828 + gadget->connected = 0; 829 + 830 + mutex_lock(&udc_lock); 831 + if (gadget->udc->driver) 832 + gadget->udc->driver->disconnect(gadget); 833 + mutex_unlock(&udc_lock); 834 + 835 + out: 836 + trace_usb_gadget_disconnect(gadget, ret); 749 837 750 838 return ret; 751 839 } ··· 794 832 if (gadget->deactivated) 795 833 goto out; 796 834 797 - mutex_lock(&gadget->udc->connect_lock); 798 835 if (gadget->connected) { 799 - ret = usb_gadget_disconnect_locked(gadget); 836 + ret = usb_gadget_disconnect(gadget); 800 837 if (ret) 801 - goto unlock; 838 + goto out; 802 839 803 840 /* 804 841 * If gadget was being connected before deactivation, we want ··· 807 846 } 808 847 gadget->deactivated = true; 809 848 810 - unlock: 811 - mutex_unlock(&gadget->udc->connect_lock); 812 849 out: 813 850 trace_usb_gadget_deactivate(gadget, ret); 814 851 ··· 830 871 if (!gadget->deactivated) 831 872 goto out; 832 873 833 - mutex_lock(&gadget->udc->connect_lock); 834 874 gadget->deactivated = false; 835 875 836 876 /* ··· 837 879 * while it was being deactivated, we call usb_gadget_connect(). 838 880 */ 839 881 if (gadget->connected) 840 - ret = usb_gadget_connect_locked(gadget); 841 - mutex_unlock(&gadget->udc->connect_lock); 882 + ret = usb_gadget_connect(gadget); 842 883 843 884 out: 844 885 trace_usb_gadget_activate(gadget, ret); ··· 1078 1121 1079 1122 /* ------------------------------------------------------------------------- */ 1080 1123 1081 - /* Acquire connect_lock before calling this function. */ 1082 - static void usb_udc_connect_control_locked(struct usb_udc *udc) __must_hold(&udc->connect_lock) 1124 + static void usb_udc_connect_control(struct usb_udc *udc) 1083 1125 { 1084 - if (udc->vbus && udc->started) 1085 - usb_gadget_connect_locked(udc->gadget); 1126 + if (udc->vbus) 1127 + usb_gadget_connect(udc->gadget); 1086 1128 else 1087 - usb_gadget_disconnect_locked(udc->gadget); 1129 + usb_gadget_disconnect(udc->gadget); 1088 1130 } 1089 1131 1090 1132 /** ··· 1099 1143 { 1100 1144 struct usb_udc *udc = gadget->udc; 1101 1145 1102 - mutex_lock(&udc->connect_lock); 1103 1146 if (udc) { 1104 1147 udc->vbus = status; 1105 - usb_udc_connect_control_locked(udc); 1148 + usb_udc_connect_control(udc); 1106 1149 } 1107 - mutex_unlock(&udc->connect_lock); 1108 1150 } 1109 1151 EXPORT_SYMBOL_GPL(usb_udc_vbus_handler); 1110 1152 ··· 1124 1170 EXPORT_SYMBOL_GPL(usb_gadget_udc_reset); 1125 1171 1126 1172 /** 1127 - * usb_gadget_udc_start_locked - tells usb device controller to start up 1173 + * usb_gadget_udc_start - tells usb device controller to start up 1128 1174 * @udc: The UDC to be started 1129 1175 * 1130 1176 * This call is issued by the UDC Class driver when it's about ··· 1135 1181 * necessary to have it powered on. 1136 1182 * 1137 1183 * Returns zero on success, else negative errno. 1138 - * 1139 - * Caller should acquire connect_lock before invoking this function. 1140 1184 */ 1141 - static inline int usb_gadget_udc_start_locked(struct usb_udc *udc) 1142 - __must_hold(&udc->connect_lock) 1185 + static inline int usb_gadget_udc_start(struct usb_udc *udc) 1143 1186 { 1144 1187 int ret; 1145 1188 ··· 1153 1202 } 1154 1203 1155 1204 /** 1156 - * usb_gadget_udc_stop_locked - tells usb device controller we don't need it anymore 1205 + * usb_gadget_udc_stop - tells usb device controller we don't need it anymore 1157 1206 * @udc: The UDC to be stopped 1158 1207 * 1159 1208 * This call is issued by the UDC Class driver after calling ··· 1162 1211 * The details are implementation specific, but it can go as 1163 1212 * far as powering off UDC completely and disable its data 1164 1213 * line pullups. 1165 - * 1166 - * Caller should acquire connect lock before invoking this function. 1167 1214 */ 1168 - static inline void usb_gadget_udc_stop_locked(struct usb_udc *udc) 1169 - __must_hold(&udc->connect_lock) 1215 + static inline void usb_gadget_udc_stop(struct usb_udc *udc) 1170 1216 { 1171 1217 if (!udc->started) { 1172 1218 dev_err(&udc->dev, "UDC had already stopped\n"); ··· 1322 1374 1323 1375 udc->gadget = gadget; 1324 1376 gadget->udc = udc; 1325 - mutex_init(&udc->connect_lock); 1326 1377 1327 1378 udc->started = false; 1328 1379 ··· 1523 1576 if (ret) 1524 1577 goto err_bind; 1525 1578 1526 - mutex_lock(&udc->connect_lock); 1527 - ret = usb_gadget_udc_start_locked(udc); 1528 - if (ret) { 1529 - mutex_unlock(&udc->connect_lock); 1579 + ret = usb_gadget_udc_start(udc); 1580 + if (ret) 1530 1581 goto err_start; 1531 - } 1532 1582 usb_gadget_enable_async_callbacks(udc); 1533 - usb_udc_connect_control_locked(udc); 1534 - mutex_unlock(&udc->connect_lock); 1583 + usb_udc_connect_control(udc); 1535 1584 1536 1585 kobject_uevent(&udc->dev.kobj, KOBJ_CHANGE); 1537 1586 return 0; ··· 1558 1615 1559 1616 kobject_uevent(&udc->dev.kobj, KOBJ_CHANGE); 1560 1617 1561 - mutex_lock(&udc->connect_lock); 1562 - usb_gadget_disconnect_locked(gadget); 1618 + usb_gadget_disconnect(gadget); 1563 1619 usb_gadget_disable_async_callbacks(udc); 1564 1620 if (gadget->irq) 1565 1621 synchronize_irq(gadget->irq); 1566 1622 udc->driver->unbind(gadget); 1567 - usb_gadget_udc_stop_locked(udc); 1568 - mutex_unlock(&udc->connect_lock); 1623 + usb_gadget_udc_stop(udc); 1569 1624 1570 1625 mutex_lock(&udc_lock); 1571 1626 driver->is_bound = false; ··· 1649 1708 } 1650 1709 1651 1710 if (sysfs_streq(buf, "connect")) { 1652 - mutex_lock(&udc->connect_lock); 1653 - usb_gadget_udc_start_locked(udc); 1654 - usb_gadget_connect_locked(udc->gadget); 1655 - mutex_unlock(&udc->connect_lock); 1711 + usb_gadget_udc_start(udc); 1712 + usb_gadget_connect(udc->gadget); 1656 1713 } else if (sysfs_streq(buf, "disconnect")) { 1657 - mutex_lock(&udc->connect_lock); 1658 - usb_gadget_disconnect_locked(udc->gadget); 1659 - usb_gadget_udc_stop_locked(udc); 1660 - mutex_unlock(&udc->connect_lock); 1714 + usb_gadget_disconnect(udc->gadget); 1715 + usb_gadget_udc_stop(udc); 1661 1716 } else { 1662 1717 dev_err(dev, "unsupported command '%s'\n", buf); 1663 1718 ret = -EINVAL;
+6 -4
drivers/usb/host/uhci-pci.c
··· 119 119 120 120 uhci->rh_numports = uhci_count_ports(hcd); 121 121 122 - /* Intel controllers report the OverCurrent bit active on. 123 - * VIA controllers report it active off, so we'll adjust the 124 - * bit value. (It's not standardized in the UHCI spec.) 122 + /* 123 + * Intel controllers report the OverCurrent bit active on. VIA 124 + * and ZHAOXIN controllers report it active off, so we'll adjust 125 + * the bit value. (It's not standardized in the UHCI spec.) 125 126 */ 126 - if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_VIA) 127 + if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_VIA || 128 + to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_ZHAOXIN) 127 129 uhci->oc_low = 1; 128 130 129 131 /* HP's server management chip requires a longer port reset delay. */
+10 -2
drivers/usb/host/xhci-pci.c
··· 13 13 #include <linux/module.h> 14 14 #include <linux/acpi.h> 15 15 #include <linux/reset.h> 16 + #include <linux/suspend.h> 16 17 17 18 #include "xhci.h" 18 19 #include "xhci-trace.h" ··· 388 387 389 388 if (pdev->vendor == PCI_VENDOR_ID_AMD && 390 389 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 391 - xhci->quirks |= XHCI_BROKEN_D3COLD; 390 + xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 392 391 393 392 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 394 393 xhci->quirks |= XHCI_LPM_SUPPORT; ··· 802 801 * Systems with the TI redriver that loses port status change events 803 802 * need to have the registers polled during D3, so avoid D3cold. 804 803 */ 805 - if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 804 + if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 806 805 pci_d3cold_disable(pdev); 806 + 807 + #ifdef CONFIG_SUSPEND 808 + /* d3cold is broken, but only when s2idle is used */ 809 + if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 810 + xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 811 + pci_d3cold_disable(pdev); 812 + #endif 807 813 808 814 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 809 815 xhci_pme_quirk(hcd);
+28 -1
drivers/usb/host/xhci-ring.c
··· 276 276 trace_xhci_inc_enq(ring); 277 277 } 278 278 279 + static int xhci_num_trbs_to(struct xhci_segment *start_seg, union xhci_trb *start, 280 + struct xhci_segment *end_seg, union xhci_trb *end, 281 + unsigned int num_segs) 282 + { 283 + union xhci_trb *last_on_seg; 284 + int num = 0; 285 + int i = 0; 286 + 287 + do { 288 + if (start_seg == end_seg && end >= start) 289 + return num + (end - start); 290 + last_on_seg = &start_seg->trbs[TRBS_PER_SEGMENT - 1]; 291 + num += last_on_seg - start; 292 + start_seg = start_seg->next; 293 + start = start_seg->trbs; 294 + } while (i++ <= num_segs); 295 + 296 + return -EINVAL; 297 + } 298 + 279 299 /* 280 300 * Check to see if there's room to enqueue num_trbs on the ring and make sure 281 301 * enqueue pointer will not advance into dequeue segment. See rules above. ··· 2160 2140 u32 trb_comp_code) 2161 2141 { 2162 2142 struct xhci_ep_ctx *ep_ctx; 2143 + int trbs_freed; 2163 2144 2164 2145 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); 2165 2146 ··· 2230 2209 } 2231 2210 2232 2211 /* Update ring dequeue pointer */ 2212 + trbs_freed = xhci_num_trbs_to(ep_ring->deq_seg, ep_ring->dequeue, 2213 + td->last_trb_seg, td->last_trb, 2214 + ep_ring->num_segs); 2215 + if (trbs_freed < 0) 2216 + xhci_dbg(xhci, "Failed to count freed trbs at TD finish\n"); 2217 + else 2218 + ep_ring->num_trbs_free += trbs_freed; 2233 2219 ep_ring->dequeue = td->last_trb; 2234 2220 ep_ring->deq_seg = td->last_trb_seg; 2235 - ep_ring->num_trbs_free += td->num_trbs - 1; 2236 2221 inc_deq(xhci, ep_ring); 2237 2222 2238 2223 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
+1 -1
drivers/usb/host/xhci.h
··· 1901 1901 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1902 1902 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1903 1903 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1904 - #define XHCI_BROKEN_D3COLD BIT_ULL(41) 1904 + #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1905 1905 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1906 1906 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1907 1907 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
+21 -7
drivers/usb/storage/scsiglue.c
··· 406 406 ***********************************************************************/ 407 407 408 408 /* Command timeout and abort */ 409 - static int command_abort(struct scsi_cmnd *srb) 409 + static int command_abort_matching(struct us_data *us, struct scsi_cmnd *srb_match) 410 410 { 411 - struct us_data *us = host_to_us(srb->device->host); 412 - 413 - usb_stor_dbg(us, "%s called\n", __func__); 414 - 415 411 /* 416 412 * us->srb together with the TIMED_OUT, RESETTING, and ABORTING 417 413 * bits are protected by the host lock. 418 414 */ 419 415 scsi_lock(us_to_host(us)); 420 416 421 - /* Is this command still active? */ 422 - if (us->srb != srb) { 417 + /* is there any active pending command to abort ? */ 418 + if (!us->srb) { 423 419 scsi_unlock(us_to_host(us)); 424 420 usb_stor_dbg(us, "-- nothing to abort\n"); 421 + return SUCCESS; 422 + } 423 + 424 + /* Does the command match the passed srb if any ? */ 425 + if (srb_match && us->srb != srb_match) { 426 + scsi_unlock(us_to_host(us)); 427 + usb_stor_dbg(us, "-- pending command mismatch\n"); 425 428 return FAILED; 426 429 } 427 430 ··· 447 444 return SUCCESS; 448 445 } 449 446 447 + static int command_abort(struct scsi_cmnd *srb) 448 + { 449 + struct us_data *us = host_to_us(srb->device->host); 450 + 451 + usb_stor_dbg(us, "%s called\n", __func__); 452 + return command_abort_matching(us, srb); 453 + } 454 + 450 455 /* 451 456 * This invokes the transport reset mechanism to reset the state of the 452 457 * device ··· 465 454 int result; 466 455 467 456 usb_stor_dbg(us, "%s called\n", __func__); 457 + 458 + /* abort any pending command before reset */ 459 + command_abort_matching(us, NULL); 468 460 469 461 /* lock the device pointers and do the reset */ 470 462 mutex_lock(&(us->dev_mutex));
+4
drivers/usb/typec/altmodes/displayport.c
··· 516 516 517 517 mutex_unlock(&dp->lock); 518 518 519 + /* get_current_pin_assignments can return 0 when no matching pin assignments are found */ 520 + if (len == 0) 521 + len++; 522 + 519 523 buf[len - 1] = '\n'; 520 524 return len; 521 525 }
+3
drivers/usb/typec/tipd/core.c
··· 886 886 { 887 887 struct tps6598x *tps = i2c_get_clientdata(client); 888 888 889 + if (!client->irq) 890 + cancel_delayed_work_sync(&tps->wq_poll); 891 + 889 892 tps6598x_disconnect(tps, 0); 890 893 typec_unregister_port(tps->port); 891 894 usb_role_switch_put(tps->role_sw);
+1 -1
drivers/video/fbdev/Kconfig
··· 124 124 depends on FB 125 125 help 126 126 Allow generic frame-buffer to provide get_fb_unmapped_area 127 - function. 127 + function to provide shareable character device support on nommu. 128 128 129 129 menuconfig FB_FOREIGN_ENDIAN 130 130 bool "Framebuffer foreign endianness support"
-5
drivers/video/fbdev/aty/atyfb_base.c
··· 3498 3498 if (ret) 3499 3499 goto atyfb_setup_generic_fail; 3500 3500 #endif 3501 - if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN)) 3502 - par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2; 3503 - else 3504 - par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U; 3505 - 3506 3501 /* according to ATI, we should use clock 3 for acelerated mode */ 3507 3502 par->clk_wr_offset = 3; 3508 3503
+1 -1
drivers/video/fbdev/core/fbmem.c
··· 1468 1468 } 1469 1469 1470 1470 #if defined(CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA) && !defined(CONFIG_MMU) 1471 - unsigned long get_fb_unmapped_area(struct file *filp, 1471 + static unsigned long get_fb_unmapped_area(struct file *filp, 1472 1472 unsigned long addr, unsigned long len, 1473 1473 unsigned long pgoff, unsigned long flags) 1474 1474 {
+2 -1
drivers/video/fbdev/i810/i810_dvt.c
··· 14 14 15 15 #include "i810_regs.h" 16 16 #include "i810.h" 17 + #include "i810_main.h" 17 18 18 19 struct mode_registers std_modes[] = { 19 20 /* 640x480 @ 60Hz */ ··· 277 276 var->upper_margin = total - (yres + var->lower_margin + var->vsync_len); 278 277 } 279 278 280 - u32 i810_get_watermark(struct fb_var_screeninfo *var, 279 + u32 i810_get_watermark(const struct fb_var_screeninfo *var, 281 280 struct i810fb_par *par) 282 281 { 283 282 struct mode_registers *params = &par->regs;
+2 -1
drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c
··· 491 491 492 492 ddata->vcc_reg = devm_regulator_get(&spi->dev, "vcc"); 493 493 if (IS_ERR(ddata->vcc_reg)) { 494 - r = dev_err_probe(&spi->dev, r, "failed to get LCD VCC regulator\n"); 494 + r = dev_err_probe(&spi->dev, PTR_ERR(ddata->vcc_reg), 495 + "failed to get LCD VCC regulator\n"); 495 496 goto err_regulator; 496 497 } 497 498
+3 -3
drivers/video/fbdev/stifb.c
··· 741 741 packed_len = (fb->info.var.xres << 16) | fb->info.var.yres; 742 742 NGLE_SET_DSTXY(fb, packed_dst); 743 743 744 - /* Write zeroes to overlay planes */ 744 + /* Write zeroes to overlay planes */ 745 745 NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb, 746 746 IBOvals(RopSrc, MaskAddrOffset(0), 747 747 BitmapExtent08, StaticReg(0), ··· 1297 1297 break; 1298 1298 default: 1299 1299 #ifdef FALLBACK_TO_1BPP 1300 - printk(KERN_WARNING 1300 + printk(KERN_WARNING 1301 1301 "stifb: Unsupported graphics card (id=0x%08x) " 1302 1302 "- now trying 1bpp mode instead\n", 1303 1303 fb->id); 1304 1304 bpp = 1; /* default to 1 bpp */ 1305 1305 break; 1306 1306 #else 1307 - printk(KERN_WARNING 1307 + printk(KERN_WARNING 1308 1308 "stifb: Unsupported graphics card (id=0x%08x) " 1309 1309 "- skipping.\n", 1310 1310 fb->id);
+11 -16
drivers/video/fbdev/udlfb.c
··· 27 27 #include <video/udlfb.h> 28 28 #include "edid.h" 29 29 30 + #define OUT_EP_NUM 1 /* The endpoint number we will use */ 31 + 30 32 static const struct fb_fix_screeninfo dlfb_fix = { 31 33 .id = "udlfb", 32 34 .type = FB_TYPE_PACKED_PIXELS, ··· 1543 1541 static int dlfb_select_std_channel(struct dlfb_data *dlfb) 1544 1542 { 1545 1543 int ret; 1546 - void *buf; 1547 1544 static const u8 set_def_chn[] = { 1548 1545 0x57, 0xCD, 0xDC, 0xA7, 1549 1546 0x1C, 0x88, 0x5E, 0x15, 1550 1547 0x60, 0xFE, 0xC6, 0x97, 1551 1548 0x16, 0x3D, 0x47, 0xF2 }; 1552 1549 1553 - buf = kmemdup(set_def_chn, sizeof(set_def_chn), GFP_KERNEL); 1554 - 1555 - if (!buf) 1556 - return -ENOMEM; 1557 - 1558 - ret = usb_control_msg(dlfb->udev, usb_sndctrlpipe(dlfb->udev, 0), 1559 - NR_USB_REQUEST_CHANNEL, 1550 + ret = usb_control_msg_send(dlfb->udev, 0, NR_USB_REQUEST_CHANNEL, 1560 1551 (USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0, 1561 - buf, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT); 1562 - 1563 - kfree(buf); 1552 + &set_def_chn, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT, 1553 + GFP_KERNEL); 1564 1554 1565 1555 return ret; 1566 1556 } ··· 1646 1652 struct fb_info *info; 1647 1653 int retval; 1648 1654 struct usb_device *usbdev = interface_to_usbdev(intf); 1649 - struct usb_endpoint_descriptor *out; 1655 + static u8 out_ep[] = {OUT_EP_NUM + USB_DIR_OUT, 0}; 1650 1656 1651 1657 /* usb initialization */ 1652 1658 dlfb = kzalloc(sizeof(*dlfb), GFP_KERNEL); ··· 1660 1666 dlfb->udev = usb_get_dev(usbdev); 1661 1667 usb_set_intfdata(intf, dlfb); 1662 1668 1663 - retval = usb_find_common_endpoints(intf->cur_altsetting, NULL, &out, NULL, NULL); 1664 - if (retval) { 1665 - dev_err(&intf->dev, "Device should have at lease 1 bulk endpoint!\n"); 1669 + if (!usb_check_bulk_endpoints(intf, out_ep)) { 1670 + dev_err(&intf->dev, "Invalid DisplayLink device!\n"); 1671 + retval = -EINVAL; 1666 1672 goto error; 1667 1673 } 1668 1674 ··· 1921 1927 } 1922 1928 1923 1929 /* urb->transfer_buffer_length set to actual before submit */ 1924 - usb_fill_bulk_urb(urb, dlfb->udev, usb_sndbulkpipe(dlfb->udev, 1), 1930 + usb_fill_bulk_urb(urb, dlfb->udev, 1931 + usb_sndbulkpipe(dlfb->udev, OUT_EP_NUM), 1925 1932 buf, size, dlfb_urb_completion, unode); 1926 1933 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; 1927 1934
+2 -1
fs/ceph/mds_client.c
··· 3942 3942 struct dentry *dentry; 3943 3943 struct ceph_cap *cap; 3944 3944 char *path; 3945 - int pathlen = 0, err = 0; 3945 + int pathlen = 0, err; 3946 3946 u64 pathbase; 3947 3947 u64 snap_follows; 3948 3948 ··· 3965 3965 cap = __get_cap_for_mds(ci, mds); 3966 3966 if (!cap) { 3967 3967 spin_unlock(&ci->i_ceph_lock); 3968 + err = 0; 3968 3969 goto out_err; 3969 3970 } 3970 3971 dout(" adding %p ino %llx.%llx cap %p %lld %s\n",
+13
fs/ceph/snap.c
··· 1111 1111 continue; 1112 1112 adjust_snap_realm_parent(mdsc, child, realm->ino); 1113 1113 } 1114 + } else { 1115 + /* 1116 + * In the non-split case both 'num_split_inos' and 1117 + * 'num_split_realms' should be 0, making this a no-op. 1118 + * However the MDS happens to populate 'split_realms' list 1119 + * in one of the UPDATE op cases by mistake. 1120 + * 1121 + * Skip both lists just in case to ensure that 'p' is 1122 + * positioned at the start of realm info, as expected by 1123 + * ceph_update_snap_trace(). 1124 + */ 1125 + p += sizeof(u64) * num_split_inos; 1126 + p += sizeof(u64) * num_split_realms; 1114 1127 } 1115 1128 1116 1129 /*
+2 -2
fs/cifs/cifsglob.h
··· 424 424 /* check for STATUS_NETWORK_SESSION_EXPIRED */ 425 425 bool (*is_session_expired)(char *); 426 426 /* send oplock break response */ 427 - int (*oplock_response)(struct cifs_tcon *, struct cifs_fid *, 428 - struct cifsInodeInfo *); 427 + int (*oplock_response)(struct cifs_tcon *tcon, __u64 persistent_fid, __u64 volatile_fid, 428 + __u16 net_fid, struct cifsInodeInfo *cifs_inode); 429 429 /* query remote filesystem */ 430 430 int (*queryfs)(const unsigned int, struct cifs_tcon *, 431 431 struct cifs_sb_info *, struct kstatfs *);
+13 -13
fs/cifs/file.c
··· 4881 4881 struct cifs_tcon *tcon = tlink_tcon(cfile->tlink); 4882 4882 struct TCP_Server_Info *server = tcon->ses->server; 4883 4883 int rc = 0; 4884 - bool purge_cache = false; 4885 - struct cifs_deferred_close *dclose; 4886 - bool is_deferred = false; 4884 + bool purge_cache = false, oplock_break_cancelled; 4885 + __u64 persistent_fid, volatile_fid; 4886 + __u16 net_fid; 4887 4887 4888 4888 wait_on_bit(&cinode->flags, CIFS_INODE_PENDING_WRITERS, 4889 4889 TASK_UNINTERRUPTIBLE); ··· 4924 4924 * file handles but cached, then schedule deferred close immediately. 4925 4925 * So, new open will not use cached handle. 4926 4926 */ 4927 - spin_lock(&CIFS_I(inode)->deferred_lock); 4928 - is_deferred = cifs_is_deferred_close(cfile, &dclose); 4929 - spin_unlock(&CIFS_I(inode)->deferred_lock); 4930 4927 4931 - if (!CIFS_CACHE_HANDLE(cinode) && is_deferred && 4932 - cfile->deferred_close_scheduled && delayed_work_pending(&cfile->deferred)) { 4928 + if (!CIFS_CACHE_HANDLE(cinode) && !list_empty(&cinode->deferred_closes)) 4933 4929 cifs_close_deferred_file(cinode); 4934 - } 4935 4930 4931 + persistent_fid = cfile->fid.persistent_fid; 4932 + volatile_fid = cfile->fid.volatile_fid; 4933 + net_fid = cfile->fid.netfid; 4934 + oplock_break_cancelled = cfile->oplock_break_cancelled; 4935 + 4936 + _cifsFileInfo_put(cfile, false /* do not wait for ourself */, false); 4936 4937 /* 4937 4938 * releasing stale oplock after recent reconnect of smb session using 4938 4939 * a now incorrect file handle is not a data integrity issue but do 4939 4940 * not bother sending an oplock release if session to server still is 4940 4941 * disconnected since oplock already released by the server 4941 4942 */ 4942 - if (!cfile->oplock_break_cancelled) { 4943 - rc = tcon->ses->server->ops->oplock_response(tcon, &cfile->fid, 4944 - cinode); 4943 + if (!oplock_break_cancelled) { 4944 + rc = tcon->ses->server->ops->oplock_response(tcon, persistent_fid, 4945 + volatile_fid, net_fid, cinode); 4945 4946 cifs_dbg(FYI, "Oplock release rc = %d\n", rc); 4946 4947 } 4947 4948 4948 - _cifsFileInfo_put(cfile, false /* do not wait for ourself */, false); 4949 4949 cifs_done_oplock_break(cinode); 4950 4950 } 4951 4951
+4 -5
fs/cifs/smb1ops.c
··· 897 897 } 898 898 899 899 static int 900 - cifs_oplock_response(struct cifs_tcon *tcon, struct cifs_fid *fid, 901 - struct cifsInodeInfo *cinode) 900 + cifs_oplock_response(struct cifs_tcon *tcon, __u64 persistent_fid, 901 + __u64 volatile_fid, __u16 net_fid, struct cifsInodeInfo *cinode) 902 902 { 903 - return CIFSSMBLock(0, tcon, fid->netfid, current->tgid, 0, 0, 0, 0, 904 - LOCKING_ANDX_OPLOCK_RELEASE, false, 905 - CIFS_CACHE_READ(cinode) ? 1 : 0); 903 + return CIFSSMBLock(0, tcon, net_fid, current->tgid, 0, 0, 0, 0, 904 + LOCKING_ANDX_OPLOCK_RELEASE, false, CIFS_CACHE_READ(cinode) ? 1 : 0); 906 905 } 907 906 908 907 static int
+3 -4
fs/cifs/smb2ops.c
··· 2383 2383 } 2384 2384 2385 2385 static int 2386 - smb2_oplock_response(struct cifs_tcon *tcon, struct cifs_fid *fid, 2387 - struct cifsInodeInfo *cinode) 2386 + smb2_oplock_response(struct cifs_tcon *tcon, __u64 persistent_fid, 2387 + __u64 volatile_fid, __u16 net_fid, struct cifsInodeInfo *cinode) 2388 2388 { 2389 2389 if (tcon->ses->server->capabilities & SMB2_GLOBAL_CAP_LEASING) 2390 2390 return SMB2_lease_break(0, tcon, cinode->lease_key, 2391 2391 smb2_get_lease_state(cinode)); 2392 2392 2393 - return SMB2_oplock_break(0, tcon, fid->persistent_fid, 2394 - fid->volatile_fid, 2393 + return SMB2_oplock_break(0, tcon, persistent_fid, volatile_fid, 2395 2394 CIFS_CACHE_READ(cinode) ? 1 : 0); 2396 2395 } 2397 2396
+2 -1
fs/ksmbd/connection.c
··· 351 351 break; 352 352 353 353 /* 4 for rfc1002 length field */ 354 - size = pdu_size + 4; 354 + /* 1 for implied bcc[0] */ 355 + size = pdu_size + 4 + 1; 355 356 conn->request_buf = kvmalloc(size, GFP_KERNEL); 356 357 if (!conn->request_buf) 357 358 break;
+3 -2
fs/ksmbd/oplock.c
··· 1449 1449 * smb2_find_context_vals() - find a particular context info in open request 1450 1450 * @open_req: buffer containing smb2 file open(create) request 1451 1451 * @tag: context name to search for 1452 + * @tag_len: the length of tag 1452 1453 * 1453 1454 * Return: pointer to requested context, NULL if @str context not found 1454 1455 * or error pointer if name length is invalid. 1455 1456 */ 1456 - struct create_context *smb2_find_context_vals(void *open_req, const char *tag) 1457 + struct create_context *smb2_find_context_vals(void *open_req, const char *tag, int tag_len) 1457 1458 { 1458 1459 struct create_context *cc; 1459 1460 unsigned int next = 0; ··· 1493 1492 return ERR_PTR(-EINVAL); 1494 1493 1495 1494 name = (char *)cc + name_off; 1496 - if (memcmp(name, tag, name_len) == 0) 1495 + if (name_len == tag_len && !memcmp(name, tag, name_len)) 1497 1496 return cc; 1498 1497 1499 1498 remain_len -= next;
+1 -1
fs/ksmbd/oplock.h
··· 118 118 void create_mxac_rsp_buf(char *cc, int maximal_access); 119 119 void create_disk_id_rsp_buf(char *cc, __u64 file_id, __u64 vol_id); 120 120 void create_posix_rsp_buf(char *cc, struct ksmbd_file *fp); 121 - struct create_context *smb2_find_context_vals(void *open_req, const char *str); 121 + struct create_context *smb2_find_context_vals(void *open_req, const char *tag, int tag_len); 122 122 struct oplock_info *lookup_lease_in_table(struct ksmbd_conn *conn, 123 123 char *lease_key); 124 124 int find_same_lease_key(struct ksmbd_session *sess, struct ksmbd_inode *ci,
+4 -1
fs/ksmbd/smb2misc.c
··· 416 416 417 417 /* 418 418 * Allow a message that padded to 8byte boundary. 419 + * Linux 4.19.217 with smb 3.0.2 are sometimes 420 + * sending messages where the cls_len is exactly 421 + * 8 bytes less than len. 419 422 */ 420 - if (clc_len < len && (len - clc_len) < 8) 423 + if (clc_len < len && (len - clc_len) <= 8) 421 424 goto validate_credit; 422 425 423 426 pr_err_ratelimited(
+9 -10
fs/ksmbd/smb2pdu.c
··· 1356 1356 struct authenticate_message *authblob; 1357 1357 struct ksmbd_user *user; 1358 1358 char *name; 1359 - unsigned int auth_msg_len, name_off, name_len, secbuf_len; 1359 + unsigned int name_off, name_len, secbuf_len; 1360 1360 1361 1361 secbuf_len = le16_to_cpu(req->SecurityBufferLength); 1362 1362 if (secbuf_len < sizeof(struct authenticate_message)) { ··· 1366 1366 authblob = user_authblob(conn, req); 1367 1367 name_off = le32_to_cpu(authblob->UserName.BufferOffset); 1368 1368 name_len = le16_to_cpu(authblob->UserName.Length); 1369 - auth_msg_len = le16_to_cpu(req->SecurityBufferOffset) + secbuf_len; 1370 1369 1371 - if (auth_msg_len < (u64)name_off + name_len) 1370 + if (secbuf_len < (u64)name_off + name_len) 1372 1371 return NULL; 1373 1372 1374 1373 name = smb_strndup_from_utf16((const char *)authblob + name_off, ··· 2463 2464 return -ENOENT; 2464 2465 2465 2466 /* Parse SD BUFFER create contexts */ 2466 - context = smb2_find_context_vals(req, SMB2_CREATE_SD_BUFFER); 2467 + context = smb2_find_context_vals(req, SMB2_CREATE_SD_BUFFER, 4); 2467 2468 if (!context) 2468 2469 return -ENOENT; 2469 2470 else if (IS_ERR(context)) ··· 2665 2666 2666 2667 if (req->CreateContextsOffset) { 2667 2668 /* Parse non-durable handle create contexts */ 2668 - context = smb2_find_context_vals(req, SMB2_CREATE_EA_BUFFER); 2669 + context = smb2_find_context_vals(req, SMB2_CREATE_EA_BUFFER, 4); 2669 2670 if (IS_ERR(context)) { 2670 2671 rc = PTR_ERR(context); 2671 2672 goto err_out1; ··· 2685 2686 } 2686 2687 2687 2688 context = smb2_find_context_vals(req, 2688 - SMB2_CREATE_QUERY_MAXIMAL_ACCESS_REQUEST); 2689 + SMB2_CREATE_QUERY_MAXIMAL_ACCESS_REQUEST, 4); 2689 2690 if (IS_ERR(context)) { 2690 2691 rc = PTR_ERR(context); 2691 2692 goto err_out1; ··· 2696 2697 } 2697 2698 2698 2699 context = smb2_find_context_vals(req, 2699 - SMB2_CREATE_TIMEWARP_REQUEST); 2700 + SMB2_CREATE_TIMEWARP_REQUEST, 4); 2700 2701 if (IS_ERR(context)) { 2701 2702 rc = PTR_ERR(context); 2702 2703 goto err_out1; ··· 2708 2709 2709 2710 if (tcon->posix_extensions) { 2710 2711 context = smb2_find_context_vals(req, 2711 - SMB2_CREATE_TAG_POSIX); 2712 + SMB2_CREATE_TAG_POSIX, 16); 2712 2713 if (IS_ERR(context)) { 2713 2714 rc = PTR_ERR(context); 2714 2715 goto err_out1; ··· 3106 3107 struct create_alloc_size_req *az_req; 3107 3108 3108 3109 az_req = (struct create_alloc_size_req *)smb2_find_context_vals(req, 3109 - SMB2_CREATE_ALLOCATION_SIZE); 3110 + SMB2_CREATE_ALLOCATION_SIZE, 4); 3110 3111 if (IS_ERR(az_req)) { 3111 3112 rc = PTR_ERR(az_req); 3112 3113 goto err_out; ··· 3133 3134 err); 3134 3135 } 3135 3136 3136 - context = smb2_find_context_vals(req, SMB2_CREATE_QUERY_ON_DISK_ID); 3137 + context = smb2_find_context_vals(req, SMB2_CREATE_QUERY_ON_DISK_ID, 4); 3137 3138 if (IS_ERR(context)) { 3138 3139 rc = PTR_ERR(context); 3139 3140 goto err_out;
+1 -1
fs/lockd/svc.c
··· 77 77 static const unsigned long nlm_grace_period_max = 240; 78 78 static const unsigned long nlm_timeout_min = 3; 79 79 static const unsigned long nlm_timeout_max = 20; 80 - static const int nlm_port_min = 0, nlm_port_max = 65535; 81 80 82 81 #ifdef CONFIG_SYSCTL 82 + static const int nlm_port_min = 0, nlm_port_max = 65535; 83 83 static struct ctl_table_header * nlm_sysctl_table; 84 84 #endif 85 85
+13 -12
fs/nfsd/nfsctl.c
··· 153 153 return 0; 154 154 } 155 155 156 - static int exports_proc_open(struct inode *inode, struct file *file) 157 - { 158 - return exports_net_open(current->nsproxy->net_ns, file); 159 - } 160 - 161 - static const struct proc_ops exports_proc_ops = { 162 - .proc_open = exports_proc_open, 163 - .proc_read = seq_read, 164 - .proc_lseek = seq_lseek, 165 - .proc_release = seq_release, 166 - }; 167 - 168 156 static int exports_nfsd_open(struct inode *inode, struct file *file) 169 157 { 170 158 return exports_net_open(inode->i_sb->s_fs_info, file); ··· 1446 1458 MODULE_ALIAS_FS("nfsd"); 1447 1459 1448 1460 #ifdef CONFIG_PROC_FS 1461 + 1462 + static int exports_proc_open(struct inode *inode, struct file *file) 1463 + { 1464 + return exports_net_open(current->nsproxy->net_ns, file); 1465 + } 1466 + 1467 + static const struct proc_ops exports_proc_ops = { 1468 + .proc_open = exports_proc_open, 1469 + .proc_read = seq_read, 1470 + .proc_lseek = seq_lseek, 1471 + .proc_release = seq_release, 1472 + }; 1473 + 1449 1474 static int create_proc_exports_entry(void) 1450 1475 { 1451 1476 struct proc_dir_entry *entry;
+3 -3
fs/nfsd/trace.h
··· 1365 1365 __field(u32, cl_id) 1366 1366 __field(unsigned long, authflavor) 1367 1367 __sockaddr(addr, clp->cl_cb_conn.cb_addrlen) 1368 - __array(unsigned char, netid, 8) 1368 + __string(netid, netid) 1369 1369 ), 1370 1370 TP_fast_assign( 1371 1371 __entry->cl_boot = clp->cl_clientid.cl_boot; 1372 1372 __entry->cl_id = clp->cl_clientid.cl_id; 1373 - strlcpy(__entry->netid, netid, sizeof(__entry->netid)); 1373 + __assign_str(netid, netid); 1374 1374 __entry->authflavor = authflavor; 1375 1375 __assign_sockaddr(addr, &clp->cl_cb_conn.cb_addr, 1376 1376 clp->cl_cb_conn.cb_addrlen) 1377 1377 ), 1378 1378 TP_printk("addr=%pISpc client %08x:%08x proto=%s flavor=%s", 1379 1379 __get_sockaddr(addr), __entry->cl_boot, __entry->cl_id, 1380 - __entry->netid, show_nfsd_authflavor(__entry->authflavor)) 1380 + __get_str(netid), show_nfsd_authflavor(__entry->authflavor)) 1381 1381 ); 1382 1382 1383 1383 TRACE_EVENT(nfsd_cb_setup_err,
+18
fs/nilfs2/inode.c
··· 917 917 struct nilfs_transaction_info ti; 918 918 struct super_block *sb = inode->i_sb; 919 919 struct nilfs_inode_info *ii = NILFS_I(inode); 920 + struct the_nilfs *nilfs; 920 921 int ret; 921 922 922 923 if (inode->i_nlink || !ii->i_root || unlikely(is_bad_inode(inode))) { ··· 929 928 nilfs_transaction_begin(sb, &ti, 0); /* never fails */ 930 929 931 930 truncate_inode_pages_final(&inode->i_data); 931 + 932 + nilfs = sb->s_fs_info; 933 + if (unlikely(sb_rdonly(sb) || !nilfs->ns_writer)) { 934 + /* 935 + * If this inode is about to be disposed after the file system 936 + * has been degraded to read-only due to file system corruption 937 + * or after the writer has been detached, do not make any 938 + * changes that cause writes, just clear it. 939 + * Do this check after read-locking ns_segctor_sem by 940 + * nilfs_transaction_begin() in order to avoid a race with 941 + * the writer detach operation. 942 + */ 943 + clear_inode(inode); 944 + nilfs_clear_inode(inode); 945 + nilfs_transaction_abort(sb); 946 + return; 947 + } 932 948 933 949 /* TODO: some of the following operations may fail. */ 934 950 nilfs_truncate_bmap(ii, 0);
+2 -2
fs/statfs.c
··· 130 130 if (sizeof(buf) == sizeof(*st)) 131 131 memcpy(&buf, st, sizeof(*st)); 132 132 else { 133 + memset(&buf, 0, sizeof(buf)); 133 134 if (sizeof buf.f_blocks == 4) { 134 135 if ((st->f_blocks | st->f_bfree | st->f_bavail | 135 136 st->f_bsize | st->f_frsize) & ··· 159 158 buf.f_namelen = st->f_namelen; 160 159 buf.f_frsize = st->f_frsize; 161 160 buf.f_flags = st->f_flags; 162 - memset(buf.f_spare, 0, sizeof(buf.f_spare)); 163 161 } 164 162 if (copy_to_user(p, &buf, sizeof(buf))) 165 163 return -EFAULT; ··· 171 171 if (sizeof(buf) == sizeof(*st)) 172 172 memcpy(&buf, st, sizeof(*st)); 173 173 else { 174 + memset(&buf, 0, sizeof(buf)); 174 175 buf.f_type = st->f_type; 175 176 buf.f_bsize = st->f_bsize; 176 177 buf.f_blocks = st->f_blocks; ··· 183 182 buf.f_namelen = st->f_namelen; 184 183 buf.f_frsize = st->f_frsize; 185 184 buf.f_flags = st->f_flags; 186 - memset(buf.f_spare, 0, sizeof(buf.f_spare)); 187 185 } 188 186 if (copy_to_user(p, &buf, sizeof(buf))) 189 187 return -EFAULT;
-2
include/linux/blkdev.h
··· 1376 1376 BLK_UID_NAA = 3, 1377 1377 }; 1378 1378 1379 - #define NFL4_UFLG_MASK 0x0000003F 1380 - 1381 1379 struct block_device_operations { 1382 1380 void (*submit_bio)(struct bio *bio); 1383 1381 int (*poll_bio)(struct bio *bio, struct io_comp_batch *iob,
+2 -3
include/linux/compiler.h
··· 12 12 * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code 13 13 * to disable branch tracing on a per file basis. 14 14 */ 15 - #if defined(CONFIG_TRACE_BRANCH_PROFILING) \ 16 - && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__) 17 15 void ftrace_likely_update(struct ftrace_likely_data *f, int val, 18 16 int expect, int is_constant); 19 - 17 + #if defined(CONFIG_TRACE_BRANCH_PROFILING) \ 18 + && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__) 20 19 #define likely_notrace(x) __builtin_expect(!!(x), 1) 21 20 #define unlikely_notrace(x) __builtin_expect(!!(x), 0) 22 21
+1
include/linux/device/class.h
··· 74 74 struct class_dev_iter { 75 75 struct klist_iter ki; 76 76 const struct device_type *type; 77 + struct subsys_private *sp; 77 78 }; 78 79 79 80 int __must_check class_register(const struct class *class);
-2
include/linux/phy.h
··· 1900 1900 int devm_phy_package_join(struct device *dev, struct phy_device *phydev, 1901 1901 int addr, size_t priv_size); 1902 1902 1903 - #if IS_ENABLED(CONFIG_PHYLIB) 1904 1903 int __init mdio_bus_init(void); 1905 1904 void mdio_bus_exit(void); 1906 - #endif 1907 1905 1908 1906 int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data); 1909 1907 int phy_ethtool_get_sset_count(struct phy_device *phydev);
+11 -2
include/linux/shrinker.h
··· 107 107 108 108 #ifdef CONFIG_SHRINKER_DEBUG 109 109 extern int shrinker_debugfs_add(struct shrinker *shrinker); 110 - extern struct dentry *shrinker_debugfs_remove(struct shrinker *shrinker); 110 + extern struct dentry *shrinker_debugfs_detach(struct shrinker *shrinker, 111 + int *debugfs_id); 112 + extern void shrinker_debugfs_remove(struct dentry *debugfs_entry, 113 + int debugfs_id); 111 114 extern int __printf(2, 3) shrinker_debugfs_rename(struct shrinker *shrinker, 112 115 const char *fmt, ...); 113 116 #else /* CONFIG_SHRINKER_DEBUG */ ··· 118 115 { 119 116 return 0; 120 117 } 121 - static inline struct dentry *shrinker_debugfs_remove(struct shrinker *shrinker) 118 + static inline struct dentry *shrinker_debugfs_detach(struct shrinker *shrinker, 119 + int *debugfs_id) 122 120 { 121 + *debugfs_id = -1; 123 122 return NULL; 123 + } 124 + static inline void shrinker_debugfs_remove(struct dentry *debugfs_entry, 125 + int debugfs_id) 126 + { 124 127 } 125 128 static inline __printf(2, 3) 126 129 int shrinker_debugfs_rename(struct shrinker *shrinker, const char *fmt, ...)
+1 -1
include/linux/sunrpc/svc_rdma.h
··· 176 176 extern void svc_rdma_recv_ctxt_put(struct svcxprt_rdma *rdma, 177 177 struct svc_rdma_recv_ctxt *ctxt); 178 178 extern void svc_rdma_flush_recv_queues(struct svcxprt_rdma *rdma); 179 - extern void svc_rdma_release_rqst(struct svc_rqst *rqstp); 179 + extern void svc_rdma_release_ctxt(struct svc_xprt *xprt, void *ctxt); 180 180 extern int svc_rdma_recvfrom(struct svc_rqst *); 181 181 182 182 /* svc_rdma_rw.c */
+1 -1
include/linux/sunrpc/svc_xprt.h
··· 23 23 int (*xpo_sendto)(struct svc_rqst *); 24 24 int (*xpo_result_payload)(struct svc_rqst *, unsigned int, 25 25 unsigned int); 26 - void (*xpo_release_rqst)(struct svc_rqst *); 26 + void (*xpo_release_ctxt)(struct svc_xprt *xprt, void *ctxt); 27 27 void (*xpo_detach)(struct svc_xprt *); 28 28 void (*xpo_free)(struct svc_xprt *); 29 29 void (*xpo_kill_temp_xprt)(struct svc_xprt *);
+1
include/linux/tpm.h
··· 282 282 TPM_CHIP_FLAG_ALWAYS_POWERED = BIT(5), 283 283 TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED = BIT(6), 284 284 TPM_CHIP_FLAG_FIRMWARE_UPGRADE = BIT(7), 285 + TPM_CHIP_FLAG_SUSPENDED = BIT(8), 285 286 }; 286 287 287 288 #define to_tpm_chip(d) container_of(d, struct tpm_chip, dev)
+1 -1
include/linux/usb/composite.h
··· 443 443 * @bcd_webusb_version: 0x0100 by default, WebUSB specification version 444 444 * @b_webusb_vendor_code: 0x0 by default, vendor code for WebUSB 445 445 * @landing_page: empty by default, landing page to announce in WebUSB 446 - * @use_webusb:: false by default, interested gadgets set it 446 + * @use_webusb: false by default, interested gadgets set it 447 447 * @os_desc_config: the configuration to be used with OS descriptors 448 448 * @setup_pending: true when setup request is queued but not completed 449 449 * @os_desc_pending: true when os_desc request is queued but not completed
+5 -1
include/media/dvb_frontend.h
··· 686 686 * @id: Frontend ID 687 687 * @exit: Used to inform the DVB core that the frontend 688 688 * thread should exit (usually, means that the hardware 689 - * got disconnected. 689 + * got disconnected). 690 + * @remove_mutex: mutex that avoids a race condition between a callback 691 + * called when the hardware is disconnected and the 692 + * file_operations of dvb_frontend. 690 693 */ 691 694 692 695 struct dvb_frontend { ··· 707 704 int (*callback)(void *adapter_priv, int component, int cmd, int arg); 708 705 int id; 709 706 unsigned int exit; 707 + struct mutex remove_mutex; 710 708 }; 711 709 712 710 /**
+4
include/media/dvb_net.h
··· 39 39 * @exit: flag to indicate when the device is being removed. 40 40 * @demux: pointer to &struct dmx_demux. 41 41 * @ioctl_mutex: protect access to this struct. 42 + * @remove_mutex: mutex that avoids a race condition between a callback 43 + * called when the hardware is disconnected and the 44 + * file_operations of dvb_net. 42 45 * 43 46 * Currently, the core supports up to %DVB_NET_DEVICES_MAX (10) network 44 47 * devices. ··· 54 51 unsigned int exit:1; 55 52 struct dmx_demux *demux; 56 53 struct mutex ioctl_mutex; 54 + struct mutex remove_mutex; 57 55 }; 58 56 59 57 /**
+15
include/media/dvbdev.h
··· 194 194 }; 195 195 196 196 /** 197 + * struct dvbdevfops_node - fops nodes registered in dvbdevfops_list 198 + * 199 + * @fops: Dynamically allocated fops for ->owner registration 200 + * @type: type of dvb_device 201 + * @template: dvb_device used for registration 202 + * @list_head: list_head for dvbdevfops_list 203 + */ 204 + struct dvbdevfops_node { 205 + struct file_operations *fops; 206 + enum dvb_device_type type; 207 + const struct dvb_device *template; 208 + struct list_head list_head; 209 + }; 210 + 211 + /** 197 212 * dvb_device_get - Increase dvb_device reference 198 213 * 199 214 * @dvbdev: pointer to struct dvb_device
-23
include/net/nexthop.h
··· 497 497 return NULL; 498 498 } 499 499 500 - /* Variant of nexthop_fib6_nh(). 501 - * Caller should either hold rcu_read_lock(), or RTNL. 502 - */ 503 - static inline struct fib6_nh *nexthop_fib6_nh_bh(struct nexthop *nh) 504 - { 505 - struct nh_info *nhi; 506 - 507 - if (nh->is_group) { 508 - struct nh_group *nh_grp; 509 - 510 - nh_grp = rcu_dereference_rtnl(nh->nh_grp); 511 - nh = nexthop_mpath_select(nh_grp, 0); 512 - if (!nh) 513 - return NULL; 514 - } 515 - 516 - nhi = rcu_dereference_rtnl(nh->nh_info); 517 - if (nhi->family == AF_INET6) 518 - return &nhi->fib6_nh; 519 - 520 - return NULL; 521 - } 522 - 523 500 static inline struct net_device *fib6_info_nh_dev(struct fib6_info *f6i) 524 501 { 525 502 struct fib6_nh *fib6_nh;
+14
include/sound/hda-mlink.h
··· 44 44 45 45 int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num); 46 46 47 + int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, 48 + int channel_mask, int stream_id, int dir); 49 + 47 50 void hda_bus_ml_put_all(struct hdac_bus *bus); 48 51 void hda_bus_ml_reset_losidv(struct hdac_bus *bus); 49 52 int hda_bus_ml_resume(struct hdac_bus *bus); ··· 54 51 55 52 struct hdac_ext_link *hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus); 56 53 struct hdac_ext_link *hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus); 54 + struct hdac_ext_link *hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus); 57 55 58 56 struct mutex *hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid); 59 57 ··· 148 144 static inline int 149 145 hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num) { return 0; } 150 146 147 + static inline int 148 + hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, 149 + int channel_mask, int stream_id, int dir) 150 + { 151 + return 0; 152 + } 153 + 151 154 static inline void hda_bus_ml_put_all(struct hdac_bus *bus) { } 152 155 static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { } 153 156 static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; } ··· 165 154 166 155 static inline struct hdac_ext_link * 167 156 hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus) { return NULL; } 157 + 158 + static inline struct hdac_ext_link * 159 + hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus) { return NULL; } 168 160 169 161 static inline struct mutex * 170 162 hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid) { return NULL; }
+2 -1
include/uapi/sound/sof/tokens.h
··· 183 183 #define SOF_TKN_CAVS_AUDIO_FORMAT_IN_INTERLEAVING_STYLE 1906 184 184 #define SOF_TKN_CAVS_AUDIO_FORMAT_IN_FMT_CFG 1907 185 185 #define SOF_TKN_CAVS_AUDIO_FORMAT_IN_SAMPLE_TYPE 1908 186 - #define SOF_TKN_CAVS_AUDIO_FORMAT_PIN_INDEX 1909 186 + #define SOF_TKN_CAVS_AUDIO_FORMAT_INPUT_PIN_INDEX 1909 187 187 /* intentional token numbering discontinuity, reserved for future use */ 188 188 #define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_RATE 1930 189 189 #define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_BIT_DEPTH 1931 ··· 194 194 #define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_INTERLEAVING_STYLE 1936 195 195 #define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_FMT_CFG 1937 196 196 #define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_SAMPLE_TYPE 1938 197 + #define SOF_TKN_CAVS_AUDIO_FORMAT_OUTPUT_PIN_INDEX 1939 197 198 /* intentional token numbering discontinuity, reserved for future use */ 198 199 #define SOF_TKN_CAVS_AUDIO_FORMAT_IBS 1970 199 200 #define SOF_TKN_CAVS_AUDIO_FORMAT_OBS 1971
+1 -1
include/ufs/ufshcd.h
··· 1133 1133 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1134 1134 #endif 1135 1135 1136 - static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba *hba) 1136 + static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1137 1137 { 1138 1138 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1139 1139 }
+58 -15
kernel/trace/fprobe.c
··· 17 17 struct fprobe_rethook_node { 18 18 struct rethook_node node; 19 19 unsigned long entry_ip; 20 + unsigned long entry_parent_ip; 20 21 char data[]; 21 22 }; 22 23 23 - static void fprobe_handler(unsigned long ip, unsigned long parent_ip, 24 - struct ftrace_ops *ops, struct ftrace_regs *fregs) 24 + static inline void __fprobe_handler(unsigned long ip, unsigned long parent_ip, 25 + struct ftrace_ops *ops, struct ftrace_regs *fregs) 25 26 { 26 27 struct fprobe_rethook_node *fpr; 27 28 struct rethook_node *rh = NULL; 28 29 struct fprobe *fp; 29 30 void *entry_data = NULL; 30 - int bit, ret; 31 + int ret = 0; 31 32 32 33 fp = container_of(ops, struct fprobe, ops); 33 - if (fprobe_disabled(fp)) 34 - return; 35 - 36 - bit = ftrace_test_recursion_trylock(ip, parent_ip); 37 - if (bit < 0) { 38 - fp->nmissed++; 39 - return; 40 - } 41 34 42 35 if (fp->exit_handler) { 43 36 rh = rethook_try_get(fp->rethook); 44 37 if (!rh) { 45 38 fp->nmissed++; 46 - goto out; 39 + return; 47 40 } 48 41 fpr = container_of(rh, struct fprobe_rethook_node, node); 49 42 fpr->entry_ip = ip; 43 + fpr->entry_parent_ip = parent_ip; 50 44 if (fp->entry_data_size) 51 45 entry_data = fpr->data; 52 46 } ··· 55 61 else 56 62 rethook_hook(rh, ftrace_get_regs(fregs), true); 57 63 } 58 - out: 64 + } 65 + 66 + static void fprobe_handler(unsigned long ip, unsigned long parent_ip, 67 + struct ftrace_ops *ops, struct ftrace_regs *fregs) 68 + { 69 + struct fprobe *fp; 70 + int bit; 71 + 72 + fp = container_of(ops, struct fprobe, ops); 73 + if (fprobe_disabled(fp)) 74 + return; 75 + 76 + /* recursion detection has to go before any traceable function and 77 + * all functions before this point should be marked as notrace 78 + */ 79 + bit = ftrace_test_recursion_trylock(ip, parent_ip); 80 + if (bit < 0) { 81 + fp->nmissed++; 82 + return; 83 + } 84 + __fprobe_handler(ip, parent_ip, ops, fregs); 59 85 ftrace_test_recursion_unlock(bit); 86 + 60 87 } 61 88 NOKPROBE_SYMBOL(fprobe_handler); 62 89 63 90 static void fprobe_kprobe_handler(unsigned long ip, unsigned long parent_ip, 64 91 struct ftrace_ops *ops, struct ftrace_regs *fregs) 65 92 { 66 - struct fprobe *fp = container_of(ops, struct fprobe, ops); 93 + struct fprobe *fp; 94 + int bit; 95 + 96 + fp = container_of(ops, struct fprobe, ops); 97 + if (fprobe_disabled(fp)) 98 + return; 99 + 100 + /* recursion detection has to go before any traceable function and 101 + * all functions called before this point should be marked as notrace 102 + */ 103 + bit = ftrace_test_recursion_trylock(ip, parent_ip); 104 + if (bit < 0) { 105 + fp->nmissed++; 106 + return; 107 + } 67 108 68 109 if (unlikely(kprobe_running())) { 69 110 fp->nmissed++; 70 111 return; 71 112 } 113 + 72 114 kprobe_busy_begin(); 73 - fprobe_handler(ip, parent_ip, ops, fregs); 115 + __fprobe_handler(ip, parent_ip, ops, fregs); 74 116 kprobe_busy_end(); 117 + ftrace_test_recursion_unlock(bit); 75 118 } 76 119 77 120 static void fprobe_exit_handler(struct rethook_node *rh, void *data, ··· 116 85 { 117 86 struct fprobe *fp = (struct fprobe *)data; 118 87 struct fprobe_rethook_node *fpr; 88 + int bit; 119 89 120 90 if (!fp || fprobe_disabled(fp)) 121 91 return; 122 92 123 93 fpr = container_of(rh, struct fprobe_rethook_node, node); 124 94 95 + /* 96 + * we need to assure no calls to traceable functions in-between the 97 + * end of fprobe_handler and the beginning of fprobe_exit_handler. 98 + */ 99 + bit = ftrace_test_recursion_trylock(fpr->entry_ip, fpr->entry_parent_ip); 100 + if (bit < 0) { 101 + fp->nmissed++; 102 + return; 103 + } 104 + 125 105 fp->exit_handler(fp, fpr->entry_ip, regs, 126 106 fp->entry_data_size ? (void *)fpr->data : NULL); 107 + ftrace_test_recursion_unlock(bit); 127 108 } 128 109 NOKPROBE_SYMBOL(fprobe_exit_handler); 129 110
+2 -2
kernel/trace/rethook.c
··· 288 288 * These loops must be protected from rethook_free_rcu() because those 289 289 * are accessing 'rhn->rethook'. 290 290 */ 291 - preempt_disable(); 291 + preempt_disable_notrace(); 292 292 293 293 /* 294 294 * Run the handler on the shadow stack. Do not unlink the list here because ··· 321 321 first = first->next; 322 322 rethook_recycle(rhn); 323 323 } 324 - preempt_enable(); 324 + preempt_enable_notrace(); 325 325 326 326 return correct_ret_addr; 327 327 }
+3 -9
lib/maple_tree.c
··· 5317 5317 5318 5318 mt = mte_node_type(mas->node); 5319 5319 pivots = ma_pivots(mas_mn(mas), mt); 5320 - if (offset) 5321 - mas->min = pivots[offset - 1] + 1; 5322 - 5323 - if (offset < mt_pivots[mt]) 5324 - mas->max = pivots[offset]; 5325 - 5326 - if (mas->index < mas->min) 5327 - mas->index = mas->min; 5328 - 5320 + min = mas_safe_min(mas, pivots, offset); 5321 + if (mas->index < min) 5322 + mas->index = min; 5329 5323 mas->last = mas->index + size - 1; 5330 5324 return 0; 5331 5325 }
+1 -1
mm/kfence/kfence.h
··· 29 29 * canary of every 8 bytes is the same. 64-bit memory can be filled and checked 30 30 * at a time instead of byte by byte to improve performance. 31 31 */ 32 - #define KFENCE_CANARY_PATTERN_U64 ((u64)0xaaaaaaaaaaaaaaaa ^ (u64)(0x0706050403020100)) 32 + #define KFENCE_CANARY_PATTERN_U64 ((u64)0xaaaaaaaaaaaaaaaa ^ (u64)(le64_to_cpu(0x0706050403020100))) 33 33 34 34 /* Maximum stack depth for reports. */ 35 35 #define KFENCE_STACK_DEPTH 64
+10 -5
mm/shrinker_debug.c
··· 237 237 } 238 238 EXPORT_SYMBOL(shrinker_debugfs_rename); 239 239 240 - struct dentry *shrinker_debugfs_remove(struct shrinker *shrinker) 240 + struct dentry *shrinker_debugfs_detach(struct shrinker *shrinker, 241 + int *debugfs_id) 241 242 { 242 243 struct dentry *entry = shrinker->debugfs_entry; 243 244 ··· 247 246 kfree_const(shrinker->name); 248 247 shrinker->name = NULL; 249 248 250 - if (entry) { 251 - ida_free(&shrinker_debugfs_ida, shrinker->debugfs_id); 252 - shrinker->debugfs_entry = NULL; 253 - } 249 + *debugfs_id = entry ? shrinker->debugfs_id : -1; 250 + shrinker->debugfs_entry = NULL; 254 251 255 252 return entry; 253 + } 254 + 255 + void shrinker_debugfs_remove(struct dentry *debugfs_entry, int debugfs_id) 256 + { 257 + debugfs_remove_recursive(debugfs_entry); 258 + ida_free(&shrinker_debugfs_ida, debugfs_id); 256 259 } 257 260 258 261 static int __init shrinker_debugfs_init(void)
+3 -2
mm/vmscan.c
··· 805 805 void unregister_shrinker(struct shrinker *shrinker) 806 806 { 807 807 struct dentry *debugfs_entry; 808 + int debugfs_id; 808 809 809 810 if (!(shrinker->flags & SHRINKER_REGISTERED)) 810 811 return; ··· 815 814 shrinker->flags &= ~SHRINKER_REGISTERED; 816 815 if (shrinker->flags & SHRINKER_MEMCG_AWARE) 817 816 unregister_memcg_shrinker(shrinker); 818 - debugfs_entry = shrinker_debugfs_remove(shrinker); 817 + debugfs_entry = shrinker_debugfs_detach(shrinker, &debugfs_id); 819 818 mutex_unlock(&shrinker_mutex); 820 819 821 820 atomic_inc(&shrinker_srcu_generation); 822 821 synchronize_srcu(&shrinker_srcu); 823 822 824 - debugfs_remove_recursive(debugfs_entry); 823 + shrinker_debugfs_remove(debugfs_entry, debugfs_id); 825 824 826 825 kfree(shrinker->nr_deferred); 827 826 shrinker->nr_deferred = NULL;
+9 -27
mm/zsmalloc.c
··· 1331 1331 obj_to_location(obj, &page, &obj_idx); 1332 1332 zspage = get_zspage(page); 1333 1333 1334 - #ifdef CONFIG_ZPOOL 1335 - /* 1336 - * Move the zspage to front of pool's LRU. 1337 - * 1338 - * Note that this is swap-specific, so by definition there are no ongoing 1339 - * accesses to the memory while the page is swapped out that would make 1340 - * it "hot". A new entry is hot, then ages to the tail until it gets either 1341 - * written back or swaps back in. 1342 - * 1343 - * Furthermore, map is also called during writeback. We must not put an 1344 - * isolated page on the LRU mid-reclaim. 1345 - * 1346 - * As a result, only update the LRU when the page is mapped for write 1347 - * when it's first instantiated. 1348 - * 1349 - * This is a deviation from the other backends, which perform this update 1350 - * in the allocation function (zbud_alloc, z3fold_alloc). 1351 - */ 1352 - if (mm == ZS_MM_WO) { 1353 - if (!list_empty(&zspage->lru)) 1354 - list_del(&zspage->lru); 1355 - list_add(&zspage->lru, &pool->lru); 1356 - } 1357 - #endif 1358 - 1359 1334 /* 1360 1335 * migration cannot move any zpages in this zspage. Here, pool->lock 1361 1336 * is too heavy since callers would take some time until they calls ··· 1500 1525 fix_fullness_group(class, zspage); 1501 1526 record_obj(handle, obj); 1502 1527 class_stat_inc(class, ZS_OBJS_INUSE, 1); 1503 - spin_unlock(&pool->lock); 1504 1528 1505 - return handle; 1529 + goto out; 1506 1530 } 1507 1531 1508 1532 spin_unlock(&pool->lock); ··· 1524 1550 1525 1551 /* We completely set up zspage so mark them as movable */ 1526 1552 SetZsPageMovable(pool, zspage); 1553 + out: 1554 + #ifdef CONFIG_ZPOOL 1555 + /* Add/move zspage to beginning of LRU */ 1556 + if (!list_empty(&zspage->lru)) 1557 + list_del(&zspage->lru); 1558 + list_add(&zspage->lru, &pool->lru); 1559 + #endif 1560 + 1527 1561 spin_unlock(&pool->lock); 1528 1562 1529 1563 return handle;
+16
mm/zswap.c
··· 1020 1020 goto fail; 1021 1021 1022 1022 case ZSWAP_SWAPCACHE_NEW: /* page is locked */ 1023 + /* 1024 + * Having a local reference to the zswap entry doesn't exclude 1025 + * swapping from invalidating and recycling the swap slot. Once 1026 + * the swapcache is secured against concurrent swapping to and 1027 + * from the slot, recheck that the entry is still current before 1028 + * writing. 1029 + */ 1030 + spin_lock(&tree->lock); 1031 + if (zswap_rb_search(&tree->rbroot, entry->offset) != entry) { 1032 + spin_unlock(&tree->lock); 1033 + delete_from_swap_cache(page_folio(page)); 1034 + ret = -ENOMEM; 1035 + goto fail; 1036 + } 1037 + spin_unlock(&tree->lock); 1038 + 1023 1039 /* decompress */ 1024 1040 acomp_ctx = raw_cpu_ptr(entry->pool->acomp_ctx); 1025 1041 dlen = PAGE_SIZE;
+2 -2
net/8021q/vlan_dev.c
··· 109 109 * NOTE: THIS ASSUMES DIX ETHERNET, SPECIFICALLY NOT SUPPORTING 110 110 * OTHER THINGS LIKE FDDI/TokenRing/802.3 SNAPs... 111 111 */ 112 - if (veth->h_vlan_proto != vlan->vlan_proto || 113 - vlan->flags & VLAN_FLAG_REORDER_HDR) { 112 + if (vlan->flags & VLAN_FLAG_REORDER_HDR || 113 + veth->h_vlan_proto != vlan->vlan_proto) { 114 114 u16 vlan_tci; 115 115 vlan_tci = vlan->vlan_id; 116 116 vlan_tci |= vlan_dev_get_egress_qos_mask(dev, skb->priority);
+2
net/atm/resources.c
··· 400 400 return error; 401 401 } 402 402 403 + #ifdef CONFIG_PROC_FS 403 404 void *atm_dev_seq_start(struct seq_file *seq, loff_t *pos) 404 405 { 405 406 mutex_lock(&atm_dev_mutex); ··· 416 415 { 417 416 return seq_list_next(v, &atm_devs, pos); 418 417 } 418 + #endif
+4 -4
net/bridge/br_private_tunnel.h
··· 27 27 int br_get_vlan_tunnel_info_size(struct net_bridge_vlan_group *vg); 28 28 int br_fill_vlan_tunnel_info(struct sk_buff *skb, 29 29 struct net_bridge_vlan_group *vg); 30 + bool vlan_tunid_inrange(const struct net_bridge_vlan *v_curr, 31 + const struct net_bridge_vlan *v_last); 32 + int br_vlan_tunnel_info(const struct net_bridge_port *p, int cmd, 33 + u16 vid, u32 tun_id, bool *changed); 30 34 31 35 #ifdef CONFIG_BRIDGE_VLAN_FILTERING 32 36 /* br_vlan_tunnel.c */ ··· 47 43 struct net_bridge_vlan_group *vg); 48 44 int br_handle_egress_vlan_tunnel(struct sk_buff *skb, 49 45 struct net_bridge_vlan *vlan); 50 - bool vlan_tunid_inrange(const struct net_bridge_vlan *v_curr, 51 - const struct net_bridge_vlan *v_last); 52 - int br_vlan_tunnel_info(const struct net_bridge_port *p, int cmd, 53 - u16 vid, u32 tun_id, bool *changed); 54 46 #else 55 47 static inline int vlan_tunnel_init(struct net_bridge_vlan_group *vg) 56 48 {
+1 -1
net/can/isotp.c
··· 1139 1139 struct isotp_sock *so = isotp_sk(sk); 1140 1140 int ret = 0; 1141 1141 1142 - if (flags & ~(MSG_DONTWAIT | MSG_TRUNC | MSG_PEEK)) 1142 + if (flags & ~(MSG_DONTWAIT | MSG_TRUNC | MSG_PEEK | MSG_CMSG_COMPAT)) 1143 1143 return -EINVAL; 1144 1144 1145 1145 if (!so->bound)
+1 -1
net/can/j1939/socket.c
··· 798 798 struct j1939_sk_buff_cb *skcb; 799 799 int ret = 0; 800 800 801 - if (flags & ~(MSG_DONTWAIT | MSG_ERRQUEUE)) 801 + if (flags & ~(MSG_DONTWAIT | MSG_ERRQUEUE | MSG_CMSG_COMPAT)) 802 802 return -EINVAL; 803 803 804 804 if (flags & MSG_ERRQUEUE)
+7 -9
net/devlink/core.c
··· 204 204 if (ret < 0) 205 205 goto err_xa_alloc; 206 206 207 - devlink->netdevice_nb.notifier_call = devlink_port_netdevice_event; 208 - ret = register_netdevice_notifier(&devlink->netdevice_nb); 209 - if (ret) 210 - goto err_register_netdevice_notifier; 211 - 212 207 devlink->dev = dev; 213 208 devlink->ops = ops; 214 209 xa_init_flags(&devlink->ports, XA_FLAGS_ALLOC); ··· 228 233 229 234 return devlink; 230 235 231 - err_register_netdevice_notifier: 232 - xa_erase(&devlinks, devlink->index); 233 236 err_xa_alloc: 234 237 kfree(devlink); 235 238 return NULL; ··· 258 265 xa_destroy(&devlink->snapshot_ids); 259 266 xa_destroy(&devlink->params); 260 267 xa_destroy(&devlink->ports); 261 - 262 - WARN_ON_ONCE(unregister_netdevice_notifier(&devlink->netdevice_nb)); 263 268 264 269 xa_erase(&devlinks, devlink->index); 265 270 ··· 294 303 .pre_exit = devlink_pernet_pre_exit, 295 304 }; 296 305 306 + static struct notifier_block devlink_port_netdevice_nb = { 307 + .notifier_call = devlink_port_netdevice_event, 308 + }; 309 + 297 310 static int __init devlink_init(void) 298 311 { 299 312 int err; ··· 306 311 if (err) 307 312 goto out; 308 313 err = register_pernet_subsys(&devlink_pernet_ops); 314 + if (err) 315 + goto out; 316 + err = register_netdevice_notifier(&devlink_port_netdevice_nb); 309 317 310 318 out: 311 319 WARN_ON(err);
-1
net/devlink/devl_internal.h
··· 50 50 u8 reload_failed:1; 51 51 refcount_t refcount; 52 52 struct rcu_work rwork; 53 - struct notifier_block netdevice_nb; 54 53 char priv[] __aligned(NETDEV_ALIGN); 55 54 }; 56 55
+2 -3
net/devlink/leftover.c
··· 7073 7073 struct devlink_port *devlink_port = netdev->devlink_port; 7074 7074 struct devlink *devlink; 7075 7075 7076 - devlink = container_of(nb, struct devlink, netdevice_nb); 7077 - 7078 - if (!devlink_port || devlink_port->devlink != devlink) 7076 + if (!devlink_port) 7079 7077 return NOTIFY_OK; 7078 + devlink = devlink_port->devlink; 7080 7079 7081 7080 switch (event) { 7082 7081 case NETDEV_POST_INIT:
+3 -2
net/ipv4/tcp_ipv4.c
··· 829 829 inet_twsk(sk)->tw_priority : sk->sk_priority; 830 830 transmit_time = tcp_transmit_time(sk); 831 831 xfrm_sk_clone_policy(ctl_sk, sk); 832 + } else { 833 + ctl_sk->sk_mark = 0; 834 + ctl_sk->sk_priority = 0; 832 835 } 833 836 ip_send_unicast_reply(ctl_sk, 834 837 skb, &TCP_SKB_CB(skb)->header.h4.opt, ··· 839 836 &arg, arg.iov[0].iov_len, 840 837 transmit_time); 841 838 842 - ctl_sk->sk_mark = 0; 843 839 xfrm_sk_free_policy(ctl_sk); 844 840 sock_net_set(ctl_sk, &init_net); 845 841 __TCP_INC_STATS(net, TCP_MIB_OUTSEGS); ··· 937 935 &arg, arg.iov[0].iov_len, 938 936 transmit_time); 939 937 940 - ctl_sk->sk_mark = 0; 941 938 sock_net_set(ctl_sk, &init_net); 942 939 __TCP_INC_STATS(net, TCP_MIB_OUTSEGS); 943 940 local_bh_enable();
+8 -8
net/ipv6/ip6_fib.c
··· 2491 2491 const struct net_device *dev; 2492 2492 2493 2493 if (rt->nh) 2494 - fib6_nh = nexthop_fib6_nh_bh(rt->nh); 2494 + fib6_nh = nexthop_fib6_nh(rt->nh); 2495 2495 2496 2496 seq_printf(seq, "%pi6 %02x ", &rt->fib6_dst.addr, rt->fib6_dst.plen); 2497 2497 ··· 2556 2556 2557 2557 if (tbl) { 2558 2558 h = (tbl->tb6_id & (FIB6_TABLE_HASHSZ - 1)) + 1; 2559 - node = rcu_dereference_bh(hlist_next_rcu(&tbl->tb6_hlist)); 2559 + node = rcu_dereference(hlist_next_rcu(&tbl->tb6_hlist)); 2560 2560 } else { 2561 2561 h = 0; 2562 2562 node = NULL; 2563 2563 } 2564 2564 2565 2565 while (!node && h < FIB6_TABLE_HASHSZ) { 2566 - node = rcu_dereference_bh( 2566 + node = rcu_dereference( 2567 2567 hlist_first_rcu(&net->ipv6.fib_table_hash[h++])); 2568 2568 } 2569 2569 return hlist_entry_safe(node, struct fib6_table, tb6_hlist); ··· 2593 2593 if (!v) 2594 2594 goto iter_table; 2595 2595 2596 - n = rcu_dereference_bh(((struct fib6_info *)v)->fib6_next); 2596 + n = rcu_dereference(((struct fib6_info *)v)->fib6_next); 2597 2597 if (n) 2598 2598 return n; 2599 2599 ··· 2619 2619 } 2620 2620 2621 2621 static void *ipv6_route_seq_start(struct seq_file *seq, loff_t *pos) 2622 - __acquires(RCU_BH) 2622 + __acquires(RCU) 2623 2623 { 2624 2624 struct net *net = seq_file_net(seq); 2625 2625 struct ipv6_route_iter *iter = seq->private; 2626 2626 2627 - rcu_read_lock_bh(); 2627 + rcu_read_lock(); 2628 2628 iter->tbl = ipv6_route_seq_next_table(NULL, net); 2629 2629 iter->skip = *pos; 2630 2630 ··· 2645 2645 } 2646 2646 2647 2647 static void ipv6_route_native_seq_stop(struct seq_file *seq, void *v) 2648 - __releases(RCU_BH) 2648 + __releases(RCU) 2649 2649 { 2650 2650 struct net *net = seq_file_net(seq); 2651 2651 struct ipv6_route_iter *iter = seq->private; ··· 2653 2653 if (ipv6_route_iter_active(iter)) 2654 2654 fib6_walker_unlink(net, &iter->w); 2655 2655 2656 - rcu_read_unlock_bh(); 2656 + rcu_read_unlock(); 2657 2657 } 2658 2658 2659 2659 #if IS_BUILTIN(CONFIG_IPV6) && defined(CONFIG_BPF_SYSCALL)
+8 -5
net/ipv6/ip6_gre.c
··· 1015 1015 ntohl(tun_id), 1016 1016 ntohl(md->u.index), truncate, 1017 1017 false); 1018 + proto = htons(ETH_P_ERSPAN); 1018 1019 } else if (md->version == 2) { 1019 1020 erspan_build_header_v2(skb, 1020 1021 ntohl(tun_id), 1021 1022 md->u.md2.dir, 1022 1023 get_hwid(&md->u.md2), 1023 1024 truncate, false); 1025 + proto = htons(ETH_P_ERSPAN2); 1024 1026 } else { 1025 1027 goto tx_err; 1026 1028 } ··· 1045 1043 break; 1046 1044 } 1047 1045 1048 - if (t->parms.erspan_ver == 1) 1046 + if (t->parms.erspan_ver == 1) { 1049 1047 erspan_build_header(skb, ntohl(t->parms.o_key), 1050 1048 t->parms.index, 1051 1049 truncate, false); 1052 - else if (t->parms.erspan_ver == 2) 1050 + proto = htons(ETH_P_ERSPAN); 1051 + } else if (t->parms.erspan_ver == 2) { 1053 1052 erspan_build_header_v2(skb, ntohl(t->parms.o_key), 1054 1053 t->parms.dir, 1055 1054 t->parms.hwid, 1056 1055 truncate, false); 1057 - else 1056 + proto = htons(ETH_P_ERSPAN2); 1057 + } else { 1058 1058 goto tx_err; 1059 + } 1059 1060 1060 1061 fl6.daddr = t->parms.raddr; 1061 1062 } 1062 1063 1063 1064 /* Push GRE header. */ 1064 - proto = (t->parms.erspan_ver == 1) ? htons(ETH_P_ERSPAN) 1065 - : htons(ETH_P_ERSPAN2); 1066 1065 gre_build_header(skb, 8, TUNNEL_SEQ, proto, 0, htonl(atomic_fetch_inc(&t->o_seqno))); 1067 1066 1068 1067 /* TooBig packet may have updated dst->dev's mtu */
+8 -4
net/key/af_key.c
··· 1940 1940 } 1941 1941 1942 1942 static int 1943 - parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_ipsecrequest *rq) 1943 + parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_policy *pol, 1944 + struct sadb_x_ipsecrequest *rq) 1944 1945 { 1945 1946 struct net *net = xp_net(xp); 1946 1947 struct xfrm_tmpl *t = xp->xfrm_vec + xp->xfrm_nr; ··· 1959 1958 if ((mode = pfkey_mode_to_xfrm(rq->sadb_x_ipsecrequest_mode)) < 0) 1960 1959 return -EINVAL; 1961 1960 t->mode = mode; 1962 - if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_USE) 1961 + if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_USE) { 1962 + if ((mode == XFRM_MODE_TUNNEL || mode == XFRM_MODE_BEET) && 1963 + pol->sadb_x_policy_dir == IPSEC_DIR_OUTBOUND) 1964 + return -EINVAL; 1963 1965 t->optional = 1; 1964 - else if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_UNIQUE) { 1966 + } else if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_UNIQUE) { 1965 1967 t->reqid = rq->sadb_x_ipsecrequest_reqid; 1966 1968 if (t->reqid > IPSEC_MANUAL_REQID_MAX) 1967 1969 t->reqid = 0; ··· 2006 2002 rq->sadb_x_ipsecrequest_len < sizeof(*rq)) 2007 2003 return -EINVAL; 2008 2004 2009 - if ((err = parse_ipsecrequest(xp, rq)) < 0) 2005 + if ((err = parse_ipsecrequest(xp, pol, rq)) < 0) 2010 2006 return err; 2011 2007 len -= rq->sadb_x_ipsecrequest_len; 2012 2008 rq = (void*)((u8*)rq + rq->sadb_x_ipsecrequest_len);
+4 -3
net/mac80211/cfg.c
··· 1578 1578 sdata_dereference(link->u.ap.unsol_bcast_probe_resp, 1579 1579 sdata); 1580 1580 1581 - /* abort any running channel switch */ 1581 + /* abort any running channel switch or color change */ 1582 1582 mutex_lock(&local->mtx); 1583 1583 link_conf->csa_active = false; 1584 + link_conf->color_change_active = false; 1584 1585 if (link->csa_block_tx) { 1585 1586 ieee80211_wake_vif_queues(local, sdata, 1586 1587 IEEE80211_QUEUE_STOP_REASON_CSA); ··· 3590 3589 EXPORT_SYMBOL(ieee80211_channel_switch_disconnect); 3591 3590 3592 3591 static int ieee80211_set_after_csa_beacon(struct ieee80211_sub_if_data *sdata, 3593 - u32 *changed) 3592 + u64 *changed) 3594 3593 { 3595 3594 int err; 3596 3595 ··· 3633 3632 static int __ieee80211_csa_finalize(struct ieee80211_sub_if_data *sdata) 3634 3633 { 3635 3634 struct ieee80211_local *local = sdata->local; 3636 - u32 changed = 0; 3635 + u64 changed = 0; 3637 3636 int err; 3638 3637 3639 3638 sdata_assert_lock(sdata);
+47 -28
net/mac80211/chan.c
··· 258 258 259 259 static enum nl80211_chan_width 260 260 ieee80211_get_chanctx_vif_max_required_bw(struct ieee80211_sub_if_data *sdata, 261 - struct ieee80211_chanctx_conf *conf) 261 + struct ieee80211_chanctx *ctx, 262 + struct ieee80211_link_data *rsvd_for) 262 263 { 263 264 enum nl80211_chan_width max_bw = NL80211_CHAN_WIDTH_20_NOHT; 264 265 struct ieee80211_vif *vif = &sdata->vif; ··· 268 267 rcu_read_lock(); 269 268 for (link_id = 0; link_id < ARRAY_SIZE(sdata->link); link_id++) { 270 269 enum nl80211_chan_width width = NL80211_CHAN_WIDTH_20_NOHT; 271 - struct ieee80211_bss_conf *link_conf = 272 - rcu_dereference(sdata->vif.link_conf[link_id]); 270 + struct ieee80211_link_data *link = 271 + rcu_dereference(sdata->link[link_id]); 273 272 274 - if (!link_conf) 273 + if (!link) 275 274 continue; 276 275 277 - if (rcu_access_pointer(link_conf->chanctx_conf) != conf) 276 + if (link != rsvd_for && 277 + rcu_access_pointer(link->conf->chanctx_conf) != &ctx->conf) 278 278 continue; 279 279 280 280 switch (vif->type) { ··· 289 287 * point, so take the width from the chandef, but 290 288 * account also for TDLS peers 291 289 */ 292 - width = max(link_conf->chandef.width, 290 + width = max(link->conf->chandef.width, 293 291 ieee80211_get_max_required_bw(sdata, link_id)); 294 292 break; 295 293 case NL80211_IFTYPE_P2P_DEVICE: ··· 298 296 case NL80211_IFTYPE_ADHOC: 299 297 case NL80211_IFTYPE_MESH_POINT: 300 298 case NL80211_IFTYPE_OCB: 301 - width = link_conf->chandef.width; 299 + width = link->conf->chandef.width; 302 300 break; 303 301 case NL80211_IFTYPE_WDS: 304 302 case NL80211_IFTYPE_UNSPECIFIED: ··· 318 316 319 317 static enum nl80211_chan_width 320 318 ieee80211_get_chanctx_max_required_bw(struct ieee80211_local *local, 321 - struct ieee80211_chanctx_conf *conf) 319 + struct ieee80211_chanctx *ctx, 320 + struct ieee80211_link_data *rsvd_for) 322 321 { 323 322 struct ieee80211_sub_if_data *sdata; 324 323 enum nl80211_chan_width max_bw = NL80211_CHAN_WIDTH_20_NOHT; ··· 331 328 if (!ieee80211_sdata_running(sdata)) 332 329 continue; 333 330 334 - width = ieee80211_get_chanctx_vif_max_required_bw(sdata, conf); 331 + width = ieee80211_get_chanctx_vif_max_required_bw(sdata, ctx, 332 + rsvd_for); 335 333 336 334 max_bw = max(max_bw, width); 337 335 } ··· 340 336 /* use the configured bandwidth in case of monitor interface */ 341 337 sdata = rcu_dereference(local->monitor_sdata); 342 338 if (sdata && 343 - rcu_access_pointer(sdata->vif.bss_conf.chanctx_conf) == conf) 344 - max_bw = max(max_bw, conf->def.width); 339 + rcu_access_pointer(sdata->vif.bss_conf.chanctx_conf) == &ctx->conf) 340 + max_bw = max(max_bw, ctx->conf.def.width); 345 341 346 342 rcu_read_unlock(); 347 343 ··· 353 349 * the max of min required widths of all the interfaces bound to this 354 350 * channel context. 355 351 */ 356 - static u32 _ieee80211_recalc_chanctx_min_def(struct ieee80211_local *local, 357 - struct ieee80211_chanctx *ctx) 352 + static u32 353 + _ieee80211_recalc_chanctx_min_def(struct ieee80211_local *local, 354 + struct ieee80211_chanctx *ctx, 355 + struct ieee80211_link_data *rsvd_for) 358 356 { 359 357 enum nl80211_chan_width max_bw; 360 358 struct cfg80211_chan_def min_def; ··· 376 370 return 0; 377 371 } 378 372 379 - max_bw = ieee80211_get_chanctx_max_required_bw(local, &ctx->conf); 373 + max_bw = ieee80211_get_chanctx_max_required_bw(local, ctx, rsvd_for); 380 374 381 375 /* downgrade chandef up to max_bw */ 382 376 min_def = ctx->conf.def; ··· 454 448 * channel context. 455 449 */ 456 450 void ieee80211_recalc_chanctx_min_def(struct ieee80211_local *local, 457 - struct ieee80211_chanctx *ctx) 451 + struct ieee80211_chanctx *ctx, 452 + struct ieee80211_link_data *rsvd_for) 458 453 { 459 - u32 changed = _ieee80211_recalc_chanctx_min_def(local, ctx); 454 + u32 changed = _ieee80211_recalc_chanctx_min_def(local, ctx, rsvd_for); 460 455 461 456 if (!changed) 462 457 return; ··· 471 464 ieee80211_chan_bw_change(local, ctx, false); 472 465 } 473 466 474 - static void ieee80211_change_chanctx(struct ieee80211_local *local, 475 - struct ieee80211_chanctx *ctx, 476 - struct ieee80211_chanctx *old_ctx, 477 - const struct cfg80211_chan_def *chandef) 467 + static void _ieee80211_change_chanctx(struct ieee80211_local *local, 468 + struct ieee80211_chanctx *ctx, 469 + struct ieee80211_chanctx *old_ctx, 470 + const struct cfg80211_chan_def *chandef, 471 + struct ieee80211_link_data *rsvd_for) 478 472 { 479 473 u32 changed; 480 474 ··· 500 492 ieee80211_chan_bw_change(local, old_ctx, true); 501 493 502 494 if (cfg80211_chandef_identical(&ctx->conf.def, chandef)) { 503 - ieee80211_recalc_chanctx_min_def(local, ctx); 495 + ieee80211_recalc_chanctx_min_def(local, ctx, rsvd_for); 504 496 return; 505 497 } 506 498 ··· 510 502 511 503 /* check if min chanctx also changed */ 512 504 changed = IEEE80211_CHANCTX_CHANGE_WIDTH | 513 - _ieee80211_recalc_chanctx_min_def(local, ctx); 505 + _ieee80211_recalc_chanctx_min_def(local, ctx, rsvd_for); 514 506 drv_change_chanctx(local, ctx, changed); 515 507 516 508 if (!local->use_chanctx) { ··· 520 512 521 513 /* check is BW wider */ 522 514 ieee80211_chan_bw_change(local, old_ctx, false); 515 + } 516 + 517 + static void ieee80211_change_chanctx(struct ieee80211_local *local, 518 + struct ieee80211_chanctx *ctx, 519 + struct ieee80211_chanctx *old_ctx, 520 + const struct cfg80211_chan_def *chandef) 521 + { 522 + _ieee80211_change_chanctx(local, ctx, old_ctx, chandef, NULL); 523 523 } 524 524 525 525 static struct ieee80211_chanctx * ··· 654 638 ctx->conf.rx_chains_dynamic = 1; 655 639 ctx->mode = mode; 656 640 ctx->conf.radar_enabled = false; 657 - ieee80211_recalc_chanctx_min_def(local, ctx); 641 + _ieee80211_recalc_chanctx_min_def(local, ctx, NULL); 658 642 659 643 return ctx; 660 644 } ··· 871 855 } 872 856 873 857 if (new_ctx) { 858 + /* recalc considering the link we'll use it for now */ 859 + ieee80211_recalc_chanctx_min_def(local, new_ctx, link); 860 + 874 861 ret = drv_assign_vif_chanctx(local, sdata, link->conf, new_ctx); 875 862 if (ret) 876 863 goto out; ··· 892 873 ieee80211_recalc_chanctx_chantype(local, curr_ctx); 893 874 ieee80211_recalc_smps_chanctx(local, curr_ctx); 894 875 ieee80211_recalc_radar_chanctx(local, curr_ctx); 895 - ieee80211_recalc_chanctx_min_def(local, curr_ctx); 876 + ieee80211_recalc_chanctx_min_def(local, curr_ctx, NULL); 896 877 } 897 878 898 879 if (new_ctx && ieee80211_chanctx_num_assigned(local, new_ctx) > 0) { 899 880 ieee80211_recalc_txpower(sdata, false); 900 - ieee80211_recalc_chanctx_min_def(local, new_ctx); 881 + ieee80211_recalc_chanctx_min_def(local, new_ctx, NULL); 901 882 } 902 883 903 884 if (sdata->vif.type != NL80211_IFTYPE_P2P_DEVICE && ··· 1289 1270 1290 1271 ieee80211_link_update_chandef(link, &link->reserved_chandef); 1291 1272 1292 - ieee80211_change_chanctx(local, new_ctx, old_ctx, chandef); 1273 + _ieee80211_change_chanctx(local, new_ctx, old_ctx, chandef, link); 1293 1274 1294 1275 vif_chsw[0].vif = &sdata->vif; 1295 1276 vif_chsw[0].old_ctx = &old_ctx->conf; ··· 1319 1300 if (ieee80211_chanctx_refcount(local, old_ctx) == 0) 1320 1301 ieee80211_free_chanctx(local, old_ctx); 1321 1302 1322 - ieee80211_recalc_chanctx_min_def(local, new_ctx); 1303 + ieee80211_recalc_chanctx_min_def(local, new_ctx, NULL); 1323 1304 ieee80211_recalc_smps_chanctx(local, new_ctx); 1324 1305 ieee80211_recalc_radar_chanctx(local, new_ctx); 1325 1306 ··· 1684 1665 ieee80211_recalc_chanctx_chantype(local, ctx); 1685 1666 ieee80211_recalc_smps_chanctx(local, ctx); 1686 1667 ieee80211_recalc_radar_chanctx(local, ctx); 1687 - ieee80211_recalc_chanctx_min_def(local, ctx); 1668 + ieee80211_recalc_chanctx_min_def(local, ctx, NULL); 1688 1669 1689 1670 list_for_each_entry_safe(link, link_tmp, &ctx->reserved_links, 1690 1671 reserved_chanctx_list) {
+2 -1
net/mac80211/ieee80211_i.h
··· 2537 2537 void ieee80211_recalc_smps_chanctx(struct ieee80211_local *local, 2538 2538 struct ieee80211_chanctx *chanctx); 2539 2539 void ieee80211_recalc_chanctx_min_def(struct ieee80211_local *local, 2540 - struct ieee80211_chanctx *ctx); 2540 + struct ieee80211_chanctx *ctx, 2541 + struct ieee80211_link_data *rsvd_for); 2541 2542 bool ieee80211_is_radar_required(struct ieee80211_local *local); 2542 2543 2543 2544 void ieee80211_dfs_cac_timer(unsigned long data);
+1 -1
net/mac80211/trace.h
··· 67 67 __entry->min_freq_offset = (c)->chan ? (c)->chan->freq_offset : 0; \ 68 68 __entry->min_chan_width = (c)->width; \ 69 69 __entry->min_center_freq1 = (c)->center_freq1; \ 70 - __entry->freq1_offset = (c)->freq1_offset; \ 70 + __entry->min_freq1_offset = (c)->freq1_offset; \ 71 71 __entry->min_center_freq2 = (c)->center_freq2; 72 72 #define MIN_CHANDEF_PR_FMT " min_control:%d.%03d MHz min_width:%d min_center: %d.%03d/%d MHz" 73 73 #define MIN_CHANDEF_PR_ARG __entry->min_control_freq, __entry->min_freq_offset, \
+3 -2
net/mac80211/tx.c
··· 3791 3791 ieee80211_tx_result r; 3792 3792 struct ieee80211_vif *vif = txq->vif; 3793 3793 int q = vif->hw_queue[txq->ac]; 3794 + unsigned long flags; 3794 3795 bool q_stopped; 3795 3796 3796 3797 WARN_ON_ONCE(softirq_count() == 0); ··· 3800 3799 return NULL; 3801 3800 3802 3801 begin: 3803 - spin_lock(&local->queue_stop_reason_lock); 3802 + spin_lock_irqsave(&local->queue_stop_reason_lock, flags); 3804 3803 q_stopped = local->queue_stop_reasons[q]; 3805 - spin_unlock(&local->queue_stop_reason_lock); 3804 + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); 3806 3805 3807 3806 if (unlikely(q_stopped)) { 3808 3807 /* mark for waking later */
+1 -1
net/mac80211/util.c
··· 3015 3015 3016 3016 chanctx = container_of(chanctx_conf, struct ieee80211_chanctx, 3017 3017 conf); 3018 - ieee80211_recalc_chanctx_min_def(local, chanctx); 3018 + ieee80211_recalc_chanctx_min_def(local, chanctx, NULL); 3019 3019 } 3020 3020 unlock: 3021 3021 mutex_unlock(&local->chanctx_mtx);
+4
net/netfilter/nf_conntrack_netlink.c
··· 2976 2976 return -1; 2977 2977 } 2978 2978 2979 + #if IS_ENABLED(CONFIG_NF_NAT) 2979 2980 static const union nf_inet_addr any_addr; 2981 + #endif 2980 2982 2981 2983 static __be32 nf_expect_get_id(const struct nf_conntrack_expect *exp) 2982 2984 { ··· 3462 3460 return 0; 3463 3461 } 3464 3462 3463 + #if IS_ENABLED(CONFIG_NF_NAT) 3465 3464 static const struct nla_policy exp_nat_nla_policy[CTA_EXPECT_NAT_MAX+1] = { 3466 3465 [CTA_EXPECT_NAT_DIR] = { .type = NLA_U32 }, 3467 3466 [CTA_EXPECT_NAT_TUPLE] = { .type = NLA_NESTED }, 3468 3467 }; 3468 + #endif 3469 3469 3470 3470 static int 3471 3471 ctnetlink_parse_expect_nat(const struct nlattr *attr,
+1 -3
net/netfilter/nf_tables_api.c
··· 3865 3865 struct nft_trans *trans; 3866 3866 3867 3867 list_for_each_entry(trans, &nft_net->commit_list, list) { 3868 - struct nft_rule *rule = nft_trans_rule(trans); 3869 - 3870 3868 if (trans->msg_type == NFT_MSG_NEWRULE && 3871 3869 trans->ctx.chain == chain && 3872 3870 id == nft_trans_rule_id(trans)) 3873 - return rule; 3871 + return nft_trans_rule(trans); 3874 3872 } 3875 3873 return ERR_PTR(-ENOENT); 3876 3874 }
+13 -7
net/netfilter/nft_set_rbtree.c
··· 221 221 { 222 222 struct nft_set *set = (struct nft_set *)__set; 223 223 struct rb_node *prev = rb_prev(&rbe->node); 224 - struct nft_rbtree_elem *rbe_prev; 224 + struct nft_rbtree_elem *rbe_prev = NULL; 225 225 struct nft_set_gc_batch *gcb; 226 226 227 227 gcb = nft_set_gc_batch_check(set, NULL, GFP_ATOMIC); ··· 229 229 return -ENOMEM; 230 230 231 231 /* search for expired end interval coming before this element. */ 232 - do { 232 + while (prev) { 233 233 rbe_prev = rb_entry(prev, struct nft_rbtree_elem, node); 234 234 if (nft_rbtree_interval_end(rbe_prev)) 235 235 break; 236 236 237 237 prev = rb_prev(prev); 238 - } while (prev != NULL); 238 + } 239 239 240 - rb_erase(&rbe_prev->node, &priv->root); 240 + if (rbe_prev) { 241 + rb_erase(&rbe_prev->node, &priv->root); 242 + atomic_dec(&set->nelems); 243 + } 244 + 241 245 rb_erase(&rbe->node, &priv->root); 242 - atomic_sub(2, &set->nelems); 246 + atomic_dec(&set->nelems); 243 247 244 248 nft_set_gc_batch_add(gcb, rbe); 245 249 nft_set_gc_batch_complete(gcb); ··· 272 268 struct nft_set_ext **ext) 273 269 { 274 270 struct nft_rbtree_elem *rbe, *rbe_le = NULL, *rbe_ge = NULL; 275 - struct rb_node *node, *parent, **p, *first = NULL; 271 + struct rb_node *node, *next, *parent, **p, *first = NULL; 276 272 struct nft_rbtree *priv = nft_set_priv(set); 277 273 u8 genmask = nft_genmask_next(net); 278 274 int d, err; ··· 311 307 * Values stored in the tree are in reversed order, starting from 312 308 * highest to lowest value. 313 309 */ 314 - for (node = first; node != NULL; node = rb_next(node)) { 310 + for (node = first; node != NULL; node = next) { 311 + next = rb_next(node); 312 + 315 313 rbe = rb_entry(node, struct nft_rbtree_elem, node); 316 314 317 315 if (!nft_set_elem_active(&rbe->ext, genmask))
+3 -5
net/nsh/nsh.c
··· 77 77 netdev_features_t features) 78 78 { 79 79 struct sk_buff *segs = ERR_PTR(-EINVAL); 80 + u16 mac_offset = skb->mac_header; 80 81 unsigned int nsh_len, mac_len; 81 82 __be16 proto; 82 - int nhoff; 83 83 84 84 skb_reset_network_header(skb); 85 85 86 - nhoff = skb->network_header - skb->mac_header; 87 86 mac_len = skb->mac_len; 88 87 89 88 if (unlikely(!pskb_may_pull(skb, NSH_BASE_HDR_LEN))) ··· 107 108 segs = skb_mac_gso_segment(skb, features); 108 109 if (IS_ERR_OR_NULL(segs)) { 109 110 skb_gso_error_unwind(skb, htons(ETH_P_NSH), nsh_len, 110 - skb->network_header - nhoff, 111 - mac_len); 111 + mac_offset, mac_len); 112 112 goto out; 113 113 } 114 114 115 115 for (skb = segs; skb; skb = skb->next) { 116 116 skb->protocol = htons(ETH_P_NSH); 117 117 __skb_push(skb, nsh_len); 118 - skb_set_mac_header(skb, -nhoff); 118 + skb->mac_header = mac_offset; 119 119 skb->network_header = skb->mac_header + mac_len; 120 120 skb->mac_len = mac_len; 121 121 }
+10
net/sunrpc/auth_gss/gss_krb5_crypto.c
··· 639 639 640 640 ret = write_bytes_to_xdr_buf(buf, offset, data, len); 641 641 642 + #if IS_ENABLED(CONFIG_KUNIT) 643 + /* 644 + * CBC-CTS does not define an output IV but RFC 3962 defines it as the 645 + * penultimate block of ciphertext, so copy that into the IV buffer 646 + * before returning. 647 + */ 648 + if (encrypt) 649 + memcpy(iv, data, crypto_sync_skcipher_ivsize(cipher)); 650 + #endif 651 + 642 652 out: 643 653 kfree(data); 644 654 return ret;
+12 -7
net/sunrpc/svc.c
··· 1052 1052 #endif 1053 1053 } 1054 1054 1055 - trace_svc_register(progname, version, protocol, port, family, error); 1055 + trace_svc_register(progname, version, family, protocol, port, error); 1056 1056 return error; 1057 1057 } 1058 1058 ··· 1416 1416 /* Only RPCv2 supported */ 1417 1417 xdr_stream_encode_u32(xdr, RPC_VERSION); 1418 1418 xdr_stream_encode_u32(xdr, RPC_VERSION); 1419 - goto sendit; 1419 + return 1; /* don't wrap */ 1420 1420 1421 1421 err_bad_auth: 1422 1422 dprintk("svc: authentication failed (%d)\n", ··· 1432 1432 err_bad_prog: 1433 1433 dprintk("svc: unknown program %d\n", rqstp->rq_prog); 1434 1434 serv->sv_stats->rpcbadfmt++; 1435 - xdr_stream_encode_u32(xdr, RPC_PROG_UNAVAIL); 1435 + *rqstp->rq_accept_statp = rpc_prog_unavail; 1436 1436 goto sendit; 1437 1437 1438 1438 err_bad_vers: ··· 1440 1440 rqstp->rq_vers, rqstp->rq_prog, progp->pg_name); 1441 1441 1442 1442 serv->sv_stats->rpcbadfmt++; 1443 - xdr_stream_encode_u32(xdr, RPC_PROG_MISMATCH); 1443 + *rqstp->rq_accept_statp = rpc_prog_mismatch; 1444 + 1445 + /* 1446 + * svc_authenticate() has already added the verifier and 1447 + * advanced the stream just past rq_accept_statp. 1448 + */ 1444 1449 xdr_stream_encode_u32(xdr, process.mismatch.lovers); 1445 1450 xdr_stream_encode_u32(xdr, process.mismatch.hivers); 1446 1451 goto sendit; ··· 1454 1449 svc_printk(rqstp, "unknown procedure (%d)\n", rqstp->rq_proc); 1455 1450 1456 1451 serv->sv_stats->rpcbadfmt++; 1457 - xdr_stream_encode_u32(xdr, RPC_PROC_UNAVAIL); 1452 + *rqstp->rq_accept_statp = rpc_proc_unavail; 1458 1453 goto sendit; 1459 1454 1460 1455 err_garbage_args: 1461 1456 svc_printk(rqstp, "failed to decode RPC header\n"); 1462 1457 1463 1458 serv->sv_stats->rpcbadfmt++; 1464 - xdr_stream_encode_u32(xdr, RPC_GARBAGE_ARGS); 1459 + *rqstp->rq_accept_statp = rpc_garbage_args; 1465 1460 goto sendit; 1466 1461 1467 1462 err_system_err: 1468 1463 serv->sv_stats->rpcbadfmt++; 1469 - xdr_stream_encode_u32(xdr, RPC_SYSTEM_ERR); 1464 + *rqstp->rq_accept_statp = rpc_system_err; 1470 1465 goto sendit; 1471 1466 } 1472 1467
+18 -6
net/sunrpc/svc_xprt.c
··· 532 532 } 533 533 EXPORT_SYMBOL_GPL(svc_reserve); 534 534 535 + static void free_deferred(struct svc_xprt *xprt, struct svc_deferred_req *dr) 536 + { 537 + if (!dr) 538 + return; 539 + 540 + xprt->xpt_ops->xpo_release_ctxt(xprt, dr->xprt_ctxt); 541 + kfree(dr); 542 + } 543 + 535 544 static void svc_xprt_release(struct svc_rqst *rqstp) 536 545 { 537 546 struct svc_xprt *xprt = rqstp->rq_xprt; 538 547 539 - xprt->xpt_ops->xpo_release_rqst(rqstp); 548 + xprt->xpt_ops->xpo_release_ctxt(xprt, rqstp->rq_xprt_ctxt); 549 + rqstp->rq_xprt_ctxt = NULL; 540 550 541 - kfree(rqstp->rq_deferred); 551 + free_deferred(xprt, rqstp->rq_deferred); 542 552 rqstp->rq_deferred = NULL; 543 553 544 554 svc_rqst_release_pages(rqstp); ··· 1064 1054 spin_unlock_bh(&serv->sv_lock); 1065 1055 1066 1056 while ((dr = svc_deferred_dequeue(xprt)) != NULL) 1067 - kfree(dr); 1057 + free_deferred(xprt, dr); 1068 1058 1069 1059 call_xpt_users(xprt); 1070 1060 svc_xprt_put(xprt); ··· 1186 1176 if (too_many || test_bit(XPT_DEAD, &xprt->xpt_flags)) { 1187 1177 spin_unlock(&xprt->xpt_lock); 1188 1178 trace_svc_defer_drop(dr); 1179 + free_deferred(xprt, dr); 1189 1180 svc_xprt_put(xprt); 1190 - kfree(dr); 1191 1181 return; 1192 1182 } 1193 1183 dr->xprt = NULL; ··· 1232 1222 dr->addrlen = rqstp->rq_addrlen; 1233 1223 dr->daddr = rqstp->rq_daddr; 1234 1224 dr->argslen = rqstp->rq_arg.len >> 2; 1235 - dr->xprt_ctxt = rqstp->rq_xprt_ctxt; 1236 - rqstp->rq_xprt_ctxt = NULL; 1237 1225 1238 1226 /* back up head to the start of the buffer and copy */ 1239 1227 skip = rqstp->rq_arg.len - rqstp->rq_arg.head[0].iov_len; 1240 1228 memcpy(dr->args, rqstp->rq_arg.head[0].iov_base - skip, 1241 1229 dr->argslen << 2); 1242 1230 } 1231 + dr->xprt_ctxt = rqstp->rq_xprt_ctxt; 1232 + rqstp->rq_xprt_ctxt = NULL; 1243 1233 trace_svc_defer(rqstp); 1244 1234 svc_xprt_get(rqstp->rq_xprt); 1245 1235 dr->xprt = rqstp->rq_xprt; ··· 1272 1262 rqstp->rq_daddr = dr->daddr; 1273 1263 rqstp->rq_respages = rqstp->rq_pages; 1274 1264 rqstp->rq_xprt_ctxt = dr->xprt_ctxt; 1265 + 1266 + dr->xprt_ctxt = NULL; 1275 1267 svc_xprt_received(rqstp->rq_xprt); 1276 1268 return dr->argslen << 2; 1277 1269 }
+20 -26
net/sunrpc/svcsock.c
··· 121 121 #endif 122 122 123 123 /** 124 - * svc_tcp_release_rqst - Release transport-related resources 125 - * @rqstp: request structure with resources to be released 124 + * svc_tcp_release_ctxt - Release transport-related resources 125 + * @xprt: the transport which owned the context 126 + * @ctxt: the context from rqstp->rq_xprt_ctxt or dr->xprt_ctxt 126 127 * 127 128 */ 128 - static void svc_tcp_release_rqst(struct svc_rqst *rqstp) 129 + static void svc_tcp_release_ctxt(struct svc_xprt *xprt, void *ctxt) 129 130 { 130 131 } 131 132 132 133 /** 133 - * svc_udp_release_rqst - Release transport-related resources 134 - * @rqstp: request structure with resources to be released 134 + * svc_udp_release_ctxt - Release transport-related resources 135 + * @xprt: the transport which owned the context 136 + * @ctxt: the context from rqstp->rq_xprt_ctxt or dr->xprt_ctxt 135 137 * 136 138 */ 137 - static void svc_udp_release_rqst(struct svc_rqst *rqstp) 139 + static void svc_udp_release_ctxt(struct svc_xprt *xprt, void *ctxt) 138 140 { 139 - struct sk_buff *skb = rqstp->rq_xprt_ctxt; 141 + struct sk_buff *skb = ctxt; 140 142 141 - if (skb) { 142 - rqstp->rq_xprt_ctxt = NULL; 143 + if (skb) 143 144 consume_skb(skb); 144 - } 145 145 } 146 146 147 147 union svc_pktinfo_u { ··· 696 696 unsigned int sent; 697 697 int err; 698 698 699 - svc_udp_release_rqst(rqstp); 699 + svc_udp_release_ctxt(xprt, rqstp->rq_xprt_ctxt); 700 + rqstp->rq_xprt_ctxt = NULL; 700 701 701 702 svc_set_cmsg_data(rqstp, cmh); 702 703 ··· 769 768 .xpo_recvfrom = svc_udp_recvfrom, 770 769 .xpo_sendto = svc_udp_sendto, 771 770 .xpo_result_payload = svc_sock_result_payload, 772 - .xpo_release_rqst = svc_udp_release_rqst, 771 + .xpo_release_ctxt = svc_udp_release_ctxt, 773 772 .xpo_detach = svc_sock_detach, 774 773 .xpo_free = svc_sock_free, 775 774 .xpo_has_wspace = svc_udp_has_wspace, ··· 896 895 trace_svcsock_accept_err(xprt, serv->sv_name, err); 897 896 return NULL; 898 897 } 898 + if (IS_ERR(sock_alloc_file(newsock, O_NONBLOCK, NULL))) 899 + return NULL; 900 + 899 901 set_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags); 900 902 901 903 err = kernel_getpeername(newsock, sin); ··· 939 935 return &newsvsk->sk_xprt; 940 936 941 937 failed: 942 - sock_release(newsock); 938 + sockfd_put(newsock); 943 939 return NULL; 944 940 } 945 941 ··· 1302 1298 unsigned int sent; 1303 1299 int err; 1304 1300 1305 - svc_tcp_release_rqst(rqstp); 1301 + svc_tcp_release_ctxt(xprt, rqstp->rq_xprt_ctxt); 1302 + rqstp->rq_xprt_ctxt = NULL; 1306 1303 1307 1304 atomic_inc(&svsk->sk_sendqlen); 1308 1305 mutex_lock(&xprt->xpt_mutex); ··· 1348 1343 .xpo_recvfrom = svc_tcp_recvfrom, 1349 1344 .xpo_sendto = svc_tcp_sendto, 1350 1345 .xpo_result_payload = svc_sock_result_payload, 1351 - .xpo_release_rqst = svc_tcp_release_rqst, 1346 + .xpo_release_ctxt = svc_tcp_release_ctxt, 1352 1347 .xpo_detach = svc_tcp_sock_detach, 1353 1348 .xpo_free = svc_sock_free, 1354 1349 .xpo_has_wspace = svc_tcp_has_wspace, ··· 1435 1430 struct socket *sock, 1436 1431 int flags) 1437 1432 { 1438 - struct file *filp = NULL; 1439 1433 struct svc_sock *svsk; 1440 1434 struct sock *inet; 1441 1435 int pmap_register = !(flags & SVC_SOCK_ANONYMOUS); ··· 1442 1438 svsk = kzalloc(sizeof(*svsk), GFP_KERNEL); 1443 1439 if (!svsk) 1444 1440 return ERR_PTR(-ENOMEM); 1445 - 1446 - if (!sock->file) { 1447 - filp = sock_alloc_file(sock, O_NONBLOCK, NULL); 1448 - if (IS_ERR(filp)) { 1449 - kfree(svsk); 1450 - return ERR_CAST(filp); 1451 - } 1452 - } 1453 1441 1454 1442 inet = sock->sk; 1455 1443 ··· 1452 1456 inet->sk_protocol, 1453 1457 ntohs(inet_sk(inet)->inet_sport)); 1454 1458 if (err < 0) { 1455 - if (filp) 1456 - fput(filp); 1457 1459 kfree(svsk); 1458 1460 return ERR_PTR(err); 1459 1461 }
+5 -6
net/sunrpc/xprtrdma/svc_rdma_recvfrom.c
··· 239 239 } 240 240 241 241 /** 242 - * svc_rdma_release_rqst - Release transport-specific per-rqst resources 243 - * @rqstp: svc_rqst being released 242 + * svc_rdma_release_ctxt - Release transport-specific per-rqst resources 243 + * @xprt: the transport which owned the context 244 + * @vctxt: the context from rqstp->rq_xprt_ctxt or dr->xprt_ctxt 244 245 * 245 246 * Ensure that the recv_ctxt is released whether or not a Reply 246 247 * was sent. For example, the client could close the connection, 247 248 * or svc_process could drop an RPC, before the Reply is sent. 248 249 */ 249 - void svc_rdma_release_rqst(struct svc_rqst *rqstp) 250 + void svc_rdma_release_ctxt(struct svc_xprt *xprt, void *vctxt) 250 251 { 251 - struct svc_rdma_recv_ctxt *ctxt = rqstp->rq_xprt_ctxt; 252 - struct svc_xprt *xprt = rqstp->rq_xprt; 252 + struct svc_rdma_recv_ctxt *ctxt = vctxt; 253 253 struct svcxprt_rdma *rdma = 254 254 container_of(xprt, struct svcxprt_rdma, sc_xprt); 255 255 256 - rqstp->rq_xprt_ctxt = NULL; 257 256 if (ctxt) 258 257 svc_rdma_recv_ctxt_put(rdma, ctxt); 259 258 }
+1 -1
net/sunrpc/xprtrdma/svc_rdma_transport.c
··· 80 80 .xpo_recvfrom = svc_rdma_recvfrom, 81 81 .xpo_sendto = svc_rdma_sendto, 82 82 .xpo_result_payload = svc_rdma_result_payload, 83 - .xpo_release_rqst = svc_rdma_release_rqst, 83 + .xpo_release_ctxt = svc_rdma_release_ctxt, 84 84 .xpo_detach = svc_rdma_detach, 85 85 .xpo_free = svc_rdma_free, 86 86 .xpo_has_wspace = svc_rdma_has_wspace,
+15 -2
net/tipc/bearer.c
··· 541 541 return mtu; 542 542 } 543 543 544 + int tipc_bearer_min_mtu(struct net *net, u32 bearer_id) 545 + { 546 + int mtu = TIPC_MIN_BEARER_MTU; 547 + struct tipc_bearer *b; 548 + 549 + rcu_read_lock(); 550 + b = bearer_get(net, bearer_id); 551 + if (b) 552 + mtu += b->encap_hlen; 553 + rcu_read_unlock(); 554 + return mtu; 555 + } 556 + 544 557 /* tipc_bearer_xmit_skb - sends buffer to destination over bearer 545 558 */ 546 559 void tipc_bearer_xmit_skb(struct net *net, u32 bearer_id, ··· 1151 1138 return -EINVAL; 1152 1139 } 1153 1140 #ifdef CONFIG_TIPC_MEDIA_UDP 1154 - if (tipc_udp_mtu_bad(nla_get_u32 1155 - (props[TIPC_NLA_PROP_MTU]))) { 1141 + if (nla_get_u32(props[TIPC_NLA_PROP_MTU]) < 1142 + b->encap_hlen + TIPC_MIN_BEARER_MTU) { 1156 1143 NL_SET_ERR_MSG(info->extack, 1157 1144 "MTU value is out-of-range"); 1158 1145 return -EINVAL;
+3
net/tipc/bearer.h
··· 146 146 * @identity: array index of this bearer within TIPC bearer array 147 147 * @disc: ptr to link setup request 148 148 * @net_plane: network plane ('A' through 'H') currently associated with bearer 149 + * @encap_hlen: encap headers length 149 150 * @up: bearer up flag (bit 0) 150 151 * @refcnt: tipc_bearer reference counter 151 152 * ··· 171 170 u32 identity; 172 171 struct tipc_discoverer *disc; 173 172 char net_plane; 173 + u16 encap_hlen; 174 174 unsigned long up; 175 175 refcount_t refcnt; 176 176 }; ··· 234 232 void tipc_bearer_cleanup(void); 235 233 void tipc_bearer_stop(struct net *net); 236 234 int tipc_bearer_mtu(struct net *net, u32 bearer_id); 235 + int tipc_bearer_min_mtu(struct net *net, u32 bearer_id); 237 236 bool tipc_bearer_bcast_support(struct net *net, u32 bearer_id); 238 237 void tipc_bearer_xmit_skb(struct net *net, u32 bearer_id, 239 238 struct sk_buff *skb,
+6 -3
net/tipc/link.c
··· 2200 2200 struct tipc_msg *hdr = buf_msg(skb); 2201 2201 struct tipc_gap_ack_blks *ga = NULL; 2202 2202 bool reply = msg_probe(hdr), retransmitted = false; 2203 - u32 dlen = msg_data_sz(hdr), glen = 0; 2203 + u32 dlen = msg_data_sz(hdr), glen = 0, msg_max; 2204 2204 u16 peers_snd_nxt = msg_next_sent(hdr); 2205 2205 u16 peers_tol = msg_link_tolerance(hdr); 2206 2206 u16 peers_prio = msg_linkprio(hdr); ··· 2239 2239 switch (mtyp) { 2240 2240 case RESET_MSG: 2241 2241 case ACTIVATE_MSG: 2242 + msg_max = msg_max_pkt(hdr); 2243 + if (msg_max < tipc_bearer_min_mtu(l->net, l->bearer_id)) 2244 + break; 2242 2245 /* Complete own link name with peer's interface name */ 2243 2246 if_name = strrchr(l->name, ':') + 1; 2244 2247 if (sizeof(l->name) - (if_name - l->name) <= TIPC_MAX_IF_NAME) ··· 2286 2283 l->peer_session = msg_session(hdr); 2287 2284 l->in_session = true; 2288 2285 l->peer_bearer_id = msg_bearer_id(hdr); 2289 - if (l->mtu > msg_max_pkt(hdr)) 2290 - l->mtu = msg_max_pkt(hdr); 2286 + if (l->mtu > msg_max) 2287 + l->mtu = msg_max; 2291 2288 break; 2292 2289 2293 2290 case STATE_MSG:
+3 -2
net/tipc/udp_media.c
··· 738 738 udp_conf.local_ip.s_addr = local.ipv4.s_addr; 739 739 udp_conf.use_udp_checksums = false; 740 740 ub->ifindex = dev->ifindex; 741 - if (tipc_mtu_bad(dev, sizeof(struct iphdr) + 742 - sizeof(struct udphdr))) { 741 + b->encap_hlen = sizeof(struct iphdr) + sizeof(struct udphdr); 742 + if (tipc_mtu_bad(dev, b->encap_hlen)) { 743 743 err = -EINVAL; 744 744 goto err; 745 745 } ··· 760 760 else 761 761 udp_conf.local_ip6 = local.ipv6; 762 762 ub->ifindex = dev->ifindex; 763 + b->encap_hlen = sizeof(struct ipv6hdr) + sizeof(struct udphdr); 763 764 b->mtu = 1280; 764 765 #endif 765 766 } else {
+1 -1
net/vmw_vsock/af_vsock.c
··· 1462 1462 vsock_transport_cancel_pkt(vsk); 1463 1463 vsock_remove_connected(vsk); 1464 1464 goto out_wait; 1465 - } else if (timeout == 0) { 1465 + } else if ((sk->sk_state != TCP_ESTABLISHED) && (timeout == 0)) { 1466 1466 err = -ETIMEDOUT; 1467 1467 sk->sk_state = TCP_CLOSE; 1468 1468 sock->state = SS_UNCONNECTED;
+5 -1
net/wireless/scan.c
··· 5 5 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net> 6 6 * Copyright 2013-2014 Intel Mobile Communications GmbH 7 7 * Copyright 2016 Intel Deutschland GmbH 8 - * Copyright (C) 2018-2022 Intel Corporation 8 + * Copyright (C) 2018-2023 Intel Corporation 9 9 */ 10 10 #include <linux/kernel.h> 11 11 #include <linux/slab.h> ··· 539 539 { 540 540 /* skip the TBTT offset */ 541 541 pos++; 542 + 543 + /* ignore entries with invalid BSSID */ 544 + if (!is_valid_ether_addr(pos)) 545 + return -EINVAL; 542 546 543 547 memcpy(entry->bssid, pos, ETH_ALEN); 544 548 pos += ETH_ALEN;
+1 -1
net/xfrm/xfrm_device.c
··· 378 378 break; 379 379 default: 380 380 xdo->dev = NULL; 381 - dev_put(dev); 381 + netdev_put(dev, &xdo->dev_tracker); 382 382 NL_SET_ERR_MSG(extack, "Unrecognized offload direction"); 383 383 return -EINVAL; 384 384 }
+4 -50
net/xfrm/xfrm_interface_core.c
··· 310 310 skb->mark = 0; 311 311 } 312 312 313 - static int xfrmi_input(struct sk_buff *skb, int nexthdr, __be32 spi, 314 - int encap_type, unsigned short family) 315 - { 316 - struct sec_path *sp; 317 - 318 - sp = skb_sec_path(skb); 319 - if (sp && (sp->len || sp->olen) && 320 - !xfrm_policy_check(NULL, XFRM_POLICY_IN, skb, family)) 321 - goto discard; 322 - 323 - XFRM_SPI_SKB_CB(skb)->family = family; 324 - if (family == AF_INET) { 325 - XFRM_SPI_SKB_CB(skb)->daddroff = offsetof(struct iphdr, daddr); 326 - XFRM_TUNNEL_SKB_CB(skb)->tunnel.ip4 = NULL; 327 - } else { 328 - XFRM_SPI_SKB_CB(skb)->daddroff = offsetof(struct ipv6hdr, daddr); 329 - XFRM_TUNNEL_SKB_CB(skb)->tunnel.ip6 = NULL; 330 - } 331 - 332 - return xfrm_input(skb, nexthdr, spi, encap_type); 333 - discard: 334 - kfree_skb(skb); 335 - return 0; 336 - } 337 - 338 - static int xfrmi4_rcv(struct sk_buff *skb) 339 - { 340 - return xfrmi_input(skb, ip_hdr(skb)->protocol, 0, 0, AF_INET); 341 - } 342 - 343 - static int xfrmi6_rcv(struct sk_buff *skb) 344 - { 345 - return xfrmi_input(skb, skb_network_header(skb)[IP6CB(skb)->nhoff], 346 - 0, 0, AF_INET6); 347 - } 348 - 349 - static int xfrmi4_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type) 350 - { 351 - return xfrmi_input(skb, nexthdr, spi, encap_type, AF_INET); 352 - } 353 - 354 - static int xfrmi6_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type) 355 - { 356 - return xfrmi_input(skb, nexthdr, spi, encap_type, AF_INET6); 357 - } 358 - 359 313 static int xfrmi_rcv_cb(struct sk_buff *skb, int err) 360 314 { 361 315 const struct xfrm_mode *inner_mode; ··· 945 991 }; 946 992 947 993 static struct xfrm6_protocol xfrmi_esp6_protocol __read_mostly = { 948 - .handler = xfrmi6_rcv, 949 - .input_handler = xfrmi6_input, 994 + .handler = xfrm6_rcv, 995 + .input_handler = xfrm_input, 950 996 .cb_handler = xfrmi_rcv_cb, 951 997 .err_handler = xfrmi6_err, 952 998 .priority = 10, ··· 996 1042 #endif 997 1043 998 1044 static struct xfrm4_protocol xfrmi_esp4_protocol __read_mostly = { 999 - .handler = xfrmi4_rcv, 1000 - .input_handler = xfrmi4_input, 1045 + .handler = xfrm4_rcv, 1046 + .input_handler = xfrm_input, 1001 1047 .cb_handler = xfrmi_rcv_cb, 1002 1048 .err_handler = xfrmi4_err, 1003 1049 .priority = 10,
+6 -14
net/xfrm/xfrm_policy.c
··· 3312 3312 3313 3313 static inline int 3314 3314 xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, 3315 - unsigned short family) 3315 + unsigned short family, u32 if_id) 3316 3316 { 3317 3317 if (xfrm_state_kern(x)) 3318 3318 return tmpl->optional && !xfrm_state_addr_cmp(tmpl, x, tmpl->encap_family); ··· 3323 3323 (tmpl->allalgs || (tmpl->aalgos & (1<<x->props.aalgo)) || 3324 3324 !(xfrm_id_proto_match(tmpl->id.proto, IPSEC_PROTO_ANY))) && 3325 3325 !(x->props.mode != XFRM_MODE_TRANSPORT && 3326 - xfrm_state_addr_cmp(tmpl, x, family)); 3326 + xfrm_state_addr_cmp(tmpl, x, family)) && 3327 + (if_id == 0 || if_id == x->if_id); 3327 3328 } 3328 3329 3329 3330 /* ··· 3336 3335 */ 3337 3336 static inline int 3338 3337 xfrm_policy_ok(const struct xfrm_tmpl *tmpl, const struct sec_path *sp, int start, 3339 - unsigned short family) 3338 + unsigned short family, u32 if_id) 3340 3339 { 3341 3340 int idx = start; 3342 3341 ··· 3346 3345 } else 3347 3346 start = -1; 3348 3347 for (; idx < sp->len; idx++) { 3349 - if (xfrm_state_ok(tmpl, sp->xvec[idx], family)) 3348 + if (xfrm_state_ok(tmpl, sp->xvec[idx], family, if_id)) 3350 3349 return ++idx; 3351 3350 if (sp->xvec[idx]->props.mode != XFRM_MODE_TRANSPORT) { 3352 3351 if (start == -1) ··· 3713 3712 } 3714 3713 xfrm_nr = ti; 3715 3714 3716 - if (net->xfrm.policy_default[dir] == XFRM_USERPOLICY_BLOCK && 3717 - !xfrm_nr) { 3718 - XFRM_INC_STATS(net, LINUX_MIB_XFRMINNOSTATES); 3719 - goto reject; 3720 - } 3721 - 3722 3715 if (npols > 1) { 3723 3716 xfrm_tmpl_sort(stp, tpp, xfrm_nr, family); 3724 3717 tpp = stp; ··· 3725 3730 * are implied between each two transformations. 3726 3731 */ 3727 3732 for (i = xfrm_nr-1, k = 0; i >= 0; i--) { 3728 - k = xfrm_policy_ok(tpp[i], sp, k, family); 3733 + k = xfrm_policy_ok(tpp[i], sp, k, family, if_id); 3729 3734 if (k < 0) { 3730 3735 if (k < -1) 3731 3736 /* "-2 - errored_index" returned */ ··· 3739 3744 XFRM_INC_STATS(net, LINUX_MIB_XFRMINTMPLMISMATCH); 3740 3745 goto reject; 3741 3746 } 3742 - 3743 - if (if_id) 3744 - secpath_reset(skb); 3745 3747 3746 3748 xfrm_pols_put(pols, npols); 3747 3749 return 1;
+10 -5
net/xfrm/xfrm_user.c
··· 1770 1770 } 1771 1771 1772 1772 static int validate_tmpl(int nr, struct xfrm_user_tmpl *ut, u16 family, 1773 - struct netlink_ext_ack *extack) 1773 + int dir, struct netlink_ext_ack *extack) 1774 1774 { 1775 1775 u16 prev_family; 1776 1776 int i; ··· 1796 1796 switch (ut[i].mode) { 1797 1797 case XFRM_MODE_TUNNEL: 1798 1798 case XFRM_MODE_BEET: 1799 + if (ut[i].optional && dir == XFRM_POLICY_OUT) { 1800 + NL_SET_ERR_MSG(extack, "Mode in optional template not allowed in outbound policy"); 1801 + return -EINVAL; 1802 + } 1799 1803 break; 1800 1804 default: 1801 1805 if (ut[i].family != prev_family) { ··· 1837 1833 } 1838 1834 1839 1835 static int copy_from_user_tmpl(struct xfrm_policy *pol, struct nlattr **attrs, 1840 - struct netlink_ext_ack *extack) 1836 + int dir, struct netlink_ext_ack *extack) 1841 1837 { 1842 1838 struct nlattr *rt = attrs[XFRMA_TMPL]; 1843 1839 ··· 1848 1844 int nr = nla_len(rt) / sizeof(*utmpl); 1849 1845 int err; 1850 1846 1851 - err = validate_tmpl(nr, utmpl, pol->family, extack); 1847 + err = validate_tmpl(nr, utmpl, pol->family, dir, extack); 1852 1848 if (err) 1853 1849 return err; 1854 1850 ··· 1925 1921 if (err) 1926 1922 goto error; 1927 1923 1928 - if (!(err = copy_from_user_tmpl(xp, attrs, extack))) 1924 + if (!(err = copy_from_user_tmpl(xp, attrs, p->dir, extack))) 1929 1925 err = copy_from_user_sec_ctx(xp, attrs); 1930 1926 if (err) 1931 1927 goto error; ··· 1984 1980 1985 1981 if (err) { 1986 1982 xfrm_dev_policy_delete(xp); 1983 + xfrm_dev_policy_free(xp); 1987 1984 security_xfrm_policy_free(xp->security); 1988 1985 kfree(xp); 1989 1986 return err; ··· 3504 3499 return NULL; 3505 3500 3506 3501 nr = ((len - sizeof(*p)) / sizeof(*ut)); 3507 - if (validate_tmpl(nr, ut, p->sel.family, NULL)) 3502 + if (validate_tmpl(nr, ut, p->sel.family, p->dir, NULL)) 3508 3503 return NULL; 3509 3504 3510 3505 if (p->dir > XFRM_POLICY_OUT)
+8 -8
sound/core/oss/pcm_plugin.h
··· 141 141 142 142 void *snd_pcm_plug_buf_alloc(struct snd_pcm_substream *plug, snd_pcm_uframes_t size); 143 143 void snd_pcm_plug_buf_unlock(struct snd_pcm_substream *plug, void *ptr); 144 + #else 145 + 146 + static inline snd_pcm_sframes_t snd_pcm_plug_client_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t drv_size) { return drv_size; } 147 + static inline snd_pcm_sframes_t snd_pcm_plug_slave_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t clt_size) { return clt_size; } 148 + static inline int snd_pcm_plug_slave_format(int format, const struct snd_mask *format_mask) { return format; } 149 + 150 + #endif 151 + 144 152 snd_pcm_sframes_t snd_pcm_oss_write3(struct snd_pcm_substream *substream, 145 153 const char *ptr, snd_pcm_uframes_t size, 146 154 int in_kernel); ··· 158 150 void **bufs, snd_pcm_uframes_t frames); 159 151 snd_pcm_sframes_t snd_pcm_oss_readv3(struct snd_pcm_substream *substream, 160 152 void **bufs, snd_pcm_uframes_t frames); 161 - 162 - #else 163 - 164 - static inline snd_pcm_sframes_t snd_pcm_plug_client_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t drv_size) { return drv_size; } 165 - static inline snd_pcm_sframes_t snd_pcm_plug_slave_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t clt_size) { return clt_size; } 166 - static inline int snd_pcm_plug_slave_format(int format, const struct snd_mask *format_mask) { return format; } 167 - 168 - #endif 169 153 170 154 #ifdef PLUGIN_DEBUG 171 155 #define pdprintf(fmt, args...) printk(KERN_DEBUG "plugin: " fmt, ##args)
+3 -1
sound/firewire/digi00x/digi00x-stream.c
··· 259 259 return err; 260 260 261 261 err = init_stream(dg00x, &dg00x->tx_stream); 262 - if (err < 0) 262 + if (err < 0) { 263 263 destroy_stream(dg00x, &dg00x->rx_stream); 264 + return err; 265 + } 264 266 265 267 err = amdtp_domain_init(&dg00x->domain); 266 268 if (err < 0) {
+1 -1
sound/pci/cs46xx/cs46xx_lib.c
··· 531 531 return err; 532 532 } 533 533 534 - int snd_cs46xx_download_image(struct snd_cs46xx *chip) 534 + static __maybe_unused int snd_cs46xx_download_image(struct snd_cs46xx *chip) 535 535 { 536 536 int idx, err; 537 537 unsigned int offset = 0;
+4 -3
sound/pci/hda/hda_generic.c
··· 1155 1155 return path && path->ctls[ctl_type]; 1156 1156 } 1157 1157 1158 - static const char * const channel_name[4] = { 1159 - "Front", "Surround", "CLFE", "Side" 1158 + static const char * const channel_name[] = { 1159 + "Front", "Surround", "CLFE", "Side", "Back", 1160 1160 }; 1161 1161 1162 1162 /* give some appropriate ctl name prefix for the given line out channel */ ··· 1182 1182 1183 1183 /* multi-io channels */ 1184 1184 if (ch >= cfg->line_outs) 1185 - return channel_name[ch]; 1185 + goto fixed_name; 1186 1186 1187 1187 switch (cfg->line_out_type) { 1188 1188 case AUTO_PIN_SPEAKER_OUT: ··· 1234 1234 if (cfg->line_outs == 1 && !spec->multi_ios) 1235 1235 return "Line Out"; 1236 1236 1237 + fixed_name: 1237 1238 if (ch >= ARRAY_SIZE(channel_name)) { 1238 1239 snd_BUG(); 1239 1240 return "PCM";
+5
sound/pci/hda/patch_hdmi.c
··· 4589 4589 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4590 4590 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4591 4591 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4592 + HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi), 4593 + HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi), 4594 + HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi), 4595 + HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi), 4596 + HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi), 4592 4597 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4593 4598 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4594 4599 HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
+32 -2
sound/pci/hda/patch_realtek.c
··· 7063 7063 ALC225_FIXUP_DELL1_MIC_NO_PRESENCE, 7064 7064 ALC295_FIXUP_DISABLE_DAC3, 7065 7065 ALC285_FIXUP_SPEAKER2_TO_DAC1, 7066 + ALC285_FIXUP_ASUS_SPEAKER2_TO_DAC1, 7067 + ALC285_FIXUP_ASUS_HEADSET_MIC, 7066 7068 ALC280_FIXUP_HP_HEADSET_MIC, 7067 7069 ALC221_FIXUP_HP_FRONT_MIC, 7068 7070 ALC292_FIXUP_TPT460, ··· 8034 8032 .v.func = alc285_fixup_speaker2_to_dac1, 8035 8033 .chained = true, 8036 8034 .chain_id = ALC269_FIXUP_THINKPAD_ACPI 8035 + }, 8036 + [ALC285_FIXUP_ASUS_SPEAKER2_TO_DAC1] = { 8037 + .type = HDA_FIXUP_FUNC, 8038 + .v.func = alc285_fixup_speaker2_to_dac1, 8039 + .chained = true, 8040 + .chain_id = ALC245_FIXUP_CS35L41_SPI_2 8041 + }, 8042 + [ALC285_FIXUP_ASUS_HEADSET_MIC] = { 8043 + .type = HDA_FIXUP_PINS, 8044 + .v.pins = (const struct hda_pintbl[]) { 8045 + { 0x19, 0x03a11050 }, 8046 + { 0x1b, 0x03a11c30 }, 8047 + { } 8048 + }, 8049 + .chained = true, 8050 + .chain_id = ALC285_FIXUP_ASUS_SPEAKER2_TO_DAC1 8037 8051 }, 8038 8052 [ALC256_FIXUP_DELL_INSPIRON_7559_SUBWOOFER] = { 8039 8053 .type = HDA_FIXUP_PINS, ··· 9381 9363 SND_PCI_QUIRK(0x103c, 0x802f, "HP Z240", ALC221_FIXUP_HP_MIC_NO_PRESENCE), 9382 9364 SND_PCI_QUIRK(0x103c, 0x8077, "HP", ALC256_FIXUP_HP_HEADSET_MIC), 9383 9365 SND_PCI_QUIRK(0x103c, 0x8158, "HP", ALC256_FIXUP_HP_HEADSET_MIC), 9384 - SND_PCI_QUIRK(0x103c, 0x820d, "HP Pavilion 15", ALC269_FIXUP_HP_MUTE_LED_MIC3), 9366 + SND_PCI_QUIRK(0x103c, 0x820d, "HP Pavilion 15", ALC295_FIXUP_HP_X360), 9385 9367 SND_PCI_QUIRK(0x103c, 0x8256, "HP", ALC221_FIXUP_HP_FRONT_MIC), 9386 9368 SND_PCI_QUIRK(0x103c, 0x827e, "HP x360", ALC295_FIXUP_HP_X360), 9387 9369 SND_PCI_QUIRK(0x103c, 0x827f, "HP x360", ALC269_FIXUP_HP_MUTE_LED_MIC3), ··· 9476 9458 SND_PCI_QUIRK(0x103c, 0x8aa3, "HP ProBook 450 G9 (MB 8AA1)", ALC236_FIXUP_HP_GPIO_LED), 9477 9459 SND_PCI_QUIRK(0x103c, 0x8aa8, "HP EliteBook 640 G9 (MB 8AA6)", ALC236_FIXUP_HP_GPIO_LED), 9478 9460 SND_PCI_QUIRK(0x103c, 0x8aab, "HP EliteBook 650 G9 (MB 8AA9)", ALC236_FIXUP_HP_GPIO_LED), 9479 - SND_PCI_QUIRK(0x103c, 0x8abb, "HP ZBook Firefly 14 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9461 + SND_PCI_QUIRK(0x103c, 0x8abb, "HP ZBook Firefly 14 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9480 9462 SND_PCI_QUIRK(0x103c, 0x8ad1, "HP EliteBook 840 14 inch G9 Notebook PC", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9481 9463 SND_PCI_QUIRK(0x103c, 0x8ad2, "HP EliteBook 860 16 inch G9 Notebook PC", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9482 9464 SND_PCI_QUIRK(0x103c, 0x8b42, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), ··· 9487 9469 SND_PCI_QUIRK(0x103c, 0x8b47, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9488 9470 SND_PCI_QUIRK(0x103c, 0x8b5d, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9489 9471 SND_PCI_QUIRK(0x103c, 0x8b5e, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9472 + SND_PCI_QUIRK(0x103c, 0x8b63, "HP Elite Dragonfly 13.5 inch G4", ALC245_FIXUP_CS35L41_SPI_4_HP_GPIO_LED), 9490 9473 SND_PCI_QUIRK(0x103c, 0x8b65, "HP ProBook 455 15.6 inch G10 Notebook PC", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9491 9474 SND_PCI_QUIRK(0x103c, 0x8b66, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9475 + SND_PCI_QUIRK(0x103c, 0x8b70, "HP EliteBook 835 G10", ALC287_FIXUP_CS35L41_I2C_2), 9476 + SND_PCI_QUIRK(0x103c, 0x8b72, "HP EliteBook 845 G10", ALC287_FIXUP_CS35L41_I2C_2), 9477 + SND_PCI_QUIRK(0x103c, 0x8b74, "HP EliteBook 845W G10", ALC287_FIXUP_CS35L41_I2C_2), 9478 + SND_PCI_QUIRK(0x103c, 0x8b77, "HP ElieBook 865 G10", ALC287_FIXUP_CS35L41_I2C_2), 9492 9479 SND_PCI_QUIRK(0x103c, 0x8b7a, "HP", ALC236_FIXUP_HP_GPIO_LED), 9493 9480 SND_PCI_QUIRK(0x103c, 0x8b7d, "HP", ALC236_FIXUP_HP_GPIO_LED), 9494 9481 SND_PCI_QUIRK(0x103c, 0x8b87, "HP", ALC236_FIXUP_HP_GPIO_LED), ··· 9503 9480 SND_PCI_QUIRK(0x103c, 0x8b8f, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9504 9481 SND_PCI_QUIRK(0x103c, 0x8b92, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9505 9482 SND_PCI_QUIRK(0x103c, 0x8b96, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9483 + SND_PCI_QUIRK(0x103c, 0x8b97, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9506 9484 SND_PCI_QUIRK(0x103c, 0x8bf0, "HP", ALC236_FIXUP_HP_GPIO_LED), 9485 + SND_PCI_QUIRK(0x103c, 0x8c26, "HP HP EliteBook 800G11", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9507 9486 SND_PCI_QUIRK(0x1043, 0x103e, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), 9508 9487 SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300), 9509 9488 SND_PCI_QUIRK(0x1043, 0x106d, "Asus K53BE", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), ··· 9525 9500 SND_PCI_QUIRK(0x1043, 0x1313, "Asus K42JZ", ALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE), 9526 9501 SND_PCI_QUIRK(0x1043, 0x13b0, "ASUS Z550SA", ALC256_FIXUP_ASUS_MIC), 9527 9502 SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_ASUS_ZENBOOK), 9503 + SND_PCI_QUIRK(0x1043, 0x1473, "ASUS GU604V", ALC285_FIXUP_ASUS_HEADSET_MIC), 9504 + SND_PCI_QUIRK(0x1043, 0x1483, "ASUS GU603V", ALC285_FIXUP_ASUS_HEADSET_MIC), 9528 9505 SND_PCI_QUIRK(0x1043, 0x1517, "Asus Zenbook UX31A", ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A), 9529 9506 SND_PCI_QUIRK(0x1043, 0x1662, "ASUS GV301QH", ALC294_FIXUP_ASUS_DUAL_SPK), 9530 9507 SND_PCI_QUIRK(0x1043, 0x1683, "ASUS UM3402YAR", ALC287_FIXUP_CS35L41_I2C_2), ··· 9549 9522 SND_PCI_QUIRK(0x1043, 0x1b13, "Asus U41SV", ALC269_FIXUP_INV_DMIC), 9550 9523 SND_PCI_QUIRK(0x1043, 0x1bbd, "ASUS Z550MA", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE), 9551 9524 SND_PCI_QUIRK(0x1043, 0x1c23, "Asus X55U", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), 9525 + SND_PCI_QUIRK(0x1043, 0x1c62, "ASUS GU603", ALC289_FIXUP_ASUS_GA401), 9552 9526 SND_PCI_QUIRK(0x1043, 0x1c92, "ASUS ROG Strix G15", ALC285_FIXUP_ASUS_G533Z_PINS), 9553 9527 SND_PCI_QUIRK(0x1043, 0x1ccd, "ASUS X555UB", ALC256_FIXUP_ASUS_MIC), 9554 9528 SND_PCI_QUIRK(0x1043, 0x1d42, "ASUS Zephyrus G14 2022", ALC289_FIXUP_ASUS_GA401), ··· 9646 9618 SND_PCI_QUIRK(0x1558, 0x7716, "Clevo NS50PU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9647 9619 SND_PCI_QUIRK(0x1558, 0x7717, "Clevo NS70PU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9648 9620 SND_PCI_QUIRK(0x1558, 0x7718, "Clevo L140PU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9621 + SND_PCI_QUIRK(0x1558, 0x7724, "Clevo L140AU", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9649 9622 SND_PCI_QUIRK(0x1558, 0x8228, "Clevo NR40BU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9650 9623 SND_PCI_QUIRK(0x1558, 0x8520, "Clevo NH50D[CD]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 9651 9624 SND_PCI_QUIRK(0x1558, 0x8521, "Clevo NH77D[CD]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), ··· 11692 11663 SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800), 11693 11664 SND_PCI_QUIRK(0x103c, 0x870c, "HP", ALC897_FIXUP_HP_HSMIC_VERB), 11694 11665 SND_PCI_QUIRK(0x103c, 0x8719, "HP", ALC897_FIXUP_HP_HSMIC_VERB), 11666 + SND_PCI_QUIRK(0x103c, 0x872b, "HP", ALC897_FIXUP_HP_HSMIC_VERB), 11695 11667 SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2), 11696 11668 SND_PCI_QUIRK(0x103c, 0x877e, "HP 288 Pro G6", ALC671_FIXUP_HP_HEADSET_MIC2), 11697 11669 SND_PCI_QUIRK(0x103c, 0x885f, "HP 288 Pro G8", ALC671_FIXUP_HP_HEADSET_MIC2),
+2 -1
sound/soc/codecs/cs35l56.c
··· 850 850 */ 851 851 if (cs35l56->sdw_peripheral) { 852 852 cs35l56->sdw_irq_no_unmask = true; 853 - cancel_work_sync(&cs35l56->sdw_irq_work); 853 + flush_work(&cs35l56->sdw_irq_work); 854 854 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0); 855 855 sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1); 856 856 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF); 857 + flush_work(&cs35l56->sdw_irq_work); 857 858 } 858 859 859 860 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_SHUTDOWN);
+14 -9
sound/soc/codecs/es8316.c
··· 52 52 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9600, 50, 1); 53 53 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_max_gain_tlv, -650, 150, 0); 54 54 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_min_gain_tlv, -1200, 150, 0); 55 - static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_target_tlv, -1650, 150, 0); 55 + 56 + static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(alc_target_tlv, 57 + 0, 10, TLV_DB_SCALE_ITEM(-1650, 150, 0), 58 + 11, 11, TLV_DB_SCALE_ITEM(-150, 0, 0), 59 + ); 60 + 56 61 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(hpmixer_gain_tlv, 57 62 0, 4, TLV_DB_SCALE_ITEM(-1200, 150, 0), 58 63 8, 11, TLV_DB_SCALE_ITEM(-450, 150, 0), ··· 120 115 alc_max_gain_tlv), 121 116 SOC_SINGLE_TLV("ALC Capture Min Volume", ES8316_ADC_ALC2, 0, 28, 0, 122 117 alc_min_gain_tlv), 123 - SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 10, 0, 118 + SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 11, 0, 124 119 alc_target_tlv), 125 120 SOC_SINGLE("ALC Capture Hold Time", ES8316_ADC_ALC3, 0, 10, 0), 126 121 SOC_SINGLE("ALC Capture Decay Time", ES8316_ADC_ALC4, 4, 10, 0), ··· 369 364 int count = 0; 370 365 371 366 es8316->sysclk = freq; 367 + es8316->sysclk_constraints.list = NULL; 368 + es8316->sysclk_constraints.count = 0; 372 369 373 - if (freq == 0) { 374 - es8316->sysclk_constraints.list = NULL; 375 - es8316->sysclk_constraints.count = 0; 376 - 370 + if (freq == 0) 377 371 return 0; 378 - } 379 372 380 373 ret = clk_set_rate(es8316->mclk, freq); 381 374 if (ret) ··· 389 386 es8316->allowed_rates[count++] = freq / ratio; 390 387 } 391 388 392 - es8316->sysclk_constraints.list = es8316->allowed_rates; 393 - es8316->sysclk_constraints.count = count; 389 + if (count) { 390 + es8316->sysclk_constraints.list = es8316->allowed_rates; 391 + es8316->sysclk_constraints.count = count; 392 + } 394 393 395 394 return 0; 396 395 }
-6
sound/soc/mediatek/mt8186/mt8186-afe-clk.c
··· 644 644 645 645 return 0; 646 646 } 647 - 648 - void mt8186_deinit_clock(void *priv) 649 - { 650 - struct mtk_base_afe *afe = priv; 651 - mt8186_audsys_clk_unregister(afe); 652 - }
-1
sound/soc/mediatek/mt8186/mt8186-afe-clk.h
··· 81 81 struct mtk_base_afe; 82 82 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, int clk_id); 83 83 int mt8186_init_clock(struct mtk_base_afe *afe); 84 - void mt8186_deinit_clock(void *priv); 85 84 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe); 86 85 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe); 87 86 int mt8186_afe_enable_clock(struct mtk_base_afe *afe);
-4
sound/soc/mediatek/mt8186/mt8186-afe-pcm.c
··· 2848 2848 return ret; 2849 2849 } 2850 2850 2851 - ret = devm_add_action_or_reset(dev, mt8186_deinit_clock, (void *)afe); 2852 - if (ret) 2853 - return ret; 2854 - 2855 2851 /* init memif */ 2856 2852 afe->memif_32bit_supported = 0; 2857 2853 afe->memif_size = MT8186_MEMIF_NUM;
+24 -22
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
··· 84 84 GATE_AUD2(CLK_AUD_ETDM_OUT1_BCLK, "aud_etdm_out1_bclk", "top_audio", 24), 85 85 }; 86 86 87 + static void mt8186_audsys_clk_unregister(void *data) 88 + { 89 + struct mtk_base_afe *afe = data; 90 + struct mt8186_afe_private *afe_priv = afe->platform_priv; 91 + struct clk *clk; 92 + struct clk_lookup *cl; 93 + int i; 94 + 95 + if (!afe_priv) 96 + return; 97 + 98 + for (i = 0; i < CLK_AUD_NR_CLK; i++) { 99 + cl = afe_priv->lookup[i]; 100 + if (!cl) 101 + continue; 102 + 103 + clk = cl->clk; 104 + clk_unregister_gate(clk); 105 + 106 + clkdev_drop(cl); 107 + } 108 + } 109 + 87 110 int mt8186_audsys_clk_register(struct mtk_base_afe *afe) 88 111 { 89 112 struct mt8186_afe_private *afe_priv = afe->platform_priv; ··· 147 124 afe_priv->lookup[i] = cl; 148 125 } 149 126 150 - return 0; 127 + return devm_add_action_or_reset(afe->dev, mt8186_audsys_clk_unregister, afe); 151 128 } 152 129 153 - void mt8186_audsys_clk_unregister(struct mtk_base_afe *afe) 154 - { 155 - struct mt8186_afe_private *afe_priv = afe->platform_priv; 156 - struct clk *clk; 157 - struct clk_lookup *cl; 158 - int i; 159 - 160 - if (!afe_priv) 161 - return; 162 - 163 - for (i = 0; i < CLK_AUD_NR_CLK; i++) { 164 - cl = afe_priv->lookup[i]; 165 - if (!cl) 166 - continue; 167 - 168 - clk = cl->clk; 169 - clk_unregister_gate(clk); 170 - 171 - clkdev_drop(cl); 172 - } 173 - }
-1
sound/soc/mediatek/mt8186/mt8186-audsys-clk.h
··· 10 10 #define _MT8186_AUDSYS_CLK_H_ 11 11 12 12 int mt8186_audsys_clk_register(struct mtk_base_afe *afe); 13 - void mt8186_audsys_clk_unregister(struct mtk_base_afe *afe); 14 13 15 14 #endif
+2 -2
sound/soc/sof/debug.c
··· 438 438 /* should we prevent DSP entering D3 ? */ 439 439 if (!sdev->ipc_dump_printed) 440 440 dev_info(sdev->dev, 441 - "preventing DSP entering D3 state to preserve context\n"); 442 - pm_runtime_get_noresume(sdev->dev); 441 + "Attempting to prevent DSP from entering D3 state to preserve context\n"); 442 + pm_runtime_get_if_in_use(sdev->dev); 443 443 } 444 444 445 445 /* dump vital information to the logs */
+87 -9
sound/soc/sof/intel/hda-mlink.c
··· 19 19 20 20 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_MLINK) 21 21 22 + /* worst-case number of sublinks is used for sublink refcount array allocation only */ 23 + #define HDAML_MAX_SUBLINKS (AZX_ML_LCTL_CPA_SHIFT - AZX_ML_LCTL_SPA_SHIFT) 24 + 22 25 /** 23 26 * struct hdac_ext2_link - HDAudio extended+alternate link 24 27 * ··· 36 33 * @leptr: extended link pointer 37 34 * @eml_lock: mutual exclusion to access shared registers e.g. CPA/SPA bits 38 35 * in LCTL register 36 + * @sublink_ref_count: array of refcounts, required to power-manage sublinks independently 39 37 * @base_ptr: pointer to shim/ip/shim_vs space 40 38 * @instance_offset: offset between each of @slcount instances managed by link 41 39 * @shim_offset: offset to SHIM register base ··· 57 53 u32 leptr; 58 54 59 55 struct mutex eml_lock; /* prevent concurrent access to e.g. CPA/SPA */ 56 + int sublink_ref_count[HDAML_MAX_SUBLINKS]; 60 57 61 58 /* internal values computed from LCAP contents */ 62 59 void __iomem *base_ptr; ··· 73 68 #define AZX_REG_SDW_SHIM_OFFSET 0x0 74 69 #define AZX_REG_SDW_IP_OFFSET 0x100 75 70 #define AZX_REG_SDW_VS_SHIM_OFFSET 0x6000 71 + #define AZX_REG_SDW_SHIM_PCMSyCM(y) (0x16 + 0x4 * (y)) 76 72 77 73 /* only one instance supported */ 78 74 #define AZX_REG_INTEL_DMIC_SHIM_OFFSET 0x0 ··· 97 91 */ 98 92 99 93 static int hdaml_lnk_enum(struct device *dev, struct hdac_ext2_link *h2link, 100 - void __iomem *ml_addr, int link_idx) 94 + void __iomem *remap_addr, void __iomem *ml_addr, int link_idx) 101 95 { 102 96 struct hdac_ext_link *hlink = &h2link->hext_link; 103 97 u32 base_offset; ··· 132 126 link_idx, h2link->slcount); 133 127 134 128 /* find IP ID and offsets */ 135 - h2link->leptr = readl(hlink->ml_addr + AZX_REG_ML_LEPTR); 129 + h2link->leptr = readl(ml_addr + AZX_REG_ML_LEPTR); 136 130 137 131 h2link->elid = FIELD_GET(AZX_REG_ML_LEPTR_ID, h2link->leptr); 138 132 139 133 base_offset = FIELD_GET(AZX_REG_ML_LEPTR_PTR, h2link->leptr); 140 - h2link->base_ptr = hlink->ml_addr + base_offset; 134 + h2link->base_ptr = remap_addr + base_offset; 141 135 142 136 switch (h2link->elid) { 143 137 case AZX_REG_ML_LEPTR_ID_SDW: 138 + h2link->instance_offset = AZX_REG_SDW_INSTANCE_OFFSET; 144 139 h2link->shim_offset = AZX_REG_SDW_SHIM_OFFSET; 145 140 h2link->ip_offset = AZX_REG_SDW_IP_OFFSET; 146 141 h2link->shim_vs_offset = AZX_REG_SDW_VS_SHIM_OFFSET; ··· 156 149 link_idx, base_offset); 157 150 break; 158 151 case AZX_REG_ML_LEPTR_ID_INTEL_SSP: 152 + h2link->instance_offset = AZX_REG_INTEL_SSP_INSTANCE_OFFSET; 159 153 h2link->shim_offset = AZX_REG_INTEL_SSP_SHIM_OFFSET; 160 154 h2link->ip_offset = AZX_REG_INTEL_SSP_IP_OFFSET; 161 155 h2link->shim_vs_offset = AZX_REG_INTEL_SSP_VS_SHIM_OFFSET; ··· 341 333 writel(val, lsdiid); 342 334 } 343 335 336 + static void hdaml_shim_map_stream_ch(u16 __iomem *pcmsycm, int lchan, int hchan, 337 + int stream_id, int dir) 338 + { 339 + u16 val; 340 + 341 + val = readw(pcmsycm); 342 + 343 + u16p_replace_bits(&val, lchan, GENMASK(3, 0)); 344 + u16p_replace_bits(&val, hchan, GENMASK(7, 4)); 345 + u16p_replace_bits(&val, stream_id, GENMASK(13, 8)); 346 + u16p_replace_bits(&val, dir, BIT(15)); 347 + 348 + writew(val, pcmsycm); 349 + } 350 + 344 351 static void hdaml_lctl_offload_enable(u32 __iomem *lctl, bool enable) 345 352 { 346 353 u32 val = readl(lctl); ··· 387 364 hlink->bus = bus; 388 365 hlink->ml_addr = bus->mlcap + AZX_ML_BASE + (AZX_ML_INTERVAL * index); 389 366 390 - ret = hdaml_lnk_enum(bus->dev, h2link, hlink->ml_addr, index); 367 + ret = hdaml_lnk_enum(bus->dev, h2link, bus->remap_addr, hlink->ml_addr, index); 391 368 if (ret < 0) { 392 369 kfree(h2link); 393 370 return ret; ··· 664 641 if (eml_lock) 665 642 mutex_lock(&h2link->eml_lock); 666 643 667 - if (++hlink->ref_count > 1) 668 - goto skip_init; 644 + if (!alt) { 645 + if (++hlink->ref_count > 1) 646 + goto skip_init; 647 + } else { 648 + if (++h2link->sublink_ref_count[sublink] > 1) 649 + goto skip_init; 650 + } 669 651 670 652 ret = hdaml_link_init(hlink->ml_addr + AZX_REG_ML_LCTL, sublink); 671 653 ··· 712 684 if (eml_lock) 713 685 mutex_lock(&h2link->eml_lock); 714 686 715 - if (--hlink->ref_count > 0) 716 - goto skip_shutdown; 717 - 687 + if (!alt) { 688 + if (--hlink->ref_count > 0) 689 + goto skip_shutdown; 690 + } else { 691 + if (--h2link->sublink_ref_count[sublink] > 0) 692 + goto skip_shutdown; 693 + } 718 694 ret = hdaml_link_shutdown(hlink->ml_addr + AZX_REG_ML_LCTL, sublink); 719 695 720 696 skip_shutdown: ··· 771 739 772 740 return 0; 773 741 } EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_set_lsdiid, SND_SOC_SOF_HDA_MLINK); 742 + 743 + /* 744 + * the 'y' parameter comes from the PCMSyCM hardware register naming. 'y' refers to the 745 + * PDI index, i.e. the FIFO used for RX or TX 746 + */ 747 + int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, 748 + int channel_mask, int stream_id, int dir) 749 + { 750 + struct hdac_ext2_link *h2link; 751 + u16 __iomem *pcmsycm; 752 + u16 val; 753 + 754 + h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 755 + if (!h2link) 756 + return -ENODEV; 757 + 758 + pcmsycm = h2link->base_ptr + h2link->shim_offset + 759 + h2link->instance_offset * sublink + 760 + AZX_REG_SDW_SHIM_PCMSyCM(y); 761 + 762 + mutex_lock(&h2link->eml_lock); 763 + 764 + hdaml_shim_map_stream_ch(pcmsycm, 0, hweight32(channel_mask), 765 + stream_id, dir); 766 + 767 + mutex_unlock(&h2link->eml_lock); 768 + 769 + val = readw(pcmsycm); 770 + 771 + dev_dbg(bus->dev, "channel_mask %#x stream_id %d dir %d pcmscm %#x\n", 772 + channel_mask, stream_id, dir, val); 773 + 774 + return 0; 775 + } EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_map_stream_ch, SND_SOC_SOF_HDA_MLINK); 774 776 775 777 void hda_bus_ml_put_all(struct hdac_bus *bus) 776 778 { ··· 901 835 return &h2link->hext_link; 902 836 } 903 837 EXPORT_SYMBOL_NS(hdac_bus_eml_dmic_get_hlink, SND_SOC_SOF_HDA_MLINK); 838 + 839 + struct hdac_ext_link *hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus) 840 + { 841 + struct hdac_ext2_link *h2link; 842 + 843 + h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 844 + if (!h2link) 845 + return NULL; 846 + 847 + return &h2link->hext_link; 848 + } 849 + EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_get_hlink, SND_SOC_SOF_HDA_MLINK); 904 850 905 851 int hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable) 906 852 {
+5 -2
sound/soc/sof/ipc3-topology.c
··· 2103 2103 * For the case of PAUSE/HW_FREE, since there are no quirks, flags can be used as is. 2104 2104 */ 2105 2105 2106 - if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) 2106 + if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) { 2107 + /* Clear stale command */ 2108 + config->flags &= ~SOF_DAI_CONFIG_FLAGS_CMD_MASK; 2107 2109 config->flags |= flags; 2108 - else 2110 + } else { 2109 2111 config->flags = flags; 2112 + } 2110 2113 2111 2114 /* only send the IPC if the widget is set up in the DSP */ 2112 2115 if (swidget->use_count > 0) {
+2 -2
sound/soc/sof/ipc4-topology.c
··· 57 57 audio_fmt.interleaving_style)}, 58 58 {SOF_TKN_CAVS_AUDIO_FORMAT_IN_FMT_CFG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 59 59 offsetof(struct sof_ipc4_pin_format, audio_fmt.fmt_cfg)}, 60 - {SOF_TKN_CAVS_AUDIO_FORMAT_PIN_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 60 + {SOF_TKN_CAVS_AUDIO_FORMAT_INPUT_PIN_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 61 61 offsetof(struct sof_ipc4_pin_format, pin_index)}, 62 62 {SOF_TKN_CAVS_AUDIO_FORMAT_IBS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 63 63 offsetof(struct sof_ipc4_pin_format, buffer_size)}, ··· 77 77 audio_fmt.interleaving_style)}, 78 78 {SOF_TKN_CAVS_AUDIO_FORMAT_OUT_FMT_CFG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 79 79 offsetof(struct sof_ipc4_pin_format, audio_fmt.fmt_cfg)}, 80 - {SOF_TKN_CAVS_AUDIO_FORMAT_PIN_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 80 + {SOF_TKN_CAVS_AUDIO_FORMAT_OUTPUT_PIN_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 81 81 offsetof(struct sof_ipc4_pin_format, pin_index)}, 82 82 {SOF_TKN_CAVS_AUDIO_FORMAT_OBS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 83 83 offsetof(struct sof_ipc4_pin_format, buffer_size)},
+9 -8
sound/soc/sof/pcm.c
··· 643 643 "%s/%s", 644 644 plat_data->tplg_filename_prefix, 645 645 plat_data->tplg_filename); 646 - if (!tplg_filename) 647 - return -ENOMEM; 648 - 649 - ret = snd_sof_load_topology(component, tplg_filename); 650 - if (ret < 0) { 651 - dev_err(component->dev, "error: failed to load DSP topology %d\n", 652 - ret); 653 - return ret; 646 + if (!tplg_filename) { 647 + ret = -ENOMEM; 648 + goto pm_error; 654 649 } 655 650 651 + ret = snd_sof_load_topology(component, tplg_filename); 652 + if (ret < 0) 653 + dev_err(component->dev, "error: failed to load DSP topology %d\n", 654 + ret); 655 + 656 + pm_error: 656 657 pm_runtime_mark_last_busy(component->dev); 657 658 pm_runtime_put_autosuspend(component->dev); 658 659
+13 -1
sound/soc/sof/pm.c
··· 164 164 ret = tplg_ops->set_up_all_pipelines(sdev, false); 165 165 if (ret < 0) { 166 166 dev_err(sdev->dev, "Failed to restore pipeline after resume %d\n", ret); 167 - return ret; 167 + goto setup_fail; 168 168 } 169 169 } 170 170 ··· 177 177 if (ret < 0) 178 178 dev_err(sdev->dev, "ctx_restore IPC error during resume: %d\n", ret); 179 179 } 180 + 181 + setup_fail: 182 + #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) 183 + if (ret < 0) { 184 + /* 185 + * Debugfs cannot be read in runtime suspend, so cache 186 + * the contents upon failure. This allows to capture 187 + * possible DSP coredump information. 188 + */ 189 + sof_cache_debugfs(sdev); 190 + } 191 + #endif 180 192 181 193 return ret; 182 194 }
+8 -6
sound/soc/sof/sof-client-probes.c
··· 218 218 219 219 ret = ipc->points_info(cdev, &desc, &num_desc); 220 220 if (ret < 0) 221 - goto exit; 222 - 223 - pm_runtime_mark_last_busy(dev); 224 - err = pm_runtime_put_autosuspend(dev); 225 - if (err < 0) 226 - dev_err_ratelimited(dev, "debugfs read failed to idle %d\n", err); 221 + goto pm_error; 227 222 228 223 for (i = 0; i < num_desc; i++) { 229 224 offset = strlen(buf); ··· 236 241 ret = simple_read_from_buffer(to, count, ppos, buf, strlen(buf)); 237 242 238 243 kfree(desc); 244 + 245 + pm_error: 246 + pm_runtime_mark_last_busy(dev); 247 + err = pm_runtime_put_autosuspend(dev); 248 + if (err < 0) 249 + dev_err_ratelimited(dev, "debugfs read failed to idle %d\n", err); 250 + 239 251 exit: 240 252 kfree(buf); 241 253 return ret;
+5 -1
sound/soc/sof/topology.c
··· 586 586 if (*num_copied_tuples == tuples_size) 587 587 return 0; 588 588 } 589 + 590 + /* stop when we've found the required token instances */ 591 + if (found == num_tokens * token_instance_num) 592 + return 0; 589 593 } 590 594 591 595 /* next array */ ··· 1265 1261 if (num_sets > 1) { 1266 1262 struct snd_sof_tuple *new_tuples; 1267 1263 1268 - num_tuples += token_list[object_token_list[i]].count * num_sets; 1264 + num_tuples += token_list[object_token_list[i]].count * (num_sets - 1); 1269 1265 new_tuples = krealloc(swidget->tuples, 1270 1266 sizeof(*new_tuples) * num_tuples, GFP_KERNEL); 1271 1267 if (!new_tuples) {
+1
sound/usb/format.c
··· 423 423 case USB_ID(0x0e41, 0x4248): /* Line6 Helix >= fw 2.82 */ 424 424 case USB_ID(0x0e41, 0x4249): /* Line6 Helix Rack >= fw 2.82 */ 425 425 case USB_ID(0x0e41, 0x424a): /* Line6 Helix LT >= fw 2.82 */ 426 + case USB_ID(0x0e41, 0x424b): /* Line6 Pod Go */ 426 427 case USB_ID(0x19f7, 0x0011): /* Rode Rodecaster Pro */ 427 428 return set_fixed_rate(fp, 48000, SNDRV_PCM_RATE_48000); 428 429 }
+36
tools/arch/arm64/include/uapi/asm/kvm.h
··· 198 198 __u64 reserved[2]; 199 199 }; 200 200 201 + /* 202 + * Counter/Timer offset structure. Describe the virtual/physical offset. 203 + * To be used with KVM_ARM_SET_COUNTER_OFFSET. 204 + */ 205 + struct kvm_arm_counter_offset { 206 + __u64 counter_offset; 207 + __u64 reserved; 208 + }; 209 + 201 210 #define KVM_ARM_TAGS_TO_GUEST 0 202 211 #define KVM_ARM_TAGS_FROM_GUEST 1 203 212 ··· 381 372 #endif 382 373 }; 383 374 375 + /* Device Control API on vm fd */ 376 + #define KVM_ARM_VM_SMCCC_CTRL 0 377 + #define KVM_ARM_VM_SMCCC_FILTER 0 378 + 384 379 /* Device Control API: ARM VGIC */ 385 380 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 386 381 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 ··· 424 411 #define KVM_ARM_VCPU_TIMER_CTRL 1 425 412 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 426 413 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 414 + #define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 415 + #define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 427 416 #define KVM_ARM_VCPU_PVTIME_CTRL 2 428 417 #define KVM_ARM_VCPU_PVTIME_IPA 0 429 418 ··· 483 468 484 469 /* run->fail_entry.hardware_entry_failure_reason codes. */ 485 470 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 471 + 472 + enum kvm_smccc_filter_action { 473 + KVM_SMCCC_FILTER_HANDLE = 0, 474 + KVM_SMCCC_FILTER_DENY, 475 + KVM_SMCCC_FILTER_FWD_TO_USER, 476 + 477 + #ifdef __KERNEL__ 478 + NR_SMCCC_FILTER_ACTIONS 479 + #endif 480 + }; 481 + 482 + struct kvm_smccc_filter { 483 + __u32 base; 484 + __u32 nr_functions; 485 + __u8 action; 486 + __u8 pad[15]; 487 + }; 488 + 489 + /* arm64-specific KVM_EXIT_HYPERCALL flags */ 490 + #define KVM_HYPERCALL_EXIT_SMC (1U << 0) 491 + #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) 486 492 487 493 #endif 488 494
+21 -5
tools/arch/x86/include/asm/cpufeatures.h
··· 97 97 #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ 98 98 #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ 99 99 #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ 100 - #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ 100 + /* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ 101 101 #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ 102 102 #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ 103 103 #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ ··· 226 226 227 227 /* Virtualization flags: Linux defined, word 8 */ 228 228 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ 229 - #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ 230 - #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ 231 - #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ 232 - #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ 229 + #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 1) /* Intel FlexPriority */ 230 + #define X86_FEATURE_EPT ( 8*32+ 2) /* Intel Extended Page Table */ 231 + #define X86_FEATURE_VPID ( 8*32+ 3) /* Intel Virtual Processor ID */ 233 232 234 233 #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ 235 234 #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ ··· 306 307 #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */ 307 308 #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ 308 309 #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ 310 + #define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */ 311 + #define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */ 309 312 310 313 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ 311 314 #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ 312 315 #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ 313 316 #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ 317 + #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */ 318 + #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ 319 + #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ 320 + #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ 314 321 #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ 315 322 #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ 316 323 #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ 324 + #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ 317 325 318 326 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ 319 327 #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ ··· 337 331 #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ 338 332 #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ 339 333 #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ 334 + #define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */ 340 335 #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ 341 336 #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ 342 337 ··· 370 363 #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ 371 364 #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */ 372 365 #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ 366 + #define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */ 373 367 #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */ 374 368 375 369 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ ··· 435 427 #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ 436 428 #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ 437 429 430 + /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ 431 + #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ 432 + #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ 433 + #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */ 434 + #define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" Automatic IBRS */ 435 + #define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */ 436 + 438 437 /* 439 438 * BUG word(s) 440 439 */ ··· 482 467 #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */ 483 468 #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */ 484 469 #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */ 470 + #define X86_BUG_SMT_RSB X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */ 485 471 486 472 #endif /* _ASM_X86_CPUFEATURES_H */
+7 -1
tools/arch/x86/include/asm/disabled-features.h
··· 75 75 # define DISABLE_CALL_DEPTH_TRACKING (1 << (X86_FEATURE_CALL_DEPTH & 31)) 76 76 #endif 77 77 78 + #ifdef CONFIG_ADDRESS_MASKING 79 + # define DISABLE_LAM 0 80 + #else 81 + # define DISABLE_LAM (1 << (X86_FEATURE_LAM & 31)) 82 + #endif 83 + 78 84 #ifdef CONFIG_INTEL_IOMMU_SVM 79 85 # define DISABLE_ENQCMD 0 80 86 #else ··· 121 115 #define DISABLED_MASK10 0 122 116 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ 123 117 DISABLE_CALL_DEPTH_TRACKING) 124 - #define DISABLED_MASK12 0 118 + #define DISABLED_MASK12 (DISABLE_LAM) 125 119 #define DISABLED_MASK13 0 126 120 #define DISABLED_MASK14 0 127 121 #define DISABLED_MASK15 0
+2
tools/arch/x86/include/asm/msr-index.h
··· 206 206 207 207 /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 208 208 #define MSR_INTEGRITY_CAPS 0x000002d9 209 + #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 210 + #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) 209 211 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 210 212 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 211 213
+3
tools/arch/x86/include/uapi/asm/kvm.h
··· 559 559 #define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */ 560 560 #define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */ 561 561 562 + /* x86-specific KVM_EXIT_HYPERCALL flags. */ 563 + #define KVM_EXIT_HYPERCALL_LONG_MODE BIT(0) 564 + 562 565 #endif /* _ASM_X86_KVM_H */
+8
tools/arch/x86/include/uapi/asm/prctl.h
··· 16 16 #define ARCH_GET_XCOMP_GUEST_PERM 0x1024 17 17 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 18 18 19 + #define ARCH_XCOMP_TILECFG 17 20 + #define ARCH_XCOMP_TILEDATA 18 21 + 19 22 #define ARCH_MAP_VDSO_X32 0x2001 20 23 #define ARCH_MAP_VDSO_32 0x2002 21 24 #define ARCH_MAP_VDSO_64 0x2003 25 + 26 + #define ARCH_GET_UNTAG_MASK 0x4001 27 + #define ARCH_ENABLE_TAGGED_ADDR 0x4002 28 + #define ARCH_GET_MAX_TAG_BITS 0x4003 29 + #define ARCH_FORCE_TAGGED_SVA 0x4004 22 30 23 31 #endif /* _ASM_X86_PRCTL_H */
+3
tools/arch/x86/include/uapi/asm/unistd_32.h
··· 2 2 #ifndef __NR_fork 3 3 #define __NR_fork 2 4 4 #endif 5 + #ifndef __NR_execve 6 + #define __NR_execve 11 7 + #endif 5 8 #ifndef __NR_getppid 6 9 #define __NR_getppid 64 7 10 #endif
+10 -24
tools/arch/x86/lib/memcpy_64.S
··· 10 10 .section .noinstr.text, "ax" 11 11 12 12 /* 13 - * We build a jump to memcpy_orig by default which gets NOPped out on 14 - * the majority of x86 CPUs which set REP_GOOD. In addition, CPUs which 15 - * have the enhanced REP MOVSB/STOSB feature (ERMS), change those NOPs 16 - * to a jmp to memcpy_erms which does the REP; MOVSB mem copy. 17 - */ 18 - 19 - /* 20 13 * memcpy - Copy a memory block. 21 14 * 22 15 * Input: ··· 19 26 * 20 27 * Output: 21 28 * rax original destination 29 + * 30 + * The FSRM alternative should be done inline (avoiding the call and 31 + * the disgusting return handling), but that would require some help 32 + * from the compiler for better calling conventions. 33 + * 34 + * The 'rep movsb' itself is small enough to replace the call, but the 35 + * two register moves blow up the code. And one of them is "needed" 36 + * only for the return value that is the same as the source input, 37 + * which the compiler could/should do much better anyway. 22 38 */ 23 39 SYM_TYPED_FUNC_START(__memcpy) 24 - ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \ 25 - "jmp memcpy_erms", X86_FEATURE_ERMS 40 + ALTERNATIVE "jmp memcpy_orig", "", X86_FEATURE_FSRM 26 41 27 42 movq %rdi, %rax 28 43 movq %rdx, %rcx 29 - shrq $3, %rcx 30 - andl $7, %edx 31 - rep movsq 32 - movl %edx, %ecx 33 44 rep movsb 34 45 RET 35 46 SYM_FUNC_END(__memcpy) ··· 41 44 42 45 SYM_FUNC_ALIAS(memcpy, __memcpy) 43 46 EXPORT_SYMBOL(memcpy) 44 - 45 - /* 46 - * memcpy_erms() - enhanced fast string memcpy. This is faster and 47 - * simpler than memcpy. Use memcpy_erms when possible. 48 - */ 49 - SYM_FUNC_START_LOCAL(memcpy_erms) 50 - movq %rdi, %rax 51 - movq %rdx, %rcx 52 - rep movsb 53 - RET 54 - SYM_FUNC_END(memcpy_erms) 55 47 56 48 SYM_FUNC_START_LOCAL(memcpy_orig) 57 49 movq %rdi, %rax
+11 -36
tools/arch/x86/lib/memset_64.S
··· 18 18 * rdx count (bytes) 19 19 * 20 20 * rax original destination 21 + * 22 + * The FSRS alternative should be done inline (avoiding the call and 23 + * the disgusting return handling), but that would require some help 24 + * from the compiler for better calling conventions. 25 + * 26 + * The 'rep stosb' itself is small enough to replace the call, but all 27 + * the register moves blow up the code. And two of them are "needed" 28 + * only for the return value that is the same as the source input, 29 + * which the compiler could/should do much better anyway. 21 30 */ 22 31 SYM_FUNC_START(__memset) 23 - /* 24 - * Some CPUs support enhanced REP MOVSB/STOSB feature. It is recommended 25 - * to use it when possible. If not available, use fast string instructions. 26 - * 27 - * Otherwise, use original memset function. 28 - */ 29 - ALTERNATIVE_2 "jmp memset_orig", "", X86_FEATURE_REP_GOOD, \ 30 - "jmp memset_erms", X86_FEATURE_ERMS 32 + ALTERNATIVE "jmp memset_orig", "", X86_FEATURE_FSRS 31 33 32 34 movq %rdi,%r9 35 + movb %sil,%al 33 36 movq %rdx,%rcx 34 - andl $7,%edx 35 - shrq $3,%rcx 36 - /* expand byte value */ 37 - movzbl %sil,%esi 38 - movabs $0x0101010101010101,%rax 39 - imulq %rsi,%rax 40 - rep stosq 41 - movl %edx,%ecx 42 37 rep stosb 43 38 movq %r9,%rax 44 39 RET ··· 42 47 43 48 SYM_FUNC_ALIAS(memset, __memset) 44 49 EXPORT_SYMBOL(memset) 45 - 46 - /* 47 - * ISO C memset - set a memory block to a byte value. This function uses 48 - * enhanced rep stosb to override the fast string function. 49 - * The code is simpler and shorter than the fast string function as well. 50 - * 51 - * rdi destination 52 - * rsi value (char) 53 - * rdx count (bytes) 54 - * 55 - * rax original destination 56 - */ 57 - SYM_FUNC_START_LOCAL(memset_erms) 58 - movq %rdi,%r9 59 - movb %sil,%al 60 - movq %rdx,%rcx 61 - rep stosb 62 - movq %r9,%rax 63 - RET 64 - SYM_FUNC_END(memset_erms) 65 50 66 51 SYM_FUNC_START_LOCAL(memset_orig) 67 52 movq %rdi,%r10
+1 -2
tools/include/asm/alternative.h
··· 4 4 5 5 /* Just disable it so we can build arch/x86/lib/memcpy_64.S for perf bench: */ 6 6 7 - #define altinstruction_entry # 8 - #define ALTERNATIVE_2 # 7 + #define ALTERNATIVE # 9 8 10 9 #endif
+55 -2
tools/include/uapi/drm/drm.h
··· 972 972 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 973 973 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 974 974 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 975 + /** 976 + * DRM_IOCTL_GEM_CLOSE - Close a GEM handle. 977 + * 978 + * GEM handles are not reference-counted by the kernel. User-space is 979 + * responsible for managing their lifetime. For example, if user-space imports 980 + * the same memory object twice on the same DRM file description, the same GEM 981 + * handle is returned by both imports, and user-space needs to ensure 982 + * &DRM_IOCTL_GEM_CLOSE is performed once only. The same situation can happen 983 + * when a memory object is allocated, then exported and imported again on the 984 + * same DRM file description. The &DRM_IOCTL_MODE_GETFB2 IOCTL is an exception 985 + * and always returns fresh new GEM handles even if an existing GEM handle 986 + * already refers to the same memory object before the IOCTL is performed. 987 + */ 975 988 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 976 989 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 977 990 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) ··· 1025 1012 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 1026 1013 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 1027 1014 1015 + /** 1016 + * DRM_IOCTL_PRIME_HANDLE_TO_FD - Convert a GEM handle to a DMA-BUF FD. 1017 + * 1018 + * User-space sets &drm_prime_handle.handle with the GEM handle to export and 1019 + * &drm_prime_handle.flags, and gets back a DMA-BUF file descriptor in 1020 + * &drm_prime_handle.fd. 1021 + * 1022 + * The export can fail for any driver-specific reason, e.g. because export is 1023 + * not supported for this specific GEM handle (but might be for others). 1024 + * 1025 + * Support for exporting DMA-BUFs is advertised via &DRM_PRIME_CAP_EXPORT. 1026 + */ 1028 1027 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 1028 + /** 1029 + * DRM_IOCTL_PRIME_FD_TO_HANDLE - Convert a DMA-BUF FD to a GEM handle. 1030 + * 1031 + * User-space sets &drm_prime_handle.fd with a DMA-BUF file descriptor to 1032 + * import, and gets back a GEM handle in &drm_prime_handle.handle. 1033 + * &drm_prime_handle.flags is unused. 1034 + * 1035 + * If an existing GEM handle refers to the memory object backing the DMA-BUF, 1036 + * that GEM handle is returned. Therefore user-space which needs to handle 1037 + * arbitrary DMA-BUFs must have a user-space lookup data structure to manually 1038 + * reference-count duplicated GEM handles. For more information see 1039 + * &DRM_IOCTL_GEM_CLOSE. 1040 + * 1041 + * The import can fail for any driver-specific reason, e.g. because import is 1042 + * only supported for DMA-BUFs allocated on this DRM device. 1043 + * 1044 + * Support for importing DMA-BUFs is advertised via &DRM_PRIME_CAP_IMPORT. 1045 + */ 1029 1046 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 1030 1047 1031 1048 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) ··· 1147 1104 * struct as the output. 1148 1105 * 1149 1106 * If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles 1150 - * will be filled with GEM buffer handles. Planes are valid until one has a 1151 - * zero handle -- this can be used to compute the number of planes. 1107 + * will be filled with GEM buffer handles. Fresh new GEM handles are always 1108 + * returned, even if another GEM handle referring to the same memory object 1109 + * already exists on the DRM file description. The caller is responsible for 1110 + * removing the new handles, e.g. via the &DRM_IOCTL_GEM_CLOSE IOCTL. The same 1111 + * new handle will be returned for multiple planes in case they use the same 1112 + * memory object. Planes are valid until one has a zero handle -- this can be 1113 + * used to compute the number of planes. 1152 1114 * 1153 1115 * Otherwise, &drm_mode_fb_cmd2.handles will be zeroed and planes are valid 1154 1116 * until one has a zero &drm_mode_fb_cmd2.pitches. ··· 1161 1113 * If the framebuffer has a format modifier, &DRM_MODE_FB_MODIFIERS will be set 1162 1114 * in &drm_mode_fb_cmd2.flags and &drm_mode_fb_cmd2.modifier will contain the 1163 1115 * modifier. Otherwise, user-space must ignore &drm_mode_fb_cmd2.modifier. 1116 + * 1117 + * To obtain DMA-BUF FDs for each plane without leaking GEM handles, user-space 1118 + * can export each handle via &DRM_IOCTL_PRIME_HANDLE_TO_FD, then immediately 1119 + * close each unique handle via &DRM_IOCTL_GEM_CLOSE, making sure to not 1120 + * double-close handles which are specified multiple times in the array. 1164 1121 */ 1165 1122 #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) 1166 1123
+24 -1
tools/include/uapi/drm/i915_drm.h
··· 2491 2491 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 2492 2492 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 2493 2493 #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ 2494 - struct i915_engine_class_instance engines[0]; 2494 + struct i915_engine_class_instance engines[]; 2495 2495 } __attribute__((packed)); 2496 2496 2497 2497 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ ··· 2676 2676 I915_OAR_FORMAT_A32u40_A4u32_B8_C8, 2677 2677 I915_OA_FORMAT_A24u40_A14u32_B8_C8, 2678 2678 2679 + /* MTL OAM */ 2680 + I915_OAM_FORMAT_MPEC8u64_B8_C8, 2681 + I915_OAM_FORMAT_MPEC8u32_B8_C8, 2682 + 2679 2683 I915_OA_FORMAT_MAX /* non-ABI */ 2680 2684 }; 2681 2685 ··· 2761 2757 * This property is available in perf revision 5. 2762 2758 */ 2763 2759 DRM_I915_PERF_PROP_POLL_OA_PERIOD, 2760 + 2761 + /** 2762 + * Multiple engines may be mapped to the same OA unit. The OA unit is 2763 + * identified by class:instance of any engine mapped to it. 2764 + * 2765 + * This parameter specifies the engine class and must be passed along 2766 + * with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE. 2767 + * 2768 + * This property is available in perf revision 6. 2769 + */ 2770 + DRM_I915_PERF_PROP_OA_ENGINE_CLASS, 2771 + 2772 + /** 2773 + * This parameter specifies the engine instance and must be passed along 2774 + * with DRM_I915_PERF_PROP_OA_ENGINE_CLASS. 2775 + * 2776 + * This property is available in perf revision 6. 2777 + */ 2778 + DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE, 2764 2779 2765 2780 DRM_I915_PERF_PROP_MAX /* non-ABI */ 2766 2781 };
+1 -1
tools/include/uapi/linux/const.h
··· 28 28 #define _BITUL(x) (_UL(1) << (x)) 29 29 #define _BITULL(x) (_ULL(1) << (x)) 30 30 31 - #define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) 31 + #define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - 1) 32 32 #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) 33 33 34 34 #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+1
tools/include/uapi/linux/in.h
··· 162 162 #define MCAST_MSFILTER 48 163 163 #define IP_MULTICAST_ALL 49 164 164 #define IP_UNICAST_IF 50 165 + #define IP_LOCAL_PORT_RANGE 51 165 166 166 167 #define MCAST_EXCLUDE 0 167 168 #define MCAST_INCLUDE 1
+10 -2
tools/include/uapi/linux/kvm.h
··· 341 341 __u64 nr; 342 342 __u64 args[6]; 343 343 __u64 ret; 344 - __u32 longmode; 345 - __u32 pad; 344 + 345 + union { 346 + #ifndef __KERNEL__ 347 + __u32 longmode; 348 + #endif 349 + __u64 flags; 350 + }; 346 351 } hypercall; 347 352 /* KVM_EXIT_TPR_ACCESS */ 348 353 struct { ··· 1189 1184 #define KVM_CAP_S390_PROTECTED_ASYNC_DISABLE 224 1190 1185 #define KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP 225 1191 1186 #define KVM_CAP_PMU_EVENT_MASKED_EVENTS 226 1187 + #define KVM_CAP_COUNTER_OFFSET 227 1192 1188 1193 1189 #ifdef KVM_CAP_IRQ_ROUTING 1194 1190 ··· 1549 1543 #define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter) 1550 1544 #define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3) 1551 1545 #define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte_tags) 1546 + /* Available with KVM_CAP_COUNTER_OFFSET */ 1547 + #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_counter_offset) 1552 1548 1553 1549 /* ioctl for vm fd */ 1554 1550 #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
+2
tools/include/uapi/linux/prctl.h
··· 290 290 #define PR_SET_VMA 0x53564d41 291 291 # define PR_SET_VMA_ANON_NAME 0 292 292 293 + #define PR_GET_AUXV 0x41555856 294 + 293 295 #define PR_SET_MEMORY_MERGE 67 294 296 #define PR_GET_MEMORY_MERGE 68 295 297 #endif /* _LINUX_PRCTL_H */
+10 -4
tools/include/uapi/sound/asound.h
··· 429 429 snd_pcm_uframes_t avail_min; /* min avail frames for wakeup */ 430 430 snd_pcm_uframes_t xfer_align; /* obsolete: xfer size need to be a multiple */ 431 431 snd_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */ 432 - snd_pcm_uframes_t stop_threshold; /* min avail frames for automatic stop */ 433 - snd_pcm_uframes_t silence_threshold; /* min distance from noise for silence filling */ 434 - snd_pcm_uframes_t silence_size; /* silence block size */ 432 + /* 433 + * The following two thresholds alleviate playback buffer underruns; when 434 + * hw_avail drops below the threshold, the respective action is triggered: 435 + */ 436 + snd_pcm_uframes_t stop_threshold; /* - stop playback */ 437 + snd_pcm_uframes_t silence_threshold; /* - pre-fill buffer with silence */ 438 + snd_pcm_uframes_t silence_size; /* max size of silence pre-fill; when >= boundary, 439 + * fill played area with silence immediately */ 435 440 snd_pcm_uframes_t boundary; /* pointers wrap point */ 436 441 unsigned int proto; /* protocol version */ 437 442 unsigned int tstamp_type; /* timestamp type (req. proto >= 2.0.12) */ ··· 575 570 struct __snd_pcm_mmap_control64 { 576 571 __pad_before_uframe __pad1; 577 572 snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ 578 - __pad_before_uframe __pad2; 573 + __pad_before_uframe __pad2; // This should be __pad_after_uframe, but binary 574 + // backwards compatibility constraints prevent a fix. 579 575 580 576 __pad_before_uframe __pad3; 581 577 snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */
+6
tools/perf/Makefile.config
··· 216 216 dummy := $(error Error: $(BISON) is missing on this system, please install it) 217 217 endif 218 218 219 + ifeq ($(BUILD_BPF_SKEL),1) 220 + ifeq ($(call get-executable,$(CLANG)),) 221 + dummy := $(error $(CLANG) is missing on this system, please install it to be able to build with BUILD_BPF_SKEL=1) 222 + endif 223 + endif 224 + 219 225 ifneq ($(OUTPUT),) 220 226 ifeq ($(shell expr $(shell $(BISON) --version | grep bison | sed -e 's/.\+ \([0-9]\+\).\([0-9]\+\).\([0-9]\+\)/\1\2\3/g') \>\= 371), 1) 221 227 BISON_FILE_PREFIX_MAP := --file-prefix-map=$(OUTPUT)=
+20 -2
tools/perf/Makefile.perf
··· 1057 1057 1058 1058 ifdef BUILD_BPF_SKEL 1059 1059 BPFTOOL := $(SKEL_TMP_OUT)/bootstrap/bpftool 1060 - BPF_INCLUDE := -I$(SKEL_TMP_OUT)/.. -I$(LIBBPF_INCLUDE) 1060 + # Get Clang's default includes on this system, as opposed to those seen by 1061 + # '-target bpf'. This fixes "missing" files on some architectures/distros, 1062 + # such as asm/byteorder.h, asm/socket.h, asm/sockios.h, sys/cdefs.h etc. 1063 + # 1064 + # Use '-idirafter': Don't interfere with include mechanics except where the 1065 + # build would have failed anyways. 1066 + define get_sys_includes 1067 + $(shell $(1) $(2) -v -E - </dev/null 2>&1 \ 1068 + | sed -n '/<...> search starts here:/,/End of search list./{ s| \(/.*\)|-idirafter \1|p }') \ 1069 + $(shell $(1) $(2) -dM -E - </dev/null | grep '__riscv_xlen ' | awk '{printf("-D__riscv_xlen=%d -D__BITS_PER_LONG=%d", $$3, $$3)}') 1070 + endef 1071 + 1072 + ifneq ($(CROSS_COMPILE),) 1073 + CLANG_TARGET_ARCH = --target=$(notdir $(CROSS_COMPILE:%-=%)) 1074 + endif 1075 + 1076 + CLANG_SYS_INCLUDES = $(call get_sys_includes,$(CLANG),$(CLANG_TARGET_ARCH)) 1077 + BPF_INCLUDE := -I$(SKEL_TMP_OUT)/.. -I$(LIBBPF_INCLUDE) $(CLANG_SYS_INCLUDES) 1078 + TOOLS_UAPI_INCLUDE := -I$(srctree)/tools/include/uapi 1061 1079 1062 1080 $(BPFTOOL): | $(SKEL_TMP_OUT) 1063 1081 $(Q)CFLAGS= $(MAKE) -C ../bpf/bpftool \ 1064 1082 OUTPUT=$(SKEL_TMP_OUT)/ bootstrap 1065 1083 1066 1084 $(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) | $(SKEL_TMP_OUT) 1067 - $(QUIET_CLANG)$(CLANG) -g -O2 -target bpf -Wall -Werror $(BPF_INCLUDE) \ 1085 + $(QUIET_CLANG)$(CLANG) -g -O2 -target bpf -Wall -Werror $(BPF_INCLUDE) $(TOOLS_UAPI_INCLUDE) \ 1068 1086 -c $(filter util/bpf_skel/%.bpf.c,$^) -o $@ && $(LLVM_STRIP) -g $@ 1069 1087 1070 1088 $(SKEL_OUT)/%.skel.h: $(SKEL_TMP_OUT)/%.bpf.o | $(BPFTOOL)
+4 -5
tools/perf/arch/arm/util/cs-etm.c
··· 78 78 char path[PATH_MAX]; 79 79 int err; 80 80 u32 val; 81 - u64 contextid = 82 - evsel->core.attr.config & 83 - (perf_pmu__format_bits(&cs_etm_pmu->format, "contextid1") | 81 + u64 contextid = evsel->core.attr.config & 82 + (perf_pmu__format_bits(&cs_etm_pmu->format, "contextid") | 83 + perf_pmu__format_bits(&cs_etm_pmu->format, "contextid1") | 84 84 perf_pmu__format_bits(&cs_etm_pmu->format, "contextid2")); 85 85 86 86 if (!contextid) ··· 114 114 * 0b00100 Maximum of 32-bit Context ID size. 115 115 * All other values are reserved. 116 116 */ 117 - val = BMVAL(val, 5, 9); 118 - if (!val || val != 0x4) { 117 + if (BMVAL(val, 5, 9) != 0x4) { 119 118 pr_err("%s: CONTEXTIDR_EL1 isn't supported, disable with %s/contextid1=0/\n", 120 119 CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); 121 120 return -EINVAL;
+2 -2
tools/perf/arch/arm64/util/header.c
··· 29 29 char path[PATH_MAX]; 30 30 FILE *file; 31 31 32 - scnprintf(path, PATH_MAX, "%s/devices/system/cpu/cpu%d"MIDR, 33 - sysfs, cpus->map[cpu]); 32 + scnprintf(path, PATH_MAX, "%s/devices/system/cpu/cpu%d" MIDR, 33 + sysfs, RC_CHK_ACCESS(cpus)->map[cpu].cpu); 34 34 35 35 file = fopen(path, "r"); 36 36 if (!file) {
+1 -1
tools/perf/arch/arm64/util/pmu.c
··· 18 18 * The cpumap should cover all CPUs. Otherwise, some CPUs may 19 19 * not support some events or have different event IDs. 20 20 */ 21 - if (pmu->cpus->nr != cpu__max_cpu().cpu) 21 + if (RC_CHK_ACCESS(pmu->cpus)->nr != cpu__max_cpu().cpu) 22 22 return NULL; 23 23 24 24 return pmu;
+1 -1
tools/perf/arch/s390/entry/syscalls/syscall.tbl
··· 449 449 444 common landlock_create_ruleset sys_landlock_create_ruleset sys_landlock_create_ruleset 450 450 445 common landlock_add_rule sys_landlock_add_rule sys_landlock_add_rule 451 451 446 common landlock_restrict_self sys_landlock_restrict_self sys_landlock_restrict_self 452 - # 447 reserved for memfd_secret 452 + 447 common memfd_secret sys_memfd_secret sys_memfd_secret 453 453 448 common process_mrelease sys_process_mrelease sys_process_mrelease 454 454 449 common futex_waitv sys_futex_waitv sys_futex_waitv 455 455 450 common set_mempolicy_home_node sys_set_mempolicy_home_node sys_set_mempolicy_home_node
-4
tools/perf/bench/mem-memcpy-x86-64-asm-def.h
··· 7 7 MEMCPY_FN(__memcpy, 8 8 "x86-64-movsq", 9 9 "movsq-based memcpy() in arch/x86/lib/memcpy_64.S") 10 - 11 - MEMCPY_FN(memcpy_erms, 12 - "x86-64-movsb", 13 - "movsb-based memcpy() in arch/x86/lib/memcpy_64.S")
+1 -1
tools/perf/bench/mem-memcpy-x86-64-asm.S
··· 2 2 3 3 /* Various wrappers to make the kernel .S file build in user-space: */ 4 4 5 - // memcpy_orig and memcpy_erms are being defined as SYM_L_LOCAL but we need it 5 + // memcpy_orig is being defined as SYM_L_LOCAL but we need it 6 6 #define SYM_FUNC_START_LOCAL(name) \ 7 7 SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) 8 8 #define memcpy MEMCPY /* don't hide glibc's memcpy() */
-4
tools/perf/bench/mem-memset-x86-64-asm-def.h
··· 7 7 MEMSET_FN(__memset, 8 8 "x86-64-stosq", 9 9 "movsq-based memset() in arch/x86/lib/memset_64.S") 10 - 11 - MEMSET_FN(memset_erms, 12 - "x86-64-stosb", 13 - "movsb-based memset() in arch/x86/lib/memset_64.S")
+1 -1
tools/perf/bench/mem-memset-x86-64-asm.S
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 - // memset_orig and memset_erms are being defined as SYM_L_LOCAL but we need it 2 + // memset_orig is being defined as SYM_L_LOCAL but we need it 3 3 #define SYM_FUNC_START_LOCAL(name) \ 4 4 SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) 5 5 #define memset MEMSET /* don't hide glibc's memset() */
+7
tools/perf/builtin-script.c
··· 3647 3647 union perf_event *event) 3648 3648 { 3649 3649 perf_event__read_stat_config(&stat_config, &event->stat_config); 3650 + 3651 + /* 3652 + * Aggregation modes are not used since post-processing scripts are 3653 + * supposed to take care of such requirements 3654 + */ 3655 + stat_config.aggr_mode = AGGR_NONE; 3656 + 3650 3657 return 0; 3651 3658 } 3652 3659
+29 -9
tools/perf/builtin-stat.c
··· 667 667 evsel_list->core.threads->err_thread = -1; 668 668 return COUNTER_RETRY; 669 669 } 670 + } else if (counter->skippable) { 671 + if (verbose > 0) 672 + ui__warning("skipping event %s that kernel failed to open .\n", 673 + evsel__name(counter)); 674 + counter->supported = false; 675 + counter->errored = true; 676 + return COUNTER_SKIP; 670 677 } 671 678 672 679 evsel__open_strerror(counter, &target, errno, msg, sizeof(msg)); ··· 1897 1890 * caused by exposing latent bugs. This is fixed properly in: 1898 1891 * https://lore.kernel.org/lkml/bff481ba-e60a-763f-0aa0-3ee53302c480@linux.intel.com/ 1899 1892 */ 1900 - if (metricgroup__has_metric("TopdownL1") && !perf_pmu__has_hybrid() && 1901 - metricgroup__parse_groups(evsel_list, "TopdownL1", 1902 - /*metric_no_group=*/false, 1903 - /*metric_no_merge=*/false, 1904 - /*metric_no_threshold=*/true, 1905 - stat_config.user_requested_cpu_list, 1906 - stat_config.system_wide, 1907 - &stat_config.metric_events) < 0) 1908 - return -1; 1893 + if (metricgroup__has_metric("TopdownL1") && !perf_pmu__has_hybrid()) { 1894 + struct evlist *metric_evlist = evlist__new(); 1895 + struct evsel *metric_evsel; 1896 + 1897 + if (!metric_evlist) 1898 + return -1; 1899 + 1900 + if (metricgroup__parse_groups(metric_evlist, "TopdownL1", 1901 + /*metric_no_group=*/false, 1902 + /*metric_no_merge=*/false, 1903 + /*metric_no_threshold=*/true, 1904 + stat_config.user_requested_cpu_list, 1905 + stat_config.system_wide, 1906 + &stat_config.metric_events) < 0) 1907 + return -1; 1908 + 1909 + evlist__for_each_entry(metric_evlist, metric_evsel) { 1910 + metric_evsel->skippable = true; 1911 + } 1912 + evlist__splice_list_tail(evsel_list, &metric_evlist->core.entries); 1913 + evlist__delete(metric_evlist); 1914 + } 1909 1915 1910 1916 /* Platform specific attrs */ 1911 1917 if (evlist__add_default_attrs(evsel_list, default_null_attrs) < 0)
+26
tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
··· 133 133 "MetricGroup": "TopdownL1;tma_L1_group", 134 134 "MetricName": "tma_backend_bound", 135 135 "MetricThreshold": "tma_backend_bound > 0.1", 136 + "MetricgroupNoGroup": "TopdownL1", 136 137 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", 137 138 "ScaleUnit": "100%", 138 139 "Unit": "cpu_atom" ··· 144 143 "MetricGroup": "TopdownL1;tma_L1_group", 145 144 "MetricName": "tma_backend_bound_aux", 146 145 "MetricThreshold": "tma_backend_bound_aux > 0.2", 146 + "MetricgroupNoGroup": "TopdownL1", 147 147 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", 148 148 "ScaleUnit": "100%", 149 149 "Unit": "cpu_atom" ··· 155 153 "MetricGroup": "TopdownL1;tma_L1_group", 156 154 "MetricName": "tma_bad_speculation", 157 155 "MetricThreshold": "tma_bad_speculation > 0.15", 156 + "MetricgroupNoGroup": "TopdownL1", 158 157 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", 159 158 "ScaleUnit": "100%", 160 159 "Unit": "cpu_atom" ··· 166 163 "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", 167 164 "MetricName": "tma_base", 168 165 "MetricThreshold": "tma_base > 0.6", 166 + "MetricgroupNoGroup": "TopdownL2", 169 167 "ScaleUnit": "100%", 170 168 "Unit": "cpu_atom" 171 169 }, ··· 186 182 "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", 187 183 "MetricName": "tma_branch_mispredicts", 188 184 "MetricThreshold": "tma_branch_mispredicts > 0.05", 185 + "MetricgroupNoGroup": "TopdownL2", 189 186 "ScaleUnit": "100%", 190 187 "Unit": "cpu_atom" 191 188 }, ··· 214 209 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", 215 210 "MetricName": "tma_core_bound", 216 211 "MetricThreshold": "tma_core_bound > 0.1", 212 + "MetricgroupNoGroup": "TopdownL2", 217 213 "ScaleUnit": "100%", 218 214 "Unit": "cpu_atom" 219 215 }, ··· 261 255 "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", 262 256 "MetricName": "tma_fetch_bandwidth", 263 257 "MetricThreshold": "tma_fetch_bandwidth > 0.1", 258 + "MetricgroupNoGroup": "TopdownL2", 264 259 "ScaleUnit": "100%", 265 260 "Unit": "cpu_atom" 266 261 }, ··· 271 264 "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", 272 265 "MetricName": "tma_fetch_latency", 273 266 "MetricThreshold": "tma_fetch_latency > 0.15", 267 + "MetricgroupNoGroup": "TopdownL2", 274 268 "ScaleUnit": "100%", 275 269 "Unit": "cpu_atom" 276 270 }, ··· 299 291 "MetricGroup": "TopdownL1;tma_L1_group", 300 292 "MetricName": "tma_frontend_bound", 301 293 "MetricThreshold": "tma_frontend_bound > 0.2", 294 + "MetricgroupNoGroup": "TopdownL1", 302 295 "ScaleUnit": "100%", 303 296 "Unit": "cpu_atom" 304 297 }, ··· 602 593 "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", 603 594 "MetricName": "tma_machine_clears", 604 595 "MetricThreshold": "tma_machine_clears > 0.05", 596 + "MetricgroupNoGroup": "TopdownL2", 605 597 "ScaleUnit": "100%", 606 598 "Unit": "cpu_atom" 607 599 }, ··· 621 611 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", 622 612 "MetricName": "tma_memory_bound", 623 613 "MetricThreshold": "tma_memory_bound > 0.2", 614 + "MetricgroupNoGroup": "TopdownL2", 624 615 "ScaleUnit": "100%", 625 616 "Unit": "cpu_atom" 626 617 }, ··· 640 629 "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", 641 630 "MetricName": "tma_ms_uops", 642 631 "MetricThreshold": "tma_ms_uops > 0.05", 632 + "MetricgroupNoGroup": "TopdownL2", 643 633 "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", 644 634 "ScaleUnit": "100%", 645 635 "Unit": "cpu_atom" ··· 741 729 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", 742 730 "MetricName": "tma_resource_bound", 743 731 "MetricThreshold": "tma_resource_bound > 0.2", 732 + "MetricgroupNoGroup": "TopdownL2", 744 733 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", 745 734 "ScaleUnit": "100%", 746 735 "Unit": "cpu_atom" ··· 752 739 "MetricGroup": "TopdownL1;tma_L1_group", 753 740 "MetricName": "tma_retiring", 754 741 "MetricThreshold": "tma_retiring > 0.75", 742 + "MetricgroupNoGroup": "TopdownL1", 755 743 "ScaleUnit": "100%", 756 744 "Unit": "cpu_atom" 757 745 }, ··· 862 848 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 863 849 "MetricName": "tma_backend_bound", 864 850 "MetricThreshold": "tma_backend_bound > 0.2", 851 + "MetricgroupNoGroup": "TopdownL1", 865 852 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 866 853 "ScaleUnit": "100%", 867 854 "Unit": "cpu_core" ··· 873 858 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 874 859 "MetricName": "tma_bad_speculation", 875 860 "MetricThreshold": "tma_bad_speculation > 0.15", 861 + "MetricgroupNoGroup": "TopdownL1", 876 862 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 877 863 "ScaleUnit": "100%", 878 864 "Unit": "cpu_core" ··· 884 868 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 885 869 "MetricName": "tma_branch_mispredicts", 886 870 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 871 + "MetricgroupNoGroup": "TopdownL2", 887 872 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 888 873 "ScaleUnit": "100%", 889 874 "Unit": "cpu_core" ··· 936 919 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 937 920 "MetricName": "tma_core_bound", 938 921 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 922 + "MetricgroupNoGroup": "TopdownL2", 939 923 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 940 924 "ScaleUnit": "100%", 941 925 "Unit": "cpu_core" ··· 1049 1031 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 1050 1032 "MetricName": "tma_fetch_bandwidth", 1051 1033 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35", 1034 + "MetricgroupNoGroup": "TopdownL2", 1052 1035 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 1053 1036 "ScaleUnit": "100%", 1054 1037 "Unit": "cpu_core" ··· 1060 1041 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 1061 1042 "MetricName": "tma_fetch_latency", 1062 1043 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 1044 + "MetricgroupNoGroup": "TopdownL2", 1063 1045 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 1064 1046 "ScaleUnit": "100%", 1065 1047 "Unit": "cpu_core" ··· 1141 1121 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 1142 1122 "MetricName": "tma_frontend_bound", 1143 1123 "MetricThreshold": "tma_frontend_bound > 0.15", 1124 + "MetricgroupNoGroup": "TopdownL1", 1144 1125 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 1145 1126 "ScaleUnit": "100%", 1146 1127 "Unit": "cpu_core" ··· 1162 1141 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1163 1142 "MetricName": "tma_heavy_operations", 1164 1143 "MetricThreshold": "tma_heavy_operations > 0.1", 1144 + "MetricgroupNoGroup": "TopdownL2", 1165 1145 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY", 1166 1146 "ScaleUnit": "100%", 1167 1147 "Unit": "cpu_core" ··· 2045 2023 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 2046 2024 "MetricName": "tma_light_operations", 2047 2025 "MetricThreshold": "tma_light_operations > 0.6", 2026 + "MetricgroupNoGroup": "TopdownL2", 2048 2027 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 2049 2028 "ScaleUnit": "100%", 2050 2029 "Unit": "cpu_core" ··· 2105 2082 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 2106 2083 "MetricName": "tma_machine_clears", 2107 2084 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 2085 + "MetricgroupNoGroup": "TopdownL2", 2108 2086 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 2109 2087 "ScaleUnit": "100%", 2110 2088 "Unit": "cpu_core" ··· 2136 2112 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 2137 2113 "MetricName": "tma_memory_bound", 2138 2114 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 2115 + "MetricgroupNoGroup": "TopdownL2", 2139 2116 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 2140 2117 "ScaleUnit": "100%", 2141 2118 "Unit": "cpu_core" ··· 2335 2310 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 2336 2311 "MetricName": "tma_retiring", 2337 2312 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 2313 + "MetricgroupNoGroup": "TopdownL1", 2338 2314 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 2339 2315 "ScaleUnit": "100%", 2340 2316 "Unit": "cpu_core"
+14
tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
··· 98 98 "MetricGroup": "TopdownL1;tma_L1_group", 99 99 "MetricName": "tma_backend_bound", 100 100 "MetricThreshold": "tma_backend_bound > 0.1", 101 + "MetricgroupNoGroup": "TopdownL1", 101 102 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", 102 103 "ScaleUnit": "100%" 103 104 }, ··· 108 107 "MetricGroup": "TopdownL1;tma_L1_group", 109 108 "MetricName": "tma_backend_bound_aux", 110 109 "MetricThreshold": "tma_backend_bound_aux > 0.2", 110 + "MetricgroupNoGroup": "TopdownL1", 111 111 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", 112 112 "ScaleUnit": "100%" 113 113 }, ··· 118 116 "MetricGroup": "TopdownL1;tma_L1_group", 119 117 "MetricName": "tma_bad_speculation", 120 118 "MetricThreshold": "tma_bad_speculation > 0.15", 119 + "MetricgroupNoGroup": "TopdownL1", 121 120 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", 122 121 "ScaleUnit": "100%" 123 122 }, ··· 128 125 "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", 129 126 "MetricName": "tma_base", 130 127 "MetricThreshold": "tma_base > 0.6", 128 + "MetricgroupNoGroup": "TopdownL2", 131 129 "ScaleUnit": "100%" 132 130 }, 133 131 { ··· 146 142 "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", 147 143 "MetricName": "tma_branch_mispredicts", 148 144 "MetricThreshold": "tma_branch_mispredicts > 0.05", 145 + "MetricgroupNoGroup": "TopdownL2", 149 146 "ScaleUnit": "100%" 150 147 }, 151 148 { ··· 171 166 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", 172 167 "MetricName": "tma_core_bound", 173 168 "MetricThreshold": "tma_core_bound > 0.1", 169 + "MetricgroupNoGroup": "TopdownL2", 174 170 "ScaleUnit": "100%" 175 171 }, 176 172 { ··· 213 207 "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", 214 208 "MetricName": "tma_fetch_bandwidth", 215 209 "MetricThreshold": "tma_fetch_bandwidth > 0.1", 210 + "MetricgroupNoGroup": "TopdownL2", 216 211 "ScaleUnit": "100%" 217 212 }, 218 213 { ··· 222 215 "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", 223 216 "MetricName": "tma_fetch_latency", 224 217 "MetricThreshold": "tma_fetch_latency > 0.15", 218 + "MetricgroupNoGroup": "TopdownL2", 225 219 "ScaleUnit": "100%" 226 220 }, 227 221 { ··· 247 239 "MetricGroup": "TopdownL1;tma_L1_group", 248 240 "MetricName": "tma_frontend_bound", 249 241 "MetricThreshold": "tma_frontend_bound > 0.2", 242 + "MetricgroupNoGroup": "TopdownL1", 250 243 "ScaleUnit": "100%" 251 244 }, 252 245 { ··· 508 499 "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", 509 500 "MetricName": "tma_machine_clears", 510 501 "MetricThreshold": "tma_machine_clears > 0.05", 502 + "MetricgroupNoGroup": "TopdownL2", 511 503 "ScaleUnit": "100%" 512 504 }, 513 505 { ··· 525 515 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", 526 516 "MetricName": "tma_memory_bound", 527 517 "MetricThreshold": "tma_memory_bound > 0.2", 518 + "MetricgroupNoGroup": "TopdownL2", 528 519 "ScaleUnit": "100%" 529 520 }, 530 521 { ··· 542 531 "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", 543 532 "MetricName": "tma_ms_uops", 544 533 "MetricThreshold": "tma_ms_uops > 0.05", 534 + "MetricgroupNoGroup": "TopdownL2", 545 535 "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", 546 536 "ScaleUnit": "100%" 547 537 }, ··· 632 620 "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", 633 621 "MetricName": "tma_resource_bound", 634 622 "MetricThreshold": "tma_resource_bound > 0.2", 623 + "MetricgroupNoGroup": "TopdownL2", 635 624 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", 636 625 "ScaleUnit": "100%" 637 626 }, ··· 642 629 "MetricGroup": "TopdownL1;tma_L1_group", 643 630 "MetricName": "tma_retiring", 644 631 "MetricThreshold": "tma_retiring > 0.75", 632 + "MetricgroupNoGroup": "TopdownL1", 645 633 "ScaleUnit": "100%" 646 634 }, 647 635 {
+12
tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json
··· 103 103 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 104 104 "MetricName": "tma_backend_bound", 105 105 "MetricThreshold": "tma_backend_bound > 0.2", 106 + "MetricgroupNoGroup": "TopdownL1", 106 107 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 107 108 "ScaleUnit": "100%" 108 109 }, ··· 113 112 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 114 113 "MetricName": "tma_bad_speculation", 115 114 "MetricThreshold": "tma_bad_speculation > 0.15", 115 + "MetricgroupNoGroup": "TopdownL1", 116 116 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 117 117 "ScaleUnit": "100%" 118 118 }, ··· 124 122 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 125 123 "MetricName": "tma_branch_mispredicts", 126 124 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 125 + "MetricgroupNoGroup": "TopdownL2", 127 126 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 128 127 "ScaleUnit": "100%" 129 128 }, ··· 173 170 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 174 171 "MetricName": "tma_core_bound", 175 172 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 173 + "MetricgroupNoGroup": "TopdownL2", 176 174 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 177 175 "ScaleUnit": "100%" 178 176 }, ··· 267 263 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 268 264 "MetricName": "tma_fetch_bandwidth", 269 265 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 266 + "MetricgroupNoGroup": "TopdownL2", 270 267 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 271 268 "ScaleUnit": "100%" 272 269 }, ··· 277 272 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 278 273 "MetricName": "tma_fetch_latency", 279 274 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 275 + "MetricgroupNoGroup": "TopdownL2", 280 276 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 281 277 "ScaleUnit": "100%" 282 278 }, ··· 332 326 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 333 327 "MetricName": "tma_frontend_bound", 334 328 "MetricThreshold": "tma_frontend_bound > 0.15", 329 + "MetricgroupNoGroup": "TopdownL1", 335 330 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 336 331 "ScaleUnit": "100%" 337 332 }, ··· 342 335 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 343 336 "MetricName": "tma_heavy_operations", 344 337 "MetricThreshold": "tma_heavy_operations > 0.1", 338 + "MetricgroupNoGroup": "TopdownL2", 345 339 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 346 340 "ScaleUnit": "100%" 347 341 }, ··· 836 828 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 837 829 "MetricName": "tma_light_operations", 838 830 "MetricThreshold": "tma_light_operations > 0.6", 831 + "MetricgroupNoGroup": "TopdownL2", 839 832 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 840 833 "ScaleUnit": "100%" 841 834 }, ··· 867 858 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 868 859 "MetricName": "tma_machine_clears", 869 860 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 861 + "MetricgroupNoGroup": "TopdownL2", 870 862 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 871 863 "ScaleUnit": "100%" 872 864 }, ··· 896 886 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 897 887 "MetricName": "tma_memory_bound", 898 888 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 889 + "MetricgroupNoGroup": "TopdownL2", 899 890 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 900 891 "ScaleUnit": "100%" 901 892 }, ··· 1059 1048 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1060 1049 "MetricName": "tma_retiring", 1061 1050 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1051 + "MetricgroupNoGroup": "TopdownL1", 1062 1052 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 1063 1053 "ScaleUnit": "100%" 1064 1054 },
+12
tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
··· 97 97 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 98 98 "MetricName": "tma_backend_bound", 99 99 "MetricThreshold": "tma_backend_bound > 0.2", 100 + "MetricgroupNoGroup": "TopdownL1", 100 101 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 101 102 "ScaleUnit": "100%" 102 103 }, ··· 107 106 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 108 107 "MetricName": "tma_bad_speculation", 109 108 "MetricThreshold": "tma_bad_speculation > 0.15", 109 + "MetricgroupNoGroup": "TopdownL1", 110 110 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 111 111 "ScaleUnit": "100%" 112 112 }, ··· 118 116 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 119 117 "MetricName": "tma_branch_mispredicts", 120 118 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 119 + "MetricgroupNoGroup": "TopdownL2", 121 120 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 122 121 "ScaleUnit": "100%" 123 122 }, ··· 167 164 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 168 165 "MetricName": "tma_core_bound", 169 166 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 167 + "MetricgroupNoGroup": "TopdownL2", 170 168 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 171 169 "ScaleUnit": "100%" 172 170 }, ··· 252 248 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 253 249 "MetricName": "tma_fetch_bandwidth", 254 250 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 251 + "MetricgroupNoGroup": "TopdownL2", 255 252 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 256 253 "ScaleUnit": "100%" 257 254 }, ··· 262 257 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 263 258 "MetricName": "tma_fetch_latency", 264 259 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 260 + "MetricgroupNoGroup": "TopdownL2", 265 261 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 266 262 "ScaleUnit": "100%" 267 263 }, ··· 317 311 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 318 312 "MetricName": "tma_frontend_bound", 319 313 "MetricThreshold": "tma_frontend_bound > 0.15", 314 + "MetricgroupNoGroup": "TopdownL1", 320 315 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 321 316 "ScaleUnit": "100%" 322 317 }, ··· 327 320 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 328 321 "MetricName": "tma_heavy_operations", 329 322 "MetricThreshold": "tma_heavy_operations > 0.1", 323 + "MetricgroupNoGroup": "TopdownL2", 330 324 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 331 325 "ScaleUnit": "100%" 332 326 }, ··· 803 795 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 804 796 "MetricName": "tma_light_operations", 805 797 "MetricThreshold": "tma_light_operations > 0.6", 798 + "MetricgroupNoGroup": "TopdownL2", 806 799 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 807 800 "ScaleUnit": "100%" 808 801 }, ··· 834 825 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 835 826 "MetricName": "tma_machine_clears", 836 827 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 828 + "MetricgroupNoGroup": "TopdownL2", 837 829 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 838 830 "ScaleUnit": "100%" 839 831 }, ··· 863 853 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 864 854 "MetricName": "tma_memory_bound", 865 855 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 856 + "MetricgroupNoGroup": "TopdownL2", 866 857 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 867 858 "ScaleUnit": "100%" 868 859 }, ··· 1024 1013 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1025 1014 "MetricName": "tma_retiring", 1026 1015 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1016 + "MetricgroupNoGroup": "TopdownL1", 1027 1017 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 1028 1018 "ScaleUnit": "100%" 1029 1019 },
+12
tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
··· 103 103 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 104 104 "MetricName": "tma_backend_bound", 105 105 "MetricThreshold": "tma_backend_bound > 0.2", 106 + "MetricgroupNoGroup": "TopdownL1", 106 107 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 107 108 "ScaleUnit": "100%" 108 109 }, ··· 113 112 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 114 113 "MetricName": "tma_bad_speculation", 115 114 "MetricThreshold": "tma_bad_speculation > 0.15", 115 + "MetricgroupNoGroup": "TopdownL1", 116 116 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 117 117 "ScaleUnit": "100%" 118 118 }, ··· 124 122 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 125 123 "MetricName": "tma_branch_mispredicts", 126 124 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 125 + "MetricgroupNoGroup": "TopdownL2", 127 126 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 128 127 "ScaleUnit": "100%" 129 128 }, ··· 173 170 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 174 171 "MetricName": "tma_core_bound", 175 172 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 173 + "MetricgroupNoGroup": "TopdownL2", 176 174 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 177 175 "ScaleUnit": "100%" 178 176 }, ··· 267 263 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 268 264 "MetricName": "tma_fetch_bandwidth", 269 265 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 266 + "MetricgroupNoGroup": "TopdownL2", 270 267 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 271 268 "ScaleUnit": "100%" 272 269 }, ··· 277 272 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 278 273 "MetricName": "tma_fetch_latency", 279 274 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 275 + "MetricgroupNoGroup": "TopdownL2", 280 276 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 281 277 "ScaleUnit": "100%" 282 278 }, ··· 332 326 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 333 327 "MetricName": "tma_frontend_bound", 334 328 "MetricThreshold": "tma_frontend_bound > 0.15", 329 + "MetricgroupNoGroup": "TopdownL1", 335 330 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 336 331 "ScaleUnit": "100%" 337 332 }, ··· 342 335 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 343 336 "MetricName": "tma_heavy_operations", 344 337 "MetricThreshold": "tma_heavy_operations > 0.1", 338 + "MetricgroupNoGroup": "TopdownL2", 345 339 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 346 340 "ScaleUnit": "100%" 347 341 }, ··· 837 829 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 838 830 "MetricName": "tma_light_operations", 839 831 "MetricThreshold": "tma_light_operations > 0.6", 832 + "MetricgroupNoGroup": "TopdownL2", 840 833 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 841 834 "ScaleUnit": "100%" 842 835 }, ··· 878 869 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 879 870 "MetricName": "tma_machine_clears", 880 871 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 872 + "MetricgroupNoGroup": "TopdownL2", 881 873 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 882 874 "ScaleUnit": "100%" 883 875 }, ··· 907 897 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 908 898 "MetricName": "tma_memory_bound", 909 899 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 900 + "MetricgroupNoGroup": "TopdownL2", 910 901 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 911 902 "ScaleUnit": "100%" 912 903 }, ··· 1090 1079 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1091 1080 "MetricName": "tma_retiring", 1092 1081 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1082 + "MetricgroupNoGroup": "TopdownL1", 1093 1083 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 1094 1084 "ScaleUnit": "100%" 1095 1085 },
+12
tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
··· 101 101 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 102 102 "MetricName": "tma_backend_bound", 103 103 "MetricThreshold": "tma_backend_bound > 0.2", 104 + "MetricgroupNoGroup": "TopdownL1", 104 105 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 105 106 "ScaleUnit": "100%" 106 107 }, ··· 111 110 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 112 111 "MetricName": "tma_bad_speculation", 113 112 "MetricThreshold": "tma_bad_speculation > 0.15", 113 + "MetricgroupNoGroup": "TopdownL1", 114 114 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 115 115 "ScaleUnit": "100%" 116 116 }, ··· 122 120 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 123 121 "MetricName": "tma_branch_mispredicts", 124 122 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 123 + "MetricgroupNoGroup": "TopdownL2", 125 124 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 126 125 "ScaleUnit": "100%" 127 126 }, ··· 170 167 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 171 168 "MetricName": "tma_core_bound", 172 169 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 170 + "MetricgroupNoGroup": "TopdownL2", 173 171 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 174 172 "ScaleUnit": "100%" 175 173 }, ··· 275 271 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 276 272 "MetricName": "tma_fetch_bandwidth", 277 273 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 274 + "MetricgroupNoGroup": "TopdownL2", 278 275 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 279 276 "ScaleUnit": "100%" 280 277 }, ··· 285 280 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 286 281 "MetricName": "tma_fetch_latency", 287 282 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 283 + "MetricgroupNoGroup": "TopdownL2", 288 284 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 289 285 "ScaleUnit": "100%" 290 286 }, ··· 360 354 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 361 355 "MetricName": "tma_frontend_bound", 362 356 "MetricThreshold": "tma_frontend_bound > 0.15", 357 + "MetricgroupNoGroup": "TopdownL1", 363 358 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 364 359 "ScaleUnit": "100%" 365 360 }, ··· 379 372 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 380 373 "MetricName": "tma_heavy_operations", 381 374 "MetricThreshold": "tma_heavy_operations > 0.1", 375 + "MetricgroupNoGroup": "TopdownL2", 382 376 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 383 377 "ScaleUnit": "100%" 384 378 }, ··· 1150 1142 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1151 1143 "MetricName": "tma_light_operations", 1152 1144 "MetricThreshold": "tma_light_operations > 0.6", 1145 + "MetricgroupNoGroup": "TopdownL2", 1153 1146 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1154 1147 "ScaleUnit": "100%" 1155 1148 }, ··· 1205 1196 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1206 1197 "MetricName": "tma_machine_clears", 1207 1198 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1199 + "MetricgroupNoGroup": "TopdownL2", 1208 1200 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1209 1201 "ScaleUnit": "100%" 1210 1202 }, ··· 1234 1224 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1235 1225 "MetricName": "tma_memory_bound", 1236 1226 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1227 + "MetricgroupNoGroup": "TopdownL2", 1237 1228 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1238 1229 "ScaleUnit": "100%" 1239 1230 }, ··· 1469 1458 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1470 1459 "MetricName": "tma_retiring", 1471 1460 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1461 + "MetricgroupNoGroup": "TopdownL1", 1472 1462 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 1473 1463 "ScaleUnit": "100%" 1474 1464 },
+12
tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
··· 103 103 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 104 104 "MetricName": "tma_backend_bound", 105 105 "MetricThreshold": "tma_backend_bound > 0.2", 106 + "MetricgroupNoGroup": "TopdownL1", 106 107 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 107 108 "ScaleUnit": "100%" 108 109 }, ··· 113 112 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 114 113 "MetricName": "tma_bad_speculation", 115 114 "MetricThreshold": "tma_bad_speculation > 0.15", 115 + "MetricgroupNoGroup": "TopdownL1", 116 116 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 117 117 "ScaleUnit": "100%" 118 118 }, ··· 124 122 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 125 123 "MetricName": "tma_branch_mispredicts", 126 124 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 125 + "MetricgroupNoGroup": "TopdownL2", 127 126 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 128 127 "ScaleUnit": "100%" 129 128 }, ··· 164 161 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 165 162 "MetricName": "tma_core_bound", 166 163 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 164 + "MetricgroupNoGroup": "TopdownL2", 167 165 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 168 166 "ScaleUnit": "100%" 169 167 }, ··· 258 254 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 259 255 "MetricName": "tma_fetch_bandwidth", 260 256 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 257 + "MetricgroupNoGroup": "TopdownL2", 261 258 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 262 259 "ScaleUnit": "100%" 263 260 }, ··· 268 263 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 269 264 "MetricName": "tma_fetch_latency", 270 265 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 266 + "MetricgroupNoGroup": "TopdownL2", 271 267 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 272 268 "ScaleUnit": "100%" 273 269 }, ··· 278 272 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 279 273 "MetricName": "tma_frontend_bound", 280 274 "MetricThreshold": "tma_frontend_bound > 0.15", 275 + "MetricgroupNoGroup": "TopdownL1", 281 276 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 282 277 "ScaleUnit": "100%" 283 278 }, ··· 288 281 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 289 282 "MetricName": "tma_heavy_operations", 290 283 "MetricThreshold": "tma_heavy_operations > 0.1", 284 + "MetricgroupNoGroup": "TopdownL2", 291 285 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 292 286 "ScaleUnit": "100%" 293 287 }, ··· 671 663 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 672 664 "MetricName": "tma_light_operations", 673 665 "MetricThreshold": "tma_light_operations > 0.6", 666 + "MetricgroupNoGroup": "TopdownL2", 674 667 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 675 668 "ScaleUnit": "100%" 676 669 }, ··· 702 693 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 703 694 "MetricName": "tma_machine_clears", 704 695 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 696 + "MetricgroupNoGroup": "TopdownL2", 705 697 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 706 698 "ScaleUnit": "100%" 707 699 }, ··· 731 721 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 732 722 "MetricName": "tma_memory_bound", 733 723 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 724 + "MetricgroupNoGroup": "TopdownL2", 734 725 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 735 726 "ScaleUnit": "100%" 736 727 }, ··· 885 874 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 886 875 "MetricName": "tma_retiring", 887 876 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 877 + "MetricgroupNoGroup": "TopdownL1", 888 878 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 889 879 "ScaleUnit": "100%" 890 880 },
+12
tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
··· 103 103 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 104 104 "MetricName": "tma_backend_bound", 105 105 "MetricThreshold": "tma_backend_bound > 0.2", 106 + "MetricgroupNoGroup": "TopdownL1", 106 107 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 107 108 "ScaleUnit": "100%" 108 109 }, ··· 113 112 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 114 113 "MetricName": "tma_bad_speculation", 115 114 "MetricThreshold": "tma_bad_speculation > 0.15", 115 + "MetricgroupNoGroup": "TopdownL1", 116 116 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 117 117 "ScaleUnit": "100%" 118 118 }, ··· 124 122 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 125 123 "MetricName": "tma_branch_mispredicts", 126 124 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 125 + "MetricgroupNoGroup": "TopdownL2", 127 126 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 128 127 "ScaleUnit": "100%" 129 128 }, ··· 164 161 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 165 162 "MetricName": "tma_core_bound", 166 163 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 164 + "MetricgroupNoGroup": "TopdownL2", 167 165 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 168 166 "ScaleUnit": "100%" 169 167 }, ··· 258 254 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 259 255 "MetricName": "tma_fetch_bandwidth", 260 256 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 257 + "MetricgroupNoGroup": "TopdownL2", 261 258 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 262 259 "ScaleUnit": "100%" 263 260 }, ··· 268 263 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 269 264 "MetricName": "tma_fetch_latency", 270 265 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 266 + "MetricgroupNoGroup": "TopdownL2", 271 267 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 272 268 "ScaleUnit": "100%" 273 269 }, ··· 278 272 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 279 273 "MetricName": "tma_frontend_bound", 280 274 "MetricThreshold": "tma_frontend_bound > 0.15", 275 + "MetricgroupNoGroup": "TopdownL1", 281 276 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 282 277 "ScaleUnit": "100%" 283 278 }, ··· 288 281 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 289 282 "MetricName": "tma_heavy_operations", 290 283 "MetricThreshold": "tma_heavy_operations > 0.1", 284 + "MetricgroupNoGroup": "TopdownL2", 291 285 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 292 286 "ScaleUnit": "100%" 293 287 }, ··· 672 664 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 673 665 "MetricName": "tma_light_operations", 674 666 "MetricThreshold": "tma_light_operations > 0.6", 667 + "MetricgroupNoGroup": "TopdownL2", 675 668 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 676 669 "ScaleUnit": "100%" 677 670 }, ··· 713 704 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 714 705 "MetricName": "tma_machine_clears", 715 706 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 707 + "MetricgroupNoGroup": "TopdownL2", 716 708 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 717 709 "ScaleUnit": "100%" 718 710 }, ··· 742 732 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 743 733 "MetricName": "tma_memory_bound", 744 734 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 735 + "MetricgroupNoGroup": "TopdownL2", 745 736 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 746 737 "ScaleUnit": "100%" 747 738 }, ··· 916 905 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 917 906 "MetricName": "tma_retiring", 918 907 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 908 + "MetricgroupNoGroup": "TopdownL1", 919 909 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 920 910 "ScaleUnit": "100%" 921 911 },
+12
tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
··· 115 115 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 116 116 "MetricName": "tma_backend_bound", 117 117 "MetricThreshold": "tma_backend_bound > 0.2", 118 + "MetricgroupNoGroup": "TopdownL1", 118 119 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 119 120 "ScaleUnit": "100%" 120 121 }, ··· 125 124 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 126 125 "MetricName": "tma_bad_speculation", 127 126 "MetricThreshold": "tma_bad_speculation > 0.15", 127 + "MetricgroupNoGroup": "TopdownL1", 128 128 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 129 129 "ScaleUnit": "100%" 130 130 }, ··· 143 141 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 144 142 "MetricName": "tma_branch_mispredicts", 145 143 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 144 + "MetricgroupNoGroup": "TopdownL2", 146 145 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 147 146 "ScaleUnit": "100%" 148 147 }, ··· 190 187 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 191 188 "MetricName": "tma_core_bound", 192 189 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 190 + "MetricgroupNoGroup": "TopdownL2", 193 191 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 194 192 "ScaleUnit": "100%" 195 193 }, ··· 292 288 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 293 289 "MetricName": "tma_fetch_bandwidth", 294 290 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35", 291 + "MetricgroupNoGroup": "TopdownL2", 295 292 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 296 293 "ScaleUnit": "100%" 297 294 }, ··· 302 297 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 303 298 "MetricName": "tma_fetch_latency", 304 299 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 300 + "MetricgroupNoGroup": "TopdownL2", 305 301 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 306 302 "ScaleUnit": "100%" 307 303 }, ··· 375 369 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 376 370 "MetricName": "tma_frontend_bound", 377 371 "MetricThreshold": "tma_frontend_bound > 0.15", 372 + "MetricgroupNoGroup": "TopdownL1", 378 373 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 379 374 "ScaleUnit": "100%" 380 375 }, ··· 385 378 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 386 379 "MetricName": "tma_heavy_operations", 387 380 "MetricThreshold": "tma_heavy_operations > 0.1", 381 + "MetricgroupNoGroup": "TopdownL2", 388 382 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 389 383 "ScaleUnit": "100%" 390 384 }, ··· 1119 1111 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1120 1112 "MetricName": "tma_light_operations", 1121 1113 "MetricThreshold": "tma_light_operations > 0.6", 1114 + "MetricgroupNoGroup": "TopdownL2", 1122 1115 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1123 1116 "ScaleUnit": "100%" 1124 1117 }, ··· 1173 1164 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1174 1165 "MetricName": "tma_machine_clears", 1175 1166 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1167 + "MetricgroupNoGroup": "TopdownL2", 1176 1168 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1177 1169 "ScaleUnit": "100%" 1178 1170 }, ··· 1201 1191 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1202 1192 "MetricName": "tma_memory_bound", 1203 1193 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1194 + "MetricgroupNoGroup": "TopdownL2", 1204 1195 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1205 1196 "ScaleUnit": "100%" 1206 1197 }, ··· 1371 1360 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1372 1361 "MetricName": "tma_retiring", 1373 1362 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1363 + "MetricgroupNoGroup": "TopdownL1", 1374 1364 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 1375 1365 "ScaleUnit": "100%" 1376 1366 },
+12
tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
··· 80 80 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 81 81 "MetricName": "tma_backend_bound", 82 82 "MetricThreshold": "tma_backend_bound > 0.2", 83 + "MetricgroupNoGroup": "TopdownL1", 83 84 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 84 85 "ScaleUnit": "100%" 85 86 }, ··· 90 89 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 91 90 "MetricName": "tma_bad_speculation", 92 91 "MetricThreshold": "tma_bad_speculation > 0.15", 92 + "MetricgroupNoGroup": "TopdownL1", 93 93 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 94 94 "ScaleUnit": "100%" 95 95 }, ··· 108 106 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 109 107 "MetricName": "tma_branch_mispredicts", 110 108 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 109 + "MetricgroupNoGroup": "TopdownL2", 111 110 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 112 111 "ScaleUnit": "100%" 113 112 }, ··· 155 152 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 156 153 "MetricName": "tma_core_bound", 157 154 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 155 + "MetricgroupNoGroup": "TopdownL2", 158 156 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 159 157 "ScaleUnit": "100%" 160 158 }, ··· 257 253 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 258 254 "MetricName": "tma_fetch_bandwidth", 259 255 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35", 256 + "MetricgroupNoGroup": "TopdownL2", 260 257 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 261 258 "ScaleUnit": "100%" 262 259 }, ··· 267 262 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 268 263 "MetricName": "tma_fetch_latency", 269 264 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 265 + "MetricgroupNoGroup": "TopdownL2", 270 266 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 271 267 "ScaleUnit": "100%" 272 268 }, ··· 340 334 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 341 335 "MetricName": "tma_frontend_bound", 342 336 "MetricThreshold": "tma_frontend_bound > 0.15", 337 + "MetricgroupNoGroup": "TopdownL1", 343 338 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 344 339 "ScaleUnit": "100%" 345 340 }, ··· 350 343 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 351 344 "MetricName": "tma_heavy_operations", 352 345 "MetricThreshold": "tma_heavy_operations > 0.1", 346 + "MetricgroupNoGroup": "TopdownL2", 353 347 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 354 348 "ScaleUnit": "100%" 355 349 }, ··· 1142 1134 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1143 1135 "MetricName": "tma_light_operations", 1144 1136 "MetricThreshold": "tma_light_operations > 0.6", 1137 + "MetricgroupNoGroup": "TopdownL2", 1145 1138 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1146 1139 "ScaleUnit": "100%" 1147 1140 }, ··· 1196 1187 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1197 1188 "MetricName": "tma_machine_clears", 1198 1189 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1190 + "MetricgroupNoGroup": "TopdownL2", 1199 1191 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1200 1192 "ScaleUnit": "100%" 1201 1193 }, ··· 1224 1214 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1225 1215 "MetricName": "tma_memory_bound", 1226 1216 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1217 + "MetricgroupNoGroup": "TopdownL2", 1227 1218 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1228 1219 "ScaleUnit": "100%" 1229 1220 }, ··· 1421 1410 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1422 1411 "MetricName": "tma_retiring", 1423 1412 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1413 + "MetricgroupNoGroup": "TopdownL1", 1424 1414 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 1425 1415 "ScaleUnit": "100%" 1426 1416 },
+12
tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
··· 103 103 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 104 104 "MetricName": "tma_backend_bound", 105 105 "MetricThreshold": "tma_backend_bound > 0.2", 106 + "MetricgroupNoGroup": "TopdownL1", 106 107 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 107 108 "ScaleUnit": "100%" 108 109 }, ··· 113 112 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 114 113 "MetricName": "tma_bad_speculation", 115 114 "MetricThreshold": "tma_bad_speculation > 0.15", 115 + "MetricgroupNoGroup": "TopdownL1", 116 116 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 117 117 "ScaleUnit": "100%" 118 118 }, ··· 124 122 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 125 123 "MetricName": "tma_branch_mispredicts", 126 124 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 125 + "MetricgroupNoGroup": "TopdownL2", 127 126 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 128 127 "ScaleUnit": "100%" 129 128 }, ··· 164 161 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 165 162 "MetricName": "tma_core_bound", 166 163 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 164 + "MetricgroupNoGroup": "TopdownL2", 167 165 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 168 166 "ScaleUnit": "100%" 169 167 }, ··· 258 254 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 259 255 "MetricName": "tma_fetch_bandwidth", 260 256 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 257 + "MetricgroupNoGroup": "TopdownL2", 261 258 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 262 259 "ScaleUnit": "100%" 263 260 }, ··· 268 263 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 269 264 "MetricName": "tma_fetch_latency", 270 265 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 266 + "MetricgroupNoGroup": "TopdownL2", 271 267 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 272 268 "ScaleUnit": "100%" 273 269 }, ··· 305 299 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 306 300 "MetricName": "tma_frontend_bound", 307 301 "MetricThreshold": "tma_frontend_bound > 0.15", 302 + "MetricgroupNoGroup": "TopdownL1", 308 303 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 309 304 "ScaleUnit": "100%" 310 305 }, ··· 315 308 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 316 309 "MetricName": "tma_heavy_operations", 317 310 "MetricThreshold": "tma_heavy_operations > 0.1", 311 + "MetricgroupNoGroup": "TopdownL2", 318 312 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 319 313 "ScaleUnit": "100%" 320 314 }, ··· 732 724 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 733 725 "MetricName": "tma_light_operations", 734 726 "MetricThreshold": "tma_light_operations > 0.6", 727 + "MetricgroupNoGroup": "TopdownL2", 735 728 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 736 729 "ScaleUnit": "100%" 737 730 }, ··· 763 754 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 764 755 "MetricName": "tma_machine_clears", 765 756 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 757 + "MetricgroupNoGroup": "TopdownL2", 766 758 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 767 759 "ScaleUnit": "100%" 768 760 }, ··· 792 782 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 793 783 "MetricName": "tma_memory_bound", 794 784 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 785 + "MetricgroupNoGroup": "TopdownL2", 795 786 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 796 787 "ScaleUnit": "100%" 797 788 }, ··· 928 917 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 929 918 "MetricName": "tma_retiring", 930 919 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 920 + "MetricgroupNoGroup": "TopdownL1", 931 921 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 932 922 "ScaleUnit": "100%" 933 923 },
+12
tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
··· 103 103 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 104 104 "MetricName": "tma_backend_bound", 105 105 "MetricThreshold": "tma_backend_bound > 0.2", 106 + "MetricgroupNoGroup": "TopdownL1", 106 107 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 107 108 "ScaleUnit": "100%" 108 109 }, ··· 113 112 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 114 113 "MetricName": "tma_bad_speculation", 115 114 "MetricThreshold": "tma_bad_speculation > 0.15", 115 + "MetricgroupNoGroup": "TopdownL1", 116 116 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 117 117 "ScaleUnit": "100%" 118 118 }, ··· 124 122 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 125 123 "MetricName": "tma_branch_mispredicts", 126 124 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 125 + "MetricgroupNoGroup": "TopdownL2", 127 126 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 128 127 "ScaleUnit": "100%" 129 128 }, ··· 164 161 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 165 162 "MetricName": "tma_core_bound", 166 163 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 164 + "MetricgroupNoGroup": "TopdownL2", 167 165 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 168 166 "ScaleUnit": "100%" 169 167 }, ··· 258 254 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 259 255 "MetricName": "tma_fetch_bandwidth", 260 256 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 257 + "MetricgroupNoGroup": "TopdownL2", 261 258 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", 262 259 "ScaleUnit": "100%" 263 260 }, ··· 268 263 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 269 264 "MetricName": "tma_fetch_latency", 270 265 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 266 + "MetricgroupNoGroup": "TopdownL2", 271 267 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 272 268 "ScaleUnit": "100%" 273 269 }, ··· 305 299 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 306 300 "MetricName": "tma_frontend_bound", 307 301 "MetricThreshold": "tma_frontend_bound > 0.15", 302 + "MetricgroupNoGroup": "TopdownL1", 308 303 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 309 304 "ScaleUnit": "100%" 310 305 }, ··· 315 308 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 316 309 "MetricName": "tma_heavy_operations", 317 310 "MetricThreshold": "tma_heavy_operations > 0.1", 311 + "MetricgroupNoGroup": "TopdownL2", 318 312 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 319 313 "ScaleUnit": "100%" 320 314 }, ··· 733 725 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 734 726 "MetricName": "tma_light_operations", 735 727 "MetricThreshold": "tma_light_operations > 0.6", 728 + "MetricgroupNoGroup": "TopdownL2", 736 729 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 737 730 "ScaleUnit": "100%" 738 731 }, ··· 774 765 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 775 766 "MetricName": "tma_machine_clears", 776 767 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 768 + "MetricgroupNoGroup": "TopdownL2", 777 769 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 778 770 "ScaleUnit": "100%" 779 771 }, ··· 803 793 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 804 794 "MetricName": "tma_memory_bound", 805 795 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 796 + "MetricgroupNoGroup": "TopdownL2", 806 797 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 807 798 "ScaleUnit": "100%" 808 799 }, ··· 959 948 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 960 949 "MetricName": "tma_retiring", 961 950 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 951 + "MetricgroupNoGroup": "TopdownL1", 962 952 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 963 953 "ScaleUnit": "100%" 964 954 },
+12
tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
··· 76 76 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 77 77 "MetricName": "tma_backend_bound", 78 78 "MetricThreshold": "tma_backend_bound > 0.2", 79 + "MetricgroupNoGroup": "TopdownL1", 79 80 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 80 81 "ScaleUnit": "100%" 81 82 }, ··· 86 85 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 87 86 "MetricName": "tma_bad_speculation", 88 87 "MetricThreshold": "tma_bad_speculation > 0.15", 88 + "MetricgroupNoGroup": "TopdownL1", 89 89 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 90 90 "ScaleUnit": "100%" 91 91 }, ··· 97 95 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 98 96 "MetricName": "tma_branch_mispredicts", 99 97 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 98 + "MetricgroupNoGroup": "TopdownL2", 100 99 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 101 100 "ScaleUnit": "100%" 102 101 }, ··· 117 114 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 118 115 "MetricName": "tma_core_bound", 119 116 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 117 + "MetricgroupNoGroup": "TopdownL2", 120 118 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 121 119 "ScaleUnit": "100%" 122 120 }, ··· 164 160 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 165 161 "MetricName": "tma_fetch_bandwidth", 166 162 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 163 + "MetricgroupNoGroup": "TopdownL2", 167 164 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", 168 165 "ScaleUnit": "100%" 169 166 }, ··· 174 169 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 175 170 "MetricName": "tma_fetch_latency", 176 171 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 172 + "MetricgroupNoGroup": "TopdownL2", 177 173 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 178 174 "ScaleUnit": "100%" 179 175 }, ··· 211 205 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 212 206 "MetricName": "tma_frontend_bound", 213 207 "MetricThreshold": "tma_frontend_bound > 0.15", 208 + "MetricgroupNoGroup": "TopdownL1", 214 209 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 215 210 "ScaleUnit": "100%" 216 211 }, ··· 221 214 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 222 215 "MetricName": "tma_heavy_operations", 223 216 "MetricThreshold": "tma_heavy_operations > 0.1", 217 + "MetricgroupNoGroup": "TopdownL2", 224 218 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 225 219 "ScaleUnit": "100%" 226 220 }, ··· 420 412 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 421 413 "MetricName": "tma_light_operations", 422 414 "MetricThreshold": "tma_light_operations > 0.6", 415 + "MetricgroupNoGroup": "TopdownL2", 423 416 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 424 417 "ScaleUnit": "100%" 425 418 }, ··· 431 422 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 432 423 "MetricName": "tma_machine_clears", 433 424 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 425 + "MetricgroupNoGroup": "TopdownL2", 434 426 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 435 427 "ScaleUnit": "100%" 436 428 }, ··· 460 450 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 461 451 "MetricName": "tma_memory_bound", 462 452 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 453 + "MetricgroupNoGroup": "TopdownL2", 463 454 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 464 455 "ScaleUnit": "100%" 465 456 }, ··· 498 487 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 499 488 "MetricName": "tma_retiring", 500 489 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 490 + "MetricgroupNoGroup": "TopdownL1", 501 491 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 502 492 "ScaleUnit": "100%" 503 493 },
+12
tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
··· 76 76 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 77 77 "MetricName": "tma_backend_bound", 78 78 "MetricThreshold": "tma_backend_bound > 0.2", 79 + "MetricgroupNoGroup": "TopdownL1", 79 80 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 80 81 "ScaleUnit": "100%" 81 82 }, ··· 86 85 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 87 86 "MetricName": "tma_bad_speculation", 88 87 "MetricThreshold": "tma_bad_speculation > 0.15", 88 + "MetricgroupNoGroup": "TopdownL1", 89 89 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 90 90 "ScaleUnit": "100%" 91 91 }, ··· 97 95 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 98 96 "MetricName": "tma_branch_mispredicts", 99 97 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 98 + "MetricgroupNoGroup": "TopdownL2", 100 99 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", 101 100 "ScaleUnit": "100%" 102 101 }, ··· 117 114 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 118 115 "MetricName": "tma_core_bound", 119 116 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 117 + "MetricgroupNoGroup": "TopdownL2", 120 118 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 121 119 "ScaleUnit": "100%" 122 120 }, ··· 164 160 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 165 161 "MetricName": "tma_fetch_bandwidth", 166 162 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 163 + "MetricgroupNoGroup": "TopdownL2", 167 164 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", 168 165 "ScaleUnit": "100%" 169 166 }, ··· 174 169 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 175 170 "MetricName": "tma_fetch_latency", 176 171 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 172 + "MetricgroupNoGroup": "TopdownL2", 177 173 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 178 174 "ScaleUnit": "100%" 179 175 }, ··· 211 205 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 212 206 "MetricName": "tma_frontend_bound", 213 207 "MetricThreshold": "tma_frontend_bound > 0.15", 208 + "MetricgroupNoGroup": "TopdownL1", 214 209 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 215 210 "ScaleUnit": "100%" 216 211 }, ··· 221 214 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 222 215 "MetricName": "tma_heavy_operations", 223 216 "MetricThreshold": "tma_heavy_operations > 0.1", 217 + "MetricgroupNoGroup": "TopdownL2", 224 218 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 225 219 "ScaleUnit": "100%" 226 220 }, ··· 419 411 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 420 412 "MetricName": "tma_light_operations", 421 413 "MetricThreshold": "tma_light_operations > 0.6", 414 + "MetricgroupNoGroup": "TopdownL2", 422 415 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 423 416 "ScaleUnit": "100%" 424 417 }, ··· 430 421 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 431 422 "MetricName": "tma_machine_clears", 432 423 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 424 + "MetricgroupNoGroup": "TopdownL2", 433 425 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 434 426 "ScaleUnit": "100%" 435 427 }, ··· 459 449 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 460 450 "MetricName": "tma_memory_bound", 461 451 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 452 + "MetricgroupNoGroup": "TopdownL2", 462 453 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 463 454 "ScaleUnit": "100%" 464 455 }, ··· 497 486 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 498 487 "MetricName": "tma_retiring", 499 488 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 489 + "MetricgroupNoGroup": "TopdownL1", 500 490 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 501 491 "ScaleUnit": "100%" 502 492 },
+12
tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
··· 87 87 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 88 88 "MetricName": "tma_backend_bound", 89 89 "MetricThreshold": "tma_backend_bound > 0.2", 90 + "MetricgroupNoGroup": "TopdownL1", 90 91 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 91 92 "ScaleUnit": "100%" 92 93 }, ··· 97 96 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 98 97 "MetricName": "tma_bad_speculation", 99 98 "MetricThreshold": "tma_bad_speculation > 0.15", 99 + "MetricgroupNoGroup": "TopdownL1", 100 100 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 101 101 "ScaleUnit": "100%" 102 102 }, ··· 107 105 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 108 106 "MetricName": "tma_branch_mispredicts", 109 107 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 108 + "MetricgroupNoGroup": "TopdownL2", 110 109 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 111 110 "ScaleUnit": "100%" 112 111 }, ··· 154 151 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 155 152 "MetricName": "tma_core_bound", 156 153 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 154 + "MetricgroupNoGroup": "TopdownL2", 157 155 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 158 156 "ScaleUnit": "100%" 159 157 }, ··· 256 252 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 257 253 "MetricName": "tma_fetch_bandwidth", 258 254 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35", 255 + "MetricgroupNoGroup": "TopdownL2", 259 256 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 260 257 "ScaleUnit": "100%" 261 258 }, ··· 266 261 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 267 262 "MetricName": "tma_fetch_latency", 268 263 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 264 + "MetricgroupNoGroup": "TopdownL2", 269 265 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 270 266 "ScaleUnit": "100%" 271 267 }, ··· 357 351 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 358 352 "MetricName": "tma_frontend_bound", 359 353 "MetricThreshold": "tma_frontend_bound > 0.15", 354 + "MetricgroupNoGroup": "TopdownL1", 360 355 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 361 356 "ScaleUnit": "100%" 362 357 }, ··· 376 369 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 377 370 "MetricName": "tma_heavy_operations", 378 371 "MetricThreshold": "tma_heavy_operations > 0.1", 372 + "MetricgroupNoGroup": "TopdownL2", 379 373 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY", 380 374 "ScaleUnit": "100%" 381 375 }, ··· 1224 1216 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1225 1217 "MetricName": "tma_light_operations", 1226 1218 "MetricThreshold": "tma_light_operations > 0.6", 1219 + "MetricgroupNoGroup": "TopdownL2", 1227 1220 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1228 1221 "ScaleUnit": "100%" 1229 1222 }, ··· 1278 1269 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1279 1270 "MetricName": "tma_machine_clears", 1280 1271 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1272 + "MetricgroupNoGroup": "TopdownL2", 1281 1273 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1282 1274 "ScaleUnit": "100%" 1283 1275 }, ··· 1314 1304 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1315 1305 "MetricName": "tma_memory_bound", 1316 1306 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1307 + "MetricgroupNoGroup": "TopdownL2", 1317 1308 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1318 1309 "ScaleUnit": "100%" 1319 1310 }, ··· 1520 1509 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1521 1510 "MetricName": "tma_retiring", 1522 1511 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1512 + "MetricgroupNoGroup": "TopdownL1", 1523 1513 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 1524 1514 "ScaleUnit": "100%" 1525 1515 },
+12
tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
··· 101 101 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 102 102 "MetricName": "tma_backend_bound", 103 103 "MetricThreshold": "tma_backend_bound > 0.2", 104 + "MetricgroupNoGroup": "TopdownL1", 104 105 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 105 106 "ScaleUnit": "100%" 106 107 }, ··· 111 110 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 112 111 "MetricName": "tma_bad_speculation", 113 112 "MetricThreshold": "tma_bad_speculation > 0.15", 113 + "MetricgroupNoGroup": "TopdownL1", 114 114 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 115 115 "ScaleUnit": "100%" 116 116 }, ··· 122 120 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 123 121 "MetricName": "tma_branch_mispredicts", 124 122 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 123 + "MetricgroupNoGroup": "TopdownL2", 125 124 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 126 125 "ScaleUnit": "100%" 127 126 }, ··· 170 167 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 171 168 "MetricName": "tma_core_bound", 172 169 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 170 + "MetricgroupNoGroup": "TopdownL2", 173 171 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 174 172 "ScaleUnit": "100%" 175 173 }, ··· 275 271 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 276 272 "MetricName": "tma_fetch_bandwidth", 277 273 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 274 + "MetricgroupNoGroup": "TopdownL2", 278 275 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 279 276 "ScaleUnit": "100%" 280 277 }, ··· 285 280 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 286 281 "MetricName": "tma_fetch_latency", 287 282 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 283 + "MetricgroupNoGroup": "TopdownL2", 288 284 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 289 285 "ScaleUnit": "100%" 290 286 }, ··· 351 345 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 352 346 "MetricName": "tma_frontend_bound", 353 347 "MetricThreshold": "tma_frontend_bound > 0.15", 348 + "MetricgroupNoGroup": "TopdownL1", 354 349 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 355 350 "ScaleUnit": "100%" 356 351 }, ··· 370 363 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 371 364 "MetricName": "tma_heavy_operations", 372 365 "MetricThreshold": "tma_heavy_operations > 0.1", 366 + "MetricgroupNoGroup": "TopdownL2", 373 367 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 374 368 "ScaleUnit": "100%" 375 369 }, ··· 1073 1065 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1074 1066 "MetricName": "tma_light_operations", 1075 1067 "MetricThreshold": "tma_light_operations > 0.6", 1068 + "MetricgroupNoGroup": "TopdownL2", 1076 1069 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1077 1070 "ScaleUnit": "100%" 1078 1071 }, ··· 1119 1110 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1120 1111 "MetricName": "tma_machine_clears", 1121 1112 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1113 + "MetricgroupNoGroup": "TopdownL2", 1122 1114 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1123 1115 "ScaleUnit": "100%" 1124 1116 }, ··· 1148 1138 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1149 1139 "MetricName": "tma_memory_bound", 1150 1140 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1141 + "MetricgroupNoGroup": "TopdownL2", 1151 1142 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1152 1143 "ScaleUnit": "100%" 1153 1144 }, ··· 1354 1343 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1355 1344 "MetricName": "tma_retiring", 1356 1345 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1346 + "MetricgroupNoGroup": "TopdownL1", 1357 1347 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 1358 1348 "ScaleUnit": "100%" 1359 1349 },
+12
tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
··· 101 101 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 102 102 "MetricName": "tma_backend_bound", 103 103 "MetricThreshold": "tma_backend_bound > 0.2", 104 + "MetricgroupNoGroup": "TopdownL1", 104 105 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 105 106 "ScaleUnit": "100%" 106 107 }, ··· 111 110 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 112 111 "MetricName": "tma_bad_speculation", 113 112 "MetricThreshold": "tma_bad_speculation > 0.15", 113 + "MetricgroupNoGroup": "TopdownL1", 114 114 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 115 115 "ScaleUnit": "100%" 116 116 }, ··· 122 120 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 123 121 "MetricName": "tma_branch_mispredicts", 124 122 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 123 + "MetricgroupNoGroup": "TopdownL2", 125 124 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 126 125 "ScaleUnit": "100%" 127 126 }, ··· 170 167 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 171 168 "MetricName": "tma_core_bound", 172 169 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 170 + "MetricgroupNoGroup": "TopdownL2", 173 171 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 174 172 "ScaleUnit": "100%" 175 173 }, ··· 275 271 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 276 272 "MetricName": "tma_fetch_bandwidth", 277 273 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", 274 + "MetricgroupNoGroup": "TopdownL2", 278 275 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 279 276 "ScaleUnit": "100%" 280 277 }, ··· 285 280 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 286 281 "MetricName": "tma_fetch_latency", 287 282 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 283 + "MetricgroupNoGroup": "TopdownL2", 288 284 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 289 285 "ScaleUnit": "100%" 290 286 }, ··· 360 354 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 361 355 "MetricName": "tma_frontend_bound", 362 356 "MetricThreshold": "tma_frontend_bound > 0.15", 357 + "MetricgroupNoGroup": "TopdownL1", 363 358 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 364 359 "ScaleUnit": "100%" 365 360 }, ··· 379 372 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 380 373 "MetricName": "tma_heavy_operations", 381 374 "MetricThreshold": "tma_heavy_operations > 0.1", 375 + "MetricgroupNoGroup": "TopdownL2", 382 376 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 383 377 "ScaleUnit": "100%" 384 378 }, ··· 1131 1123 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1132 1124 "MetricName": "tma_light_operations", 1133 1125 "MetricThreshold": "tma_light_operations > 0.6", 1126 + "MetricgroupNoGroup": "TopdownL2", 1134 1127 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1135 1128 "ScaleUnit": "100%" 1136 1129 }, ··· 1186 1177 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1187 1178 "MetricName": "tma_machine_clears", 1188 1179 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1180 + "MetricgroupNoGroup": "TopdownL2", 1189 1181 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1190 1182 "ScaleUnit": "100%" 1191 1183 }, ··· 1215 1205 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1216 1206 "MetricName": "tma_memory_bound", 1217 1207 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1208 + "MetricgroupNoGroup": "TopdownL2", 1218 1209 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1219 1210 "ScaleUnit": "100%" 1220 1211 }, ··· 1440 1429 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1441 1430 "MetricName": "tma_retiring", 1442 1431 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1432 + "MetricgroupNoGroup": "TopdownL1", 1443 1433 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 1444 1434 "ScaleUnit": "100%" 1445 1435 },
+12
tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
··· 109 109 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 110 110 "MetricName": "tma_backend_bound", 111 111 "MetricThreshold": "tma_backend_bound > 0.2", 112 + "MetricgroupNoGroup": "TopdownL1", 112 113 "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 113 114 "ScaleUnit": "100%" 114 115 }, ··· 119 118 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 120 119 "MetricName": "tma_bad_speculation", 121 120 "MetricThreshold": "tma_bad_speculation > 0.15", 121 + "MetricgroupNoGroup": "TopdownL1", 122 122 "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 123 123 "ScaleUnit": "100%" 124 124 }, ··· 137 135 "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 138 136 "MetricName": "tma_branch_mispredicts", 139 137 "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 138 + "MetricgroupNoGroup": "TopdownL2", 140 139 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", 141 140 "ScaleUnit": "100%" 142 141 }, ··· 184 181 "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 185 182 "MetricName": "tma_core_bound", 186 183 "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 184 + "MetricgroupNoGroup": "TopdownL2", 187 185 "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 188 186 "ScaleUnit": "100%" 189 187 }, ··· 286 282 "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 287 283 "MetricName": "tma_fetch_bandwidth", 288 284 "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35", 285 + "MetricgroupNoGroup": "TopdownL2", 289 286 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", 290 287 "ScaleUnit": "100%" 291 288 }, ··· 296 291 "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 297 292 "MetricName": "tma_fetch_latency", 298 293 "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 294 + "MetricgroupNoGroup": "TopdownL2", 299 295 "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 300 296 "ScaleUnit": "100%" 301 297 }, ··· 369 363 "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 370 364 "MetricName": "tma_frontend_bound", 371 365 "MetricThreshold": "tma_frontend_bound > 0.15", 366 + "MetricgroupNoGroup": "TopdownL1", 372 367 "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 373 368 "ScaleUnit": "100%" 374 369 }, ··· 379 372 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 380 373 "MetricName": "tma_heavy_operations", 381 374 "MetricThreshold": "tma_heavy_operations > 0.1", 375 + "MetricgroupNoGroup": "TopdownL2", 382 376 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 383 377 "ScaleUnit": "100%" 384 378 }, ··· 1133 1125 "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1134 1126 "MetricName": "tma_light_operations", 1135 1127 "MetricThreshold": "tma_light_operations > 0.6", 1128 + "MetricgroupNoGroup": "TopdownL2", 1136 1129 "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1137 1130 "ScaleUnit": "100%" 1138 1131 }, ··· 1187 1178 "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1188 1179 "MetricName": "tma_machine_clears", 1189 1180 "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1181 + "MetricgroupNoGroup": "TopdownL2", 1190 1182 "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1191 1183 "ScaleUnit": "100%" 1192 1184 }, ··· 1215 1205 "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1216 1206 "MetricName": "tma_memory_bound", 1217 1207 "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1208 + "MetricgroupNoGroup": "TopdownL2", 1218 1209 "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1219 1210 "ScaleUnit": "100%" 1220 1211 }, ··· 1385 1374 "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 1386 1375 "MetricName": "tma_retiring", 1387 1376 "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1377 + "MetricgroupNoGroup": "TopdownL1", 1388 1378 "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 1389 1379 "ScaleUnit": "100%" 1390 1380 },
+3 -1
tools/perf/pmu-events/jevents.py
··· 52 52 # Attributes that are in pmu_metric rather than pmu_event. 53 53 _json_metric_attributes = [ 54 54 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', 'desc', 55 - 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' 55 + 'long_desc', 'unit', 'compat', 'metricgroup_no_group', 'aggr_mode', 56 + 'event_grouping' 56 57 ] 57 58 # Attributes that are bools or enum int values, encoded as '0', '1',... 58 59 _json_enum_attributes = ['aggr_mode', 'deprecated', 'event_grouping', 'perpkg'] ··· 304 303 self.deprecated = jd.get('Deprecated') 305 304 self.metric_name = jd.get('MetricName') 306 305 self.metric_group = jd.get('MetricGroup') 306 + self.metricgroup_no_group = jd.get('MetricgroupNoGroup') 307 307 self.event_grouping = convert_metric_constraint(jd.get('MetricConstraint')) 308 308 self.metric_expr = None 309 309 if 'MetricExpr' in jd:
+1
tools/perf/pmu-events/pmu-events.h
··· 59 59 const char *compat; 60 60 const char *desc; 61 61 const char *long_desc; 62 + const char *metricgroup_no_group; 62 63 enum aggr_mode_class aggr_mode; 63 64 enum metric_event_groups event_grouping; 64 65 };
+3 -3
tools/perf/tests/attr.py
··· 152 152 # - expected values assignments 153 153 class Test(object): 154 154 def __init__(self, path, options): 155 - parser = configparser.SafeConfigParser() 155 + parser = configparser.ConfigParser() 156 156 parser.read(path) 157 157 158 158 log.warning("running '%s'" % path) ··· 247 247 return True 248 248 249 249 def load_events(self, path, events): 250 - parser_event = configparser.SafeConfigParser() 250 + parser_event = configparser.ConfigParser() 251 251 parser_event.read(path) 252 252 253 253 # The event record section header contains 'event' word, ··· 261 261 # Read parent event if there's any 262 262 if (':' in section): 263 263 base = section[section.index(':') + 1:] 264 - parser_base = configparser.SafeConfigParser() 264 + parser_base = configparser.ConfigParser() 265 265 parser_base.read(self.test_dir + '/' + base) 266 266 base_items = parser_base.items('event') 267 267
+1 -1
tools/perf/tests/attr/base-stat
··· 16 16 exclusive=0 17 17 exclude_user=0 18 18 exclude_kernel=0|1 19 - exclude_hv=0 19 + exclude_hv=0|1 20 20 exclude_idle=0 21 21 mmap=0 22 22 comm=0
+57 -39
tools/perf/tests/attr/test-stat-default
··· 40 40 type=0 41 41 config=7 42 42 optional=1 43 - 44 43 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND 45 44 [event7:base-stat] 46 45 fd=7 ··· 88 89 read_format=15 89 90 optional=1 90 91 91 - # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 92 + # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 92 93 [event13:base-stat] 93 94 fd=13 94 - group_fd=11 95 - type=4 96 - config=33024 97 - disabled=0 98 - enable_on_exec=0 99 - read_format=15 100 - optional=1 101 - 102 - # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 103 - [event14:base-stat] 104 - fd=14 105 95 group_fd=11 106 96 type=4 107 97 config=33280 ··· 100 112 optional=1 101 113 102 114 # PERF_TYPE_RAW / topdown-be-bound (0x8300) 103 - [event15:base-stat] 104 - fd=15 115 + [event14:base-stat] 116 + fd=14 105 117 group_fd=11 106 118 type=4 107 119 config=33536 ··· 110 122 read_format=15 111 123 optional=1 112 124 113 - # PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 125 + # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 126 + [event15:base-stat] 127 + fd=15 128 + group_fd=11 129 + type=4 130 + config=33024 131 + disabled=0 132 + enable_on_exec=0 133 + read_format=15 134 + optional=1 135 + 136 + # PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 114 137 [event16:base-stat] 115 138 fd=16 116 - group_fd=11 117 139 type=4 118 - config=33792 119 - disabled=0 120 - enable_on_exec=0 121 - read_format=15 140 + config=4109 122 141 optional=1 123 142 124 - # PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 143 + # PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 125 144 [event17:base-stat] 126 145 fd=17 127 - group_fd=11 128 146 type=4 129 - config=34048 130 - disabled=0 131 - enable_on_exec=0 132 - read_format=15 147 + config=17039629 133 148 optional=1 134 149 135 - # PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 150 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 136 151 [event18:base-stat] 137 152 fd=18 138 - group_fd=11 139 153 type=4 140 - config=34304 141 - disabled=0 142 - enable_on_exec=0 143 - read_format=15 154 + config=60 144 155 optional=1 145 156 146 - # PERF_TYPE_RAW / topdown-mem-bound (0x8700) 157 + # PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 147 158 [event19:base-stat] 148 159 fd=19 149 - group_fd=11 150 160 type=4 151 - config=34560 152 - disabled=0 153 - enable_on_exec=0 154 - read_format=15 161 + config=2097421 162 + optional=1 163 + 164 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 165 + [event20:base-stat] 166 + fd=20 167 + type=4 168 + config=316 169 + optional=1 170 + 171 + # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 172 + [event21:base-stat] 173 + fd=21 174 + type=4 175 + config=412 176 + optional=1 177 + 178 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 179 + [event22:base-stat] 180 + fd=22 181 + type=4 182 + config=572 183 + optional=1 184 + 185 + # PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 186 + [event23:base-stat] 187 + fd=23 188 + type=4 189 + config=706 190 + optional=1 191 + 192 + # PERF_TYPE_RAW / UOPS_ISSUED.ANY 193 + [event24:base-stat] 194 + fd=24 195 + type=4 196 + config=270 155 197 optional=1
+65 -46
tools/perf/tests/attr/test-stat-detailed-1
··· 90 90 read_format=15 91 91 optional=1 92 92 93 - # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 93 + # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 94 94 [event13:base-stat] 95 95 fd=13 96 - group_fd=11 97 - type=4 98 - config=33024 99 - disabled=0 100 - enable_on_exec=0 101 - read_format=15 102 - optional=1 103 - 104 - # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 105 - [event14:base-stat] 106 - fd=14 107 96 group_fd=11 108 97 type=4 109 98 config=33280 ··· 102 113 optional=1 103 114 104 115 # PERF_TYPE_RAW / topdown-be-bound (0x8300) 105 - [event15:base-stat] 106 - fd=15 116 + [event14:base-stat] 117 + fd=14 107 118 group_fd=11 108 119 type=4 109 120 config=33536 ··· 112 123 read_format=15 113 124 optional=1 114 125 115 - # PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 126 + # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 127 + [event15:base-stat] 128 + fd=15 129 + group_fd=11 130 + type=4 131 + config=33024 132 + disabled=0 133 + enable_on_exec=0 134 + read_format=15 135 + optional=1 136 + 137 + # PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 116 138 [event16:base-stat] 117 139 fd=16 118 - group_fd=11 119 140 type=4 120 - config=33792 121 - disabled=0 122 - enable_on_exec=0 123 - read_format=15 141 + config=4109 124 142 optional=1 125 143 126 - # PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 144 + # PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 127 145 [event17:base-stat] 128 146 fd=17 129 - group_fd=11 130 147 type=4 131 - config=34048 132 - disabled=0 133 - enable_on_exec=0 134 - read_format=15 148 + config=17039629 135 149 optional=1 136 150 137 - # PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 151 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 138 152 [event18:base-stat] 139 153 fd=18 140 - group_fd=11 141 154 type=4 142 - config=34304 143 - disabled=0 144 - enable_on_exec=0 145 - read_format=15 155 + config=60 146 156 optional=1 147 157 148 - # PERF_TYPE_RAW / topdown-mem-bound (0x8700) 158 + # PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 149 159 [event19:base-stat] 150 160 fd=19 151 - group_fd=11 152 161 type=4 153 - config=34560 154 - disabled=0 155 - enable_on_exec=0 156 - read_format=15 162 + config=2097421 163 + optional=1 164 + 165 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 166 + [event20:base-stat] 167 + fd=20 168 + type=4 169 + config=316 170 + optional=1 171 + 172 + # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 173 + [event21:base-stat] 174 + fd=21 175 + type=4 176 + config=412 177 + optional=1 178 + 179 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 180 + [event22:base-stat] 181 + fd=22 182 + type=4 183 + config=572 184 + optional=1 185 + 186 + # PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 187 + [event23:base-stat] 188 + fd=23 189 + type=4 190 + config=706 191 + optional=1 192 + 193 + # PERF_TYPE_RAW / UOPS_ISSUED.ANY 194 + [event24:base-stat] 195 + fd=24 196 + type=4 197 + config=270 157 198 optional=1 158 199 159 200 # PERF_TYPE_HW_CACHE / 160 201 # PERF_COUNT_HW_CACHE_L1D << 0 | 161 202 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 162 203 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 163 - [event20:base-stat] 164 - fd=20 204 + [event25:base-stat] 205 + fd=25 165 206 type=3 166 207 config=0 167 208 optional=1 ··· 200 181 # PERF_COUNT_HW_CACHE_L1D << 0 | 201 182 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 202 183 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 203 - [event21:base-stat] 204 - fd=21 184 + [event26:base-stat] 185 + fd=26 205 186 type=3 206 187 config=65536 207 188 optional=1 ··· 210 191 # PERF_COUNT_HW_CACHE_LL << 0 | 211 192 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 212 193 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 213 - [event22:base-stat] 214 - fd=22 194 + [event27:base-stat] 195 + fd=27 215 196 type=3 216 197 config=2 217 198 optional=1 ··· 220 201 # PERF_COUNT_HW_CACHE_LL << 0 | 221 202 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 222 203 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 223 - [event23:base-stat] 224 - fd=23 204 + [event28:base-stat] 205 + fd=28 225 206 type=3 226 207 config=65538 227 208 optional=1
+77 -58
tools/perf/tests/attr/test-stat-detailed-2
··· 90 90 read_format=15 91 91 optional=1 92 92 93 - # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 93 + # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 94 94 [event13:base-stat] 95 95 fd=13 96 - group_fd=11 97 - type=4 98 - config=33024 99 - disabled=0 100 - enable_on_exec=0 101 - read_format=15 102 - optional=1 103 - 104 - # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 105 - [event14:base-stat] 106 - fd=14 107 96 group_fd=11 108 97 type=4 109 98 config=33280 ··· 102 113 optional=1 103 114 104 115 # PERF_TYPE_RAW / topdown-be-bound (0x8300) 105 - [event15:base-stat] 106 - fd=15 116 + [event14:base-stat] 117 + fd=14 107 118 group_fd=11 108 119 type=4 109 120 config=33536 ··· 112 123 read_format=15 113 124 optional=1 114 125 115 - # PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 126 + # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 127 + [event15:base-stat] 128 + fd=15 129 + group_fd=11 130 + type=4 131 + config=33024 132 + disabled=0 133 + enable_on_exec=0 134 + read_format=15 135 + optional=1 136 + 137 + # PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 116 138 [event16:base-stat] 117 139 fd=16 118 - group_fd=11 119 140 type=4 120 - config=33792 121 - disabled=0 122 - enable_on_exec=0 123 - read_format=15 141 + config=4109 124 142 optional=1 125 143 126 - # PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 144 + # PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 127 145 [event17:base-stat] 128 146 fd=17 129 - group_fd=11 130 147 type=4 131 - config=34048 132 - disabled=0 133 - enable_on_exec=0 134 - read_format=15 148 + config=17039629 135 149 optional=1 136 150 137 - # PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 151 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 138 152 [event18:base-stat] 139 153 fd=18 140 - group_fd=11 141 154 type=4 142 - config=34304 143 - disabled=0 144 - enable_on_exec=0 145 - read_format=15 155 + config=60 146 156 optional=1 147 157 148 - # PERF_TYPE_RAW / topdown-mem-bound (0x8700) 158 + # PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 149 159 [event19:base-stat] 150 160 fd=19 151 - group_fd=11 152 161 type=4 153 - config=34560 154 - disabled=0 155 - enable_on_exec=0 156 - read_format=15 162 + config=2097421 163 + optional=1 164 + 165 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 166 + [event20:base-stat] 167 + fd=20 168 + type=4 169 + config=316 170 + optional=1 171 + 172 + # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 173 + [event21:base-stat] 174 + fd=21 175 + type=4 176 + config=412 177 + optional=1 178 + 179 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 180 + [event22:base-stat] 181 + fd=22 182 + type=4 183 + config=572 184 + optional=1 185 + 186 + # PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 187 + [event23:base-stat] 188 + fd=23 189 + type=4 190 + config=706 191 + optional=1 192 + 193 + # PERF_TYPE_RAW / UOPS_ISSUED.ANY 194 + [event24:base-stat] 195 + fd=24 196 + type=4 197 + config=270 157 198 optional=1 158 199 159 200 # PERF_TYPE_HW_CACHE / 160 201 # PERF_COUNT_HW_CACHE_L1D << 0 | 161 202 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 162 203 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 163 - [event20:base-stat] 164 - fd=20 204 + [event25:base-stat] 205 + fd=25 165 206 type=3 166 207 config=0 167 208 optional=1 ··· 200 181 # PERF_COUNT_HW_CACHE_L1D << 0 | 201 182 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 202 183 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 203 - [event21:base-stat] 204 - fd=21 184 + [event26:base-stat] 185 + fd=26 205 186 type=3 206 187 config=65536 207 188 optional=1 ··· 210 191 # PERF_COUNT_HW_CACHE_LL << 0 | 211 192 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 212 193 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 213 - [event22:base-stat] 214 - fd=22 194 + [event27:base-stat] 195 + fd=27 215 196 type=3 216 197 config=2 217 198 optional=1 ··· 220 201 # PERF_COUNT_HW_CACHE_LL << 0 | 221 202 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 222 203 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 223 - [event23:base-stat] 224 - fd=23 204 + [event28:base-stat] 205 + fd=28 225 206 type=3 226 207 config=65538 227 208 optional=1 ··· 230 211 # PERF_COUNT_HW_CACHE_L1I << 0 | 231 212 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 232 213 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 233 - [event24:base-stat] 234 - fd=24 214 + [event29:base-stat] 215 + fd=29 235 216 type=3 236 217 config=1 237 218 optional=1 ··· 240 221 # PERF_COUNT_HW_CACHE_L1I << 0 | 241 222 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 242 223 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 243 - [event25:base-stat] 244 - fd=25 224 + [event30:base-stat] 225 + fd=30 245 226 type=3 246 227 config=65537 247 228 optional=1 ··· 250 231 # PERF_COUNT_HW_CACHE_DTLB << 0 | 251 232 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 252 233 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 253 - [event26:base-stat] 254 - fd=26 234 + [event31:base-stat] 235 + fd=31 255 236 type=3 256 237 config=3 257 238 optional=1 ··· 260 241 # PERF_COUNT_HW_CACHE_DTLB << 0 | 261 242 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 262 243 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 263 - [event27:base-stat] 264 - fd=27 244 + [event32:base-stat] 245 + fd=32 265 246 type=3 266 247 config=65539 267 248 optional=1 ··· 270 251 # PERF_COUNT_HW_CACHE_ITLB << 0 | 271 252 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 272 253 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 273 - [event28:base-stat] 274 - fd=28 254 + [event33:base-stat] 255 + fd=33 275 256 type=3 276 257 config=4 277 258 optional=1 ··· 280 261 # PERF_COUNT_HW_CACHE_ITLB << 0 | 281 262 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 282 263 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 283 - [event29:base-stat] 284 - fd=29 264 + [event34:base-stat] 265 + fd=34 285 266 type=3 286 267 config=65540 287 268 optional=1
+81 -62
tools/perf/tests/attr/test-stat-detailed-3
··· 90 90 read_format=15 91 91 optional=1 92 92 93 - # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 93 + # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 94 94 [event13:base-stat] 95 95 fd=13 96 - group_fd=11 97 - type=4 98 - config=33024 99 - disabled=0 100 - enable_on_exec=0 101 - read_format=15 102 - optional=1 103 - 104 - # PERF_TYPE_RAW / topdown-fe-bound (0x8200) 105 - [event14:base-stat] 106 - fd=14 107 96 group_fd=11 108 97 type=4 109 98 config=33280 ··· 102 113 optional=1 103 114 104 115 # PERF_TYPE_RAW / topdown-be-bound (0x8300) 105 - [event15:base-stat] 106 - fd=15 116 + [event14:base-stat] 117 + fd=14 107 118 group_fd=11 108 119 type=4 109 120 config=33536 ··· 112 123 read_format=15 113 124 optional=1 114 125 115 - # PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 126 + # PERF_TYPE_RAW / topdown-bad-spec (0x8100) 127 + [event15:base-stat] 128 + fd=15 129 + group_fd=11 130 + type=4 131 + config=33024 132 + disabled=0 133 + enable_on_exec=0 134 + read_format=15 135 + optional=1 136 + 137 + # PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 116 138 [event16:base-stat] 117 139 fd=16 118 - group_fd=11 119 140 type=4 120 - config=33792 121 - disabled=0 122 - enable_on_exec=0 123 - read_format=15 141 + config=4109 124 142 optional=1 125 143 126 - # PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 144 + # PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 127 145 [event17:base-stat] 128 146 fd=17 129 - group_fd=11 130 147 type=4 131 - config=34048 132 - disabled=0 133 - enable_on_exec=0 134 - read_format=15 148 + config=17039629 135 149 optional=1 136 150 137 - # PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 151 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 138 152 [event18:base-stat] 139 153 fd=18 140 - group_fd=11 141 154 type=4 142 - config=34304 143 - disabled=0 144 - enable_on_exec=0 145 - read_format=15 155 + config=60 146 156 optional=1 147 157 148 - # PERF_TYPE_RAW / topdown-mem-bound (0x8700) 158 + # PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 149 159 [event19:base-stat] 150 160 fd=19 151 - group_fd=11 152 161 type=4 153 - config=34560 154 - disabled=0 155 - enable_on_exec=0 156 - read_format=15 162 + config=2097421 163 + optional=1 164 + 165 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 166 + [event20:base-stat] 167 + fd=20 168 + type=4 169 + config=316 170 + optional=1 171 + 172 + # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 173 + [event21:base-stat] 174 + fd=21 175 + type=4 176 + config=412 177 + optional=1 178 + 179 + # PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 180 + [event22:base-stat] 181 + fd=22 182 + type=4 183 + config=572 184 + optional=1 185 + 186 + # PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 187 + [event23:base-stat] 188 + fd=23 189 + type=4 190 + config=706 191 + optional=1 192 + 193 + # PERF_TYPE_RAW / UOPS_ISSUED.ANY 194 + [event24:base-stat] 195 + fd=24 196 + type=4 197 + config=270 157 198 optional=1 158 199 159 200 # PERF_TYPE_HW_CACHE / 160 201 # PERF_COUNT_HW_CACHE_L1D << 0 | 161 202 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 162 203 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 163 - [event20:base-stat] 164 - fd=20 204 + [event25:base-stat] 205 + fd=25 165 206 type=3 166 207 config=0 167 208 optional=1 ··· 200 181 # PERF_COUNT_HW_CACHE_L1D << 0 | 201 182 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 202 183 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 203 - [event21:base-stat] 204 - fd=21 184 + [event26:base-stat] 185 + fd=26 205 186 type=3 206 187 config=65536 207 188 optional=1 ··· 210 191 # PERF_COUNT_HW_CACHE_LL << 0 | 211 192 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 212 193 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 213 - [event22:base-stat] 214 - fd=22 194 + [event27:base-stat] 195 + fd=27 215 196 type=3 216 197 config=2 217 198 optional=1 ··· 220 201 # PERF_COUNT_HW_CACHE_LL << 0 | 221 202 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 222 203 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 223 - [event23:base-stat] 224 - fd=23 204 + [event28:base-stat] 205 + fd=28 225 206 type=3 226 207 config=65538 227 208 optional=1 ··· 230 211 # PERF_COUNT_HW_CACHE_L1I << 0 | 231 212 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 232 213 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 233 - [event24:base-stat] 234 - fd=24 214 + [event29:base-stat] 215 + fd=29 235 216 type=3 236 217 config=1 237 218 optional=1 ··· 240 221 # PERF_COUNT_HW_CACHE_L1I << 0 | 241 222 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 242 223 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 243 - [event25:base-stat] 244 - fd=25 224 + [event30:base-stat] 225 + fd=30 245 226 type=3 246 227 config=65537 247 228 optional=1 ··· 250 231 # PERF_COUNT_HW_CACHE_DTLB << 0 | 251 232 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 252 233 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 253 - [event26:base-stat] 254 - fd=26 234 + [event31:base-stat] 235 + fd=31 255 236 type=3 256 237 config=3 257 238 optional=1 ··· 260 241 # PERF_COUNT_HW_CACHE_DTLB << 0 | 261 242 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 262 243 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 263 - [event27:base-stat] 264 - fd=27 244 + [event32:base-stat] 245 + fd=32 265 246 type=3 266 247 config=65539 267 248 optional=1 ··· 270 251 # PERF_COUNT_HW_CACHE_ITLB << 0 | 271 252 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 272 253 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 273 - [event28:base-stat] 274 - fd=28 254 + [event33:base-stat] 255 + fd=33 275 256 type=3 276 257 config=4 277 258 optional=1 ··· 280 261 # PERF_COUNT_HW_CACHE_ITLB << 0 | 281 262 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 282 263 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 283 - [event29:base-stat] 284 - fd=29 264 + [event34:base-stat] 265 + fd=34 285 266 type=3 286 267 config=65540 287 268 optional=1 ··· 290 271 # PERF_COUNT_HW_CACHE_L1D << 0 | 291 272 # (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | 292 273 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 293 - [event30:base-stat] 294 - fd=30 274 + [event35:base-stat] 275 + fd=35 295 276 type=3 296 277 config=512 297 278 optional=1 ··· 300 281 # PERF_COUNT_HW_CACHE_L1D << 0 | 301 282 # (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | 302 283 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 303 - [event31:base-stat] 304 - fd=31 284 + [event36:base-stat] 285 + fd=36 305 286 type=3 306 287 config=66048 307 288 optional=1
+2 -1
tools/perf/tests/expr.c
··· 120 120 121 121 p = "FOO/0"; 122 122 ret = expr__parse(&val, ctx, p); 123 - TEST_ASSERT_VAL("division by zero", ret == -1); 123 + TEST_ASSERT_VAL("division by zero", ret == 0); 124 + TEST_ASSERT_VAL("division by zero", isnan(val)); 124 125 125 126 p = "BAR/"; 126 127 ret = expr__parse(&val, ctx, p);
+1
tools/perf/tests/parse-metric.c
··· 38 38 evlist__alloc_aggr_stats(evlist, 1); 39 39 evlist__for_each_entry(evlist, evsel) { 40 40 count = find_value(evsel->name, vals); 41 + evsel->supported = true; 41 42 evsel->stats->aggr->counts.val = count; 42 43 if (evsel__name_is(evsel, "duration_time")) 43 44 update_stats(&walltime_nsecs_stats, count);
+13
tools/perf/tests/shell/stat.sh
··· 28 28 echo "stat record and report test [Success]" 29 29 } 30 30 31 + test_stat_record_script() { 32 + echo "stat record and script test" 33 + if ! perf stat record -o - true | perf script -i - 2>&1 | \ 34 + grep -E -q "CPU[[:space:]]+THREAD[[:space:]]+VAL[[:space:]]+ENA[[:space:]]+RUN[[:space:]]+TIME[[:space:]]+EVENT" 35 + then 36 + echo "stat record and script test [Failed]" 37 + err=1 38 + return 39 + fi 40 + echo "stat record and script test [Success]" 41 + } 42 + 31 43 test_stat_repeat_weak_groups() { 32 44 echo "stat repeat weak groups test" 33 45 if ! perf stat -e '{cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles}' \ ··· 105 93 106 94 test_default_stat 107 95 test_stat_record_report 96 + test_stat_record_script 108 97 test_stat_repeat_weak_groups 109 98 test_topdown_groups 110 99 test_topdown_weak_groups
+7
tools/perf/tests/shell/test_intel_pt.sh
··· 506 506 echo "perf record failed with --aux-sample" 507 507 return 1 508 508 fi 509 + # Check with event with PMU name 510 + if perf_record_no_decode -o "${perfdatafile}" -e br_misp_retired.all_branches:u uname ; then 511 + if ! perf_record_no_decode -o "${perfdatafile}" -e '{intel_pt//,br_misp_retired.all_branches/aux-sample-size=8192/}:u' uname ; then 512 + echo "perf record failed with --aux-sample-size" 513 + return 1 514 + fi 515 + fi 509 516 echo OK 510 517 return 0 511 518 }
+1 -1
tools/perf/tests/shell/test_java_symbol.sh
··· 56 56 exit 1 57 57 fi 58 58 59 - if ! perf inject -i $PERF_DATA -o $PERF_INJ_DATA -j; then 59 + if ! DEBUGINFOD_URLS='' perf inject -i $PERF_DATA -o $PERF_INJ_DATA -j; then 60 60 echo "Fail to inject samples" 61 61 exit 1 62 62 fi
+2
tools/perf/trace/beauty/arch_prctl.c
··· 12 12 13 13 static DEFINE_STRARRAY_OFFSET(x86_arch_prctl_codes_1, "ARCH_", x86_arch_prctl_codes_1_offset); 14 14 static DEFINE_STRARRAY_OFFSET(x86_arch_prctl_codes_2, "ARCH_", x86_arch_prctl_codes_2_offset); 15 + static DEFINE_STRARRAY_OFFSET(x86_arch_prctl_codes_3, "ARCH_", x86_arch_prctl_codes_3_offset); 15 16 16 17 static struct strarray *x86_arch_prctl_codes[] = { 17 18 &strarray__x86_arch_prctl_codes_1, 18 19 &strarray__x86_arch_prctl_codes_2, 20 + &strarray__x86_arch_prctl_codes_3, 19 21 }; 20 22 21 23 static DEFINE_STRARRAYS(x86_arch_prctl_codes);
+1
tools/perf/trace/beauty/x86_arch_prctl.sh
··· 24 24 25 25 print_range 1 0x1 0x1001 26 26 print_range 2 0x2 0x2001 27 + print_range 3 0x4 0x4001
+2
tools/perf/util/bpf_skel/lock_contention.bpf.c
··· 416 416 return 0; 417 417 } 418 418 419 + struct rq {}; 420 + 419 421 extern struct rq runqueues __ksym; 420 422 421 423 struct rq___old {
+1
tools/perf/util/bpf_skel/vmlinux.h
··· 1 1 #ifndef __VMLINUX_H 2 2 #define __VMLINUX_H 3 3 4 + #include <linux/stddef.h> // for define __always_inline 4 5 #include <linux/bpf.h> 5 6 #include <linux/types.h> 6 7 #include <linux/perf_event.h>
+24 -13
tools/perf/util/evsel.c
··· 290 290 evsel->per_pkg_mask = NULL; 291 291 evsel->collect_stat = false; 292 292 evsel->pmu_name = NULL; 293 + evsel->skippable = false; 293 294 } 294 295 295 296 struct evsel *evsel__new_idx(struct perf_event_attr *attr, int idx) ··· 829 828 830 829 const char *evsel__group_pmu_name(const struct evsel *evsel) 831 830 { 832 - const struct evsel *leader; 831 + struct evsel *leader = evsel__leader(evsel); 832 + struct evsel *pos; 833 833 834 - /* If the pmu_name is set use it. pmu_name isn't set for CPU and software events. */ 835 - if (evsel->pmu_name) 836 - return evsel->pmu_name; 837 834 /* 838 835 * Software events may be in a group with other uncore PMU events. Use 839 - * the pmu_name of the group leader to avoid breaking the software event 840 - * out of the group. 836 + * the pmu_name of the first non-software event to avoid breaking the 837 + * software event out of the group. 841 838 * 842 839 * Aux event leaders, like intel_pt, expect a group with events from 843 840 * other PMUs, so substitute the AUX event's PMU in this case. 844 841 */ 845 - leader = evsel__leader(evsel); 846 - if ((evsel->core.attr.type == PERF_TYPE_SOFTWARE || evsel__is_aux_event(leader)) && 847 - leader->pmu_name) { 848 - return leader->pmu_name; 842 + if (evsel->core.attr.type == PERF_TYPE_SOFTWARE || evsel__is_aux_event(leader)) { 843 + /* Starting with the leader, find the first event with a named PMU. */ 844 + for_each_group_evsel(pos, leader) { 845 + if (pos->pmu_name) 846 + return pos->pmu_name; 847 + } 849 848 } 850 849 851 - return "cpu"; 850 + return evsel->pmu_name ?: "cpu"; 852 851 } 853 852 854 853 const char *evsel__metric_id(const struct evsel *evsel) ··· 1726 1725 return -1; 1727 1726 1728 1727 fd = FD(leader, cpu_map_idx, thread); 1729 - BUG_ON(fd == -1); 1728 + BUG_ON(fd == -1 && !leader->skippable); 1730 1729 1731 - return fd; 1730 + /* 1731 + * When the leader has been skipped, return -2 to distinguish from no 1732 + * group leader case. 1733 + */ 1734 + return fd == -1 ? -2 : fd; 1732 1735 } 1733 1736 1734 1737 static void evsel__remove_fd(struct evsel *pos, int nr_cpus, int nr_threads, int thread_idx) ··· 2113 2108 pid = perf_thread_map__pid(threads, thread); 2114 2109 2115 2110 group_fd = get_group_fd(evsel, idx, thread); 2111 + 2112 + if (group_fd == -2) { 2113 + pr_debug("broken group leader for %s\n", evsel->name); 2114 + err = -EINVAL; 2115 + goto out_close; 2116 + } 2116 2117 2117 2118 test_attr__ready(); 2118 2119
+1
tools/perf/util/evsel.h
··· 95 95 bool weak_group; 96 96 bool bpf_counter; 97 97 bool use_config_name; 98 + bool skippable; 98 99 int bpf_fd; 99 100 struct bpf_object *bpf_obj; 100 101 struct list_head config_terms;
+5 -1
tools/perf/util/expr.y
··· 225 225 { 226 226 if (fpclassify($3.val) == FP_ZERO) { 227 227 pr_debug("division by zero\n"); 228 - YYABORT; 228 + assert($3.ids == NULL); 229 + if (compute_ids) 230 + ids__free($1.ids); 231 + $$.val = NAN; 232 + $$.ids = NULL; 229 233 } else if (!compute_ids || (is_const($1.val) && is_const($3.val))) { 230 234 assert($1.ids == NULL); 231 235 assert($3.ids == NULL);
+5 -5
tools/perf/util/metricgroup.c
··· 1144 1144 struct metricgroup__add_metric_data *data = vdata; 1145 1145 int ret = 0; 1146 1146 1147 - if (pm->metric_expr && 1148 - (match_metric(pm->metric_group, data->metric_name) || 1149 - match_metric(pm->metric_name, data->metric_name))) { 1147 + if (pm->metric_expr && match_pm_metric(pm, data->metric_name)) { 1148 + bool metric_no_group = data->metric_no_group || 1149 + match_metric(data->metric_name, pm->metricgroup_no_group); 1150 1150 1151 1151 data->has_match = true; 1152 - ret = add_metric(data->list, pm, data->modifier, data->metric_no_group, 1152 + ret = add_metric(data->list, pm, data->modifier, metric_no_group, 1153 1153 data->metric_no_threshold, data->user_requested_cpu_list, 1154 1154 data->system_wide, /*root_metric=*/NULL, 1155 1155 /*visited_metrics=*/NULL, table); ··· 1672 1672 { 1673 1673 unsigned int *max_level = data; 1674 1674 unsigned int level; 1675 - const char *p = strstr(pm->metric_group, "TopdownL"); 1675 + const char *p = strstr(pm->metric_group ?: "", "TopdownL"); 1676 1676 1677 1677 if (!p || p[8] == '\0') 1678 1678 return 0;
+15 -8
tools/perf/util/parse-events.c
··· 2140 2140 int *leader_idx = state; 2141 2141 int lhs_leader_idx = *leader_idx, rhs_leader_idx = *leader_idx, ret; 2142 2142 const char *lhs_pmu_name, *rhs_pmu_name; 2143 + bool lhs_has_group = false, rhs_has_group = false; 2143 2144 2144 2145 /* 2145 2146 * First sort by grouping/leader. Read the leader idx only if the evsel 2146 2147 * is part of a group, as -1 indicates no group. 2147 2148 */ 2148 - if (lhs_core->leader != lhs_core || lhs_core->nr_members > 1) 2149 + if (lhs_core->leader != lhs_core || lhs_core->nr_members > 1) { 2150 + lhs_has_group = true; 2149 2151 lhs_leader_idx = lhs_core->leader->idx; 2150 - if (rhs_core->leader != rhs_core || rhs_core->nr_members > 1) 2152 + } 2153 + if (rhs_core->leader != rhs_core || rhs_core->nr_members > 1) { 2154 + rhs_has_group = true; 2151 2155 rhs_leader_idx = rhs_core->leader->idx; 2156 + } 2152 2157 2153 2158 if (lhs_leader_idx != rhs_leader_idx) 2154 2159 return lhs_leader_idx - rhs_leader_idx; 2155 2160 2156 - /* Group by PMU. Groups can't span PMUs. */ 2157 - lhs_pmu_name = evsel__group_pmu_name(lhs); 2158 - rhs_pmu_name = evsel__group_pmu_name(rhs); 2159 - ret = strcmp(lhs_pmu_name, rhs_pmu_name); 2160 - if (ret) 2161 - return ret; 2161 + /* Group by PMU if there is a group. Groups can't span PMUs. */ 2162 + if (lhs_has_group && rhs_has_group) { 2163 + lhs_pmu_name = evsel__group_pmu_name(lhs); 2164 + rhs_pmu_name = evsel__group_pmu_name(rhs); 2165 + ret = strcmp(lhs_pmu_name, rhs_pmu_name); 2166 + if (ret) 2167 + return ret; 2168 + } 2162 2169 2163 2170 /* Architecture specific sorting. */ 2164 2171 return arch_evlist__cmp(lhs, rhs);
+1 -1
tools/perf/util/stat-display.c
··· 431 431 struct outstate *os = ctx; 432 432 FILE *out = os->fh; 433 433 434 - fprintf(out, "\"metric-value\" : %f, ", val); 434 + fprintf(out, "\"metric-value\" : \"%f\", ", val); 435 435 fprintf(out, "\"metric-unit\" : \"%s\"", unit); 436 436 if (!config->metric_only) 437 437 fprintf(out, "}");
+19 -6
tools/perf/util/stat-shadow.c
··· 403 403 if (!aggr) 404 404 break; 405 405 406 - /* 407 - * If an event was scaled during stat gathering, reverse 408 - * the scale before computing the metric. 409 - */ 410 - val = aggr->counts.val * (1.0 / metric_events[i]->scale); 411 - source_count = evsel__source_count(metric_events[i]); 406 + if (!metric_events[i]->supported) { 407 + /* 408 + * Not supported events will have a count of 0, 409 + * which can be confusing in a 410 + * metric. Explicitly set the value to NAN. Not 411 + * counted events (enable time of 0) are read as 412 + * 0. 413 + */ 414 + val = NAN; 415 + source_count = 0; 416 + } else { 417 + /* 418 + * If an event was scaled during stat gathering, 419 + * reverse the scale before computing the 420 + * metric. 421 + */ 422 + val = aggr->counts.val * (1.0 / metric_events[i]->scale); 423 + source_count = evsel__source_count(metric_events[i]); 424 + } 412 425 } 413 426 n = strdup(evsel__metric_id(metric_events[i])); 414 427 if (!n)
+16 -7
tools/power/cpupower/lib/powercap.c
··· 40 40 { 41 41 int fd; 42 42 char yes_no; 43 + int ret = 0; 43 44 44 45 *mode = 0; 45 46 46 47 fd = open(path, O_RDONLY); 47 - if (fd == -1) 48 - return -1; 48 + if (fd == -1) { 49 + ret = -1; 50 + goto out; 51 + } 49 52 50 53 if (read(fd, &yes_no, 1) != 1) { 51 - close(fd); 52 - return -1; 54 + ret = -1; 55 + goto out_close; 53 56 } 54 57 55 58 if (yes_no == '1') { 56 59 *mode = 1; 57 - return 0; 60 + goto out_close; 58 61 } else if (yes_no == '0') { 59 - return 0; 62 + goto out_close; 63 + } else { 64 + ret = -1; 65 + goto out_close; 60 66 } 61 - return -1; 67 + out_close: 68 + close(fd); 69 + out: 70 + return ret; 62 71 } 63 72 64 73 int powercap_get_enabled(int *mode)
+14 -17
tools/power/cpupower/utils/idle_monitor/mperf_monitor.c
··· 70 70 */ 71 71 static unsigned long max_frequency; 72 72 73 - static unsigned long long tsc_at_measure_start; 74 - static unsigned long long tsc_at_measure_end; 73 + static unsigned long long *tsc_at_measure_start; 74 + static unsigned long long *tsc_at_measure_end; 75 75 static unsigned long long *mperf_previous_count; 76 76 static unsigned long long *aperf_previous_count; 77 77 static unsigned long long *mperf_current_count; ··· 169 169 aperf_diff = aperf_current_count[cpu] - aperf_previous_count[cpu]; 170 170 171 171 if (max_freq_mode == MAX_FREQ_TSC_REF) { 172 - tsc_diff = tsc_at_measure_end - tsc_at_measure_start; 172 + tsc_diff = tsc_at_measure_end[cpu] - tsc_at_measure_start[cpu]; 173 173 *percent = 100.0 * mperf_diff / tsc_diff; 174 174 dprint("%s: TSC Ref - mperf_diff: %llu, tsc_diff: %llu\n", 175 175 mperf_cstates[id].name, mperf_diff, tsc_diff); ··· 206 206 207 207 if (max_freq_mode == MAX_FREQ_TSC_REF) { 208 208 /* Calculate max_freq from TSC count */ 209 - tsc_diff = tsc_at_measure_end - tsc_at_measure_start; 209 + tsc_diff = tsc_at_measure_end[cpu] - tsc_at_measure_start[cpu]; 210 210 time_diff = timespec_diff_us(time_start, time_end); 211 211 max_frequency = tsc_diff / time_diff; 212 212 } ··· 225 225 static int mperf_start(void) 226 226 { 227 227 int cpu; 228 - unsigned long long dbg; 229 228 230 229 clock_gettime(CLOCK_REALTIME, &time_start); 231 - mperf_get_tsc(&tsc_at_measure_start); 232 230 233 - for (cpu = 0; cpu < cpu_count; cpu++) 231 + for (cpu = 0; cpu < cpu_count; cpu++) { 232 + mperf_get_tsc(&tsc_at_measure_start[cpu]); 234 233 mperf_init_stats(cpu); 234 + } 235 235 236 - mperf_get_tsc(&dbg); 237 - dprint("TSC diff: %llu\n", dbg - tsc_at_measure_start); 238 236 return 0; 239 237 } 240 238 241 239 static int mperf_stop(void) 242 240 { 243 - unsigned long long dbg; 244 241 int cpu; 245 242 246 - for (cpu = 0; cpu < cpu_count; cpu++) 243 + for (cpu = 0; cpu < cpu_count; cpu++) { 247 244 mperf_measure_stats(cpu); 245 + mperf_get_tsc(&tsc_at_measure_end[cpu]); 246 + } 248 247 249 - mperf_get_tsc(&tsc_at_measure_end); 250 248 clock_gettime(CLOCK_REALTIME, &time_end); 251 - 252 - mperf_get_tsc(&dbg); 253 - dprint("TSC diff: %llu\n", dbg - tsc_at_measure_end); 254 - 255 249 return 0; 256 250 } 257 251 ··· 347 353 aperf_previous_count = calloc(cpu_count, sizeof(unsigned long long)); 348 354 mperf_current_count = calloc(cpu_count, sizeof(unsigned long long)); 349 355 aperf_current_count = calloc(cpu_count, sizeof(unsigned long long)); 350 - 356 + tsc_at_measure_start = calloc(cpu_count, sizeof(unsigned long long)); 357 + tsc_at_measure_end = calloc(cpu_count, sizeof(unsigned long long)); 351 358 mperf_monitor.name_len = strlen(mperf_monitor.name); 352 359 return &mperf_monitor; 353 360 } ··· 359 364 free(aperf_previous_count); 360 365 free(mperf_current_count); 361 366 free(aperf_current_count); 367 + free(tsc_at_measure_start); 368 + free(tsc_at_measure_end); 362 369 free(is_valid); 363 370 } 364 371
+2 -1
tools/testing/selftests/ftrace/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 all: 3 3 4 - TEST_PROGS := ftracetest 4 + TEST_PROGS_EXTENDED := ftracetest 5 + TEST_PROGS := ftracetest-ktap 5 6 TEST_FILES := test.d settings 6 7 EXTRA_CLEAN := $(OUTPUT)/logs/* 7 8
+60 -3
tools/testing/selftests/ftrace/ftracetest
··· 13 13 echo " Options:" 14 14 echo " -h|--help Show help message" 15 15 echo " -k|--keep Keep passed test logs" 16 + echo " -K|--ktap Output in KTAP format" 16 17 echo " -v|--verbose Increase verbosity of test messages" 17 18 echo " -vv Alias of -v -v (Show all results in stdout)" 18 19 echo " -vvv Alias of -v -v -v (Show all commands immediately)" ··· 84 83 ;; 85 84 --keep|-k) 86 85 KEEP_LOG=1 86 + shift 1 87 + ;; 88 + --ktap|-K) 89 + KTAP=1 87 90 shift 1 88 91 ;; 89 92 --verbose|-v|-vv|-vvv) ··· 183 178 TEST_CASES=`find_testcases $TEST_DIR` 184 179 LOG_DIR=$TOP_DIR/logs/`date +%Y%m%d-%H%M%S`/ 185 180 KEEP_LOG=0 181 + KTAP=0 186 182 DEBUG=0 187 183 VERBOSE=0 188 184 UNSUPPORTED_RESULT=0 ··· 235 229 newline= 236 230 shift 237 231 fi 238 - printf "$*$newline" 232 + [ "$KTAP" != "1" ] && printf "$*$newline" 239 233 [ "$LOG_FILE" ] && printf "$*$newline" | strip_esc >> $LOG_FILE 240 234 } 241 235 catlog() { #file ··· 266 260 267 261 INSTANCE= 268 262 CASENO=0 263 + CASENAME= 269 264 270 265 testcase() { # testfile 271 266 CASENO=$((CASENO+1)) 272 - desc=`grep "^#[ \t]*description:" $1 | cut -f2- -d:` 273 - prlog -n "[$CASENO]$INSTANCE$desc" 267 + CASENAME=`grep "^#[ \t]*description:" $1 | cut -f2- -d:` 274 268 } 275 269 276 270 checkreq() { # testfile ··· 283 277 grep -q "^#[ \t]*flags:.*instance" $1 284 278 } 285 279 280 + ktaptest() { # result comment 281 + if [ "$KTAP" != "1" ]; then 282 + return 283 + fi 284 + 285 + local result= 286 + if [ "$1" = "1" ]; then 287 + result="ok" 288 + else 289 + result="not ok" 290 + fi 291 + shift 292 + 293 + local comment=$* 294 + if [ "$comment" != "" ]; then 295 + comment="# $comment" 296 + fi 297 + 298 + echo $CASENO $result $INSTANCE$CASENAME $comment 299 + } 300 + 286 301 eval_result() { # sigval 287 302 case $1 in 288 303 $PASS) 289 304 prlog " [${color_green}PASS${color_reset}]" 305 + ktaptest 1 290 306 PASSED_CASES="$PASSED_CASES $CASENO" 291 307 return 0 292 308 ;; 293 309 $FAIL) 294 310 prlog " [${color_red}FAIL${color_reset}]" 311 + ktaptest 0 295 312 FAILED_CASES="$FAILED_CASES $CASENO" 296 313 return 1 # this is a bug. 297 314 ;; 298 315 $UNRESOLVED) 299 316 prlog " [${color_blue}UNRESOLVED${color_reset}]" 317 + ktaptest 0 UNRESOLVED 300 318 UNRESOLVED_CASES="$UNRESOLVED_CASES $CASENO" 301 319 return $UNRESOLVED_RESULT # depends on use case 302 320 ;; 303 321 $UNTESTED) 304 322 prlog " [${color_blue}UNTESTED${color_reset}]" 323 + ktaptest 1 SKIP 305 324 UNTESTED_CASES="$UNTESTED_CASES $CASENO" 306 325 return 0 307 326 ;; 308 327 $UNSUPPORTED) 309 328 prlog " [${color_blue}UNSUPPORTED${color_reset}]" 329 + ktaptest 1 SKIP 310 330 UNSUPPORTED_CASES="$UNSUPPORTED_CASES $CASENO" 311 331 return $UNSUPPORTED_RESULT # depends on use case 312 332 ;; 313 333 $XFAIL) 314 334 prlog " [${color_green}XFAIL${color_reset}]" 335 + ktaptest 1 XFAIL 315 336 XFAILED_CASES="$XFAILED_CASES $CASENO" 316 337 return 0 317 338 ;; 318 339 *) 319 340 prlog " [${color_blue}UNDEFINED${color_reset}]" 341 + ktaptest 0 error 320 342 UNDEFINED_CASES="$UNDEFINED_CASES $CASENO" 321 343 return 1 # this must be a test bug 322 344 ;; ··· 405 371 run_test() { # testfile 406 372 local testname=`basename $1` 407 373 testcase $1 374 + prlog -n "[$CASENO]$INSTANCE$CASENAME" 408 375 if [ ! -z "$LOG_FILE" ] ; then 409 376 local testlog=`mktemp $LOG_DIR/${CASENO}-${testname}-log.XXXXXX` 410 377 else ··· 440 405 # load in the helper functions 441 406 . $TEST_DIR/functions 442 407 408 + if [ "$KTAP" = "1" ]; then 409 + echo "TAP version 13" 410 + 411 + casecount=`echo $TEST_CASES | wc -w` 412 + for t in $TEST_CASES; do 413 + test_on_instance $t || continue 414 + casecount=$((casecount+1)) 415 + done 416 + echo "1..${casecount}" 417 + fi 418 + 443 419 # Main loop 444 420 for t in $TEST_CASES; do 445 421 run_test $t ··· 484 438 prlog "# of unsupported: " `echo $UNSUPPORTED_CASES | wc -w` 485 439 prlog "# of xfailed: " `echo $XFAILED_CASES | wc -w` 486 440 prlog "# of undefined(test bug): " `echo $UNDEFINED_CASES | wc -w` 441 + 442 + if [ "$KTAP" = "1" ]; then 443 + echo -n "# Totals:" 444 + echo -n " pass:"`echo $PASSED_CASES | wc -w` 445 + echo -n " faii:"`echo $FAILED_CASES | wc -w` 446 + echo -n " xfail:"`echo $XFAILED_CASES | wc -w` 447 + echo -n " xpass:0" 448 + echo -n " skip:"`echo $UNTESTED_CASES $UNSUPPORTED_CASES | wc -w` 449 + echo -n " error:"`echo $UNRESOLVED_CASES $UNDEFINED_CASES | wc -w` 450 + echo 451 + fi 487 452 488 453 cleanup 489 454
+8
tools/testing/selftests/ftrace/ftracetest-ktap
··· 1 + #!/bin/sh -e 2 + # SPDX-License-Identifier: GPL-2.0-only 3 + # 4 + # ftracetest-ktap: Wrapper to integrate ftracetest with the kselftest runner 5 + # 6 + # Copyright (C) Arm Ltd., 2023 7 + 8 + ./ftracetest -K
+1 -1
tools/testing/selftests/net/fib_nexthops.sh
··· 2283 2283 ################################################################################ 2284 2284 # main 2285 2285 2286 - while getopts :t:pP46hv:w: o 2286 + while getopts :t:pP46hvw: o 2287 2287 do 2288 2288 case $o in 2289 2289 t) TESTS=$OPTARG;;
+11 -6
tools/testing/selftests/net/srv6_end_dt4_l3vpn_test.sh
··· 232 232 local nsname=rt-${rt} 233 233 234 234 ip netns add ${nsname} 235 + 236 + ip netns exec ${nsname} sysctl -wq net.ipv6.conf.all.accept_dad=0 237 + ip netns exec ${nsname} sysctl -wq net.ipv6.conf.default.accept_dad=0 238 + 235 239 ip link set veth-rt-${rt} netns ${nsname} 236 240 ip -netns ${nsname} link set veth-rt-${rt} name veth0 237 241 238 - ip -netns ${nsname} addr add ${IPv6_RT_NETWORK}::${rt}/64 dev veth0 242 + ip -netns ${nsname} addr add ${IPv6_RT_NETWORK}::${rt}/64 dev veth0 nodad 239 243 ip -netns ${nsname} link set veth0 up 240 244 ip -netns ${nsname} link set lo up 241 245 ··· 258 254 259 255 # set the networking for the host 260 256 ip netns add ${hsname} 257 + 258 + # disable the rp_filter otherwise the kernel gets confused about how 259 + # to route decap ipv4 packets. 260 + ip netns exec ${rtname} sysctl -wq net.ipv4.conf.all.rp_filter=0 261 + ip netns exec ${rtname} sysctl -wq net.ipv4.conf.default.rp_filter=0 262 + 261 263 ip -netns ${hsname} link add veth0 type veth peer name ${rtveth} 262 264 ip -netns ${hsname} link set ${rtveth} netns ${rtname} 263 265 ip -netns ${hsname} addr add ${IPv4_HS_NETWORK}.${hs}/24 dev veth0 ··· 281 271 ip -netns ${rtname} link set ${rtveth} up 282 272 283 273 ip netns exec ${rtname} sysctl -wq net.ipv4.conf.${rtveth}.proxy_arp=1 284 - 285 - # disable the rp_filter otherwise the kernel gets confused about how 286 - # to route decap ipv4 packets. 287 - ip netns exec ${rtname} sysctl -wq net.ipv4.conf.all.rp_filter=0 288 - ip netns exec ${rtname} sysctl -wq net.ipv4.conf.${rtveth}.rp_filter=0 289 274 290 275 ip netns exec ${rtname} sh -c "echo 1 > /proc/sys/net/vrf/strict_mode" 291 276 }
+1
tools/testing/selftests/sgx/Makefile
··· 17 17 -fno-stack-protector -mrdrnd $(INCLUDES) 18 18 19 19 TEST_CUSTOM_PROGS := $(OUTPUT)/test_sgx 20 + TEST_FILES := $(OUTPUT)/test_encl.elf 20 21 21 22 ifeq ($(CAN_BUILD_X86_64), 1) 22 23 all: $(TEST_CUSTOM_PROGS) $(OUTPUT)/test_encl.elf
+37 -22
virt/kvm/kvm_main.c
··· 3962 3962 } 3963 3963 3964 3964 vcpu->vcpu_idx = atomic_read(&kvm->online_vcpus); 3965 - r = xa_insert(&kvm->vcpu_array, vcpu->vcpu_idx, vcpu, GFP_KERNEL_ACCOUNT); 3966 - BUG_ON(r == -EBUSY); 3965 + r = xa_reserve(&kvm->vcpu_array, vcpu->vcpu_idx, GFP_KERNEL_ACCOUNT); 3967 3966 if (r) 3968 3967 goto unlock_vcpu_destroy; 3969 3968 3970 3969 /* Now it's all set up, let userspace reach it */ 3971 3970 kvm_get_kvm(kvm); 3972 3971 r = create_vcpu_fd(vcpu); 3973 - if (r < 0) { 3974 - xa_erase(&kvm->vcpu_array, vcpu->vcpu_idx); 3975 - kvm_put_kvm_no_destroy(kvm); 3976 - goto unlock_vcpu_destroy; 3972 + if (r < 0) 3973 + goto kvm_put_xa_release; 3974 + 3975 + if (KVM_BUG_ON(!!xa_store(&kvm->vcpu_array, vcpu->vcpu_idx, vcpu, 0), kvm)) { 3976 + r = -EINVAL; 3977 + goto kvm_put_xa_release; 3977 3978 } 3978 3979 3979 3980 /* ··· 3989 3988 kvm_create_vcpu_debugfs(vcpu); 3990 3989 return r; 3991 3990 3991 + kvm_put_xa_release: 3992 + kvm_put_kvm_no_destroy(kvm); 3993 + xa_release(&kvm->vcpu_array, vcpu->vcpu_idx); 3992 3994 unlock_vcpu_destroy: 3993 3995 mutex_unlock(&kvm->lock); 3994 3996 kvm_dirty_ring_free(&vcpu->dirty_ring); ··· 5188 5184 static int hardware_enable_all(void) 5189 5185 { 5190 5186 atomic_t failed = ATOMIC_INIT(0); 5191 - int r = 0; 5187 + int r; 5188 + 5189 + /* 5190 + * Do not enable hardware virtualization if the system is going down. 5191 + * If userspace initiated a forced reboot, e.g. reboot -f, then it's 5192 + * possible for an in-flight KVM_CREATE_VM to trigger hardware enabling 5193 + * after kvm_reboot() is called. Note, this relies on system_state 5194 + * being set _before_ kvm_reboot(), which is why KVM uses a syscore ops 5195 + * hook instead of registering a dedicated reboot notifier (the latter 5196 + * runs before system_state is updated). 5197 + */ 5198 + if (system_state == SYSTEM_HALT || system_state == SYSTEM_POWER_OFF || 5199 + system_state == SYSTEM_RESTART) 5200 + return -EBUSY; 5192 5201 5193 5202 /* 5194 5203 * When onlining a CPU, cpu_online_mask is set before kvm_online_cpu() ··· 5213 5196 */ 5214 5197 cpus_read_lock(); 5215 5198 mutex_lock(&kvm_lock); 5199 + 5200 + r = 0; 5216 5201 5217 5202 kvm_usage_count++; 5218 5203 if (kvm_usage_count == 1) { ··· 5232 5213 return r; 5233 5214 } 5234 5215 5235 - static int kvm_reboot(struct notifier_block *notifier, unsigned long val, 5236 - void *v) 5216 + static void kvm_shutdown(void) 5237 5217 { 5238 5218 /* 5239 - * Some (well, at least mine) BIOSes hang on reboot if 5240 - * in vmx root mode. 5241 - * 5242 - * And Intel TXT required VMX off for all cpu when system shutdown. 5219 + * Disable hardware virtualization and set kvm_rebooting to indicate 5220 + * that KVM has asynchronously disabled hardware virtualization, i.e. 5221 + * that relevant errors and exceptions aren't entirely unexpected. 5222 + * Some flavors of hardware virtualization need to be disabled before 5223 + * transferring control to firmware (to perform shutdown/reboot), e.g. 5224 + * on x86, virtualization can block INIT interrupts, which are used by 5225 + * firmware to pull APs back under firmware control. Note, this path 5226 + * is used for both shutdown and reboot scenarios, i.e. neither name is 5227 + * 100% comprehensive. 5243 5228 */ 5244 5229 pr_info("kvm: exiting hardware virtualization\n"); 5245 5230 kvm_rebooting = true; 5246 5231 on_each_cpu(hardware_disable_nolock, NULL, 1); 5247 - return NOTIFY_OK; 5248 5232 } 5249 - 5250 - static struct notifier_block kvm_reboot_notifier = { 5251 - .notifier_call = kvm_reboot, 5252 - .priority = 0, 5253 - }; 5254 5233 5255 5234 static int kvm_suspend(void) 5256 5235 { ··· 5280 5263 static struct syscore_ops kvm_syscore_ops = { 5281 5264 .suspend = kvm_suspend, 5282 5265 .resume = kvm_resume, 5266 + .shutdown = kvm_shutdown, 5283 5267 }; 5284 5268 #else /* CONFIG_KVM_GENERIC_HARDWARE_ENABLING */ 5285 5269 static int hardware_enable_all(void) ··· 5985 5967 if (r) 5986 5968 return r; 5987 5969 5988 - register_reboot_notifier(&kvm_reboot_notifier); 5989 5970 register_syscore_ops(&kvm_syscore_ops); 5990 5971 #endif 5991 5972 ··· 6056 6039 err_vcpu_cache: 6057 6040 #ifdef CONFIG_KVM_GENERIC_HARDWARE_ENABLING 6058 6041 unregister_syscore_ops(&kvm_syscore_ops); 6059 - unregister_reboot_notifier(&kvm_reboot_notifier); 6060 6042 cpuhp_remove_state_nocalls(CPUHP_AP_KVM_ONLINE); 6061 6043 #endif 6062 6044 return r; ··· 6081 6065 kvm_async_pf_deinit(); 6082 6066 #ifdef CONFIG_KVM_GENERIC_HARDWARE_ENABLING 6083 6067 unregister_syscore_ops(&kvm_syscore_ops); 6084 - unregister_reboot_notifier(&kvm_reboot_notifier); 6085 6068 cpuhp_remove_state_nocalls(CPUHP_AP_KVM_ONLINE); 6086 6069 #endif 6087 6070 kvm_irqfd_exit();