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dt-bindings: clk: add PolarFire SoC fabric clock ids

Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.

Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com

authored by

Conor Dooley and committed by
Claudiu Beznea b4b02524 3ffb5ad2

+23
+23
include/dt-bindings/clock/microchip,mpfs-clock.h
··· 45 45 #define CLK_RTCREF 33 46 46 #define CLK_MSSPLL 34 47 47 48 + /* Clock Conditioning Circuitry Clock IDs */ 49 + 50 + #define CLK_CCC_PLL0 0 51 + #define CLK_CCC_PLL1 1 52 + #define CLK_CCC_DLL0 2 53 + #define CLK_CCC_DLL1 3 54 + 55 + #define CLK_CCC_PLL0_OUT0 4 56 + #define CLK_CCC_PLL0_OUT1 5 57 + #define CLK_CCC_PLL0_OUT2 6 58 + #define CLK_CCC_PLL0_OUT3 7 59 + 60 + #define CLK_CCC_PLL1_OUT0 8 61 + #define CLK_CCC_PLL1_OUT1 9 62 + #define CLK_CCC_PLL1_OUT2 10 63 + #define CLK_CCC_PLL1_OUT3 11 64 + 65 + #define CLK_CCC_DLL0_OUT0 12 66 + #define CLK_CCC_DLL0_OUT1 13 67 + 68 + #define CLK_CCC_DLL1_OUT0 14 69 + #define CLK_CCC_DLL1_OUT1 15 70 + 48 71 #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */