Merge tag 'iio-for-6.7a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next

+75

Documentation/ABI/testing/sysfs-bus-iio

··· 279 279 but should match other such assignments on device). 280 280 Units after application of scale and offset are m/s^2. 281 281 282 + What: /sys/bus/iio/devices/iio:deviceX/in_deltaangl_x_raw 283 + What: /sys/bus/iio/devices/iio:deviceX/in_deltaangl_y_raw 284 + What: /sys/bus/iio/devices/iio:deviceX/in_deltaangl_z_raw 285 + KernelVersion: 6.5 286 + Contact: linux-iio@vger.kernel.org 287 + Description: 288 + Angular displacement between two consecutive samples on x, y or 289 + z (may be arbitrarily assigned but should match other such 290 + assignments on device). 291 + In order to compute the total angular displacement during a 292 + desired period of time, the application should sum-up the delta 293 + angle samples acquired during that time. 294 + Units after application of scale and offset are radians. 295 + 296 + What: /sys/bus/iio/devices/iio:deviceX/in_deltavelocity_x_raw 297 + What: /sys/bus/iio/devices/iio:deviceX/in_deltavelocity_y_raw 298 + What: /sys/bus/iio/devices/iio:deviceX/in_deltavelocity_z_raw 299 + KernelVersion: 6.5 300 + Contact: linux-iio@vger.kernel.org 301 + Description: 302 + The linear velocity change between two consecutive samples on x, 303 + y or z (may be arbitrarily assigned but should match other such 304 + assignments on device). 305 + In order to compute the total linear velocity change during a 306 + desired period of time, the application should sum-up the delta 307 + velocity samples acquired during that time. 308 + Units after application of scale and offset are meters per 309 + second. 310 + 282 311 What: /sys/bus/iio/devices/iio:deviceX/in_angl_raw 283 312 What: /sys/bus/iio/devices/iio:deviceX/in_anglY_raw 284 313 KernelVersion: 4.17 ··· 490 461 What: /sys/bus/iio/devices/iio:deviceX/in_velocity_sqrt(x^2+y^2+z^2)_scale 491 462 What: /sys/bus/iio/devices/iio:deviceX/in_illuminance_scale 492 463 What: /sys/bus/iio/devices/iio:deviceX/in_countY_scale 464 + What: /sys/bus/iio/devices/iio:deviceX/in_deltaangl_scale 465 + What: /sys/bus/iio/devices/iio:deviceX/in_deltavelocity_scale 493 466 What: /sys/bus/iio/devices/iio:deviceX/in_angl_scale 494 467 What: /sys/bus/iio/devices/iio:deviceX/in_intensity_x_scale 495 468 What: /sys/bus/iio/devices/iio:deviceX/in_intensity_y_scale ··· 1363 1332 What: /sys/.../iio:deviceX/bufferY/in_accel_x_en 1364 1333 What: /sys/.../iio:deviceX/bufferY/in_accel_y_en 1365 1334 What: /sys/.../iio:deviceX/bufferY/in_accel_z_en 1335 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_x_en 1336 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_y_en 1337 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_z_en 1338 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_x_en 1339 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_y_en 1340 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_z_en 1366 1341 What: /sys/.../iio:deviceX/bufferY/in_anglvel_x_en 1367 1342 What: /sys/.../iio:deviceX/bufferY/in_anglvel_y_en 1368 1343 What: /sys/.../iio:deviceX/bufferY/in_anglvel_z_en ··· 1399 1362 Scan element control for triggered data capture. 1400 1363 1401 1364 What: /sys/.../iio:deviceX/bufferY/in_accel_type 1365 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_type 1366 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_type 1402 1367 What: /sys/.../iio:deviceX/bufferY/in_anglvel_type 1403 1368 What: /sys/.../iio:deviceX/bufferY/in_magn_type 1404 1369 What: /sys/.../iio:deviceX/bufferY/in_incli_type ··· 1455 1416 What: /sys/.../iio:deviceX/bufferY/in_accel_x_index 1456 1417 What: /sys/.../iio:deviceX/bufferY/in_accel_y_index 1457 1418 What: /sys/.../iio:deviceX/bufferY/in_accel_z_index 1419 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_x_index 1420 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_y_index 1421 + What: /sys/.../iio:deviceX/bufferY/in_deltaangl_z_index 1422 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_x_index 1423 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_y_index 1424 + What: /sys/.../iio:deviceX/bufferY/in_deltavelocity_z_index 1458 1425 What: /sys/.../iio:deviceX/bufferY/in_anglvel_x_index 1459 1426 What: /sys/.../iio:deviceX/bufferY/in_anglvel_y_index 1460 1427 What: /sys/.../iio:deviceX/bufferY/in_anglvel_z_index ··· 2224 2179 Description: 2225 2180 Number of conditions that must occur, during a running 2226 2181 period, before an event is generated. 2182 + 2183 + What: /sys/bus/iio/devices/iio:deviceX/in_colortemp_raw 2184 + KernelVersion: 6.7 2185 + Contact: linux-iio@vger.kernel.org 2186 + Description: 2187 + Represents light color temperature, which measures light color 2188 + temperature in Kelvin. 2189 + 2190 + What: /sys/bus/iio/devices/iio:deviceX/in_chromaticity_x_raw 2191 + What: /sys/bus/iio/devices/iio:deviceX/in_chromaticity_y_raw 2192 + KernelVersion: 6.7 2193 + Contact: linux-iio@vger.kernel.org 2194 + Description: 2195 + The x and y light color coordinate on the CIE 1931 chromaticity 2196 + diagram. 2197 + 2198 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltageY_mag_either_label 2199 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltageY_mag_rising_label 2200 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltageY_thresh_falling_label 2201 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltageY_thresh_rising_label 2202 + What: /sys/bus/iio/devices/iio:deviceX/events/in_anglvelY_mag_rising_label 2203 + What: /sys/bus/iio/devices/iio:deviceX/events/in_anglY_thresh_rising_label 2204 + What: /sys/bus/iio/devices/iio:deviceX/events/in_phaseY_mag_rising_label 2205 + KernelVersion: 6.7 2206 + Contact: linux-iio@vger.kernel.org 2207 + Description: 2208 + Optional symbolic label to a device channel event. 2209 + If a label is defined for this event add that to the event 2210 + specific attributes. This is useful for userspace to be able to 2211 + better identify an individual event.

+53

Documentation/ABI/testing/sysfs-bus-iio-adc-mcp3564

··· 1 + What: /sys/bus/iio/devices/iio:deviceX/boost_current_gain 2 + KernelVersion: 6.4 3 + Contact: linux-iio@vger.kernel.org 4 + Description: 5 + This attribute is used to set the gain of the biasing current 6 + circuit of the Delta-Sigma modulator. The different BOOST 7 + settings are applied to the entire modulator circuit, including 8 + the voltage reference buffers. 9 + 10 + What: /sys/bus/iio/devices/iio:deviceX/boost_current_gain_available 11 + KernelVersion: 6.4 12 + Contact: linux-iio@vger.kernel.org 13 + Description: 14 + Reading returns a list with the possible gain values for 15 + the current biasing circuit of the Delta-Sigma modulator. 16 + 17 + What: /sys/bus/iio/devices/iio:deviceX/auto_zeroing_mux_enable 18 + KernelVersion: 6.4 19 + Contact: linux-iio@vger.kernel.org 20 + Description: 21 + This attribute is used to enable the analog input multiplexer 22 + auto-zeroing algorithm (the input multiplexer and the ADC 23 + include an offset cancellation algorithm that cancels the offset 24 + contribution of the ADC). When the offset cancellation algorithm 25 + is enabled, ADC takes two conversions, one with the differential 26 + input as VIN+/VIN-, one with VIN+/VIN- inverted. In this case the 27 + conversion time is multiplied by two compared to the default 28 + case where the algorithm is disabled. This technique allows the 29 + cancellation of the ADC offset error and the achievement of 30 + ultra-low offset without any digital calibration. The resulting 31 + offset is the residue of the difference between the two 32 + conversions, which is on the order of magnitude of the noise 33 + floor. This offset is effectively canceled at every conversion, 34 + so the residual offset error temperature drift is extremely low. 35 + Write '1' to enable it, write '0' to disable it. 36 + 37 + What: /sys/bus/iio/devices/iio:deviceX/auto_zeroing_ref_enable 38 + KernelVersion: 6.4 39 + Contact: linux-iio@vger.kernel.org 40 + Description: 41 + This attribute is used to enable the chopping algorithm for the 42 + internal voltage reference buffer. This setting has no effect 43 + when external voltage reference is selected. 44 + Internal voltage reference buffer injects a certain quantity of 45 + 1/f noise into the system that can be modulated with the 46 + incoming input signals and can limit the SNR performance at 47 + higher Oversampling Ratio values (over 256). To overcome this 48 + limitation, the buffer includes an auto-zeroing algorithm that 49 + greatly reduces (cancels out) the 1/f noise and cancels the 50 + offset value of the reference buffer. As a result, the SNR of 51 + the system is not affected by this 1/f noise component of the 52 + reference buffer, even at maximum oversampling ratio values. 53 + Write '1' to enable it, write '0' to disable it.

+27

Documentation/ABI/testing/sysfs-bus-iio-resolver-ad2s1210

··· 1 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltage0_mag_rising_reset_max 2 + KernelVersion: 6.7 3 + Contact: linux-iio@vger.kernel.org 4 + Description: 5 + Reading returns the current Degradation of Signal Reset Maximum 6 + Threshold value in millivolts. Writing sets the value. 7 + 8 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltage0_mag_rising_reset_max_available 9 + KernelVersion: 6.7 10 + Contact: linux-iio@vger.kernel.org 11 + Description: 12 + Reading returns the allowable voltage range for 13 + in_altvoltage0_mag_rising_reset_max. 14 + 15 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltage0_mag_rising_reset_min 16 + KernelVersion: 6.7 17 + Contact: linux-iio@vger.kernel.org 18 + Description: 19 + Reading returns the current Degradation of Signal Reset Minimum 20 + Threshold value in millivolts. Writing sets the value. 21 + 22 + What: /sys/bus/iio/devices/iio:deviceX/events/in_altvoltage0_mag_rising_reset_min_available 23 + KernelVersion: 6.7 24 + Contact: linux-iio@vger.kernel.org 25 + Description: 26 + Reading returns the allowable voltage range for 27 + in_altvoltage0_mag_rising_reset_min.

+9 -5

Documentation/devicetree/bindings/iio/accel/kionix,kx022a.yaml

··· 4 4 $id: http://devicetree.org/schemas/iio/accel/kionix,kx022a.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: ROHM/Kionix KX022A Accelerometer 7 + title: ROHM/Kionix KX022A, KX132-1211 and KX132ACR-LBZ Accelerometers 8 8 9 9 maintainers: 10 10 - Matti Vaittinen <mazziesaccount@gmail.com> 11 11 12 12 description: | 13 - KX022A is a 3-axis accelerometer supporting +/- 2G, 4G, 8G and 16G ranges, 14 - output data-rates from 0.78Hz to 1600Hz and a hardware-fifo buffering. 15 - KX022A can be accessed either via I2C or SPI. 13 + KX022A, KX132ACR-LBZ and KX132-1211 are 3-axis accelerometers supporting 14 + +/- 2G, 4G, 8G and 16G ranges, variable output data-rates and a 15 + hardware-fifo buffering. These accelerometers can be accessed either 16 + via I2C or SPI. 16 17 17 18 properties: 18 19 compatible: 19 - const: kionix,kx022a 20 + enum: 21 + - kionix,kx022a 22 + - kionix,kx132-1211 23 + - rohm,kx132acr-lbz 20 24 21 25 reg: 22 26 maxItems: 1

+15 -5

Documentation/devicetree/bindings/iio/adc/lltc,ltc2497.yaml

··· 4 4 $id: http://devicetree.org/schemas/iio/adc/lltc,ltc2497.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Linear Technology / Analog Devices LTC2497 ADC 7 + title: Linear Technology / Analog Devices LTC2497 and LTC2309 ADC 8 8 9 9 maintainers: 10 10 - Michael Hennerich <michael.hennerich@analog.com> 11 + - Liam Beguin <liambeguin@gmail.com> 11 12 12 13 description: | 13 - 16bit ADC supporting up to 16 single ended or 8 differential inputs. 14 - I2C interface. 14 + LTC2309: 15 + low noise, low power, 8-channel, 12-bit successive approximation ADC with an 16 + I2C compatible serial interface. 15 17 16 - https://www.analog.com/media/en/technical-documentation/data-sheets/2497fb.pdf 17 - https://www.analog.com/media/en/technical-documentation/data-sheets/2499fe.pdf 18 + https://www.analog.com/media/en/technical-documentation/data-sheets/2309fd.pdf 19 + 20 + LTC2497: 21 + LTC2499: 22 + 16bit ADC supporting up to 16 single ended or 8 differential inputs. 23 + I2C interface. 24 + 25 + https://www.analog.com/media/en/technical-documentation/data-sheets/2497fb.pdf 26 + https://www.analog.com/media/en/technical-documentation/data-sheets/2499fe.pdf 18 27 19 28 properties: 20 29 compatible: 21 30 enum: 31 + - lltc,ltc2309 22 32 - lltc,ltc2497 23 33 - lltc,ltc2499 24 34

+205

Documentation/devicetree/bindings/iio/adc/microchip,mcp3564.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/iio/adc/microchip,mcp3564.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Microchip MCP346X and MCP356X ADC Family 8 + 9 + maintainers: 10 + - Marius Cristea <marius.cristea@microchip.com> 11 + 12 + description: | 13 + Bindings for the Microchip family of 153.6 ksps, Low-Noise 16/24-Bit 14 + Delta-Sigma ADCs with an SPI interface. Datasheet can be found here: 15 + Datasheet for MCP3561, MCP3562, MCP3564 can be found here: 16 + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP3561-2-4-Family-Data-Sheet-DS20006181C.pdf 17 + Datasheet for MCP3561R, MCP3562R, MCP3564R can be found here: 18 + https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3561_2_4R-Data-Sheet-DS200006391C.pdf 19 + Datasheet for MCP3461, MCP3462, MCP3464 can be found here: 20 + https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180D.pdf 21 + Datasheet for MCP3461R, MCP3462R, MCP3464R can be found here: 22 + https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4R-Family-Data-Sheet-DS20006404C.pdf 23 + 24 + properties: 25 + compatible: 26 + enum: 27 + - microchip,mcp3461 28 + - microchip,mcp3462 29 + - microchip,mcp3464 30 + - microchip,mcp3461r 31 + - microchip,mcp3462r 32 + - microchip,mcp3464r 33 + - microchip,mcp3561 34 + - microchip,mcp3562 35 + - microchip,mcp3564 36 + - microchip,mcp3561r 37 + - microchip,mcp3562r 38 + - microchip,mcp3564r 39 + 40 + reg: 41 + maxItems: 1 42 + 43 + spi-max-frequency: 44 + maximum: 20000000 45 + 46 + spi-cpha: true 47 + 48 + spi-cpol: true 49 + 50 + vdd-supply: true 51 + 52 + avdd-supply: true 53 + 54 + clocks: 55 + description: 56 + Phandle and clock identifier for external sampling clock. 57 + If not specified, the internal crystal oscillator will be used. 58 + maxItems: 1 59 + 60 + interrupts: 61 + description: IRQ line of the ADC 62 + maxItems: 1 63 + 64 + drive-open-drain: 65 + description: 66 + Whether to drive the IRQ signal as push-pull (default) or open-drain. Note 67 + that the device requires this pin to become "high", otherwise it will stop 68 + converting. 69 + type: boolean 70 + 71 + vref-supply: 72 + description: 73 + Some devices have a specific reference voltage supplied on a different 74 + pin to the other supplies. Needed to be able to establish channel scaling 75 + unless there is also an internal reference available (e.g. mcp3564r). In 76 + case of "r" devices (e. g. mcp3564r), if it does not exists the internal 77 + reference will be used. 78 + 79 + microchip,hw-device-address: 80 + $ref: /schemas/types.yaml#/definitions/uint32 81 + minimum: 0 82 + maximum: 3 83 + description: 84 + The address is set on a per-device basis by fuses in the factory, 85 + configured on request. If not requested, the fuses are set for 0x1. 86 + The device address is part of the device markings to avoid 87 + potential confusion. This address is coded on two bits, so four possible 88 + addresses are available when multiple devices are present on the same 89 + SPI bus with only one Chip Select line for all devices. 90 + Each device communication starts by a CS falling edge, followed by the 91 + clocking of the device address (BITS[7:6] - top two bits of COMMAND BYTE 92 + which is first one on the wire). 93 + 94 + "#io-channel-cells": 95 + const: 1 96 + 97 + "#address-cells": 98 + const: 1 99 + 100 + "#size-cells": 101 + const: 0 102 + 103 + patternProperties: 104 + "^channel@([0-9]|([1-7][0-9]))$": 105 + $ref: adc.yaml 106 + type: object 107 + unevaluatedProperties: false 108 + description: Represents the external channels which are connected to the ADC. 109 + 110 + properties: 111 + reg: 112 + description: The channel number in single-ended and differential mode. 113 + minimum: 0 114 + maximum: 79 115 + 116 + required: 117 + - reg 118 + 119 + dependencies: 120 + spi-cpol: [ spi-cpha ] 121 + spi-cpha: [ spi-cpol ] 122 + 123 + required: 124 + - compatible 125 + - reg 126 + - microchip,hw-device-address 127 + - spi-max-frequency 128 + 129 + allOf: 130 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 131 + - # External vref, no internal reference 132 + if: 133 + properties: 134 + compatible: 135 + contains: 136 + enum: 137 + - microchip,mcp3461 138 + - microchip,mcp3462 139 + - microchip,mcp3464 140 + - microchip,mcp3561 141 + - microchip,mcp3562 142 + - microchip,mcp3564 143 + then: 144 + required: 145 + - vref-supply 146 + 147 + unevaluatedProperties: false 148 + 149 + examples: 150 + - | 151 + spi { 152 + #address-cells = <1>; 153 + #size-cells = <0>; 154 + 155 + adc@0 { 156 + compatible = "microchip,mcp3564r"; 157 + reg = <0>; 158 + vref-supply = <&vref_reg>; 159 + spi-cpha; 160 + spi-cpol; 161 + spi-max-frequency = <10000000>; 162 + microchip,hw-device-address = <1>; 163 + 164 + #address-cells = <1>; 165 + #size-cells = <0>; 166 + 167 + channel@0 { 168 + /* CH0 to AGND */ 169 + reg = <0>; 170 + label = "CH0"; 171 + }; 172 + 173 + channel@1 { 174 + /* CH1 to AGND */ 175 + reg = <1>; 176 + label = "CH1"; 177 + }; 178 + 179 + /* diff-channels */ 180 + channel@11 { 181 + reg = <11>; 182 + 183 + /* CN0, CN1 */ 184 + diff-channels = <0 1>; 185 + label = "CH0_CH1"; 186 + }; 187 + 188 + channel@22 { 189 + reg = <0x22>; 190 + 191 + /* CN1, CN2 */ 192 + diff-channels = <1 2>; 193 + label = "CH1_CH3"; 194 + }; 195 + 196 + channel@23 { 197 + reg = <0x23>; 198 + 199 + /* CN1, CN3 */ 200 + diff-channels = <1 3>; 201 + label = "CH1_CH3"; 202 + }; 203 + }; 204 + }; 205 + ...

+6

Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml

··· 18 18 properties: 19 19 compatible: 20 20 enum: 21 + - microchip,mcp3910 21 22 - microchip,mcp3911 23 + - microchip,mcp3912 24 + - microchip,mcp3913 25 + - microchip,mcp3914 26 + - microchip,mcp3918 27 + - microchip,mcp3919 22 28 23 29 reg: 24 30 maxItems: 1

+3

Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml

··· 23 23 reg: 24 24 maxItems: 1 25 25 26 + interrupts: 27 + maxItems: 1 28 + 26 29 "#address-cells": 27 30 const: 1 28 31

+43

Documentation/devicetree/bindings/iio/adc/ti,twl6030-gpadc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/iio/adc/ti,twl6030-gpadc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: GPADC subsystem in the TWL6030 power module 8 + 9 + maintainers: 10 + - Andreas Kemnade <andreas@kemnade.info> 11 + 12 + description: 13 + The GPADC subsystem in the TWL603X consists of a 10-bit ADC 14 + combined with a 15-input analog multiplexer in the TWL6030 resp. a 15 + 19-input analog muliplexer in the TWL6032. 16 + 17 + properties: 18 + compatible: 19 + enum: 20 + - ti,twl6030-gpadc 21 + - ti,twl6032-gpadc 22 + 23 + interrupts: 24 + maxItems: 1 25 + 26 + "#io-channel-cells": 27 + const: 1 28 + 29 + required: 30 + - compatible 31 + - interrupts 32 + - "#io-channel-cells" 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + gpadc { 39 + compatible = "ti,twl6030-gpadc"; 40 + interrupts = <3>; 41 + #io-channel-cells = <1>; 42 + }; 43 + ...

+9 -3

Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml

··· 4 4 $id: http://devicetree.org/schemas/iio/amplifiers/adi,hmc425a.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: HMC425A 6-bit Digital Step Attenuator 7 + title: Analog Devices HMC425A and similar Digital Step Attenuators 8 8 9 9 maintainers: 10 10 - Michael Hennerich <michael.hennerich@analog.com> 11 11 12 12 description: | 13 - Digital Step Attenuator IIO device with gpio interface. 13 + Digital Step Attenuator IIO devices with gpio interface. 14 + Offer various frequency and attenuation ranges. 14 15 HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz 15 - https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf 16 + https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf 17 + 18 + HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz 19 + https://www.analog.com/media/en/technical-documentation/data-sheets/hmc540s.pdf 20 + 16 21 17 22 properties: 18 23 compatible: 19 24 enum: 20 25 - adi,hmc425a 26 + - adi,hmc540s 21 27 22 28 vcc-supply: true 23 29

+5

Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml

··· 48 48 49 49 mount-matrix: true 50 50 51 + invensense,level-shifter: 52 + type: boolean 53 + description: | 54 + From ancient platform data struct: false: VLogic, true: VDD 55 + 51 56 i2c-gate: 52 57 $ref: /schemas/i2c/i2c-controller.yaml 53 58 unevaluatedProperties: false

+3

Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml

··· 93 93 wakeup-source: 94 94 $ref: /schemas/types.yaml#/definitions/flag 95 95 96 + mount-matrix: 97 + description: an optional 3x3 mounting rotation matrix 98 + 96 99 required: 97 100 - compatible 98 101 - reg

+52

Documentation/devicetree/bindings/iio/pressure/rohm,bm1390.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/iio/pressure/rohm,bm1390.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ROHM BM1390 pressure sensor 8 + 9 + maintainers: 10 + - Matti Vaittinen <mazziesaccount@gmail.com> 11 + 12 + description: 13 + BM1390GLV-Z is a pressure sensor which performs internal temperature 14 + compensation for the MEMS. Pressure range is from 300 hPa to 1300 hPa 15 + and sample averaging and IIR filtering is built in. Temperature 16 + measurement is also supported. 17 + 18 + properties: 19 + compatible: 20 + const: rohm,bm1390glv-z 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + interrupts: 26 + maxItems: 1 27 + 28 + vdd-supply: true 29 + 30 + required: 31 + - compatible 32 + - reg 33 + - vdd-supply 34 + 35 + additionalProperties: false 36 + 37 + examples: 38 + - | 39 + #include <dt-bindings/interrupt-controller/irq.h> 40 + i2c { 41 + #address-cells = <1>; 42 + #size-cells = <0>; 43 + pressure-sensor@5d { 44 + compatible = "rohm,bm1390glv-z"; 45 + reg = <0x5d>; 46 + 47 + interrupt-parent = <&gpio1>; 48 + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 49 + 50 + vdd-supply = <&vdd>; 51 + }; 52 + };

+177

Documentation/devicetree/bindings/iio/resolver/adi,ad2s1210.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s1210.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Analog Devices AD2S1210 Resolver-to-Digital Converter 8 + 9 + maintainers: 10 + - Michael Hennerich <michael.hennerich@analog.com> 11 + 12 + description: | 13 + The AD2S1210 is a complete 10-bit to 16-bit resolution tracking 14 + resolver-to-digital converter, integrating an on-board programmable 15 + sinusoidal oscillator that provides sine wave excitation for 16 + resolvers. 17 + 18 + The AD2S1210 allows the user to read the angular position or the 19 + angular velocity data directly from the parallel outputs or through 20 + the serial interface. 21 + 22 + The mode of operation of the communication channel (parallel or serial) is 23 + selected by the A0 and A1 input pins. In normal mode, data is latched by 24 + toggling the SAMPLE line and can then be read directly. In configuration mode, 25 + data is read or written using a register access scheme (address byte with 26 + read/write flag and data byte). 27 + 28 + A1 A0 Result 29 + 0 0 Normal mode - position output 30 + 0 1 Normal mode - velocity output 31 + 1 0 Reserved 32 + 1 1 Configuration mode 33 + 34 + In normal mode, the resolution of the digital output is selected using 35 + the RES0 and RES1 input pins. In configuration mode, the resolution is 36 + selected by setting the RES0 and RES1 bits in the control register. 37 + 38 + RES1 RES0 Resolution (Bits) 39 + 0 0 10 40 + 0 1 12 41 + 1 0 14 42 + 1 1 16 43 + 44 + Note on SPI connections: The CS line on the AD2S1210 should hard-wired to 45 + logic low and the WR/FSYNC line on the AD2S1210 should be connected to the 46 + SPI CSn output of the SPI controller. 47 + 48 + Datasheet: 49 + https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf 50 + 51 + properties: 52 + compatible: 53 + const: adi,ad2s1210 54 + 55 + reg: 56 + maxItems: 1 57 + 58 + spi-max-frequency: 59 + maximum: 25000000 60 + 61 + spi-cpha: true 62 + 63 + avdd-supply: 64 + description: 65 + A 4.75 to 5.25 V regulator that powers the Analog Supply Voltage (AVDD) 66 + pin. 67 + 68 + dvdd-supply: 69 + description: 70 + A 4.75 to 5.25 V regulator that powers the Digital Supply Voltage (DVDD) 71 + pin. 72 + 73 + vdrive-supply: 74 + description: 75 + A 2.3 to 5.25 V regulator that powers the Logic Power Supply Input 76 + (VDrive) pin. 77 + 78 + clocks: 79 + maxItems: 1 80 + description: External oscillator clock (CLKIN). 81 + 82 + reset-gpios: 83 + description: 84 + GPIO connected to the /RESET pin. As the line needs to be low for the 85 + reset to be active, it should be configured as GPIO_ACTIVE_LOW. 86 + maxItems: 1 87 + 88 + sample-gpios: 89 + description: 90 + GPIO connected to the /SAMPLE pin. As the line needs to be low to trigger 91 + a sample, it should be configured as GPIO_ACTIVE_LOW. 92 + maxItems: 1 93 + 94 + mode-gpios: 95 + description: 96 + GPIO lines connected to the A0 and A1 pins. These pins select the data 97 + transfer mode. 98 + minItems: 2 99 + maxItems: 2 100 + 101 + resolution-gpios: 102 + description: 103 + GPIO lines connected to the RES0 and RES1 pins. These pins select the 104 + resolution of the digital output. If omitted, it is assumed that the 105 + RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits 106 + property. 107 + minItems: 2 108 + maxItems: 2 109 + 110 + fault-gpios: 111 + description: 112 + GPIO lines connected to the LOT and DOS pins. These pins combined indicate 113 + the type of fault present, if any. As these pins a pulled low to indicate 114 + a fault condition, they should be configured as GPIO_ACTIVE_LOW. 115 + minItems: 2 116 + maxItems: 2 117 + 118 + adi,fixed-mode: 119 + description: 120 + This is used to indicate the selected mode if A0 and A1 are hard-wired 121 + instead of connected to GPIOS (i.e. mode-gpios is omitted). 122 + $ref: /schemas/types.yaml#/definitions/string 123 + enum: [config, velocity, position] 124 + 125 + assigned-resolution-bits: 126 + description: 127 + Resolution of the digital output required by the application. This 128 + determines the precision of the angle and/or the maximum speed that can 129 + be measured. If resolution-gpios is omitted, it is assumed that RES0 and 130 + RES1 are hard-wired to match this value. 131 + enum: [10, 12, 14, 16] 132 + 133 + required: 134 + - compatible 135 + - reg 136 + - spi-cpha 137 + - avdd-supply 138 + - dvdd-supply 139 + - vdrive-supply 140 + - clocks 141 + - sample-gpios 142 + - assigned-resolution-bits 143 + 144 + oneOf: 145 + - required: 146 + - mode-gpios 147 + - required: 148 + - adi,fixed-mode 149 + 150 + allOf: 151 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 152 + 153 + unevaluatedProperties: false 154 + 155 + examples: 156 + - | 157 + #include <dt-bindings/gpio/gpio.h> 158 + 159 + spi { 160 + #address-cells = <1>; 161 + #size-cells = <0>; 162 + 163 + resolver@0 { 164 + compatible = "adi,ad2s1210"; 165 + reg = <0>; 166 + spi-max-frequency = <20000000>; 167 + spi-cpha; 168 + avdd-supply = <&avdd_regulator>; 169 + dvdd-supply = <&dvdd_regulator>; 170 + vdrive-supply = <&vdrive_regulator>; 171 + clocks = <&ext_osc>; 172 + sample-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; 173 + mode-gpios = <&gpio0 86 0>, <&gpio0 87 0>; 174 + resolution-gpios = <&gpio0 88 0>, <&gpio0 89 0>; 175 + assigned-resolution-bits = <16>; 176 + }; 177 + };

+2

Documentation/devicetree/bindings/trivial-devices.yaml

··· 348 348 # Silicon Labs SI3210 Programmable CMOS SLIC/CODEC with SPI interface 349 349 - silabs,si3210 350 350 # Relative Humidity and Temperature Sensors 351 + - silabs,si7005 352 + # Relative Humidity and Temperature Sensors 351 353 - silabs,si7020 352 354 # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply 353 355 - skyworks,sky81452

+16 -3

MAINTAINERS

··· 1118 1118 M: Cosmin Tanislav <cosmin.tanislav@analog.com> 1119 1119 L: linux-iio@vger.kernel.org 1120 1120 S: Supported 1121 - W: http://ez.analog.com/community/linux-device-drivers 1121 + W: https://ez.analog.com/linux-software-drivers 1122 1122 F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 1123 1123 F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml 1124 1124 F: drivers/iio/adc/ad4130.c ··· 1151 1151 M: Cosmin Tanislav <cosmin.tanislav@analog.com> 1152 1152 L: linux-iio@vger.kernel.org 1153 1153 S: Supported 1154 - W: http://ez.analog.com/community/linux-device-drivers 1154 + W: https://ez.analog.com/linux-software-drivers 1155 1155 F: Documentation/devicetree/bindings/iio/addac/adi,ad74115.yaml 1156 1156 F: drivers/iio/addac/ad74115.c 1157 1157 ··· 12811 12811 M: Daniel Matyas <daniel.matyas@analog.com> 12812 12812 L: linux-hwmon@vger.kernel.org 12813 12813 S: Supported 12814 - W: http://ez.analog.com/community/linux-device-drivers 12814 + W: https://ez.analog.com/linux-software-drivers 12815 12815 F: Documentation/devicetree/bindings/hwmon/adi,max31827.yaml 12816 12816 F: Documentation/hwmon/max31827.rst 12817 12817 F: drivers/hwmon/max31827.c ··· 14010 14010 S: Supported 14011 14011 F: Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt 14012 14012 F: drivers/regulator/mcp16502.c 14013 + 14014 + MICROCHIP MCP3564 ADC DRIVER 14015 + M: Marius Cristea <marius.cristea@microchip.com> 14016 + L: linux-iio@vger.kernel.org 14017 + S: Supported 14018 + F: Documentation/devicetree/bindings/iio/adc/microchip,mcp3564.yaml 14019 + F: drivers/iio/adc/mcp3564.c 14013 14020 14014 14021 MICROCHIP MCP3911 ADC DRIVER 14015 14022 M: Marcus Folkesson <marcus.folkesson@gmail.com> ··· 18561 18554 S: Maintained 18562 18555 F: Documentation/devicetree/bindings/iio/light/bh1750.yaml 18563 18556 F: drivers/iio/light/bh1750.c 18557 + 18558 + ROHM BM1390 PRESSURE SENSOR DRIVER 18559 + M: Matti Vaittinen <mazziesaccount@gmail.com> 18560 + L: linux-iio@vger.kernel.org 18561 + S: Supported 18562 + F: drivers/iio/pressure/rohm-bm1390.c 18564 18563 18565 18564 ROHM BU270xx LIGHT SENSOR DRIVERs 18566 18565 M: Matti Vaittinen <mazziesaccount@gmail.com>

+7

drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c

··· 257 257 else 258 258 als_input.illuminance_value = 259 259 (int)sensor_virt_addr[0] / AMD_SFH_FW_MULTIPLIER; 260 + 261 + if (sensor_idx == ACS_IDX) { 262 + als_input.light_color_temp = sensor_virt_addr[1]; 263 + als_input.chromaticity_x_value = sensor_virt_addr[2]; 264 + als_input.chromaticity_y_value = sensor_virt_addr[3]; 265 + } 266 + 260 267 report_size = sizeof(als_input); 261 268 memcpy(input_report, &als_input, sizeof(als_input)); 262 269 break;

+3

drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h

··· 99 99 struct common_input_property common_property; 100 100 /* values specific to this sensor */ 101 101 int illuminance_value; 102 + int light_color_temp; 103 + int chromaticity_x_value; 104 + int chromaticity_y_value; 102 105 } __packed; 103 106 104 107 struct hpd_feature_report {

+21

drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_report_desc.h

··· 641 641 0x75, 32, /* HID report size(32) */ 642 642 0x95, 1, /* HID report count (1) */ 643 643 0X81, 0x02, /* HID Input (Data_Arr_Abs) */ 644 + 0x0A, 0xD2, 0x04, /* HID usage sensor data light temperature */ 645 + 0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ 646 + 0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ 647 + 0x55, 0x0, /* HID unit exponent(0x0) */ 648 + 0x75, 32, /* HID report size(32) */ 649 + 0x95, 1, /* HID report count (1) */ 650 + 0X81, 0x02, /* HID Input (Data_Arr_Abs) */ 651 + 0x0A, 0xD4, 0x04, /* HID usage sensor data light chromaticity_x */ 652 + 0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ 653 + 0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ 654 + 0x55, 0x0, /* HID unit exponent(0x0) */ 655 + 0x75, 32, /* HID report size(32) */ 656 + 0x95, 1, /* HID report count(1) */ 657 + 0X81, 0x02, /* HID Input (Data_Var_Abs) */ 658 + 0x0A, 0xD5, 0x04, /* HID usage sensor data light chromaticity_y */ 659 + 0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ 660 + 0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ 661 + 0x55, 0x0, /* HID unit exponent(0x0) */ 662 + 0x75, 32, /* HID report size(32) */ 663 + 0x95, 1, /* HID report count (1) */ 664 + 0X81, 0x02, /* HID Input (Data_Var_Abs) */ 644 665 0xC0 /* HID end collection */ 645 666 }; 646 667

+9

drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c

··· 188 188 struct sfh_mag_data mag_data; 189 189 struct sfh_als_data als_data; 190 190 struct hpd_status hpdstatus; 191 + struct sfh_base_info binfo; 191 192 void __iomem *sensoraddr; 192 193 u8 report_size = 0; 193 194 ··· 236 235 memcpy_fromio(&als_data, sensoraddr, sizeof(struct sfh_als_data)); 237 236 get_common_inputs(&als_input.common_property, report_id); 238 237 als_input.illuminance_value = float_to_int(als_data.lux); 238 + 239 + memcpy_fromio(&binfo, mp2->vsbase, sizeof(struct sfh_base_info)); 240 + if (binfo.sbase.s_prop[ALS_IDX].sf.feat & 0x2) { 241 + als_input.light_color_temp = als_data.light_color_temp; 242 + als_input.chromaticity_x_value = float_to_int(als_data.chromaticity_x); 243 + als_input.chromaticity_y_value = float_to_int(als_data.chromaticity_y); 244 + } 245 + 239 246 report_size = sizeof(als_input); 240 247 memcpy(input_report, &als_input, sizeof(als_input)); 241 248 break;

+15

drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h

··· 88 88 }; 89 89 }; 90 90 91 + struct sfh_sensor_prop { 92 + union { 93 + u32 sprop; 94 + struct { 95 + u32 elist : 16; 96 + u32 feat : 16; 97 + } sf; 98 + }; 99 + }; 100 + 91 101 struct sfh_base_info { 92 102 union { 93 103 u32 sfh_base[24]; ··· 105 95 struct sfh_platform_info plat_info; 106 96 struct sfh_firmware_info fw_info; 107 97 struct sfh_sensor_list s_list; 98 + u32 rsvd; 99 + struct sfh_sensor_prop s_prop[16]; 108 100 } sbase; 109 101 }; 110 102 }; ··· 146 134 struct sfh_als_data { 147 135 struct sfh_common_data commondata; 148 136 u32 lux; 137 + u32 light_color_temp; 138 + u32 chromaticity_x; 139 + u32 chromaticity_y; 149 140 }; 150 141 151 142 struct hpd_status {

+6 -4

drivers/iio/accel/Kconfig

··· 418 418 select IIO_KX022A 419 419 select REGMAP_SPI 420 420 help 421 - Enable support for the Kionix KX022A digital tri-axis 422 - accelerometer connected to I2C interface. 421 + Enable support for the Kionix digital tri-axis accelerometers 422 + connected to SPI interface. Supported devices are: 423 + KX022A, KX132-1211, KX132ACR-LBZ 423 424 424 425 config IIO_KX022A_I2C 425 426 tristate "Kionix KX022A tri-axis digital accelerometer I2C interface" ··· 428 427 select IIO_KX022A 429 428 select REGMAP_I2C 430 429 help 431 - Enable support for the Kionix KX022A digital tri-axis 432 - accelerometer connected to I2C interface. 430 + Enable support for the Kionix digital tri-axis accelerometers 431 + connected to I2C interface. Supported devices are: 432 + KX022A, KX132-1211, KX132ACR-LBZ 433 433 434 434 config KXSD9 435 435 tristate "Kionix KXSD9 Accelerometer Driver"

+18 -3

drivers/iio/accel/adxl345.h

··· 8 8 #ifndef _ADXL345_H_ 9 9 #define _ADXL345_H_ 10 10 11 - enum adxl345_device_type { 12 - ADXL345 = 1, 13 - ADXL375 = 2, 11 + /* 12 + * In full-resolution mode, scale factor is maintained at ~4 mg/LSB 13 + * in all g ranges. 14 + * 15 + * At +/- 16g with 13-bit resolution, scale is computed as: 16 + * (16 + 16) * 9.81 / (2^13 - 1) = 0.0383 17 + */ 18 + #define ADXL345_USCALE 38300 19 + 20 + /* 21 + * The Datasheet lists a resolution of Resolution is ~49 mg per LSB. That's 22 + * ~480mm/s**2 per LSB. 23 + */ 24 + #define ADXL375_USCALE 480000 25 + 26 + struct adxl345_chip_info { 27 + const char *name; 28 + int uscale; 14 29 }; 15 30 16 31 int adxl345_core_probe(struct device *dev, struct regmap *regmap);

+6 -41

drivers/iio/accel/adxl345_core.c

··· 45 45 46 46 #define ADXL345_DEVID 0xE5 47 47 48 - /* 49 - * In full-resolution mode, scale factor is maintained at ~4 mg/LSB 50 - * in all g ranges. 51 - * 52 - * At +/- 16g with 13-bit resolution, scale is computed as: 53 - * (16 + 16) * 9.81 / (2^13 - 1) = 0.0383 54 - */ 55 - static const int adxl345_uscale = 38300; 56 - 57 - /* 58 - * The Datasheet lists a resolution of Resolution is ~49 mg per LSB. That's 59 - * ~480mm/s**2 per LSB. 60 - */ 61 - static const int adxl375_uscale = 480000; 62 - 63 48 struct adxl345_data { 49 + const struct adxl345_chip_info *info; 64 50 struct regmap *regmap; 65 51 u8 data_range; 66 - enum adxl345_device_type type; 67 52 }; 68 53 69 54 #define ADXL345_CHANNEL(index, axis) { \ ··· 95 110 return IIO_VAL_INT; 96 111 case IIO_CHAN_INFO_SCALE: 97 112 *val = 0; 98 - switch (data->type) { 99 - case ADXL345: 100 - *val2 = adxl345_uscale; 101 - break; 102 - case ADXL375: 103 - *val2 = adxl375_uscale; 104 - break; 105 - } 106 - 113 + *val2 = data->info->uscale; 107 114 return IIO_VAL_INT_PLUS_MICRO; 108 115 case IIO_CHAN_INFO_CALIBBIAS: 109 116 ret = regmap_read(data->regmap, ··· 199 222 200 223 int adxl345_core_probe(struct device *dev, struct regmap *regmap) 201 224 { 202 - enum adxl345_device_type type; 203 225 struct adxl345_data *data; 204 226 struct iio_dev *indio_dev; 205 - const char *name; 206 227 u32 regval; 207 228 int ret; 208 - 209 - type = (uintptr_t)device_get_match_data(dev); 210 - switch (type) { 211 - case ADXL345: 212 - name = "adxl345"; 213 - break; 214 - case ADXL375: 215 - name = "adxl375"; 216 - break; 217 - default: 218 - return -EINVAL; 219 - } 220 229 221 230 ret = regmap_read(regmap, ADXL345_REG_DEVID, &regval); 222 231 if (ret < 0) ··· 218 255 219 256 data = iio_priv(indio_dev); 220 257 data->regmap = regmap; 221 - data->type = type; 222 258 /* Enable full-resolution mode */ 223 259 data->data_range = ADXL345_DATA_FORMAT_FULL_RES; 260 + data->info = device_get_match_data(dev); 261 + if (!data->info) 262 + return -ENODEV; 224 263 225 264 ret = regmap_write(data->regmap, ADXL345_REG_DATA_FORMAT, 226 265 data->data_range); 227 266 if (ret < 0) 228 267 return dev_err_probe(dev, ret, "Failed to set data range\n"); 229 268 230 - indio_dev->name = name; 269 + indio_dev->name = data->info->name; 231 270 indio_dev->info = &adxl345_info; 232 271 indio_dev->modes = INDIO_DIRECT_MODE; 233 272 indio_dev->channels = adxl345_channels;

+15 -5

drivers/iio/accel/adxl345_i2c.c

··· 30 30 return adxl345_core_probe(&client->dev, regmap); 31 31 } 32 32 33 + static const struct adxl345_chip_info adxl345_i2c_info = { 34 + .name = "adxl345", 35 + .uscale = ADXL345_USCALE, 36 + }; 37 + 38 + static const struct adxl345_chip_info adxl375_i2c_info = { 39 + .name = "adxl375", 40 + .uscale = ADXL375_USCALE, 41 + }; 42 + 33 43 static const struct i2c_device_id adxl345_i2c_id[] = { 34 - { "adxl345", ADXL345 }, 35 - { "adxl375", ADXL375 }, 44 + { "adxl345", (kernel_ulong_t)&adxl345_i2c_info }, 45 + { "adxl375", (kernel_ulong_t)&adxl375_i2c_info }, 36 46 { } 37 47 }; 38 48 MODULE_DEVICE_TABLE(i2c, adxl345_i2c_id); 39 49 40 50 static const struct of_device_id adxl345_of_match[] = { 41 - { .compatible = "adi,adxl345", .data = (const void *)ADXL345 }, 42 - { .compatible = "adi,adxl375", .data = (const void *)ADXL375 }, 51 + { .compatible = "adi,adxl345", .data = &adxl345_i2c_info }, 52 + { .compatible = "adi,adxl375", .data = &adxl375_i2c_info }, 43 53 { } 44 54 }; 45 55 MODULE_DEVICE_TABLE(of, adxl345_of_match); 46 56 47 57 static const struct acpi_device_id adxl345_acpi_match[] = { 48 - { "ADS0345", ADXL345 }, 58 + { "ADS0345", (kernel_ulong_t)&adxl345_i2c_info }, 49 59 { } 50 60 }; 51 61 MODULE_DEVICE_TABLE(acpi, adxl345_acpi_match);

+15 -5

drivers/iio/accel/adxl345_spi.c

··· 36 36 return adxl345_core_probe(&spi->dev, regmap); 37 37 } 38 38 39 + static const struct adxl345_chip_info adxl345_spi_info = { 40 + .name = "adxl345", 41 + .uscale = ADXL345_USCALE, 42 + }; 43 + 44 + static const struct adxl345_chip_info adxl375_spi_info = { 45 + .name = "adxl375", 46 + .uscale = ADXL375_USCALE, 47 + }; 48 + 39 49 static const struct spi_device_id adxl345_spi_id[] = { 40 - { "adxl345", ADXL345 }, 41 - { "adxl375", ADXL375 }, 50 + { "adxl345", (kernel_ulong_t)&adxl345_spi_info }, 51 + { "adxl375", (kernel_ulong_t)&adxl375_spi_info }, 42 52 { } 43 53 }; 44 54 MODULE_DEVICE_TABLE(spi, adxl345_spi_id); 45 55 46 56 static const struct of_device_id adxl345_of_match[] = { 47 - { .compatible = "adi,adxl345", .data = (const void *)ADXL345 }, 48 - { .compatible = "adi,adxl375", .data = (const void *)ADXL375 }, 57 + { .compatible = "adi,adxl345", .data = &adxl345_spi_info }, 58 + { .compatible = "adi,adxl375", .data = &adxl375_spi_info }, 49 59 { } 50 60 }; 51 61 MODULE_DEVICE_TABLE(of, adxl345_of_match); 52 62 53 63 static const struct acpi_device_id adxl345_acpi_match[] = { 54 - { "ADS0345", ADXL345 }, 64 + { "ADS0345", (kernel_ulong_t)&adxl345_spi_info }, 55 65 { } 56 66 }; 57 67 MODULE_DEVICE_TABLE(acpi, adxl345_acpi_match);

+11 -16

drivers/iio/accel/bma180.c

··· 926 926 struct device *dev = &client->dev; 927 927 struct bma180_data *data; 928 928 struct iio_dev *indio_dev; 929 - enum chip_ids chip; 930 929 int ret; 931 930 932 931 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); ··· 935 936 data = iio_priv(indio_dev); 936 937 i2c_set_clientdata(client, indio_dev); 937 938 data->client = client; 938 - if (client->dev.of_node) 939 - chip = (uintptr_t)of_device_get_match_data(dev); 940 - else 941 - chip = id->driver_data; 942 - data->part_info = &bma180_part_info[chip]; 939 + data->part_info = i2c_get_match_data(client); 943 940 944 941 ret = iio_read_mount_matrix(dev, &data->orientation); 945 942 if (ret) ··· 1087 1092 static DEFINE_SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume); 1088 1093 1089 1094 static const struct i2c_device_id bma180_ids[] = { 1090 - { "bma023", BMA023 }, 1091 - { "bma150", BMA150 }, 1092 - { "bma180", BMA180 }, 1093 - { "bma250", BMA250 }, 1094 - { "smb380", BMA150 }, 1095 + { "bma023", (kernel_ulong_t)&bma180_part_info[BMA023] }, 1096 + { "bma150", (kernel_ulong_t)&bma180_part_info[BMA150] }, 1097 + { "bma180", (kernel_ulong_t)&bma180_part_info[BMA180] }, 1098 + { "bma250", (kernel_ulong_t)&bma180_part_info[BMA250] }, 1099 + { "smb380", (kernel_ulong_t)&bma180_part_info[BMA150] }, 1095 1100 { } 1096 1101 }; 1097 1102 ··· 1100 1105 static const struct of_device_id bma180_of_match[] = { 1101 1106 { 1102 1107 .compatible = "bosch,bma023", 1103 - .data = (void *)BMA023 1108 + .data = &bma180_part_info[BMA023] 1104 1109 }, 1105 1110 { 1106 1111 .compatible = "bosch,bma150", 1107 - .data = (void *)BMA150 1112 + .data = &bma180_part_info[BMA150] 1108 1113 }, 1109 1114 { 1110 1115 .compatible = "bosch,bma180", 1111 - .data = (void *)BMA180 1116 + .data = &bma180_part_info[BMA180] 1112 1117 }, 1113 1118 { 1114 1119 .compatible = "bosch,bma250", 1115 - .data = (void *)BMA250 1120 + .data = &bma180_part_info[BMA250] 1116 1121 }, 1117 1122 { 1118 1123 .compatible = "bosch,smb380", 1119 - .data = (void *)BMA150 1124 + .data = &bma180_part_info[BMA150] 1120 1125 }, 1121 1126 { } 1122 1127 };

-1

drivers/iio/accel/fxls8962af.h

··· 14 14 }; 15 15 16 16 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq); 17 - int fxls8962af_core_remove(struct device *dev); 18 17 19 18 extern const struct dev_pm_ops fxls8962af_pm_ops; 20 19 extern const struct regmap_config fxls8962af_i2c_regmap_conf;

+2 -4

drivers/iio/accel/hid-sensor-accel-3d.c

··· 422 422 } 423 423 424 424 /* Function to deinitialize the processing for usage id */ 425 - static int hid_accel_3d_remove(struct platform_device *pdev) 425 + static void hid_accel_3d_remove(struct platform_device *pdev) 426 426 { 427 427 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 428 428 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 431 431 sensor_hub_remove_callback(hsdev, hsdev->usage); 432 432 iio_device_unregister(indio_dev); 433 433 hid_sensor_remove_trigger(indio_dev, &accel_state->common_attributes); 434 - 435 - return 0; 436 434 } 437 435 438 436 static const struct platform_device_id hid_accel_3d_ids[] = { ··· 452 454 .pm = &hid_sensor_pm_ops, 453 455 }, 454 456 .probe = hid_accel_3d_probe, 455 - .remove = hid_accel_3d_remove, 457 + .remove_new = hid_accel_3d_remove, 456 458 }; 457 459 module_platform_driver(hid_accel_3d_platform_driver); 458 460

+20 -4

drivers/iio/accel/kionix-kx022a-i2c.c

··· 2 2 /* 3 3 * Copyright (C) 2022 ROHM Semiconductors 4 4 * 5 - * ROHM/KIONIX KX022A accelerometer driver 5 + * ROHM/KIONIX accelerometer driver 6 6 */ 7 7 8 8 #include <linux/i2c.h> ··· 15 15 static int kx022a_i2c_probe(struct i2c_client *i2c) 16 16 { 17 17 struct device *dev = &i2c->dev; 18 + const struct kx022a_chip_info *chip_info; 18 19 struct regmap *regmap; 19 20 20 21 if (!i2c->irq) { ··· 23 22 return -EINVAL; 24 23 } 25 24 26 - regmap = devm_regmap_init_i2c(i2c, &kx022a_regmap); 25 + chip_info = i2c_get_match_data(i2c); 26 + if (!chip_info) 27 + return -EINVAL; 28 + 29 + regmap = devm_regmap_init_i2c(i2c, chip_info->regmap_config); 27 30 if (IS_ERR(regmap)) 28 31 return dev_err_probe(dev, PTR_ERR(regmap), 29 32 "Failed to initialize Regmap\n"); 30 33 31 - return kx022a_probe_internal(dev); 34 + return kx022a_probe_internal(dev, chip_info); 32 35 } 33 36 37 + static const struct i2c_device_id kx022a_i2c_id[] = { 38 + { .name = "kx022a", .driver_data = (kernel_ulong_t)&kx022a_chip_info }, 39 + { .name = "kx132-1211", .driver_data = (kernel_ulong_t)&kx132_chip_info }, 40 + { .name = "kx132acr-lbz", .driver_data = (kernel_ulong_t)&kx132acr_chip_info }, 41 + { } 42 + }; 43 + MODULE_DEVICE_TABLE(i2c, kx022a_i2c_id); 44 + 34 45 static const struct of_device_id kx022a_of_match[] = { 35 - { .compatible = "kionix,kx022a", }, 46 + { .compatible = "kionix,kx022a", .data = &kx022a_chip_info }, 47 + { .compatible = "kionix,kx132-1211", .data = &kx132_chip_info }, 48 + { .compatible = "rohm,kx132acr-lbz", .data = &kx132acr_chip_info }, 36 49 { } 37 50 }; 38 51 MODULE_DEVICE_TABLE(of, kx022a_of_match); ··· 58 43 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 59 44 }, 60 45 .probe = kx022a_i2c_probe, 46 + .id_table = kx022a_i2c_id, 61 47 }; 62 48 module_i2c_driver(kx022a_i2c_driver); 63 49

+14 -5

drivers/iio/accel/kionix-kx022a-spi.c

··· 2 2 /* 3 3 * Copyright (C) 2022 ROHM Semiconductors 4 4 * 5 - * ROHM/KIONIX KX022A accelerometer driver 5 + * ROHM/KIONIX accelerometer driver 6 6 */ 7 7 8 8 #include <linux/interrupt.h> ··· 15 15 static int kx022a_spi_probe(struct spi_device *spi) 16 16 { 17 17 struct device *dev = &spi->dev; 18 + const struct kx022a_chip_info *chip_info; 18 19 struct regmap *regmap; 19 20 20 21 if (!spi->irq) { ··· 23 22 return -EINVAL; 24 23 } 25 24 26 - regmap = devm_regmap_init_spi(spi, &kx022a_regmap); 25 + chip_info = spi_get_device_match_data(spi); 26 + if (!chip_info) 27 + return -EINVAL; 28 + 29 + regmap = devm_regmap_init_spi(spi, chip_info->regmap_config); 27 30 if (IS_ERR(regmap)) 28 31 return dev_err_probe(dev, PTR_ERR(regmap), 29 32 "Failed to initialize Regmap\n"); 30 33 31 - return kx022a_probe_internal(dev); 34 + return kx022a_probe_internal(dev, chip_info); 32 35 } 33 36 34 37 static const struct spi_device_id kx022a_id[] = { 35 - { "kx022a" }, 38 + { .name = "kx022a", .driver_data = (kernel_ulong_t)&kx022a_chip_info }, 39 + { .name = "kx132-1211", .driver_data = (kernel_ulong_t)&kx132_chip_info }, 40 + { .name = "kx132acr-lbz", .driver_data = (kernel_ulong_t)&kx132acr_chip_info }, 36 41 { } 37 42 }; 38 43 MODULE_DEVICE_TABLE(spi, kx022a_id); 39 44 40 45 static const struct of_device_id kx022a_of_match[] = { 41 - { .compatible = "kionix,kx022a", }, 46 + { .compatible = "kionix,kx022a", .data = &kx022a_chip_info }, 47 + { .compatible = "kionix,kx132-1211", .data = &kx132_chip_info }, 48 + { .compatible = "rohm,kx132acr-lbz", .data = &kx132acr_chip_info }, 42 49 { } 43 50 }; 44 51 MODULE_DEVICE_TABLE(of, kx022a_of_match);

+292 -59

drivers/iio/accel/kionix-kx022a.c

··· 2 2 /* 3 3 * Copyright (C) 2022 ROHM Semiconductors 4 4 * 5 - * ROHM/KIONIX KX022A accelerometer driver 5 + * ROHM/KIONIX accelerometer driver 6 6 */ 7 7 8 8 #include <linux/delay.h> ··· 15 15 #include <linux/regmap.h> 16 16 #include <linux/regulator/consumer.h> 17 17 #include <linux/slab.h> 18 - #include <linux/string_helpers.h> 18 + #include <linux/string_choices.h> 19 19 #include <linux/units.h> 20 20 21 21 #include <linux/iio/iio.h> ··· 48 48 KX022A_STATE_FIFO, 49 49 }; 50 50 51 - /* Regmap configs */ 51 + /* kx022a Regmap configs */ 52 52 static const struct regmap_range kx022a_volatile_ranges[] = { 53 53 { 54 54 .range_min = KX022A_REG_XHP_L, ··· 138 138 .n_yes_ranges = ARRAY_SIZE(kx022a_noinc_read_ranges), 139 139 }; 140 140 141 - const struct regmap_config kx022a_regmap = { 141 + static const struct regmap_config kx022a_regmap_config = { 142 142 .reg_bits = 8, 143 143 .val_bits = 8, 144 144 .volatile_table = &kx022a_volatile_regs, ··· 149 149 .max_register = KX022A_MAX_REGISTER, 150 150 .cache_type = REGCACHE_RBTREE, 151 151 }; 152 - EXPORT_SYMBOL_NS_GPL(kx022a_regmap, IIO_KX022A); 152 + 153 + /* Regmap configs kx132 */ 154 + static const struct regmap_range kx132_volatile_ranges[] = { 155 + { 156 + .range_min = KX132_REG_XADP_L, 157 + .range_max = KX132_REG_COTR, 158 + }, { 159 + .range_min = KX132_REG_TSCP, 160 + .range_max = KX132_REG_INT_REL, 161 + }, { 162 + /* The reset bit will be cleared by sensor */ 163 + .range_min = KX132_REG_CNTL2, 164 + .range_max = KX132_REG_CNTL2, 165 + }, { 166 + .range_min = KX132_REG_CNTL5, 167 + .range_max = KX132_REG_CNTL5, 168 + }, { 169 + .range_min = KX132_REG_BUF_STATUS_1, 170 + .range_max = KX132_REG_BUF_READ, 171 + }, 172 + }; 173 + 174 + static const struct regmap_access_table kx132_volatile_regs = { 175 + .yes_ranges = &kx132_volatile_ranges[0], 176 + .n_yes_ranges = ARRAY_SIZE(kx132_volatile_ranges), 177 + }; 178 + 179 + static const struct regmap_range kx132_precious_ranges[] = { 180 + { 181 + .range_min = KX132_REG_INT_REL, 182 + .range_max = KX132_REG_INT_REL, 183 + }, 184 + }; 185 + 186 + static const struct regmap_access_table kx132_precious_regs = { 187 + .yes_ranges = &kx132_precious_ranges[0], 188 + .n_yes_ranges = ARRAY_SIZE(kx132_precious_ranges), 189 + }; 190 + 191 + static const struct regmap_range kx132_read_only_ranges[] = { 192 + { 193 + .range_min = KX132_REG_XADP_L, 194 + .range_max = KX132_REG_INT_REL, 195 + }, { 196 + .range_min = KX132_REG_BUF_STATUS_1, 197 + .range_max = KX132_REG_BUF_STATUS_2, 198 + }, { 199 + .range_min = KX132_REG_BUF_READ, 200 + .range_max = KX132_REG_BUF_READ, 201 + }, { 202 + /* Kionix reserved registers: should not be written */ 203 + .range_min = 0x28, 204 + .range_max = 0x28, 205 + }, { 206 + .range_min = 0x35, 207 + .range_max = 0x36, 208 + }, { 209 + .range_min = 0x3c, 210 + .range_max = 0x48, 211 + }, { 212 + .range_min = 0x4e, 213 + .range_max = 0x5c, 214 + }, { 215 + .range_min = 0x77, 216 + .range_max = 0x7f, 217 + }, 218 + }; 219 + 220 + static const struct regmap_access_table kx132_ro_regs = { 221 + .no_ranges = &kx132_read_only_ranges[0], 222 + .n_no_ranges = ARRAY_SIZE(kx132_read_only_ranges), 223 + }; 224 + 225 + static const struct regmap_range kx132_write_only_ranges[] = { 226 + { 227 + .range_min = KX132_REG_SELF_TEST, 228 + .range_max = KX132_REG_SELF_TEST, 229 + }, { 230 + .range_min = KX132_REG_BUF_CLEAR, 231 + .range_max = KX132_REG_BUF_CLEAR, 232 + }, 233 + }; 234 + 235 + static const struct regmap_access_table kx132_wo_regs = { 236 + .no_ranges = &kx132_write_only_ranges[0], 237 + .n_no_ranges = ARRAY_SIZE(kx132_write_only_ranges), 238 + }; 239 + 240 + static const struct regmap_range kx132_noinc_read_ranges[] = { 241 + { 242 + .range_min = KX132_REG_BUF_READ, 243 + .range_max = KX132_REG_BUF_READ, 244 + }, 245 + }; 246 + 247 + static const struct regmap_access_table kx132_nir_regs = { 248 + .yes_ranges = &kx132_noinc_read_ranges[0], 249 + .n_yes_ranges = ARRAY_SIZE(kx132_noinc_read_ranges), 250 + }; 251 + 252 + static const struct regmap_config kx132_regmap_config = { 253 + .reg_bits = 8, 254 + .val_bits = 8, 255 + .volatile_table = &kx132_volatile_regs, 256 + .rd_table = &kx132_wo_regs, 257 + .wr_table = &kx132_ro_regs, 258 + .rd_noinc_table = &kx132_nir_regs, 259 + .precious_table = &kx132_precious_regs, 260 + .max_register = KX132_MAX_REGISTER, 261 + .cache_type = REGCACHE_RBTREE, 262 + }; 153 263 154 264 struct kx022a_data { 155 265 struct regmap *regmap; 266 + const struct kx022a_chip_info *chip_info; 156 267 struct iio_trigger *trig; 157 268 struct device *dev; 158 269 struct iio_mount_matrix orientation; ··· 285 174 */ 286 175 struct mutex mutex; 287 176 u8 watermark; 177 + 178 + __le16 *fifo_buffer; 288 179 289 180 /* 3 x 16bit accel data + timestamp */ 290 181 __le16 buffer[8] __aligned(IIO_DMA_MINALIGN); ··· 321 208 { } 322 209 }; 323 210 324 - #define KX022A_ACCEL_CHAN(axis, index) \ 211 + #define KX022A_ACCEL_CHAN(axis, reg, index) \ 325 212 { \ 326 213 .type = IIO_ACCEL, \ 327 214 .modified = 1, \ ··· 333 220 BIT(IIO_CHAN_INFO_SCALE) | \ 334 221 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 335 222 .ext_info = kx022a_ext_info, \ 336 - .address = KX022A_REG_##axis##OUT_L, \ 223 + .address = reg, \ 337 224 .scan_index = index, \ 338 225 .scan_type = { \ 339 226 .sign = 's', \ ··· 344 231 } 345 232 346 233 static const struct iio_chan_spec kx022a_channels[] = { 347 - KX022A_ACCEL_CHAN(X, 0), 348 - KX022A_ACCEL_CHAN(Y, 1), 349 - KX022A_ACCEL_CHAN(Z, 2), 234 + KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0), 235 + KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1), 236 + KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2), 237 + IIO_CHAN_SOFT_TIMESTAMP(3), 238 + }; 239 + 240 + static const struct iio_chan_spec kx132_channels[] = { 241 + KX022A_ACCEL_CHAN(X, KX132_REG_XOUT_L, 0), 242 + KX022A_ACCEL_CHAN(Y, KX132_REG_YOUT_L, 1), 243 + KX022A_ACCEL_CHAN(Z, KX132_REG_ZOUT_L, 2), 350 244 IIO_CHAN_SOFT_TIMESTAMP(3), 351 245 }; 352 246 ··· 452 332 int ret; 453 333 454 334 if (on) 455 - ret = regmap_set_bits(data->regmap, KX022A_REG_CNTL, 335 + ret = regmap_set_bits(data->regmap, data->chip_info->cntl, 456 336 KX022A_MASK_PC1); 457 337 else 458 - ret = regmap_clear_bits(data->regmap, KX022A_REG_CNTL, 338 + ret = regmap_clear_bits(data->regmap, data->chip_info->cntl, 459 339 KX022A_MASK_PC1); 460 340 if (ret) 461 341 dev_err(data->dev, "Turn %s fail %d\n", str_on_off(on), ret); 462 342 463 343 return ret; 464 - 465 344 } 466 345 467 346 static int kx022a_turn_off_lock(struct kx022a_data *data) ··· 522 403 break; 523 404 524 405 ret = regmap_update_bits(data->regmap, 525 - KX022A_REG_ODCNTL, 406 + data->chip_info->odcntl, 526 407 KX022A_MASK_ODR, n); 527 408 data->odr_ns = kx022a_odrs[n]; 528 409 kx022a_turn_on_unlock(data); ··· 543 424 if (ret) 544 425 break; 545 426 546 - ret = regmap_update_bits(data->regmap, KX022A_REG_CNTL, 427 + ret = regmap_update_bits(data->regmap, data->chip_info->cntl, 547 428 KX022A_MASK_GSEL, 548 429 n << KX022A_GSEL_SHIFT); 549 430 kx022a_turn_on_unlock(data); ··· 565 446 566 447 threshold = data->watermark; 567 448 568 - return regmap_update_bits(data->regmap, KX022A_REG_BUF_CNTL1, 449 + return regmap_update_bits(data->regmap, data->chip_info->buf_cntl1, 569 450 KX022A_MASK_WM_TH, threshold); 570 451 } 571 452 ··· 608 489 return ret; 609 490 610 491 case IIO_CHAN_INFO_SAMP_FREQ: 611 - ret = regmap_read(data->regmap, KX022A_REG_ODCNTL, &regval); 492 + ret = regmap_read(data->regmap, data->chip_info->odcntl, &regval); 612 493 if (ret) 613 494 return ret; 614 495 ··· 623 504 return IIO_VAL_INT_PLUS_MICRO; 624 505 625 506 case IIO_CHAN_INFO_SCALE: 626 - ret = regmap_read(data->regmap, KX022A_REG_CNTL, &regval); 507 + ret = regmap_read(data->regmap, data->chip_info->cntl, &regval); 627 508 if (ret < 0) 628 509 return ret; 629 510 ··· 639 520 { 640 521 struct kx022a_data *data = iio_priv(idev); 641 522 642 - if (val > KX022A_FIFO_LENGTH) 643 - val = KX022A_FIFO_LENGTH; 523 + val = min(data->chip_info->fifo_length, val); 644 524 645 525 mutex_lock(&data->mutex); 646 526 data->watermark = val; ··· 700 582 */ 701 583 data->timestamp = 0; 702 584 703 - return regmap_write(data->regmap, KX022A_REG_BUF_CLEAR, 0x0); 585 + return regmap_write(data->regmap, data->chip_info->buf_clear, 0x0); 586 + } 587 + 588 + static int kx022a_get_fifo_bytes_available(struct kx022a_data *data) 589 + { 590 + int ret, fifo_bytes; 591 + 592 + ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes); 593 + if (ret) { 594 + dev_err(data->dev, "Error reading buffer status\n"); 595 + return ret; 596 + } 597 + 598 + if (fifo_bytes == KX022A_FIFO_FULL_VALUE) 599 + return KX022A_FIFO_MAX_BYTES; 600 + 601 + return fifo_bytes; 602 + } 603 + 604 + static int kx132_get_fifo_bytes_available(struct kx022a_data *data) 605 + { 606 + __le16 buf_status; 607 + int ret, fifo_bytes; 608 + 609 + ret = regmap_bulk_read(data->regmap, data->chip_info->buf_status1, 610 + &buf_status, sizeof(buf_status)); 611 + if (ret) { 612 + dev_err(data->dev, "Error reading buffer status\n"); 613 + return ret; 614 + } 615 + 616 + fifo_bytes = le16_to_cpu(buf_status); 617 + fifo_bytes &= data->chip_info->buf_smp_lvl_mask; 618 + fifo_bytes = min((unsigned int)fifo_bytes, data->chip_info->fifo_length * 619 + KX022A_FIFO_SAMPLES_SIZE_BYTES); 620 + 621 + return fifo_bytes; 704 622 } 705 623 706 624 static int __kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples, 707 625 bool irq) 708 626 { 709 627 struct kx022a_data *data = iio_priv(idev); 710 - struct device *dev = regmap_get_device(data->regmap); 711 - __le16 buffer[KX022A_FIFO_LENGTH * 3]; 712 628 uint64_t sample_period; 713 629 int count, fifo_bytes; 714 630 bool renable = false; 715 631 int64_t tstamp; 716 632 int ret, i; 717 633 718 - ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes); 719 - if (ret) { 720 - dev_err(dev, "Error reading buffer status\n"); 721 - return ret; 722 - } 723 - 724 - /* Let's not overflow if we for some reason get bogus value from i2c */ 725 - if (fifo_bytes == KX022A_FIFO_FULL_VALUE) 726 - fifo_bytes = KX022A_FIFO_MAX_BYTES; 634 + fifo_bytes = data->chip_info->get_fifo_bytes_available(data); 727 635 728 636 if (fifo_bytes % KX022A_FIFO_SAMPLES_SIZE_BYTES) 729 637 dev_warn(data->dev, "Bad FIFO alignment. Data may be corrupt\n"); ··· 813 669 } 814 670 815 671 fifo_bytes = count * KX022A_FIFO_SAMPLES_SIZE_BYTES; 816 - ret = regmap_noinc_read(data->regmap, KX022A_REG_BUF_READ, 817 - &buffer[0], fifo_bytes); 672 + ret = regmap_noinc_read(data->regmap, data->chip_info->buf_read, 673 + data->fifo_buffer, fifo_bytes); 818 674 if (ret) 819 675 goto renable_out; 820 676 821 677 for (i = 0; i < count; i++) { 822 - __le16 *sam = &buffer[i * 3]; 678 + __le16 *sam = &data->fifo_buffer[i * 3]; 823 679 __le16 *chs; 824 680 int bit; 825 681 ··· 866 722 static int kx022a_set_drdy_irq(struct kx022a_data *data, bool en) 867 723 { 868 724 if (en) 869 - return regmap_set_bits(data->regmap, KX022A_REG_CNTL, 725 + return regmap_set_bits(data->regmap, data->chip_info->cntl, 870 726 KX022A_MASK_DRDY); 871 727 872 - return regmap_clear_bits(data->regmap, KX022A_REG_CNTL, 728 + return regmap_clear_bits(data->regmap, data->chip_info->cntl, 873 729 KX022A_MASK_DRDY); 874 730 } 875 731 ··· 904 760 if (ret) 905 761 goto unlock_out; 906 762 907 - ret = regmap_clear_bits(data->regmap, KX022A_REG_BUF_CNTL2, 763 + ret = regmap_clear_bits(data->regmap, data->chip_info->buf_cntl2, 908 764 KX022A_MASK_BUF_EN); 909 765 if (ret) 910 766 goto unlock_out; ··· 912 768 data->state &= ~KX022A_STATE_FIFO; 913 769 914 770 kx022a_drop_fifo_contents(data); 771 + 772 + kfree(data->fifo_buffer); 915 773 916 774 return kx022a_turn_on_unlock(data); 917 775 ··· 937 791 { 938 792 int ret; 939 793 794 + data->fifo_buffer = kmalloc_array(data->chip_info->fifo_length, 795 + KX022A_FIFO_SAMPLES_SIZE_BYTES, 796 + GFP_KERNEL); 797 + if (!data->fifo_buffer) 798 + return -ENOMEM; 799 + 940 800 ret = kx022a_turn_off_lock(data); 941 801 if (ret) 942 802 return ret; ··· 953 801 goto unlock_out; 954 802 955 803 /* Enable buffer */ 956 - ret = regmap_set_bits(data->regmap, KX022A_REG_BUF_CNTL2, 804 + ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2, 957 805 KX022A_MASK_BUF_EN); 958 806 if (ret) 959 807 goto unlock_out; ··· 999 847 struct kx022a_data *data = iio_priv(idev); 1000 848 int ret; 1001 849 1002 - ret = regmap_bulk_read(data->regmap, KX022A_REG_XOUT_L, data->buffer, 850 + ret = regmap_bulk_read(data->regmap, data->chip_info->xout_l, data->buffer, 1003 851 KX022A_FIFO_SAMPLES_SIZE_BYTES); 1004 852 if (ret < 0) 1005 853 goto err_read; ··· 1047 895 if (data->state & KX022A_STATE_FIFO) { 1048 896 int ok; 1049 897 1050 - ok = __kx022a_fifo_flush(idev, KX022A_FIFO_LENGTH, true); 898 + ok = __kx022a_fifo_flush(idev, data->chip_info->fifo_length, true); 1051 899 if (ok > 0) 1052 900 ret = IRQ_HANDLED; 1053 901 } ··· 1100 948 int ret, val; 1101 949 1102 950 /* Reset the senor */ 1103 - ret = regmap_write(data->regmap, KX022A_REG_CNTL2, KX022A_MASK_SRST); 951 + ret = regmap_write(data->regmap, data->chip_info->cntl2, KX022A_MASK_SRST); 1104 952 if (ret) 1105 953 return ret; 1106 954 ··· 1110 958 */ 1111 959 msleep(1); 1112 960 1113 - ret = regmap_read_poll_timeout(data->regmap, KX022A_REG_CNTL2, val, 961 + ret = regmap_read_poll_timeout(data->regmap, data->chip_info->cntl2, val, 1114 962 !(val & KX022A_MASK_SRST), 1115 963 KX022A_SOFT_RESET_WAIT_TIME_US, 1116 964 KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US); ··· 1120 968 return ret; 1121 969 } 1122 970 1123 - ret = regmap_reinit_cache(data->regmap, &kx022a_regmap); 971 + ret = regmap_reinit_cache(data->regmap, data->chip_info->regmap_config); 1124 972 if (ret) { 1125 973 dev_err(data->dev, "Failed to reinit reg cache\n"); 1126 974 return ret; 1127 975 } 1128 976 1129 977 /* set data res 16bit */ 1130 - ret = regmap_set_bits(data->regmap, KX022A_REG_BUF_CNTL2, 978 + ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2, 1131 979 KX022A_MASK_BRES16); 1132 980 if (ret) { 1133 981 dev_err(data->dev, "Failed to set data resolution\n"); ··· 1137 985 return kx022a_prepare_irq_pin(data); 1138 986 } 1139 987 1140 - int kx022a_probe_internal(struct device *dev) 988 + const struct kx022a_chip_info kx022a_chip_info = { 989 + .name = "kx022-accel", 990 + .regmap_config = &kx022a_regmap_config, 991 + .channels = kx022a_channels, 992 + .num_channels = ARRAY_SIZE(kx022a_channels), 993 + .fifo_length = KX022A_FIFO_LENGTH, 994 + .who = KX022A_REG_WHO, 995 + .id = KX022A_ID, 996 + .cntl = KX022A_REG_CNTL, 997 + .cntl2 = KX022A_REG_CNTL2, 998 + .odcntl = KX022A_REG_ODCNTL, 999 + .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1000 + .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1001 + .buf_clear = KX022A_REG_BUF_CLEAR, 1002 + .buf_status1 = KX022A_REG_BUF_STATUS_1, 1003 + .buf_read = KX022A_REG_BUF_READ, 1004 + .inc1 = KX022A_REG_INC1, 1005 + .inc4 = KX022A_REG_INC4, 1006 + .inc5 = KX022A_REG_INC5, 1007 + .inc6 = KX022A_REG_INC6, 1008 + .xout_l = KX022A_REG_XOUT_L, 1009 + .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1010 + }; 1011 + EXPORT_SYMBOL_NS_GPL(kx022a_chip_info, IIO_KX022A); 1012 + 1013 + const struct kx022a_chip_info kx132_chip_info = { 1014 + .name = "kx132-1211", 1015 + .regmap_config = &kx132_regmap_config, 1016 + .channels = kx132_channels, 1017 + .num_channels = ARRAY_SIZE(kx132_channels), 1018 + .fifo_length = KX132_FIFO_LENGTH, 1019 + .who = KX132_REG_WHO, 1020 + .id = KX132_ID, 1021 + .cntl = KX132_REG_CNTL, 1022 + .cntl2 = KX132_REG_CNTL2, 1023 + .odcntl = KX132_REG_ODCNTL, 1024 + .buf_cntl1 = KX132_REG_BUF_CNTL1, 1025 + .buf_cntl2 = KX132_REG_BUF_CNTL2, 1026 + .buf_clear = KX132_REG_BUF_CLEAR, 1027 + .buf_status1 = KX132_REG_BUF_STATUS_1, 1028 + .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL, 1029 + .buf_read = KX132_REG_BUF_READ, 1030 + .inc1 = KX132_REG_INC1, 1031 + .inc4 = KX132_REG_INC4, 1032 + .inc5 = KX132_REG_INC5, 1033 + .inc6 = KX132_REG_INC6, 1034 + .xout_l = KX132_REG_XOUT_L, 1035 + .get_fifo_bytes_available = kx132_get_fifo_bytes_available, 1036 + }; 1037 + EXPORT_SYMBOL_NS_GPL(kx132_chip_info, IIO_KX022A); 1038 + 1039 + /* 1040 + * Despite the naming, KX132ACR-LBZ is not similar to KX132-1211 but it is 1041 + * exact subset of KX022A. KX132ACR-LBZ is meant to be used for industrial 1042 + * applications and the tap/double tap, free fall and tilt engines were 1043 + * removed. Rest of the registers and functionalities (excluding the ID 1044 + * register) are exact match to what is found in KX022. 1045 + */ 1046 + const struct kx022a_chip_info kx132acr_chip_info = { 1047 + .name = "kx132acr-lbz", 1048 + .regmap_config = &kx022a_regmap_config, 1049 + .channels = kx022a_channels, 1050 + .num_channels = ARRAY_SIZE(kx022a_channels), 1051 + .fifo_length = KX022A_FIFO_LENGTH, 1052 + .who = KX022A_REG_WHO, 1053 + .id = KX132ACR_LBZ_ID, 1054 + .cntl = KX022A_REG_CNTL, 1055 + .cntl2 = KX022A_REG_CNTL2, 1056 + .odcntl = KX022A_REG_ODCNTL, 1057 + .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1058 + .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1059 + .buf_clear = KX022A_REG_BUF_CLEAR, 1060 + .buf_status1 = KX022A_REG_BUF_STATUS_1, 1061 + .buf_read = KX022A_REG_BUF_READ, 1062 + .inc1 = KX022A_REG_INC1, 1063 + .inc4 = KX022A_REG_INC4, 1064 + .inc5 = KX022A_REG_INC5, 1065 + .inc6 = KX022A_REG_INC6, 1066 + .xout_l = KX022A_REG_XOUT_L, 1067 + .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1068 + }; 1069 + EXPORT_SYMBOL_NS_GPL(kx132acr_chip_info, IIO_KX022A); 1070 + 1071 + int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info) 1141 1072 { 1142 1073 static const char * const regulator_names[] = {"io-vdd", "vdd"}; 1143 1074 struct iio_trigger *indio_trig; ··· 1247 1012 return -ENOMEM; 1248 1013 1249 1014 data = iio_priv(idev); 1015 + data->chip_info = chip_info; 1250 1016 1251 1017 /* 1252 1018 * VDD is the analog and digital domain voltage supply and ··· 1258 1022 if (ret && ret != -ENODEV) 1259 1023 return dev_err_probe(dev, ret, "failed to enable regulator\n"); 1260 1024 1261 - ret = regmap_read(regmap, KX022A_REG_WHO, &chip_id); 1025 + ret = regmap_read(regmap, chip_info->who, &chip_id); 1262 1026 if (ret) 1263 1027 return dev_err_probe(dev, ret, "Failed to access sensor\n"); 1264 1028 1265 - if (chip_id != KX022A_ID) { 1266 - dev_err(dev, "unsupported device 0x%x\n", chip_id); 1267 - return -EINVAL; 1268 - } 1029 + if (chip_id != chip_info->id) 1030 + dev_warn(dev, "unknown device 0x%x\n", chip_id); 1269 1031 1270 1032 irq = fwnode_irq_get_byname(fwnode, "INT1"); 1271 1033 if (irq > 0) { 1272 - data->inc_reg = KX022A_REG_INC1; 1273 - data->ien_reg = KX022A_REG_INC4; 1034 + data->inc_reg = chip_info->inc1; 1035 + data->ien_reg = chip_info->inc4; 1274 1036 } else { 1275 1037 irq = fwnode_irq_get_byname(fwnode, "INT2"); 1276 1038 if (irq < 0) 1277 1039 return dev_err_probe(dev, irq, "No suitable IRQ\n"); 1278 1040 1279 - data->inc_reg = KX022A_REG_INC5; 1280 - data->ien_reg = KX022A_REG_INC6; 1041 + data->inc_reg = chip_info->inc5; 1042 + data->ien_reg = chip_info->inc6; 1281 1043 } 1282 1044 1283 1045 data->regmap = regmap; ··· 1284 1050 data->odr_ns = KX022A_DEFAULT_PERIOD_NS; 1285 1051 mutex_init(&data->mutex); 1286 1052 1287 - idev->channels = kx022a_channels; 1288 - idev->num_channels = ARRAY_SIZE(kx022a_channels); 1289 - idev->name = "kx022-accel"; 1053 + idev->channels = chip_info->channels; 1054 + idev->num_channels = chip_info->num_channels; 1055 + idev->name = chip_info->name; 1290 1056 idev->info = &kx022a_info; 1291 1057 idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1292 1058 idev->available_scan_masks = kx022a_scan_masks; ··· 1343 1109 IRQF_ONESHOT, name, idev); 1344 1110 if (ret) 1345 1111 return dev_err_probe(data->dev, ret, "Could not request IRQ\n"); 1346 - 1347 1112 1348 1113 ret = devm_iio_trigger_register(dev, indio_trig); 1349 1114 if (ret)

+112 -2

drivers/iio/accel/kionix-kx022a.h

··· 13 13 14 14 #define KX022A_REG_WHO 0x0f 15 15 #define KX022A_ID 0xc8 16 + #define KX132ACR_LBZ_ID 0xd8 16 17 17 18 #define KX022A_REG_CNTL2 0x19 18 19 #define KX022A_MASK_SRST BIT(7) ··· 75 74 #define KX022A_REG_SELF_TEST 0x60 76 75 #define KX022A_MAX_REGISTER 0x60 77 76 77 + #define KX132_REG_WHO 0x13 78 + #define KX132_ID 0x3d 79 + 80 + #define KX132_FIFO_LENGTH 86 81 + 82 + #define KX132_REG_CNTL 0x1b 83 + #define KX132_REG_CNTL2 0x1c 84 + #define KX132_REG_CNTL5 0x1f 85 + #define KX132_MASK_RES BIT(6) 86 + #define KX132_GSEL_2 0x0 87 + #define KX132_GSEL_4 BIT(3) 88 + #define KX132_GSEL_8 BIT(4) 89 + #define KX132_GSEL_16 GENMASK(4, 3) 90 + 91 + #define KX132_REG_INS2 0x17 92 + #define KX132_MASK_INS2_WMI BIT(5) 93 + 94 + #define KX132_REG_XADP_L 0x02 95 + #define KX132_REG_XOUT_L 0x08 96 + #define KX132_REG_YOUT_L 0x0a 97 + #define KX132_REG_ZOUT_L 0x0c 98 + #define KX132_REG_COTR 0x12 99 + #define KX132_REG_TSCP 0x14 100 + #define KX132_REG_INT_REL 0x1a 101 + 102 + #define KX132_REG_ODCNTL 0x21 103 + 104 + #define KX132_REG_BTS_WUF_TH 0x4a 105 + 106 + #define KX132_REG_BUF_CNTL1 0x5e 107 + #define KX132_REG_BUF_CNTL2 0x5f 108 + #define KX132_REG_BUF_STATUS_1 0x60 109 + #define KX132_REG_BUF_STATUS_2 0x61 110 + #define KX132_MASK_BUF_SMP_LVL GENMASK(9, 0) 111 + #define KX132_REG_BUF_CLEAR 0x62 112 + #define KX132_REG_BUF_READ 0x63 113 + #define KX132_ODR_SHIFT 3 114 + #define KX132_FIFO_MAX_WMI_TH 86 115 + 116 + #define KX132_REG_INC1 0x22 117 + #define KX132_REG_INC5 0x26 118 + #define KX132_REG_INC6 0x27 119 + #define KX132_IPOL_LOW 0 120 + #define KX132_IPOL_HIGH KX022A_MASK_IPOL 121 + #define KX132_ITYP_PULSE KX022A_MASK_ITYP 122 + 123 + #define KX132_REG_INC4 0x25 124 + 125 + #define KX132_REG_SELF_TEST 0x5d 126 + #define KX132_MAX_REGISTER 0x76 127 + 78 128 struct device; 79 129 80 - int kx022a_probe_internal(struct device *dev); 81 - extern const struct regmap_config kx022a_regmap; 130 + struct kx022a_data; 131 + 132 + /** 133 + * struct kx022a_chip_info - Kionix accelerometer chip specific information 134 + * 135 + * @name: name of the device 136 + * @regmap_config: pointer to register map configuration 137 + * @channels: pointer to iio_chan_spec array 138 + * @num_channels: number of iio_chan_spec channels 139 + * @fifo_length: number of 16-bit samples in a full buffer 140 + * @buf_smp_lvl_mask: buffer sample level mask 141 + * @who: WHO_AM_I register 142 + * @id: WHO_AM_I register value 143 + * @cntl: control register 1 144 + * @cntl2: control register 2 145 + * @odcntl: output data control register 146 + * @buf_cntl1: buffer control register 1 147 + * @buf_cntl2: buffer control register 2 148 + * @buf_clear: buffer clear register 149 + * @buf_status1: buffer status register 1 150 + * @buf_read: buffer read register 151 + * @inc1: interrupt control register 1 152 + * @inc4: interrupt control register 4 153 + * @inc5: interrupt control register 5 154 + * @inc6: interrupt control register 6 155 + * @xout_l: x-axis output least significant byte 156 + * @get_fifo_bytes_available: function pointer to get amount of acceleration 157 + * data bytes currently stored in the sensor's FIFO 158 + * buffer 159 + */ 160 + struct kx022a_chip_info { 161 + const char *name; 162 + const struct regmap_config *regmap_config; 163 + const struct iio_chan_spec *channels; 164 + unsigned int num_channels; 165 + unsigned int fifo_length; 166 + u16 buf_smp_lvl_mask; 167 + u8 who; 168 + u8 id; 169 + u8 cntl; 170 + u8 cntl2; 171 + u8 odcntl; 172 + u8 buf_cntl1; 173 + u8 buf_cntl2; 174 + u8 buf_clear; 175 + u8 buf_status1; 176 + u8 buf_read; 177 + u8 inc1; 178 + u8 inc4; 179 + u8 inc5; 180 + u8 inc6; 181 + u8 xout_l; 182 + int (*get_fifo_bytes_available)(struct kx022a_data *); 183 + }; 184 + 185 + int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info); 186 + 187 + extern const struct kx022a_chip_info kx022a_chip_info; 188 + extern const struct kx022a_chip_info kx132_chip_info; 189 + extern const struct kx022a_chip_info kx132acr_chip_info; 82 190 83 191 #endif

+11 -17

drivers/iio/accel/mma8452.c

··· 1535 1535 } 1536 1536 1537 1537 static const struct of_device_id mma8452_dt_ids[] = { 1538 + { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1538 1539 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1539 1540 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1540 1541 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1541 1542 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1542 1543 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1543 - { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1544 1544 { } 1545 1545 }; 1546 1546 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1547 1547 1548 1548 static int mma8452_probe(struct i2c_client *client) 1549 1549 { 1550 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 1551 1550 struct mma8452_data *data; 1552 1551 struct iio_dev *indio_dev; 1553 1552 int ret; ··· 1559 1560 data->client = client; 1560 1561 mutex_init(&data->lock); 1561 1562 1562 - data->chip_info = device_get_match_data(&client->dev); 1563 - if (!data->chip_info) { 1564 - if (id) { 1565 - data->chip_info = &mma_chip_info_table[id->driver_data]; 1566 - } else { 1567 - dev_err(&client->dev, "unknown device model\n"); 1568 - return -ENODEV; 1569 - } 1570 - } 1563 + data->chip_info = i2c_get_match_data(client); 1564 + if (!data->chip_info) 1565 + return dev_err_probe(&client->dev, -ENODEV, 1566 + "unknown device model\n"); 1571 1567 1572 1568 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 1573 1569 if (ret) ··· 1824 1830 }; 1825 1831 1826 1832 static const struct i2c_device_id mma8452_id[] = { 1827 - { "mma8451", mma8451 }, 1828 - { "mma8452", mma8452 }, 1829 - { "mma8453", mma8453 }, 1830 - { "mma8652", mma8652 }, 1831 - { "mma8653", mma8653 }, 1832 - { "fxls8471", fxls8471 }, 1833 + { "fxls8471", (kernel_ulong_t)&mma_chip_info_table[fxls8471] }, 1834 + { "mma8451", (kernel_ulong_t)&mma_chip_info_table[mma8451] }, 1835 + { "mma8452", (kernel_ulong_t)&mma_chip_info_table[mma8452] }, 1836 + { "mma8453", (kernel_ulong_t)&mma_chip_info_table[mma8453] }, 1837 + { "mma8652", (kernel_ulong_t)&mma_chip_info_table[mma8652] }, 1838 + { "mma8653", (kernel_ulong_t)&mma_chip_info_table[mma8653] }, 1833 1839 { } 1834 1840 }; 1835 1841 MODULE_DEVICE_TABLE(i2c, mma8452_id);

+1 -1

drivers/iio/accel/msa311.c

··· 33 33 #include <linux/pm.h> 34 34 #include <linux/pm_runtime.h> 35 35 #include <linux/regmap.h> 36 - #include <linux/string_helpers.h> 36 + #include <linux/string_choices.h> 37 37 #include <linux/units.h> 38 38 39 39 #include <linux/iio/buffer.h>

+8

drivers/iio/accel/mxc4005.c

··· 476 476 }; 477 477 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match); 478 478 479 + static const struct of_device_id mxc4005_of_match[] = { 480 + { .compatible = "memsic,mxc4005", }, 481 + { .compatible = "memsic,mxc6655", }, 482 + { }, 483 + }; 484 + MODULE_DEVICE_TABLE(of, mxc4005_of_match); 485 + 479 486 static const struct i2c_device_id mxc4005_id[] = { 480 487 {"mxc4005", 0}, 481 488 {"mxc6655", 0}, ··· 494 487 .driver = { 495 488 .name = MXC4005_DRV_NAME, 496 489 .acpi_match_table = ACPI_PTR(mxc4005_acpi_match), 490 + .of_match_table = mxc4005_of_match, 497 491 }, 498 492 .probe = mxc4005_probe, 499 493 .id_table = mxc4005_id,

+27 -2

drivers/iio/adc/Kconfig

··· 607 607 activate only one via device tree selection. Provides direct access 608 608 via sysfs. 609 609 610 + config LTC2309 611 + tristate "Linear Technology LTC2309 ADC driver" 612 + depends on I2C 613 + help 614 + Say yes here to build support for Linear Technology LTC2309, a low 615 + noise, low power, 8-channel, 12-bit SAR ADC 616 + 617 + This driver can also be built as a module. If so, the module will 618 + be called ltc2309. 619 + 610 620 config LTC2471 611 621 tristate "Linear Technology LTC2471 and LTC2473 ADC driver" 612 622 depends on I2C ··· 789 779 This driver can also be built as a module. If so, the module will be 790 780 called mcp3422. 791 781 782 + config MCP3564 783 + tristate "Microchip Technology MCP3461/2/4/R, MCP3561/2/4/R driver" 784 + depends on SPI 785 + depends on IIO 786 + help 787 + Say yes here to build support for Microchip Technology's MCP3461, 788 + MCP3462, MCP3464, MCP3461R, MCP3462R, MCP3464R, MCP3561, MCP3562, 789 + MCP3564, MCP3561R, MCP3562R and MCP3564R analog to digital 790 + converters. 791 + 792 + This driver can also be built as a module. If so, the module will be 793 + called mcp3564. 794 + 792 795 config MCP3911 793 796 tristate "Microchip Technology MCP3911 driver" 794 797 depends on SPI 795 798 select IIO_BUFFER 796 799 select IIO_TRIGGERED_BUFFER 797 800 help 798 - Say yes here to build support for Microchip Technology's MCP3911 799 - analog to digital converter. 801 + Say yes here to build support for one of the following 802 + Microchip Technology's analog to digital converters: 803 + MCP3910, MCP3911, MCP3912, MCP3913, MCP3914, 804 + MCP3918 and MCP3919. 800 805 801 806 This driver can also be built as a module. If so, the module will be 802 807 called mcp3911.

+2

drivers/iio/adc/Makefile

··· 56 56 obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o 57 57 obj-$(CONFIG_LPC18XX_ADC) += lpc18xx_adc.o 58 58 obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o 59 + obj-$(CONFIG_LTC2309) += ltc2309.o 59 60 obj-$(CONFIG_LTC2471) += ltc2471.o 60 61 obj-$(CONFIG_LTC2485) += ltc2485.o 61 62 obj-$(CONFIG_LTC2496) += ltc2496.o ltc2497-core.o ··· 72 71 obj-$(CONFIG_MAX9611) += max9611.o 73 72 obj-$(CONFIG_MCP320X) += mcp320x.o 74 73 obj-$(CONFIG_MCP3422) += mcp3422.o 74 + obj-$(CONFIG_MCP3564) += mcp3564.o 75 75 obj-$(CONFIG_MCP3911) += mcp3911.o 76 76 obj-$(CONFIG_MEDIATEK_MT6360_ADC) += mt6360-adc.o 77 77 obj-$(CONFIG_MEDIATEK_MT6370_ADC) += mt6370-adc.o

+2 -4

drivers/iio/adc/ab8500-gpadc.c

··· 1179 1179 return ret; 1180 1180 } 1181 1181 1182 - static int ab8500_gpadc_remove(struct platform_device *pdev) 1182 + static void ab8500_gpadc_remove(struct platform_device *pdev) 1183 1183 { 1184 1184 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1185 1185 struct ab8500_gpadc *gpadc = iio_priv(indio_dev); ··· 1188 1188 pm_runtime_put_noidle(gpadc->dev); 1189 1189 pm_runtime_disable(gpadc->dev); 1190 1190 regulator_disable(gpadc->vddadc); 1191 - 1192 - return 0; 1193 1191 } 1194 1192 1195 1193 static DEFINE_RUNTIME_DEV_PM_OPS(ab8500_gpadc_pm_ops, ··· 1196 1198 1197 1199 static struct platform_driver ab8500_gpadc_driver = { 1198 1200 .probe = ab8500_gpadc_probe, 1199 - .remove = ab8500_gpadc_remove, 1201 + .remove_new = ab8500_gpadc_remove, 1200 1202 .driver = { 1201 1203 .name = "ab8500-gpadc", 1202 1204 .pm = pm_ptr(&ab8500_gpadc_pm_ops),

+3 -12

drivers/iio/adc/ad4130.c

··· 1817 1817 .unprepare = ad4130_int_clk_unprepare, 1818 1818 }; 1819 1819 1820 - static void ad4130_clk_del_provider(void *of_node) 1821 - { 1822 - of_clk_del_provider(of_node); 1823 - } 1824 - 1825 1820 static int ad4130_setup_int_clk(struct ad4130_state *st) 1826 1821 { 1827 1822 struct device *dev = &st->spi->dev; 1828 1823 struct device_node *of_node = dev_of_node(dev); 1829 1824 struct clk_init_data init; 1830 1825 const char *clk_name; 1831 - struct clk *clk; 1832 1826 int ret; 1833 1827 1834 1828 if (st->int_pin_sel == AD4130_INT_PIN_CLK || ··· 1839 1845 init.ops = &ad4130_int_clk_ops; 1840 1846 1841 1847 st->int_clk_hw.init = &init; 1842 - clk = devm_clk_register(dev, &st->int_clk_hw); 1843 - if (IS_ERR(clk)) 1844 - return PTR_ERR(clk); 1845 - 1846 - ret = of_clk_add_provider(of_node, of_clk_src_simple_get, clk); 1848 + ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1847 1849 if (ret) 1848 1850 return ret; 1849 1851 1850 - return devm_add_action_or_reset(dev, ad4130_clk_del_provider, of_node); 1852 + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1853 + &st->int_clk_hw); 1851 1854 } 1852 1855 1853 1856 static int ad4130_setup(struct iio_dev *indio_dev)

+172 -97

drivers/iio/adc/ad7192.c

··· 6 6 */ 7 7 8 8 #include <linux/interrupt.h> 9 + #include <linux/bitfield.h> 9 10 #include <linux/clk.h> 10 11 #include <linux/device.h> 11 12 #include <linux/kernel.h> ··· 44 43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 45 44 #define AD7192_COMM_WRITE 0 /* Write Operation */ 46 45 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 47 - #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 46 + #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */ 48 47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 49 48 50 49 /* Status Register Bit Designations (AD7192_REG_STAT) */ ··· 57 56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 58 57 59 58 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 60 - #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ 61 - #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ 62 - #define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */ 59 + #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */ 63 60 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ 64 - #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 61 + #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */ 62 + #define AD7192_MODE_AVG_MASK GENMASK(17, 16) 63 + /* Fast Settling Filter Average Select Mask (AD7193 only) */ 65 64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 66 65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 67 66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 68 67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 69 68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 70 - #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ 69 + /* Filter Update Rate Select Mask */ 70 + #define AD7192_MODE_RATE_MASK GENMASK(9, 0) 71 71 72 72 /* Mode Register: AD7192_MODE_SEL options */ 73 73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ ··· 94 92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 95 93 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */ 96 94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 97 - #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */ 98 - #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */ 95 + #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */ 99 96 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 100 97 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 101 98 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 102 99 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 103 - #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ 100 + #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */ 104 101 105 102 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 106 103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ ··· 131 130 #define CHIPID_AD7192 0x0 132 131 #define CHIPID_AD7193 0x2 133 132 #define CHIPID_AD7195 0x6 134 - #define AD7192_ID_MASK 0x0F 133 + #define AD7192_ID_MASK GENMASK(3, 0) 135 134 136 135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 137 136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ ··· 173 172 struct ad7192_chip_info { 174 173 unsigned int chip_id; 175 174 const char *name; 175 + const struct iio_chan_spec *channels; 176 + u8 num_channels; 177 + const struct iio_info *info; 176 178 }; 177 179 178 180 struct ad7192_state { ··· 185 181 struct clk *mclk; 186 182 u16 int_vref_mv; 187 183 u32 fclk; 188 - u32 f_order; 189 184 u32 mode; 190 185 u32 conf; 191 186 u32 scale_avail[8][2]; 187 + u32 oversampling_ratio_avail[4]; 192 188 u8 gpocon; 193 189 u8 clock_sel; 194 190 struct mutex lock; /* protect sensor state */ ··· 277 273 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 278 274 279 275 st->conf &= ~AD7192_CONF_CHAN_MASK; 280 - st->conf |= AD7192_CONF_CHAN(channel); 276 + st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); 281 277 282 278 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 283 279 } ··· 288 284 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 289 285 290 286 st->mode &= ~AD7192_MODE_SEL_MASK; 291 - st->mode |= AD7192_MODE_SEL(mode); 287 + st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); 292 288 293 289 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 294 290 } ··· 300 296 int ret; 301 297 302 298 mode &= ~AD7192_MODE_STA_MASK; 303 - mode |= AD7192_MODE_STA(append); 299 + mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append); 304 300 305 301 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); 306 302 if (ret < 0) ··· 404 400 if (ret) 405 401 return ret; 406 402 407 - id &= AD7192_ID_MASK; 403 + id = FIELD_GET(AD7192_ID_MASK, id); 408 404 409 405 if (id != st->chip_info->chip_id) 410 406 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n", 411 407 id, st->chip_info->chip_id); 412 408 413 - st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | 414 - AD7192_MODE_CLKSRC(st->clock_sel) | 415 - AD7192_MODE_RATE(480); 409 + st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | 410 + FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | 411 + FIELD_PREP(AD7192_MODE_RATE_MASK, 480); 416 412 417 - st->conf = AD7192_CONF_GAIN(0); 413 + st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); 418 414 419 415 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable"); 420 416 if (rej60_en) ··· 425 421 st->conf |= AD7192_CONF_REFSEL; 426 422 427 423 st->conf &= ~AD7192_CONF_CHOP; 428 - st->f_order = AD7192_NO_SYNC_FILTER; 429 424 430 425 buf_en = of_property_read_bool(np, "adi,buffer-enable"); 431 426 if (buf_en) ··· 459 456 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 460 457 scale_uv = ((u64)st->int_vref_mv * 100000000) 461 458 >> (indio_dev->channels[0].scan_type.realbits - 462 - ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); 459 + !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); 463 460 scale_uv >>= i; 464 461 465 462 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 466 463 st->scale_avail[i][0] = scale_uv; 467 464 } 465 + 466 + st->oversampling_ratio_avail[0] = 1; 467 + st->oversampling_ratio_avail[1] = 2; 468 + st->oversampling_ratio_avail[2] = 8; 469 + st->oversampling_ratio_avail[3] = 16; 468 470 469 471 return 0; 470 472 } ··· 481 473 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 482 474 struct ad7192_state *st = iio_priv(indio_dev); 483 475 484 - return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX)); 476 + return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); 485 477 } 486 478 487 479 static ssize_t ad7192_show_bridge_switch(struct device *dev, ··· 491 483 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 492 484 struct ad7192_state *st = iio_priv(indio_dev); 493 485 494 - return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); 486 + return sysfs_emit(buf, "%ld\n", 487 + FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); 495 488 } 496 489 497 490 static ssize_t ad7192_set(struct device *dev, ··· 540 531 return ret ? ret : len; 541 532 } 542 533 534 + static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) 535 + { 536 + u8 avg_factor_selected, oversampling_ratio; 537 + 538 + avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); 539 + 540 + if (!avg_factor_selected && !chop_en) 541 + return 1; 542 + 543 + oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; 544 + 545 + if (sinc3_en) 546 + return AD7192_SYNC3_FILTER + oversampling_ratio - 1; 547 + 548 + return AD7192_SYNC4_FILTER + oversampling_ratio - 1; 549 + } 550 + 551 + static int ad7192_get_f_order(struct ad7192_state *st) 552 + { 553 + bool sinc3_en, chop_en; 554 + 555 + sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); 556 + chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); 557 + 558 + return ad7192_compute_f_order(st, sinc3_en, chop_en); 559 + } 560 + 561 + static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, 562 + bool chop_en) 563 + { 564 + unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); 565 + 566 + return DIV_ROUND_CLOSEST(st->fclk, 567 + f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 568 + } 569 + 570 + static int ad7192_get_f_adc(struct ad7192_state *st) 571 + { 572 + unsigned int f_order = ad7192_get_f_order(st); 573 + 574 + return DIV_ROUND_CLOSEST(st->fclk, 575 + f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 576 + } 577 + 543 578 static void ad7192_get_available_filter_freq(struct ad7192_state *st, 544 579 int *freq) 545 580 { 546 581 unsigned int fadc; 547 582 548 583 /* Formulas for filter at page 25 of the datasheet */ 549 - fadc = DIV_ROUND_CLOSEST(st->fclk, 550 - AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); 584 + fadc = ad7192_compute_f_adc(st, false, true); 551 585 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 552 586 553 - fadc = DIV_ROUND_CLOSEST(st->fclk, 554 - AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); 587 + fadc = ad7192_compute_f_adc(st, true, true); 555 588 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 556 589 557 - fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); 590 + fadc = ad7192_compute_f_adc(st, false, false); 558 591 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 592 + 593 + fadc = ad7192_compute_f_adc(st, true, false); 559 594 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 560 595 } 561 596 ··· 682 629 683 630 switch (idx) { 684 631 case 0: 685 - st->f_order = AD7192_SYNC4_FILTER; 686 632 st->mode &= ~AD7192_MODE_SINC3; 687 633 688 634 st->conf |= AD7192_CONF_CHOP; 689 635 break; 690 636 case 1: 691 - st->f_order = AD7192_SYNC3_FILTER; 692 637 st->mode |= AD7192_MODE_SINC3; 693 638 694 639 st->conf |= AD7192_CONF_CHOP; 695 640 break; 696 641 case 2: 697 - st->f_order = AD7192_NO_SYNC_FILTER; 698 642 st->mode &= ~AD7192_MODE_SINC3; 699 643 700 644 st->conf &= ~AD7192_CONF_CHOP; 701 645 break; 702 646 case 3: 703 - st->f_order = AD7192_NO_SYNC_FILTER; 704 647 st->mode |= AD7192_MODE_SINC3; 705 648 706 649 st->conf &= ~AD7192_CONF_CHOP; ··· 714 665 { 715 666 unsigned int fadc; 716 667 717 - fadc = DIV_ROUND_CLOSEST(st->fclk, 718 - st->f_order * AD7192_MODE_RATE(st->mode)); 668 + fadc = ad7192_get_f_adc(st); 719 669 720 - if (st->conf & AD7192_CONF_CHOP) 670 + if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) 721 671 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 722 - if (st->mode & AD7192_MODE_SINC3) 672 + if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) 723 673 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 724 674 else 725 675 return DIV_ROUND_CLOSEST(fadc * 230, 1024); ··· 731 683 long m) 732 684 { 733 685 struct ad7192_state *st = iio_priv(indio_dev); 734 - bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); 686 + bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); 687 + u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); 735 688 736 689 switch (m) { 737 690 case IIO_CHAN_INFO_RAW: ··· 741 692 switch (chan->type) { 742 693 case IIO_VOLTAGE: 743 694 mutex_lock(&st->lock); 744 - *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; 745 - *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; 695 + *val = st->scale_avail[gain][0]; 696 + *val2 = st->scale_avail[gain][1]; 746 697 mutex_unlock(&st->lock); 747 698 return IIO_VAL_INT_PLUS_NANO; 748 699 case IIO_TEMP: ··· 762 713 *val -= 273 * ad7192_get_temp_scale(unipolar); 763 714 return IIO_VAL_INT; 764 715 case IIO_CHAN_INFO_SAMP_FREQ: 765 - *val = st->fclk / 766 - (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); 716 + *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); 767 717 return IIO_VAL_INT; 768 718 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 769 719 *val = ad7192_get_3db_filter_freq(st); 770 720 *val2 = 1000; 771 721 return IIO_VAL_FRACTIONAL; 722 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 723 + *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; 724 + return IIO_VAL_INT; 772 725 } 773 726 774 727 return -EINVAL; ··· 798 747 if (val2 == st->scale_avail[i][1]) { 799 748 ret = 0; 800 749 tmp = st->conf; 801 - st->conf &= ~AD7192_CONF_GAIN(-1); 802 - st->conf |= AD7192_CONF_GAIN(i); 750 + st->conf &= ~AD7192_CONF_GAIN_MASK; 751 + st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); 803 752 if (tmp == st->conf) 804 753 break; 805 754 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, ··· 815 764 break; 816 765 } 817 766 818 - div = st->fclk / (val * st->f_order * 1024); 767 + div = st->fclk / (val * ad7192_get_f_order(st) * 1024); 819 768 if (div < 1 || div > 1023) { 820 769 ret = -EINVAL; 821 770 break; 822 771 } 823 772 824 - st->mode &= ~AD7192_MODE_RATE(-1); 825 - st->mode |= AD7192_MODE_RATE(div); 773 + st->mode &= ~AD7192_MODE_RATE_MASK; 774 + st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); 826 775 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 827 776 break; 828 777 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 829 778 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); 779 + break; 780 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 781 + ret = -EINVAL; 782 + mutex_lock(&st->lock); 783 + for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) 784 + if (val == st->oversampling_ratio_avail[i]) { 785 + ret = 0; 786 + tmp = st->mode; 787 + st->mode &= ~AD7192_MODE_AVG_MASK; 788 + st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); 789 + if (tmp == st->mode) 790 + break; 791 + ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 792 + 3, st->mode); 793 + break; 794 + } 795 + mutex_unlock(&st->lock); 830 796 break; 831 797 default: 832 798 ret = -EINVAL; ··· 865 797 return IIO_VAL_INT; 866 798 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 867 799 return IIO_VAL_INT_PLUS_MICRO; 800 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 801 + return IIO_VAL_INT; 868 802 default: 869 803 return -EINVAL; 870 804 } ··· 887 817 *length = ARRAY_SIZE(st->scale_avail) * 2; 888 818 889 819 return IIO_AVAIL_LIST; 820 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 821 + *vals = (int *)st->oversampling_ratio_avail; 822 + *type = IIO_VAL_INT; 823 + *length = ARRAY_SIZE(st->oversampling_ratio_avail); 824 + 825 + return IIO_AVAIL_LIST; 890 826 } 891 827 892 828 return -EINVAL; ··· 907 831 908 832 conf &= ~AD7192_CONF_CHAN_MASK; 909 833 for_each_set_bit(i, scan_mask, 8) 910 - conf |= AD7192_CONF_CHAN(i); 834 + conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, i); 911 835 912 836 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 913 837 if (ret < 0) ··· 938 862 .update_scan_mode = ad7192_update_scan_mode, 939 863 }; 940 864 941 - #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \ 942 - _type, _mask_type_av, _ext_info) \ 865 + #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \ 866 + _mask_all, _mask_type_av, _mask_all_av, _ext_info) \ 943 867 { \ 944 868 .type = (_type), \ 945 869 .differential = ((_channel2) == -1 ? 0 : 1), \ ··· 947 871 .channel = (_channel1), \ 948 872 .channel2 = (_channel2), \ 949 873 .address = (_address), \ 950 - .extend_name = (_extend_name), \ 951 874 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 952 875 BIT(IIO_CHAN_INFO_OFFSET), \ 953 876 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 954 877 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 955 - BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 878 + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 879 + (_mask_all), \ 956 880 .info_mask_shared_by_type_available = (_mask_type_av), \ 881 + .info_mask_shared_by_all_available = (_mask_all_av), \ 957 882 .ext_info = (_ext_info), \ 958 883 .scan_index = (_si), \ 959 884 .scan_type = { \ ··· 966 889 } 967 890 968 891 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 969 - __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \ 970 - IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \ 971 - ad7192_calibsys_ext_info) 892 + __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \ 893 + BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 972 894 973 895 #define AD719x_CHANNEL(_si, _channel1, _address) \ 974 - __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \ 975 - BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 896 + __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \ 897 + BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 976 898 977 899 #define AD719x_TEMP_CHANNEL(_si, _address) \ 978 - __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL) 900 + __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL) 901 + 902 + #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 903 + __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \ 904 + IIO_VOLTAGE, \ 905 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 906 + BIT(IIO_CHAN_INFO_SCALE), \ 907 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 908 + ad7192_calibsys_ext_info) 909 + 910 + #define AD7193_CHANNEL(_si, _channel1, _address) \ 911 + AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address) 979 912 980 913 static const struct iio_chan_spec ad7192_channels[] = { 981 914 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), ··· 1000 913 }; 1001 914 1002 915 static const struct iio_chan_spec ad7193_channels[] = { 1003 - AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 1004 - AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 1005 - AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 1006 - AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 916 + AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 917 + AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 918 + AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 919 + AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 1007 920 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 1008 - AD719x_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), 1009 - AD719x_CHANNEL(6, 1, AD7193_CH_AIN1), 1010 - AD719x_CHANNEL(7, 2, AD7193_CH_AIN2), 1011 - AD719x_CHANNEL(8, 3, AD7193_CH_AIN3), 1012 - AD719x_CHANNEL(9, 4, AD7193_CH_AIN4), 1013 - AD719x_CHANNEL(10, 5, AD7193_CH_AIN5), 1014 - AD719x_CHANNEL(11, 6, AD7193_CH_AIN6), 1015 - AD719x_CHANNEL(12, 7, AD7193_CH_AIN7), 1016 - AD719x_CHANNEL(13, 8, AD7193_CH_AIN8), 921 + AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), 922 + AD7193_CHANNEL(6, 1, AD7193_CH_AIN1), 923 + AD7193_CHANNEL(7, 2, AD7193_CH_AIN2), 924 + AD7193_CHANNEL(8, 3, AD7193_CH_AIN3), 925 + AD7193_CHANNEL(9, 4, AD7193_CH_AIN4), 926 + AD7193_CHANNEL(10, 5, AD7193_CH_AIN5), 927 + AD7193_CHANNEL(11, 6, AD7193_CH_AIN6), 928 + AD7193_CHANNEL(12, 7, AD7193_CH_AIN7), 929 + AD7193_CHANNEL(13, 8, AD7193_CH_AIN8), 1017 930 IIO_CHAN_SOFT_TIMESTAMP(14), 1018 931 }; 1019 932 ··· 1021 934 [ID_AD7190] = { 1022 935 .chip_id = CHIPID_AD7190, 1023 936 .name = "ad7190", 937 + .channels = ad7192_channels, 938 + .num_channels = ARRAY_SIZE(ad7192_channels), 939 + .info = &ad7192_info, 1024 940 }, 1025 941 [ID_AD7192] = { 1026 942 .chip_id = CHIPID_AD7192, 1027 943 .name = "ad7192", 944 + .channels = ad7192_channels, 945 + .num_channels = ARRAY_SIZE(ad7192_channels), 946 + .info = &ad7192_info, 1028 947 }, 1029 948 [ID_AD7193] = { 1030 949 .chip_id = CHIPID_AD7193, 1031 950 .name = "ad7193", 951 + .channels = ad7193_channels, 952 + .num_channels = ARRAY_SIZE(ad7193_channels), 953 + .info = &ad7192_info, 1032 954 }, 1033 955 [ID_AD7195] = { 1034 956 .chip_id = CHIPID_AD7195, 1035 957 .name = "ad7195", 958 + .channels = ad7192_channels, 959 + .num_channels = ARRAY_SIZE(ad7192_channels), 960 + .info = &ad7195_info, 1036 961 }, 1037 962 }; 1038 - 1039 - static int ad7192_channels_config(struct iio_dev *indio_dev) 1040 - { 1041 - struct ad7192_state *st = iio_priv(indio_dev); 1042 - 1043 - switch (st->chip_info->chip_id) { 1044 - case CHIPID_AD7193: 1045 - indio_dev->channels = ad7193_channels; 1046 - indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); 1047 - break; 1048 - default: 1049 - indio_dev->channels = ad7192_channels; 1050 - indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); 1051 - break; 1052 - } 1053 - 1054 - return 0; 1055 - } 1056 963 1057 964 static void ad7192_reg_disable(void *reg) 1058 965 { ··· 1122 1041 st->chip_info = (void *)spi_get_device_id(spi)->driver_data; 1123 1042 indio_dev->name = st->chip_info->name; 1124 1043 indio_dev->modes = INDIO_DIRECT_MODE; 1125 - 1126 - ret = ad7192_channels_config(indio_dev); 1127 - if (ret < 0) 1128 - return ret; 1129 - 1130 - if (st->chip_info->chip_id == CHIPID_AD7195) 1131 - indio_dev->info = &ad7195_info; 1132 - else 1133 - indio_dev->info = &ad7192_info; 1044 + indio_dev->channels = st->chip_info->channels; 1045 + indio_dev->num_channels = st->chip_info->num_channels; 1046 + indio_dev->info = st->chip_info->info; 1134 1047 1135 1048 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); 1136 1049 if (ret)

+2 -4

drivers/iio/adc/at91-sama5d2_adc.c

··· 2486 2486 return ret; 2487 2487 } 2488 2488 2489 - static int at91_adc_remove(struct platform_device *pdev) 2489 + static void at91_adc_remove(struct platform_device *pdev) 2490 2490 { 2491 2491 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2492 2492 struct at91_adc_state *st = iio_priv(indio_dev); ··· 2501 2501 2502 2502 regulator_disable(st->vref); 2503 2503 regulator_disable(st->reg); 2504 - 2505 - return 0; 2506 2504 } 2507 2505 2508 2506 static int at91_adc_suspend(struct device *dev) ··· 2625 2627 2626 2628 static struct platform_driver at91_adc_driver = { 2627 2629 .probe = at91_adc_probe, 2628 - .remove = at91_adc_remove, 2630 + .remove_new = at91_adc_remove, 2629 2631 .driver = { 2630 2632 .name = "at91-sama5d2_adc", 2631 2633 .of_match_table = at91_adc_dt_match,

+39 -75

drivers/iio/adc/at91_adc.c

··· 1013 1013 1014 1014 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); 1015 1015 1016 - if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { 1017 - dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); 1018 - return -EINVAL; 1019 - } 1016 + if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) 1017 + return dev_err_probe(&idev->dev, -EINVAL, 1018 + "Missing adc-channels-used property in the DT.\n"); 1020 1019 st->channels_mask = prop; 1021 1020 1022 1021 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); 1023 1022 1024 - if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { 1025 - dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); 1026 - return -EINVAL; 1027 - } 1023 + if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) 1024 + return dev_err_probe(&idev->dev, -EINVAL, 1025 + "Missing adc-startup-time property in the DT.\n"); 1028 1026 st->startup_time = prop; 1029 1027 1030 1028 prop = 0; 1031 1029 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); 1032 1030 st->sample_hold_time = prop; 1033 1031 1034 - if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { 1035 - dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); 1036 - return -EINVAL; 1037 - } 1032 + if (of_property_read_u32(node, "atmel,adc-vref", &prop)) 1033 + return dev_err_probe(&idev->dev, -EINVAL, 1034 + "Missing adc-vref property in the DT.\n"); 1038 1035 st->vref_mv = prop; 1039 1036 1040 1037 st->res = st->caps->high_res_bits; ··· 1066 1069 if (IS_ERR(st->reg_base)) 1067 1070 return PTR_ERR(st->reg_base); 1068 1071 1069 - 1070 1072 /* 1071 1073 * Disable all IRQs before setting up the handler 1072 1074 */ ··· 1073 1077 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); 1074 1078 1075 1079 if (st->caps->has_tsmr) 1076 - ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, 1077 - pdev->dev.driver->name, idev); 1080 + ret = devm_request_irq(&pdev->dev, st->irq, 1081 + at91_adc_9x5_interrupt, 0, 1082 + pdev->dev.driver->name, idev); 1078 1083 else 1079 - ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, 1080 - pdev->dev.driver->name, idev); 1081 - if (ret) { 1082 - dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); 1083 - return ret; 1084 - } 1084 + ret = devm_request_irq(&pdev->dev, st->irq, 1085 + at91_adc_rl_interrupt, 0, 1086 + pdev->dev.driver->name, idev); 1087 + if (ret) 1088 + return dev_err_probe(&pdev->dev, ret, 1089 + "Failed to allocate IRQ.\n"); 1085 1090 1086 - st->clk = devm_clk_get(&pdev->dev, "adc_clk"); 1087 - if (IS_ERR(st->clk)) { 1088 - dev_err(&pdev->dev, "Failed to get the clock.\n"); 1089 - ret = PTR_ERR(st->clk); 1090 - goto error_free_irq; 1091 - } 1091 + st->clk = devm_clk_get_enabled(&pdev->dev, "adc_clk"); 1092 + if (IS_ERR(st->clk)) 1093 + return dev_err_probe(&pdev->dev, PTR_ERR(st->clk), 1094 + "Could not prepare or enable the clock.\n"); 1092 1095 1093 - ret = clk_prepare_enable(st->clk); 1094 - if (ret) { 1095 - dev_err(&pdev->dev, 1096 - "Could not prepare or enable the clock.\n"); 1097 - goto error_free_irq; 1098 - } 1099 - 1100 - st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); 1101 - if (IS_ERR(st->adc_clk)) { 1102 - dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); 1103 - ret = PTR_ERR(st->adc_clk); 1104 - goto error_disable_clk; 1105 - } 1106 - 1107 - ret = clk_prepare_enable(st->adc_clk); 1108 - if (ret) { 1109 - dev_err(&pdev->dev, 1110 - "Could not prepare or enable the ADC clock.\n"); 1111 - goto error_disable_clk; 1112 - } 1096 + st->adc_clk = devm_clk_get_enabled(&pdev->dev, "adc_op_clk"); 1097 + if (IS_ERR(st->adc_clk)) 1098 + return dev_err_probe(&pdev->dev, PTR_ERR(st->adc_clk), 1099 + "Could not prepare or enable the ADC clock.\n"); 1113 1100 1114 1101 /* 1115 1102 * Prescaler rate computation using the formula from the Atmel's ··· 1108 1129 1109 1130 prsc = (mstrclk / (2 * adc_clk)) - 1; 1110 1131 1111 - if (!st->startup_time) { 1112 - dev_err(&pdev->dev, "No startup time available.\n"); 1113 - ret = -EINVAL; 1114 - goto error_disable_adc_clk; 1115 - } 1132 + if (!st->startup_time) 1133 + return dev_err_probe(&pdev->dev, -EINVAL, 1134 + "No startup time available.\n"); 1116 1135 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); 1117 1136 1118 1137 /* ··· 1135 1158 1136 1159 /* Setup the ADC channels available on the board */ 1137 1160 ret = at91_adc_channel_init(idev); 1138 - if (ret < 0) { 1139 - dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); 1140 - goto error_disable_adc_clk; 1141 - } 1161 + if (ret < 0) 1162 + return dev_err_probe(&pdev->dev, ret, 1163 + "Couldn't initialize the channels.\n"); 1142 1164 1143 1165 init_waitqueue_head(&st->wq_data_avail); 1144 1166 mutex_init(&st->lock); ··· 1149 1173 */ 1150 1174 if (!st->touchscreen_type) { 1151 1175 ret = at91_adc_buffer_init(idev); 1152 - if (ret < 0) { 1153 - dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); 1154 - goto error_disable_adc_clk; 1155 - } 1176 + if (ret < 0) 1177 + return dev_err_probe(&pdev->dev, ret, 1178 + "Couldn't initialize the buffer.\n"); 1156 1179 1157 1180 ret = at91_adc_trigger_init(idev); 1158 1181 if (ret < 0) { 1159 1182 dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); 1160 1183 at91_adc_buffer_remove(idev); 1161 - goto error_disable_adc_clk; 1184 + return ret; 1162 1185 } 1163 1186 } else { 1164 1187 ret = at91_ts_register(idev, pdev); 1165 1188 if (ret) 1166 - goto error_disable_adc_clk; 1189 + return ret; 1167 1190 1168 1191 at91_ts_hw_init(idev, adc_clk_khz); 1169 1192 } ··· 1182 1207 } else { 1183 1208 at91_ts_unregister(st); 1184 1209 } 1185 - error_disable_adc_clk: 1186 - clk_disable_unprepare(st->adc_clk); 1187 - error_disable_clk: 1188 - clk_disable_unprepare(st->clk); 1189 - error_free_irq: 1190 - free_irq(st->irq, idev); 1191 1210 return ret; 1192 1211 } 1193 1212 1194 - static int at91_adc_remove(struct platform_device *pdev) 1213 + static void at91_adc_remove(struct platform_device *pdev) 1195 1214 { 1196 1215 struct iio_dev *idev = platform_get_drvdata(pdev); 1197 1216 struct at91_adc_state *st = iio_priv(idev); ··· 1197 1228 } else { 1198 1229 at91_ts_unregister(st); 1199 1230 } 1200 - clk_disable_unprepare(st->adc_clk); 1201 - clk_disable_unprepare(st->clk); 1202 - free_irq(st->irq, idev); 1203 - 1204 - return 0; 1205 1231 } 1206 1232 1207 1233 static int at91_adc_suspend(struct device *dev) ··· 1346 1382 1347 1383 static struct platform_driver at91_adc_driver = { 1348 1384 .probe = at91_adc_probe, 1349 - .remove = at91_adc_remove, 1385 + .remove_new = at91_adc_remove, 1350 1386 .driver = { 1351 1387 .name = DRIVER_NAME, 1352 1388 .of_match_table = at91_adc_dt_ids,

+2 -4

drivers/iio/adc/axp20x_adc.c

··· 745 745 return ret; 746 746 } 747 747 748 - static int axp20x_remove(struct platform_device *pdev) 748 + static void axp20x_remove(struct platform_device *pdev) 749 749 { 750 750 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 751 751 struct axp20x_adc_iio *info = iio_priv(indio_dev); ··· 757 757 758 758 if (info->data->adc_en2_mask) 759 759 regmap_write(info->regmap, AXP20X_ADC_EN2, 0); 760 - 761 - return 0; 762 760 } 763 761 764 762 static struct platform_driver axp20x_adc_driver = { ··· 766 768 }, 767 769 .id_table = axp20x_adc_id_match, 768 770 .probe = axp20x_probe, 769 - .remove = axp20x_remove, 771 + .remove_new = axp20x_remove, 770 772 }; 771 773 772 774 module_platform_driver(axp20x_adc_driver);

+2 -4

drivers/iio/adc/bcm_iproc_adc.c

··· 594 594 return ret; 595 595 } 596 596 597 - static int iproc_adc_remove(struct platform_device *pdev) 597 + static void iproc_adc_remove(struct platform_device *pdev) 598 598 { 599 599 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 600 600 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); ··· 602 602 iio_device_unregister(indio_dev); 603 603 iproc_adc_disable(indio_dev); 604 604 clk_disable_unprepare(adc_priv->adc_clk); 605 - 606 - return 0; 607 605 } 608 606 609 607 static const struct of_device_id iproc_adc_of_match[] = { ··· 612 614 613 615 static struct platform_driver iproc_adc_driver = { 614 616 .probe = iproc_adc_probe, 615 - .remove = iproc_adc_remove, 617 + .remove_new = iproc_adc_remove, 616 618 .driver = { 617 619 .name = "iproc-static-adc", 618 620 .of_match_table = iproc_adc_of_match,

+2 -3

drivers/iio/adc/dln2-adc.c

··· 691 691 return ret; 692 692 } 693 693 694 - static int dln2_adc_remove(struct platform_device *pdev) 694 + static void dln2_adc_remove(struct platform_device *pdev) 695 695 { 696 696 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 697 697 698 698 iio_device_unregister(indio_dev); 699 699 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV); 700 - return 0; 701 700 } 702 701 703 702 static struct platform_driver dln2_adc_driver = { 704 703 .driver.name = DLN2_ADC_MOD_NAME, 705 704 .probe = dln2_adc_probe, 706 - .remove = dln2_adc_remove, 705 + .remove_new = dln2_adc_remove, 707 706 }; 708 707 709 708 module_platform_driver(dln2_adc_driver);

+2 -4

drivers/iio/adc/ep93xx_adc.c

··· 217 217 return ret; 218 218 } 219 219 220 - static int ep93xx_adc_remove(struct platform_device *pdev) 220 + static void ep93xx_adc_remove(struct platform_device *pdev) 221 221 { 222 222 struct iio_dev *iiodev = platform_get_drvdata(pdev); 223 223 struct ep93xx_adc_priv *priv = iio_priv(iiodev); 224 224 225 225 iio_device_unregister(iiodev); 226 226 clk_disable_unprepare(priv->clk); 227 - 228 - return 0; 229 227 } 230 228 231 229 static const struct of_device_id ep93xx_adc_of_ids[] = { ··· 238 240 .of_match_table = ep93xx_adc_of_ids, 239 241 }, 240 242 .probe = ep93xx_adc_probe, 241 - .remove = ep93xx_adc_remove, 243 + .remove_new = ep93xx_adc_remove, 242 244 }; 243 245 module_platform_driver(ep93xx_adc_driver); 244 246

+2 -4

drivers/iio/adc/exynos_adc.c

··· 946 946 return ret; 947 947 } 948 948 949 - static int exynos_adc_remove(struct platform_device *pdev) 949 + static void exynos_adc_remove(struct platform_device *pdev) 950 950 { 951 951 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 952 952 struct exynos_adc *info = iio_priv(indio_dev); ··· 964 964 exynos_adc_disable_clk(info); 965 965 exynos_adc_unprepare_clk(info); 966 966 regulator_disable(info->vdd); 967 - 968 - return 0; 969 967 } 970 968 971 969 static int exynos_adc_suspend(struct device *dev) ··· 1004 1006 1005 1007 static struct platform_driver exynos_adc_driver = { 1006 1008 .probe = exynos_adc_probe, 1007 - .remove = exynos_adc_remove, 1009 + .remove_new = exynos_adc_remove, 1008 1010 .driver = { 1009 1011 .name = "exynos-adc", 1010 1012 .of_match_table = exynos_adc_match,

+2 -4

drivers/iio/adc/fsl-imx25-gcq.c

··· 384 384 return ret; 385 385 } 386 386 387 - static int mx25_gcq_remove(struct platform_device *pdev) 387 + static void mx25_gcq_remove(struct platform_device *pdev) 388 388 { 389 389 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 390 390 struct mx25_gcq_priv *priv = iio_priv(indio_dev); ··· 397 397 if (priv->vref[i]) 398 398 regulator_disable(priv->vref[i]); 399 399 } 400 - 401 - return 0; 402 400 } 403 401 404 402 static const struct of_device_id mx25_gcq_ids[] = { ··· 411 413 .of_match_table = mx25_gcq_ids, 412 414 }, 413 415 .probe = mx25_gcq_probe, 414 - .remove = mx25_gcq_remove, 416 + .remove_new = mx25_gcq_remove, 415 417 }; 416 418 module_platform_driver(mx25_gcq_driver); 417 419

+2 -4

drivers/iio/adc/hx711.c

··· 580 580 return ret; 581 581 } 582 582 583 - static int hx711_remove(struct platform_device *pdev) 583 + static void hx711_remove(struct platform_device *pdev) 584 584 { 585 585 struct hx711_data *hx711_data; 586 586 struct iio_dev *indio_dev; ··· 593 593 iio_triggered_buffer_cleanup(indio_dev); 594 594 595 595 regulator_disable(hx711_data->reg_avdd); 596 - 597 - return 0; 598 596 } 599 597 600 598 static const struct of_device_id of_hx711_match[] = { ··· 604 606 605 607 static struct platform_driver hx711_driver = { 606 608 .probe = hx711_probe, 607 - .remove = hx711_remove, 609 + .remove_new = hx711_remove, 608 610 .driver = { 609 611 .name = "hx711-gpio", 610 612 .of_match_table = of_hx711_match,

+2 -4

drivers/iio/adc/imx8qxp-adc.c

··· 404 404 return ret; 405 405 } 406 406 407 - static int imx8qxp_adc_remove(struct platform_device *pdev) 407 + static void imx8qxp_adc_remove(struct platform_device *pdev) 408 408 { 409 409 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 410 410 struct imx8qxp_adc *adc = iio_priv(indio_dev); ··· 422 422 423 423 pm_runtime_disable(dev); 424 424 pm_runtime_put_noidle(dev); 425 - 426 - return 0; 427 425 } 428 426 429 427 static int imx8qxp_adc_runtime_suspend(struct device *dev) ··· 487 489 488 490 static struct platform_driver imx8qxp_adc_driver = { 489 491 .probe = imx8qxp_adc_probe, 490 - .remove = imx8qxp_adc_remove, 492 + .remove_new = imx8qxp_adc_remove, 491 493 .driver = { 492 494 .name = ADC_DRIVER_NAME, 493 495 .of_match_table = imx8qxp_adc_match,

+2 -4

drivers/iio/adc/imx93_adc.c

··· 392 392 return ret; 393 393 } 394 394 395 - static int imx93_adc_remove(struct platform_device *pdev) 395 + static void imx93_adc_remove(struct platform_device *pdev) 396 396 { 397 397 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 398 398 struct imx93_adc *adc = iio_priv(indio_dev); ··· 410 410 free_irq(adc->irq, adc); 411 411 clk_disable_unprepare(adc->ipg_clk); 412 412 regulator_disable(adc->vref); 413 - 414 - return 0; 415 413 } 416 414 417 415 static int imx93_adc_runtime_suspend(struct device *dev) ··· 466 468 467 469 static struct platform_driver imx93_adc_driver = { 468 470 .probe = imx93_adc_probe, 469 - .remove = imx93_adc_remove, 471 + .remove_new = imx93_adc_remove, 470 472 .driver = { 471 473 .name = IMX93_ADC_DRIVER_NAME, 472 474 .of_match_table = imx93_adc_match,

+246

drivers/iio/adc/ltc2309.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * The LTC2309 is an 8-Channel, 12-Bit SAR ADC with an I2C Interface. 4 + * 5 + * Datasheet: 6 + * https://www.analog.com/media/en/technical-documentation/data-sheets/2309fd.pdf 7 + * 8 + * Copyright (c) 2023, Liam Beguin <liambeguin@gmail.com> 9 + */ 10 + #include <linux/bitfield.h> 11 + #include <linux/i2c.h> 12 + #include <linux/iio/iio.h> 13 + #include <linux/kernel.h> 14 + #include <linux/module.h> 15 + #include <linux/mutex.h> 16 + #include <linux/regulator/consumer.h> 17 + 18 + #define LTC2309_ADC_RESOLUTION 12 19 + 20 + #define LTC2309_DIN_CH_MASK GENMASK(7, 4) 21 + #define LTC2309_DIN_SDN BIT(7) 22 + #define LTC2309_DIN_OSN BIT(6) 23 + #define LTC2309_DIN_S1 BIT(5) 24 + #define LTC2309_DIN_S0 BIT(4) 25 + #define LTC2309_DIN_UNI BIT(3) 26 + #define LTC2309_DIN_SLEEP BIT(2) 27 + 28 + /** 29 + * struct ltc2309 - internal device data structure 30 + * @dev: Device reference 31 + * @client: I2C reference 32 + * @vref: External reference source 33 + * @lock: Lock to serialize data access 34 + * @vref_mv: Internal voltage reference 35 + */ 36 + struct ltc2309 { 37 + struct device *dev; 38 + struct i2c_client *client; 39 + struct regulator *vref; 40 + struct mutex lock; /* serialize data access */ 41 + int vref_mv; 42 + }; 43 + 44 + /* Order matches expected channel address, See datasheet Table 1. */ 45 + enum ltc2309_channels { 46 + LTC2309_CH0_CH1 = 0, 47 + LTC2309_CH2_CH3, 48 + LTC2309_CH4_CH5, 49 + LTC2309_CH6_CH7, 50 + LTC2309_CH1_CH0, 51 + LTC2309_CH3_CH2, 52 + LTC2309_CH5_CH4, 53 + LTC2309_CH7_CH6, 54 + LTC2309_CH0, 55 + LTC2309_CH2, 56 + LTC2309_CH4, 57 + LTC2309_CH6, 58 + LTC2309_CH1, 59 + LTC2309_CH3, 60 + LTC2309_CH5, 61 + LTC2309_CH7, 62 + }; 63 + 64 + #define LTC2309_CHAN(_chan, _addr) { \ 65 + .type = IIO_VOLTAGE, \ 66 + .indexed = 1, \ 67 + .address = _addr, \ 68 + .channel = _chan, \ 69 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 70 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 71 + } 72 + 73 + #define LTC2309_DIFF_CHAN(_chan, _chan2, _addr) { \ 74 + .type = IIO_VOLTAGE, \ 75 + .differential = 1, \ 76 + .indexed = 1, \ 77 + .address = _addr, \ 78 + .channel = _chan, \ 79 + .channel2 = _chan2, \ 80 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 81 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 82 + } 83 + 84 + static const struct iio_chan_spec ltc2309_channels[] = { 85 + LTC2309_CHAN(0, LTC2309_CH0), 86 + LTC2309_CHAN(1, LTC2309_CH1), 87 + LTC2309_CHAN(2, LTC2309_CH2), 88 + LTC2309_CHAN(3, LTC2309_CH3), 89 + LTC2309_CHAN(4, LTC2309_CH4), 90 + LTC2309_CHAN(5, LTC2309_CH5), 91 + LTC2309_CHAN(6, LTC2309_CH6), 92 + LTC2309_CHAN(7, LTC2309_CH7), 93 + LTC2309_DIFF_CHAN(0, 1, LTC2309_CH0_CH1), 94 + LTC2309_DIFF_CHAN(2, 3, LTC2309_CH2_CH3), 95 + LTC2309_DIFF_CHAN(4, 5, LTC2309_CH4_CH5), 96 + LTC2309_DIFF_CHAN(6, 7, LTC2309_CH6_CH7), 97 + LTC2309_DIFF_CHAN(1, 0, LTC2309_CH1_CH0), 98 + LTC2309_DIFF_CHAN(3, 2, LTC2309_CH3_CH2), 99 + LTC2309_DIFF_CHAN(5, 4, LTC2309_CH5_CH4), 100 + LTC2309_DIFF_CHAN(7, 6, LTC2309_CH7_CH6), 101 + }; 102 + 103 + static int ltc2309_read_raw_channel(struct ltc2309 *ltc2309, 104 + unsigned long address, int *val) 105 + { 106 + int ret; 107 + u16 buf; 108 + u8 din; 109 + 110 + din = FIELD_PREP(LTC2309_DIN_CH_MASK, address & 0x0f) | 111 + FIELD_PREP(LTC2309_DIN_UNI, 1) | 112 + FIELD_PREP(LTC2309_DIN_SLEEP, 0); 113 + 114 + ret = i2c_smbus_write_byte(ltc2309->client, din); 115 + if (ret < 0) { 116 + dev_err(ltc2309->dev, "i2c command failed: %pe\n", 117 + ERR_PTR(ret)); 118 + return ret; 119 + } 120 + 121 + ret = i2c_master_recv(ltc2309->client, (char *)&buf, 2); 122 + if (ret < 0) { 123 + dev_err(ltc2309->dev, "i2c read failed: %pe\n", ERR_PTR(ret)); 124 + return ret; 125 + } 126 + 127 + *val = be16_to_cpu(buf) >> 4; 128 + 129 + return ret; 130 + } 131 + 132 + static int ltc2309_read_raw(struct iio_dev *indio_dev, 133 + struct iio_chan_spec const *chan, int *val, 134 + int *val2, long mask) 135 + { 136 + struct ltc2309 *ltc2309 = iio_priv(indio_dev); 137 + int ret; 138 + 139 + switch (mask) { 140 + case IIO_CHAN_INFO_RAW: 141 + mutex_lock(&ltc2309->lock); 142 + ret = ltc2309_read_raw_channel(ltc2309, chan->address, val); 143 + mutex_unlock(&ltc2309->lock); 144 + if (ret < 0) 145 + return -EINVAL; 146 + return IIO_VAL_INT; 147 + case IIO_CHAN_INFO_SCALE: 148 + *val = ltc2309->vref_mv; 149 + *val2 = LTC2309_ADC_RESOLUTION; 150 + return IIO_VAL_FRACTIONAL_LOG2; 151 + default: 152 + return -EINVAL; 153 + } 154 + } 155 + 156 + static const struct iio_info ltc2309_info = { 157 + .read_raw = ltc2309_read_raw, 158 + }; 159 + 160 + static void ltc2309_regulator_disable(void *regulator) 161 + { 162 + regulator_disable(regulator); 163 + } 164 + 165 + static int ltc2309_probe(struct i2c_client *client) 166 + { 167 + struct iio_dev *indio_dev; 168 + struct ltc2309 *ltc2309; 169 + int ret; 170 + 171 + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*ltc2309)); 172 + if (!indio_dev) 173 + return -ENOMEM; 174 + 175 + ltc2309 = iio_priv(indio_dev); 176 + ltc2309->dev = &indio_dev->dev; 177 + ltc2309->client = client; 178 + ltc2309->vref_mv = 4096; /* Default to the internal ref */ 179 + 180 + indio_dev->name = "ltc2309"; 181 + indio_dev->modes = INDIO_DIRECT_MODE; 182 + indio_dev->channels = ltc2309_channels; 183 + indio_dev->num_channels = ARRAY_SIZE(ltc2309_channels); 184 + indio_dev->info = &ltc2309_info; 185 + 186 + ltc2309->vref = devm_regulator_get_optional(&client->dev, "vref"); 187 + if (IS_ERR(ltc2309->vref)) { 188 + ret = PTR_ERR(ltc2309->vref); 189 + if (ret == -ENODEV) 190 + ltc2309->vref = NULL; 191 + else 192 + return ret; 193 + } 194 + 195 + if (ltc2309->vref) { 196 + ret = regulator_enable(ltc2309->vref); 197 + if (ret) 198 + return dev_err_probe(ltc2309->dev, ret, 199 + "failed to enable vref\n"); 200 + 201 + ret = devm_add_action_or_reset(ltc2309->dev, 202 + ltc2309_regulator_disable, 203 + ltc2309->vref); 204 + if (ret) { 205 + return dev_err_probe(ltc2309->dev, ret, 206 + "failed to add regulator_disable action: %d\n", 207 + ret); 208 + } 209 + 210 + ret = regulator_get_voltage(ltc2309->vref); 211 + if (ret < 0) 212 + return ret; 213 + 214 + ltc2309->vref_mv = ret / 1000; 215 + } 216 + 217 + mutex_init(&ltc2309->lock); 218 + 219 + return devm_iio_device_register(&client->dev, indio_dev); 220 + } 221 + 222 + static const struct of_device_id ltc2309_of_match[] = { 223 + { .compatible = "lltc,ltc2309" }, 224 + { } 225 + }; 226 + MODULE_DEVICE_TABLE(of, ltc2309_of_match); 227 + 228 + static const struct i2c_device_id ltc2309_id[] = { 229 + { "ltc2309" }, 230 + { } 231 + }; 232 + MODULE_DEVICE_TABLE(i2c, ltc2309_id); 233 + 234 + static struct i2c_driver ltc2309_driver = { 235 + .driver = { 236 + .name = "ltc2309", 237 + .of_match_table = ltc2309_of_match, 238 + }, 239 + .probe = ltc2309_probe, 240 + .id_table = ltc2309_id, 241 + }; 242 + module_i2c_driver(ltc2309_driver); 243 + 244 + MODULE_AUTHOR("Liam Beguin <liambeguin@gmail.com>"); 245 + MODULE_DESCRIPTION("Linear Technology LTC2309 ADC"); 246 + MODULE_LICENSE("GPL v2");

+1 -4

drivers/iio/adc/ltc2497.c

··· 95 95 96 96 static int ltc2497_probe(struct i2c_client *client) 97 97 { 98 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 99 98 const struct ltc2497_chip_info *chip_info; 100 99 struct iio_dev *indio_dev; 101 100 struct ltc2497_driverdata *st; ··· 114 115 st->client = client; 115 116 st->common_ddata.result_and_measure = ltc2497_result_and_measure; 116 117 117 - chip_info = device_get_match_data(dev); 118 - if (!chip_info) 119 - chip_info = (const struct ltc2497_chip_info *)id->driver_data; 118 + chip_info = i2c_get_match_data(client); 120 119 st->common_ddata.chip_info = chip_info; 121 120 122 121 resolution = chip_info->resolution;

+45 -42

drivers/iio/adc/max1363.c

··· 1599 1599 if (ret) 1600 1600 return ret; 1601 1601 1602 - st->chip_info = device_get_match_data(&client->dev); 1603 - if (!st->chip_info) 1604 - st->chip_info = &max1363_chip_info_tbl[id->driver_data]; 1602 + st->chip_info = i2c_get_match_data(client); 1605 1603 st->client = client; 1606 1604 1607 1605 st->vref_uv = st->chip_info->int_vref_mv * 1000; ··· 1667 1669 return devm_iio_device_register(&client->dev, indio_dev); 1668 1670 } 1669 1671 1672 + #define MAX1363_ID_TABLE(_name, cfg) { \ 1673 + .name = _name, \ 1674 + .driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \ 1675 + } 1676 + 1670 1677 static const struct i2c_device_id max1363_id[] = { 1671 - { "max1361", max1361 }, 1672 - { "max1362", max1362 }, 1673 - { "max1363", max1363 }, 1674 - { "max1364", max1364 }, 1675 - { "max1036", max1036 }, 1676 - { "max1037", max1037 }, 1677 - { "max1038", max1038 }, 1678 - { "max1039", max1039 }, 1679 - { "max1136", max1136 }, 1680 - { "max1137", max1137 }, 1681 - { "max1138", max1138 }, 1682 - { "max1139", max1139 }, 1683 - { "max1236", max1236 }, 1684 - { "max1237", max1237 }, 1685 - { "max1238", max1238 }, 1686 - { "max1239", max1239 }, 1687 - { "max11600", max11600 }, 1688 - { "max11601", max11601 }, 1689 - { "max11602", max11602 }, 1690 - { "max11603", max11603 }, 1691 - { "max11604", max11604 }, 1692 - { "max11605", max11605 }, 1693 - { "max11606", max11606 }, 1694 - { "max11607", max11607 }, 1695 - { "max11608", max11608 }, 1696 - { "max11609", max11609 }, 1697 - { "max11610", max11610 }, 1698 - { "max11611", max11611 }, 1699 - { "max11612", max11612 }, 1700 - { "max11613", max11613 }, 1701 - { "max11614", max11614 }, 1702 - { "max11615", max11615 }, 1703 - { "max11616", max11616 }, 1704 - { "max11617", max11617 }, 1705 - { "max11644", max11644 }, 1706 - { "max11645", max11645 }, 1707 - { "max11646", max11646 }, 1708 - { "max11647", max11647 }, 1709 - {} 1678 + MAX1363_ID_TABLE("max1361", max1361), 1679 + MAX1363_ID_TABLE("max1362", max1362), 1680 + MAX1363_ID_TABLE("max1363", max1363), 1681 + MAX1363_ID_TABLE("max1364", max1364), 1682 + MAX1363_ID_TABLE("max1036", max1036), 1683 + MAX1363_ID_TABLE("max1037", max1037), 1684 + MAX1363_ID_TABLE("max1038", max1038), 1685 + MAX1363_ID_TABLE("max1039", max1039), 1686 + MAX1363_ID_TABLE("max1136", max1136), 1687 + MAX1363_ID_TABLE("max1137", max1137), 1688 + MAX1363_ID_TABLE("max1138", max1138), 1689 + MAX1363_ID_TABLE("max1139", max1139), 1690 + MAX1363_ID_TABLE("max1236", max1236), 1691 + MAX1363_ID_TABLE("max1237", max1237), 1692 + MAX1363_ID_TABLE("max1238", max1238), 1693 + MAX1363_ID_TABLE("max1239", max1239), 1694 + MAX1363_ID_TABLE("max11600", max11600), 1695 + MAX1363_ID_TABLE("max11601", max11601), 1696 + MAX1363_ID_TABLE("max11602", max11602), 1697 + MAX1363_ID_TABLE("max11603", max11603), 1698 + MAX1363_ID_TABLE("max11604", max11604), 1699 + MAX1363_ID_TABLE("max11605", max11605), 1700 + MAX1363_ID_TABLE("max11606", max11606), 1701 + MAX1363_ID_TABLE("max11607", max11607), 1702 + MAX1363_ID_TABLE("max11608", max11608), 1703 + MAX1363_ID_TABLE("max11609", max11609), 1704 + MAX1363_ID_TABLE("max11610", max11610), 1705 + MAX1363_ID_TABLE("max11611", max11611), 1706 + MAX1363_ID_TABLE("max11612", max11612), 1707 + MAX1363_ID_TABLE("max11613", max11613), 1708 + MAX1363_ID_TABLE("max11614", max11614), 1709 + MAX1363_ID_TABLE("max11615", max11615), 1710 + MAX1363_ID_TABLE("max11616", max11616), 1711 + MAX1363_ID_TABLE("max11617", max11617), 1712 + MAX1363_ID_TABLE("max11644", max11644), 1713 + MAX1363_ID_TABLE("max11645", max11645), 1714 + MAX1363_ID_TABLE("max11646", max11646), 1715 + MAX1363_ID_TABLE("max11647", max11647), 1716 + { /* sentinel */ } 1710 1717 }; 1711 1718 1712 1719 MODULE_DEVICE_TABLE(i2c, max1363_id);

+1513

drivers/iio/adc/mcp3564.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * IIO driver for MCP356X/MCP356XR and MCP346X/MCP346XR series ADC chip family 4 + * 5 + * Copyright (C) 2022-2023 Microchip Technology Inc. and its subsidiaries 6 + * 7 + * Author: Marius Cristea <marius.cristea@microchip.com> 8 + * 9 + * Datasheet for MCP3561, MCP3562, MCP3564 can be found here: 10 + * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP3561-2-4-Family-Data-Sheet-DS20006181C.pdf 11 + * Datasheet for MCP3561R, MCP3562R, MCP3564R can be found here: 12 + * https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3561_2_4R-Data-Sheet-DS200006391C.pdf 13 + * Datasheet for MCP3461, MCP3462, MCP3464 can be found here: 14 + * https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180D.pdf 15 + * Datasheet for MCP3461R, MCP3462R, MCP3464R can be found here: 16 + * https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4R-Family-Data-Sheet-DS20006404C.pdf 17 + */ 18 + 19 + #include <linux/bitfield.h> 20 + #include <linux/iopoll.h> 21 + #include <linux/regulator/consumer.h> 22 + #include <linux/spi/spi.h> 23 + #include <linux/units.h> 24 + #include <linux/util_macros.h> 25 + 26 + #include <linux/iio/iio.h> 27 + #include <linux/iio/sysfs.h> 28 + 29 + #define MCP3564_ADCDATA_REG 0x00 30 + 31 + #define MCP3564_CONFIG0_REG 0x01 32 + #define MCP3564_CONFIG0_ADC_MODE_MASK GENMASK(1, 0) 33 + /* Current Source/Sink Selection Bits for Sensor Bias */ 34 + #define MCP3564_CONFIG0_CS_SEL_MASK GENMASK(3, 2) 35 + /* Internal clock is selected and AMCLK is present on the analog master clock output pin */ 36 + #define MCP3564_CONFIG0_USE_INT_CLK_OUTPUT_EN 0x03 37 + /* Internal clock is selected and no clock output is present on the CLK pin */ 38 + #define MCP3564_CONFIG0_USE_INT_CLK 0x02 39 + /* External digital clock */ 40 + #define MCP3564_CONFIG0_USE_EXT_CLK 0x01 41 + /* External digital clock (default) */ 42 + #define MCP3564_CONFIG0_USE_EXT_CLK_DEFAULT 0x00 43 + #define MCP3564_CONFIG0_CLK_SEL_MASK GENMASK(5, 4) 44 + #define MCP3456_CONFIG0_BIT6_DEFAULT BIT(6) 45 + #define MCP3456_CONFIG0_VREF_MASK BIT(7) 46 + 47 + #define MCP3564_CONFIG1_REG 0x02 48 + #define MCP3564_CONFIG1_OVERSPL_RATIO_MASK GENMASK(5, 2) 49 + 50 + #define MCP3564_CONFIG2_REG 0x03 51 + #define MCP3564_CONFIG2_AZ_REF_MASK BIT(1) 52 + #define MCP3564_CONFIG2_AZ_MUX_MASK BIT(2) 53 + 54 + #define MCP3564_CONFIG2_HARDWARE_GAIN_MASK GENMASK(5, 3) 55 + #define MCP3564_DEFAULT_HARDWARE_GAIN 0x01 56 + #define MCP3564_CONFIG2_BOOST_CURRENT_MASK GENMASK(7, 6) 57 + 58 + #define MCP3564_CONFIG3_REG 0x04 59 + #define MCP3464_CONFIG3_EN_GAINCAL_MASK BIT(0) 60 + #define MCP3464_CONFIG3_EN_OFFCAL_MASK BIT(1) 61 + #define MCP3464_CONFIG3_EN_CRCCOM_MASK BIT(2) 62 + #define MCP3464_CONFIG3_CRC_FORMAT_MASK BIT(3) 63 + /* 64 + * ADC Output Data Format 32-bit (25-bit right justified data + Channel ID): 65 + * CHID[3:0] + SGN extension (4 bits) + 24-bit ADC data. 66 + * It allows overrange with the SGN extension. 67 + */ 68 + #define MCP3464_CONFIG3_DATA_FMT_32B_WITH_CH_ID 3 69 + /* 70 + * ADC Output Data Format 32-bit (25-bit right justified data): 71 + * SGN extension (8-bit) + 24-bit ADC data. 72 + * It allows overrange with the SGN extension. 73 + */ 74 + #define MCP3464_CONFIG3_DATA_FMT_32B_SGN_EXT 2 75 + /* 76 + * ADC Output Data Format 32-bit (24-bit left justified data): 77 + * 24-bit ADC data + 0x00 (8-bit). 78 + * It does not allow overrange (ADC code locked to 0xFFFFFF or 0x800000). 79 + */ 80 + #define MCP3464_CONFIG3_DATA_FMT_32B_LEFT_JUSTIFIED 1 81 + /* 82 + * ADC Output Data Format 24-bit (default ADC coding): 83 + * 24-bit ADC data. 84 + * It does not allow overrange (ADC code locked to 0xFFFFFF or 0x800000). 85 + */ 86 + #define MCP3464_CONFIG3_DATA_FMT_24B 0 87 + #define MCP3464_CONFIG3_DATA_FORMAT_MASK GENMASK(5, 4) 88 + 89 + /* Continuous Conversion mode or continuous conversion cycle in SCAN mode. */ 90 + #define MCP3464_CONFIG3_CONV_MODE_CONTINUOUS 3 91 + /* 92 + * One-shot conversion or one-shot cycle in SCAN mode. It sets ADC_MODE[1:0] to ‘10’ 93 + * (standby) at the end of the conversion or at the end of the conversion cycle in SCAN mode. 94 + */ 95 + #define MCP3464_CONFIG3_CONV_MODE_ONE_SHOT_STANDBY 2 96 + /* 97 + * One-shot conversion or one-shot cycle in SCAN mode. It sets ADC_MODE[1:0] to ‘0x’ (ADC 98 + * Shutdown) at the end of the conversion or at the end of the conversion cycle in SCAN 99 + * mode (default). 100 + */ 101 + #define MCP3464_CONFIG3_CONV_MODE_ONE_SHOT_SHUTDOWN 0 102 + #define MCP3464_CONFIG3_CONV_MODE_MASK GENMASK(7, 6) 103 + 104 + #define MCP3564_IRQ_REG 0x05 105 + #define MCP3464_EN_STP_MASK BIT(0) 106 + #define MCP3464_EN_FASTCMD_MASK BIT(1) 107 + #define MCP3464_IRQ_MODE_0_MASK BIT(2) 108 + #define MCP3464_IRQ_MODE_1_MASK BIT(3) 109 + #define MCP3564_POR_STATUS_MASK BIT(4) 110 + #define MCP3564_CRCCFG_STATUS_MASK BIT(5) 111 + #define MCP3564_DATA_READY_MASK BIT(6) 112 + 113 + #define MCP3564_MUX_REG 0x06 114 + #define MCP3564_MUX_VIN_P_MASK GENMASK(7, 4) 115 + #define MCP3564_MUX_VIN_N_MASK GENMASK(3, 0) 116 + #define MCP3564_MUX_SET(x, y) (FIELD_PREP(MCP3564_MUX_VIN_P_MASK, (x)) | \ 117 + FIELD_PREP(MCP3564_MUX_VIN_N_MASK, (y))) 118 + 119 + #define MCP3564_SCAN_REG 0x07 120 + #define MCP3564_SCAN_CH_SEL_MASK GENMASK(15, 0) 121 + #define MCP3564_SCAN_CH_SEL_SET(x) FIELD_PREP(MCP3564_SCAN_CH_SEL_MASK, (x)) 122 + #define MCP3564_SCAN_DELAY_TIME_MASK GENMASK(23, 21) 123 + #define MCP3564_SCAN_DELAY_TIME_SET(x) FIELD_PREP(MCP3564_SCAN_DELAY_TIME_MASK, (x)) 124 + #define MCP3564_SCAN_DEFAULT_VALUE 0 125 + 126 + #define MCP3564_TIMER_REG 0x08 127 + #define MCP3564_TIMER_DEFAULT_VALUE 0 128 + 129 + #define MCP3564_OFFSETCAL_REG 0x09 130 + #define MCP3564_DEFAULT_OFFSETCAL 0 131 + 132 + #define MCP3564_GAINCAL_REG 0x0A 133 + #define MCP3564_DEFAULT_GAINCAL 0x00800000 134 + 135 + #define MCP3564_RESERVED_B_REG 0x0B 136 + 137 + #define MCP3564_RESERVED_C_REG 0x0C 138 + #define MCP3564_C_REG_DEFAULT 0x50 139 + #define MCP3564R_C_REG_DEFAULT 0x30 140 + 141 + #define MCP3564_LOCK_REG 0x0D 142 + #define MCP3564_LOCK_WRITE_ACCESS_PASSWORD 0xA5 143 + #define MCP3564_RESERVED_E_REG 0x0E 144 + #define MCP3564_CRCCFG_REG 0x0F 145 + 146 + #define MCP3564_CMD_HW_ADDR_MASK GENMASK(7, 6) 147 + #define MCP3564_CMD_ADDR_MASK GENMASK(5, 2) 148 + 149 + #define MCP3564_HW_ADDR_MASK GENMASK(1, 0) 150 + 151 + #define MCP3564_FASTCMD_START 0x0A 152 + #define MCP3564_FASTCMD_RESET 0x0E 153 + 154 + #define MCP3461_HW_ID 0x0008 155 + #define MCP3462_HW_ID 0x0009 156 + #define MCP3464_HW_ID 0x000B 157 + 158 + #define MCP3561_HW_ID 0x000C 159 + #define MCP3562_HW_ID 0x000D 160 + #define MCP3564_HW_ID 0x000F 161 + #define MCP3564_HW_ID_MASK GENMASK(3, 0) 162 + 163 + #define MCP3564R_INT_VREF_MV 2400 164 + 165 + #define MCP3564_DATA_READY_TIMEOUT_MS 2000 166 + 167 + #define MCP3564_MAX_PGA 8 168 + #define MCP3564_MAX_BURNOUT_IDX 4 169 + #define MCP3564_MAX_CHANNELS 66 170 + 171 + enum mcp3564_ids { 172 + mcp3461, 173 + mcp3462, 174 + mcp3464, 175 + mcp3561, 176 + mcp3562, 177 + mcp3564, 178 + mcp3461r, 179 + mcp3462r, 180 + mcp3464r, 181 + mcp3561r, 182 + mcp3562r, 183 + mcp3564r, 184 + }; 185 + 186 + enum mcp3564_delay_time { 187 + MCP3564_NO_DELAY, 188 + MCP3564_DELAY_8_DMCLK, 189 + MCP3564_DELAY_16_DMCLK, 190 + MCP3564_DELAY_32_DMCLK, 191 + MCP3564_DELAY_64_DMCLK, 192 + MCP3564_DELAY_128_DMCLK, 193 + MCP3564_DELAY_256_DMCLK, 194 + MCP3564_DELAY_512_DMCLK 195 + }; 196 + 197 + enum mcp3564_adc_conversion_mode { 198 + MCP3564_ADC_MODE_DEFAULT, 199 + MCP3564_ADC_MODE_SHUTDOWN, 200 + MCP3564_ADC_MODE_STANDBY, 201 + MCP3564_ADC_MODE_CONVERSION 202 + }; 203 + 204 + enum mcp3564_adc_bias_current { 205 + MCP3564_BOOST_CURRENT_x0_50, 206 + MCP3564_BOOST_CURRENT_x0_66, 207 + MCP3564_BOOST_CURRENT_x1_00, 208 + MCP3564_BOOST_CURRENT_x2_00 209 + }; 210 + 211 + enum mcp3564_burnout { 212 + MCP3564_CONFIG0_CS_SEL_0_0_uA, 213 + MCP3564_CONFIG0_CS_SEL_0_9_uA, 214 + MCP3564_CONFIG0_CS_SEL_3_7_uA, 215 + MCP3564_CONFIG0_CS_SEL_15_uA 216 + }; 217 + 218 + enum mcp3564_channel_names { 219 + MCP3564_CH0, 220 + MCP3564_CH1, 221 + MCP3564_CH2, 222 + MCP3564_CH3, 223 + MCP3564_CH4, 224 + MCP3564_CH5, 225 + MCP3564_CH6, 226 + MCP3564_CH7, 227 + MCP3564_AGND, 228 + MCP3564_AVDD, 229 + MCP3564_RESERVED, /* do not use */ 230 + MCP3564_REFIN_POZ, 231 + MCP3564_REFIN_NEG, 232 + MCP3564_TEMP_DIODE_P, 233 + MCP3564_TEMP_DIODE_M, 234 + MCP3564_INTERNAL_VCM, 235 + }; 236 + 237 + enum mcp3564_oversampling { 238 + MCP3564_OVERSAMPLING_RATIO_32, 239 + MCP3564_OVERSAMPLING_RATIO_64, 240 + MCP3564_OVERSAMPLING_RATIO_128, 241 + MCP3564_OVERSAMPLING_RATIO_256, 242 + MCP3564_OVERSAMPLING_RATIO_512, 243 + MCP3564_OVERSAMPLING_RATIO_1024, 244 + MCP3564_OVERSAMPLING_RATIO_2048, 245 + MCP3564_OVERSAMPLING_RATIO_4096, 246 + MCP3564_OVERSAMPLING_RATIO_8192, 247 + MCP3564_OVERSAMPLING_RATIO_16384, 248 + MCP3564_OVERSAMPLING_RATIO_20480, 249 + MCP3564_OVERSAMPLING_RATIO_24576, 250 + MCP3564_OVERSAMPLING_RATIO_40960, 251 + MCP3564_OVERSAMPLING_RATIO_49152, 252 + MCP3564_OVERSAMPLING_RATIO_81920, 253 + MCP3564_OVERSAMPLING_RATIO_98304 254 + }; 255 + 256 + static const unsigned int mcp3564_oversampling_avail[] = { 257 + [MCP3564_OVERSAMPLING_RATIO_32] = 32, 258 + [MCP3564_OVERSAMPLING_RATIO_64] = 64, 259 + [MCP3564_OVERSAMPLING_RATIO_128] = 128, 260 + [MCP3564_OVERSAMPLING_RATIO_256] = 256, 261 + [MCP3564_OVERSAMPLING_RATIO_512] = 512, 262 + [MCP3564_OVERSAMPLING_RATIO_1024] = 1024, 263 + [MCP3564_OVERSAMPLING_RATIO_2048] = 2048, 264 + [MCP3564_OVERSAMPLING_RATIO_4096] = 4096, 265 + [MCP3564_OVERSAMPLING_RATIO_8192] = 8192, 266 + [MCP3564_OVERSAMPLING_RATIO_16384] = 16384, 267 + [MCP3564_OVERSAMPLING_RATIO_20480] = 20480, 268 + [MCP3564_OVERSAMPLING_RATIO_24576] = 24576, 269 + [MCP3564_OVERSAMPLING_RATIO_40960] = 40960, 270 + [MCP3564_OVERSAMPLING_RATIO_49152] = 49152, 271 + [MCP3564_OVERSAMPLING_RATIO_81920] = 81920, 272 + [MCP3564_OVERSAMPLING_RATIO_98304] = 98304 273 + }; 274 + 275 + /* 276 + * Current Source/Sink Selection Bits for Sensor Bias (source on VIN+/sink on VIN-) 277 + */ 278 + static const int mcp3564_burnout_avail[][2] = { 279 + [MCP3564_CONFIG0_CS_SEL_0_0_uA] = { 0, 0 }, 280 + [MCP3564_CONFIG0_CS_SEL_0_9_uA] = { 0, 900 }, 281 + [MCP3564_CONFIG0_CS_SEL_3_7_uA] = { 0, 3700 }, 282 + [MCP3564_CONFIG0_CS_SEL_15_uA] = { 0, 15000 } 283 + }; 284 + 285 + /* 286 + * BOOST[1:0]: ADC Bias Current Selection 287 + */ 288 + static const char * const mcp3564_boost_current_avail[] = { 289 + [MCP3564_BOOST_CURRENT_x0_50] = "0.5", 290 + [MCP3564_BOOST_CURRENT_x0_66] = "0.66", 291 + [MCP3564_BOOST_CURRENT_x1_00] = "1", 292 + [MCP3564_BOOST_CURRENT_x2_00] = "2", 293 + }; 294 + 295 + /* 296 + * Calibration bias values 297 + */ 298 + static const int mcp3564_calib_bias[] = { 299 + -8388608, /* min: -2^23 */ 300 + 1, /* step: 1 */ 301 + 8388607 /* max: 2^23 - 1 */ 302 + }; 303 + 304 + /* 305 + * Calibration scale values 306 + * The Gain Error Calibration register (GAINCAL) is an 307 + * unsigned 24-bit register that holds the digital gain error 308 + * calibration value, GAINCAL which could be calculated by 309 + * GAINCAL (V/V) = (GAINCAL[23:0])/8388608 310 + * The gain error calibration value range in equivalent voltage is [0; 2-2^(-23)] 311 + */ 312 + static const unsigned int mcp3564_calib_scale[] = { 313 + 0, /* min: 0 */ 314 + 1, /* step: 1/8388608 */ 315 + 16777215 /* max: 2 - 2^(-23) */ 316 + }; 317 + 318 + /* Programmable hardware gain x1/3, x1, x2, x4, x8, x16, x32, x64 */ 319 + static const int mcp3564_hwgain_frac[] = { 320 + 3, 10, 321 + 1, 1, 322 + 2, 1, 323 + 4, 1, 324 + 8, 1, 325 + 16, 1, 326 + 32, 1, 327 + 64, 1 328 + }; 329 + 330 + static const char *mcp3564_channel_labels[2] = { 331 + "burnout_current", "temperature", 332 + }; 333 + 334 + /** 335 + * struct mcp3564_chip_info - chip specific data 336 + * @name: device name 337 + * @num_channels: number of channels 338 + * @resolution: ADC resolution 339 + * @have_vref: does the hardware have an internal voltage reference? 340 + */ 341 + struct mcp3564_chip_info { 342 + const char *name; 343 + unsigned int num_channels; 344 + unsigned int resolution; 345 + bool have_vref; 346 + }; 347 + 348 + /** 349 + * struct mcp3564_state - working data for a ADC device 350 + * @chip_info: chip specific data 351 + * @spi: SPI device structure 352 + * @vref: the regulator device used as a voltage reference in case 353 + * external voltage reference is used 354 + * @vref_mv: voltage reference value in miliVolts 355 + * @lock: synchronize access to driver's state members 356 + * @dev_addr: hardware device address 357 + * @oversampling: the index inside oversampling list of the ADC 358 + * @hwgain: the index inside hardware gain list of the ADC 359 + * @scale_tbls: table with precalculated scale 360 + * @calib_bias: calibration bias value 361 + * @calib_scale: calibration scale value 362 + * @current_boost_mode: the index inside current boost list of the ADC 363 + * @burnout_mode: the index inside current bias list of the ADC 364 + * @auto_zeroing_mux: set if ADC auto-zeroing algorithm is enabled 365 + * @auto_zeroing_ref: set if ADC auto-Zeroing Reference Buffer Setting is enabled 366 + * @have_vref: does the ADC have an internal voltage reference? 367 + * @labels: table with channels labels 368 + */ 369 + struct mcp3564_state { 370 + const struct mcp3564_chip_info *chip_info; 371 + struct spi_device *spi; 372 + struct regulator *vref; 373 + unsigned short vref_mv; 374 + struct mutex lock; /* Synchronize access to driver's state members */ 375 + u8 dev_addr; 376 + enum mcp3564_oversampling oversampling; 377 + unsigned int hwgain; 378 + unsigned int scale_tbls[MCP3564_MAX_PGA][2]; 379 + int calib_bias; 380 + int calib_scale; 381 + unsigned int current_boost_mode; 382 + enum mcp3564_burnout burnout_mode; 383 + bool auto_zeroing_mux; 384 + bool auto_zeroing_ref; 385 + bool have_vref; 386 + const char *labels[MCP3564_MAX_CHANNELS]; 387 + }; 388 + 389 + static inline u8 mcp3564_cmd_write(u8 chip_addr, u8 reg) 390 + { 391 + return FIELD_PREP(MCP3564_CMD_HW_ADDR_MASK, chip_addr) | 392 + FIELD_PREP(MCP3564_CMD_ADDR_MASK, reg) | 393 + BIT(1); 394 + } 395 + 396 + static inline u8 mcp3564_cmd_read(u8 chip_addr, u8 reg) 397 + { 398 + return FIELD_PREP(MCP3564_CMD_HW_ADDR_MASK, chip_addr) | 399 + FIELD_PREP(MCP3564_CMD_ADDR_MASK, reg) | 400 + BIT(0); 401 + } 402 + 403 + static int mcp3564_read_8bits(struct mcp3564_state *adc, u8 reg, u8 *val) 404 + { 405 + int ret; 406 + u8 tx_buf; 407 + u8 rx_buf; 408 + 409 + tx_buf = mcp3564_cmd_read(adc->dev_addr, reg); 410 + 411 + ret = spi_write_then_read(adc->spi, &tx_buf, sizeof(tx_buf), 412 + &rx_buf, sizeof(rx_buf)); 413 + *val = rx_buf; 414 + 415 + return ret; 416 + } 417 + 418 + static int mcp3564_read_16bits(struct mcp3564_state *adc, u8 reg, u16 *val) 419 + { 420 + int ret; 421 + u8 tx_buf; 422 + __be16 rx_buf; 423 + 424 + tx_buf = mcp3564_cmd_read(adc->dev_addr, reg); 425 + 426 + ret = spi_write_then_read(adc->spi, &tx_buf, sizeof(tx_buf), 427 + &rx_buf, sizeof(rx_buf)); 428 + *val = be16_to_cpu(rx_buf); 429 + 430 + return ret; 431 + } 432 + 433 + static int mcp3564_read_32bits(struct mcp3564_state *adc, u8 reg, u32 *val) 434 + { 435 + int ret; 436 + u8 tx_buf; 437 + __be32 rx_buf; 438 + 439 + tx_buf = mcp3564_cmd_read(adc->dev_addr, reg); 440 + 441 + ret = spi_write_then_read(adc->spi, &tx_buf, sizeof(tx_buf), 442 + &rx_buf, sizeof(rx_buf)); 443 + *val = be32_to_cpu(rx_buf); 444 + 445 + return ret; 446 + } 447 + 448 + static int mcp3564_write_8bits(struct mcp3564_state *adc, u8 reg, u8 val) 449 + { 450 + u8 tx_buf[2]; 451 + 452 + tx_buf[0] = mcp3564_cmd_write(adc->dev_addr, reg); 453 + tx_buf[1] = val; 454 + 455 + return spi_write_then_read(adc->spi, tx_buf, sizeof(tx_buf), NULL, 0); 456 + } 457 + 458 + static int mcp3564_write_24bits(struct mcp3564_state *adc, u8 reg, u32 val) 459 + { 460 + __be32 val_be; 461 + 462 + val |= (mcp3564_cmd_write(adc->dev_addr, reg) << 24); 463 + val_be = cpu_to_be32(val); 464 + 465 + return spi_write_then_read(adc->spi, &val_be, sizeof(val_be), NULL, 0); 466 + } 467 + 468 + static int mcp3564_fast_cmd(struct mcp3564_state *adc, u8 fast_cmd) 469 + { 470 + u8 val; 471 + 472 + val = FIELD_PREP(MCP3564_CMD_HW_ADDR_MASK, adc->dev_addr) | 473 + FIELD_PREP(MCP3564_CMD_ADDR_MASK, fast_cmd); 474 + 475 + return spi_write_then_read(adc->spi, &val, 1, NULL, 0); 476 + } 477 + 478 + static int mcp3564_update_8bits(struct mcp3564_state *adc, u8 reg, u32 mask, u8 val) 479 + { 480 + u8 tmp; 481 + int ret; 482 + 483 + val &= mask; 484 + 485 + ret = mcp3564_read_8bits(adc, reg, &tmp); 486 + if (ret < 0) 487 + return ret; 488 + 489 + tmp &= ~mask; 490 + tmp |= val; 491 + 492 + return mcp3564_write_8bits(adc, reg, tmp); 493 + } 494 + 495 + static int mcp3564_set_current_boost_mode(struct iio_dev *indio_dev, 496 + const struct iio_chan_spec *chan, 497 + unsigned int mode) 498 + { 499 + struct mcp3564_state *adc = iio_priv(indio_dev); 500 + int ret; 501 + 502 + dev_dbg(&indio_dev->dev, "%s: %d\n", __func__, mode); 503 + 504 + mutex_lock(&adc->lock); 505 + ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, MCP3564_CONFIG2_BOOST_CURRENT_MASK, 506 + FIELD_PREP(MCP3564_CONFIG2_BOOST_CURRENT_MASK, mode)); 507 + 508 + if (ret) 509 + dev_err(&indio_dev->dev, "Failed to configure CONFIG2 register\n"); 510 + else 511 + adc->current_boost_mode = mode; 512 + 513 + mutex_unlock(&adc->lock); 514 + 515 + return ret; 516 + } 517 + 518 + static int mcp3564_get_current_boost_mode(struct iio_dev *indio_dev, 519 + const struct iio_chan_spec *chan) 520 + { 521 + struct mcp3564_state *adc = iio_priv(indio_dev); 522 + 523 + return adc->current_boost_mode; 524 + } 525 + 526 + static const struct iio_enum mcp3564_current_boost_mode_enum = { 527 + .items = mcp3564_boost_current_avail, 528 + .num_items = ARRAY_SIZE(mcp3564_boost_current_avail), 529 + .set = mcp3564_set_current_boost_mode, 530 + .get = mcp3564_get_current_boost_mode, 531 + }; 532 + 533 + static const struct iio_chan_spec_ext_info mcp3564_ext_info[] = { 534 + IIO_ENUM("boost_current_gain", IIO_SHARED_BY_ALL, &mcp3564_current_boost_mode_enum), 535 + { 536 + .name = "boost_current_gain_available", 537 + .shared = IIO_SHARED_BY_ALL, 538 + .read = iio_enum_available_read, 539 + .private = (uintptr_t)&mcp3564_current_boost_mode_enum, 540 + }, 541 + { } 542 + }; 543 + 544 + static ssize_t mcp3564_auto_zeroing_mux_show(struct device *dev, 545 + struct device_attribute *attr, 546 + char *buf) 547 + { 548 + struct iio_dev *indio_dev = dev_to_iio_dev(dev); 549 + struct mcp3564_state *adc = iio_priv(indio_dev); 550 + 551 + return sysfs_emit(buf, "%d\n", adc->auto_zeroing_mux); 552 + } 553 + 554 + static ssize_t mcp3564_auto_zeroing_mux_store(struct device *dev, 555 + struct device_attribute *attr, 556 + const char *buf, size_t len) 557 + { 558 + struct iio_dev *indio_dev = dev_to_iio_dev(dev); 559 + struct mcp3564_state *adc = iio_priv(indio_dev); 560 + bool auto_zero; 561 + int ret; 562 + 563 + ret = kstrtobool(buf, &auto_zero); 564 + if (ret) 565 + return ret; 566 + 567 + mutex_lock(&adc->lock); 568 + ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, MCP3564_CONFIG2_AZ_MUX_MASK, 569 + FIELD_PREP(MCP3564_CONFIG2_AZ_MUX_MASK, auto_zero)); 570 + 571 + if (ret) 572 + dev_err(&indio_dev->dev, "Failed to update CONFIG2 register\n"); 573 + else 574 + adc->auto_zeroing_mux = auto_zero; 575 + 576 + mutex_unlock(&adc->lock); 577 + 578 + return ret ? ret : len; 579 + } 580 + 581 + static ssize_t mcp3564_auto_zeroing_ref_show(struct device *dev, 582 + struct device_attribute *attr, 583 + char *buf) 584 + { 585 + struct iio_dev *indio_dev = dev_to_iio_dev(dev); 586 + struct mcp3564_state *adc = iio_priv(indio_dev); 587 + 588 + return sysfs_emit(buf, "%d\n", adc->auto_zeroing_ref); 589 + } 590 + 591 + static ssize_t mcp3564_auto_zeroing_ref_store(struct device *dev, 592 + struct device_attribute *attr, 593 + const char *buf, size_t len) 594 + { 595 + struct iio_dev *indio_dev = dev_to_iio_dev(dev); 596 + struct mcp3564_state *adc = iio_priv(indio_dev); 597 + bool auto_zero; 598 + int ret; 599 + 600 + ret = kstrtobool(buf, &auto_zero); 601 + if (ret) 602 + return ret; 603 + 604 + mutex_lock(&adc->lock); 605 + ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, MCP3564_CONFIG2_AZ_REF_MASK, 606 + FIELD_PREP(MCP3564_CONFIG2_AZ_REF_MASK, auto_zero)); 607 + 608 + if (ret) 609 + dev_err(&indio_dev->dev, "Failed to update CONFIG2 register\n"); 610 + else 611 + adc->auto_zeroing_ref = auto_zero; 612 + 613 + mutex_unlock(&adc->lock); 614 + 615 + return ret ? ret : len; 616 + } 617 + 618 + static const struct iio_chan_spec mcp3564_channel_template = { 619 + .type = IIO_VOLTAGE, 620 + .indexed = 1, 621 + .differential = 1, 622 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 623 + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | 624 + BIT(IIO_CHAN_INFO_CALIBSCALE) | 625 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 626 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 627 + .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SCALE) | 628 + BIT(IIO_CHAN_INFO_CALIBSCALE) | 629 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 630 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 631 + .ext_info = mcp3564_ext_info, 632 + }; 633 + 634 + static const struct iio_chan_spec mcp3564_temp_channel_template = { 635 + .type = IIO_TEMP, 636 + .channel = 0, 637 + .address = ((MCP3564_TEMP_DIODE_P << 4) | MCP3564_TEMP_DIODE_M), 638 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 639 + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | 640 + BIT(IIO_CHAN_INFO_CALIBSCALE) | 641 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 642 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 643 + .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SCALE) | 644 + BIT(IIO_CHAN_INFO_CALIBSCALE) | 645 + BIT(IIO_CHAN_INFO_CALIBBIAS) | 646 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 647 + }; 648 + 649 + static const struct iio_chan_spec mcp3564_burnout_channel_template = { 650 + .type = IIO_CURRENT, 651 + .output = true, 652 + .channel = 0, 653 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 654 + .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), 655 + }; 656 + 657 + /* 658 + * Number of channels could be calculated: 659 + * num_channels = single_ended_input + differential_input + temperature + burnout 660 + * Eg. for MCP3561 (only 2 channels available: CH0 and CH1) 661 + * single_ended_input = (CH0 - GND), (CH1 - GND) = 2 662 + * differential_input = (CH0 - CH1), (CH0 - CH0) = 2 663 + * num_channels = 2 + 2 + 2 664 + * Generic formula is: 665 + * num_channels = P^R(Number_of_single_ended_channels, 2) + 2 (temperature + burnout channels) 666 + * P^R(Number_of_single_ended_channels, 2) is Permutations with Replacement of 667 + * Number_of_single_ended_channels taken by 2 668 + */ 669 + static const struct mcp3564_chip_info mcp3564_chip_infos_tbl[] = { 670 + [mcp3461] = { 671 + .name = "mcp3461", 672 + .num_channels = 6, 673 + .resolution = 16, 674 + .have_vref = false, 675 + }, 676 + [mcp3462] = { 677 + .name = "mcp3462", 678 + .num_channels = 18, 679 + .resolution = 16, 680 + .have_vref = false, 681 + }, 682 + [mcp3464] = { 683 + .name = "mcp3464", 684 + .num_channels = 66, 685 + .resolution = 16, 686 + .have_vref = false, 687 + }, 688 + [mcp3561] = { 689 + .name = "mcp3561", 690 + .num_channels = 6, 691 + .resolution = 24, 692 + .have_vref = false, 693 + }, 694 + [mcp3562] = { 695 + .name = "mcp3562", 696 + .num_channels = 18, 697 + .resolution = 24, 698 + .have_vref = false, 699 + }, 700 + [mcp3564] = { 701 + .name = "mcp3564", 702 + .num_channels = 66, 703 + .resolution = 24, 704 + .have_vref = false, 705 + }, 706 + [mcp3461r] = { 707 + .name = "mcp3461r", 708 + .num_channels = 6, 709 + .resolution = 16, 710 + .have_vref = false, 711 + }, 712 + [mcp3462r] = { 713 + .name = "mcp3462r", 714 + .num_channels = 18, 715 + .resolution = 16, 716 + .have_vref = true, 717 + }, 718 + [mcp3464r] = { 719 + .name = "mcp3464r", 720 + .num_channels = 66, 721 + .resolution = 16, 722 + .have_vref = true, 723 + }, 724 + [mcp3561r] = { 725 + .name = "mcp3561r", 726 + .num_channels = 6, 727 + .resolution = 24, 728 + .have_vref = true, 729 + }, 730 + [mcp3562r] = { 731 + .name = "mcp3562r", 732 + .num_channels = 18, 733 + .resolution = 24, 734 + .have_vref = true, 735 + }, 736 + [mcp3564r] = { 737 + .name = "mcp3564r", 738 + .num_channels = 66, 739 + .resolution = 24, 740 + .have_vref = true, 741 + }, 742 + }; 743 + 744 + static int mcp3564_read_single_value(struct iio_dev *indio_dev, 745 + struct iio_chan_spec const *channel, 746 + int *val) 747 + { 748 + struct mcp3564_state *adc = iio_priv(indio_dev); 749 + int ret; 750 + u8 tmp; 751 + int ret_read = 0; 752 + 753 + ret = mcp3564_write_8bits(adc, MCP3564_MUX_REG, channel->address); 754 + if (ret) 755 + return ret; 756 + 757 + /* Start ADC Conversion using fast command (overwrites ADC_MODE[1:0] = 11) */ 758 + ret = mcp3564_fast_cmd(adc, MCP3564_FASTCMD_START); 759 + if (ret) 760 + return ret; 761 + 762 + /* 763 + * Check if the conversion is ready. If not, wait a little bit, and 764 + * in case of timeout exit with an error. 765 + */ 766 + ret = read_poll_timeout(mcp3564_read_8bits, ret_read, 767 + ret_read || !(tmp & MCP3564_DATA_READY_MASK), 768 + 20000, MCP3564_DATA_READY_TIMEOUT_MS * 1000, true, 769 + adc, MCP3564_IRQ_REG, &tmp); 770 + 771 + /* failed to read status register */ 772 + if (ret_read) 773 + return ret_read; 774 + 775 + if (ret) 776 + return ret; 777 + 778 + if (tmp & MCP3564_DATA_READY_MASK) 779 + /* failing to finish conversion */ 780 + return -EBUSY; 781 + 782 + return mcp3564_read_32bits(adc, MCP3564_ADCDATA_REG, val); 783 + } 784 + 785 + static int mcp3564_read_avail(struct iio_dev *indio_dev, 786 + struct iio_chan_spec const *channel, 787 + const int **vals, int *type, 788 + int *length, long mask) 789 + { 790 + struct mcp3564_state *adc = iio_priv(indio_dev); 791 + 792 + switch (mask) { 793 + case IIO_CHAN_INFO_RAW: 794 + if (!channel->output) 795 + return -EINVAL; 796 + 797 + *vals = mcp3564_burnout_avail[0]; 798 + *length = ARRAY_SIZE(mcp3564_burnout_avail) * 2; 799 + *type = IIO_VAL_INT_PLUS_MICRO; 800 + return IIO_AVAIL_LIST; 801 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 802 + *vals = mcp3564_oversampling_avail; 803 + *length = ARRAY_SIZE(mcp3564_oversampling_avail); 804 + *type = IIO_VAL_INT; 805 + return IIO_AVAIL_LIST; 806 + case IIO_CHAN_INFO_SCALE: 807 + *vals = (int *)adc->scale_tbls; 808 + *length = ARRAY_SIZE(adc->scale_tbls) * 2; 809 + *type = IIO_VAL_INT_PLUS_NANO; 810 + return IIO_AVAIL_LIST; 811 + case IIO_CHAN_INFO_CALIBBIAS: 812 + *vals = mcp3564_calib_bias; 813 + *type = IIO_VAL_INT; 814 + return IIO_AVAIL_RANGE; 815 + case IIO_CHAN_INFO_CALIBSCALE: 816 + *vals = mcp3564_calib_scale; 817 + *type = IIO_VAL_INT; 818 + return IIO_AVAIL_RANGE; 819 + default: 820 + return -EINVAL; 821 + } 822 + } 823 + 824 + static int mcp3564_read_raw(struct iio_dev *indio_dev, 825 + struct iio_chan_spec const *channel, 826 + int *val, int *val2, long mask) 827 + { 828 + struct mcp3564_state *adc = iio_priv(indio_dev); 829 + int ret; 830 + 831 + switch (mask) { 832 + case IIO_CHAN_INFO_RAW: 833 + if (channel->output) { 834 + mutex_lock(&adc->lock); 835 + *val = mcp3564_burnout_avail[adc->burnout_mode][0]; 836 + *val2 = mcp3564_burnout_avail[adc->burnout_mode][1]; 837 + mutex_unlock(&adc->lock); 838 + return IIO_VAL_INT_PLUS_MICRO; 839 + } 840 + 841 + ret = mcp3564_read_single_value(indio_dev, channel, val); 842 + if (ret) 843 + return -EINVAL; 844 + return IIO_VAL_INT; 845 + case IIO_CHAN_INFO_SCALE: 846 + mutex_lock(&adc->lock); 847 + *val = adc->scale_tbls[adc->hwgain][0]; 848 + *val2 = adc->scale_tbls[adc->hwgain][1]; 849 + mutex_unlock(&adc->lock); 850 + return IIO_VAL_INT_PLUS_NANO; 851 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 852 + *val = mcp3564_oversampling_avail[adc->oversampling]; 853 + return IIO_VAL_INT; 854 + case IIO_CHAN_INFO_CALIBBIAS: 855 + *val = adc->calib_bias; 856 + return IIO_VAL_INT; 857 + case IIO_CHAN_INFO_CALIBSCALE: 858 + *val = adc->calib_scale; 859 + return IIO_VAL_INT; 860 + default: 861 + return -EINVAL; 862 + } 863 + } 864 + 865 + static int mcp3564_write_raw_get_fmt(struct iio_dev *indio_dev, 866 + struct iio_chan_spec const *chan, 867 + long info) 868 + { 869 + switch (info) { 870 + case IIO_CHAN_INFO_RAW: 871 + return IIO_VAL_INT_PLUS_MICRO; 872 + case IIO_CHAN_INFO_CALIBBIAS: 873 + case IIO_CHAN_INFO_CALIBSCALE: 874 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 875 + return IIO_VAL_INT; 876 + case IIO_CHAN_INFO_SCALE: 877 + return IIO_VAL_INT_PLUS_NANO; 878 + default: 879 + return -EINVAL; 880 + } 881 + } 882 + 883 + static int mcp3564_write_raw(struct iio_dev *indio_dev, 884 + struct iio_chan_spec const *channel, int val, 885 + int val2, long mask) 886 + { 887 + struct mcp3564_state *adc = iio_priv(indio_dev); 888 + int tmp; 889 + unsigned int hwgain; 890 + enum mcp3564_burnout burnout; 891 + int ret = 0; 892 + 893 + switch (mask) { 894 + case IIO_CHAN_INFO_RAW: 895 + if (!channel->output) 896 + return -EINVAL; 897 + 898 + for (burnout = 0; burnout < MCP3564_MAX_BURNOUT_IDX; burnout++) 899 + if (val == mcp3564_burnout_avail[burnout][0] && 900 + val2 == mcp3564_burnout_avail[burnout][1]) 901 + break; 902 + 903 + if (burnout == MCP3564_MAX_BURNOUT_IDX) 904 + return -EINVAL; 905 + 906 + if (burnout == adc->burnout_mode) 907 + return ret; 908 + 909 + mutex_lock(&adc->lock); 910 + ret = mcp3564_update_8bits(adc, MCP3564_CONFIG0_REG, 911 + MCP3564_CONFIG0_CS_SEL_MASK, 912 + FIELD_PREP(MCP3564_CONFIG0_CS_SEL_MASK, burnout)); 913 + 914 + if (ret) 915 + dev_err(&indio_dev->dev, "Failed to configure burnout current\n"); 916 + else 917 + adc->burnout_mode = burnout; 918 + mutex_unlock(&adc->lock); 919 + return ret; 920 + case IIO_CHAN_INFO_CALIBBIAS: 921 + if (val < mcp3564_calib_bias[0] && val > mcp3564_calib_bias[2]) 922 + return -EINVAL; 923 + 924 + mutex_lock(&adc->lock); 925 + ret = mcp3564_write_24bits(adc, MCP3564_OFFSETCAL_REG, val); 926 + if (!ret) 927 + adc->calib_bias = val; 928 + mutex_unlock(&adc->lock); 929 + return ret; 930 + case IIO_CHAN_INFO_CALIBSCALE: 931 + if (val < mcp3564_calib_scale[0] && val > mcp3564_calib_scale[2]) 932 + return -EINVAL; 933 + 934 + if (adc->calib_scale == val) 935 + return ret; 936 + 937 + mutex_lock(&adc->lock); 938 + ret = mcp3564_write_24bits(adc, MCP3564_GAINCAL_REG, val); 939 + if (!ret) 940 + adc->calib_scale = val; 941 + mutex_unlock(&adc->lock); 942 + return ret; 943 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 944 + if (val < 0) 945 + return -EINVAL; 946 + 947 + tmp = find_closest(val, mcp3564_oversampling_avail, 948 + ARRAY_SIZE(mcp3564_oversampling_avail)); 949 + 950 + if (adc->oversampling == tmp) 951 + return ret; 952 + 953 + mutex_lock(&adc->lock); 954 + ret = mcp3564_update_8bits(adc, MCP3564_CONFIG1_REG, 955 + MCP3564_CONFIG1_OVERSPL_RATIO_MASK, 956 + FIELD_PREP(MCP3564_CONFIG1_OVERSPL_RATIO_MASK, 957 + adc->oversampling)); 958 + if (!ret) 959 + adc->oversampling = tmp; 960 + mutex_unlock(&adc->lock); 961 + return ret; 962 + case IIO_CHAN_INFO_SCALE: 963 + for (hwgain = 0; hwgain < MCP3564_MAX_PGA; hwgain++) 964 + if (val == adc->scale_tbls[hwgain][0] && 965 + val2 == adc->scale_tbls[hwgain][1]) 966 + break; 967 + 968 + if (hwgain == MCP3564_MAX_PGA) 969 + return -EINVAL; 970 + 971 + if (hwgain == adc->hwgain) 972 + return ret; 973 + 974 + mutex_lock(&adc->lock); 975 + ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, 976 + MCP3564_CONFIG2_HARDWARE_GAIN_MASK, 977 + FIELD_PREP(MCP3564_CONFIG2_HARDWARE_GAIN_MASK, hwgain)); 978 + if (!ret) 979 + adc->hwgain = hwgain; 980 + 981 + mutex_unlock(&adc->lock); 982 + return ret; 983 + default: 984 + return -EINVAL; 985 + } 986 + } 987 + 988 + static int mcp3564_read_label(struct iio_dev *indio_dev, 989 + struct iio_chan_spec const *chan, char *label) 990 + { 991 + struct mcp3564_state *adc = iio_priv(indio_dev); 992 + 993 + return sprintf(label, "%s\n", adc->labels[chan->scan_index]); 994 + } 995 + 996 + static int mcp3564_parse_fw_children(struct iio_dev *indio_dev) 997 + { 998 + struct mcp3564_state *adc = iio_priv(indio_dev); 999 + struct device *dev = &adc->spi->dev; 1000 + struct iio_chan_spec *channels; 1001 + struct fwnode_handle *child; 1002 + struct iio_chan_spec chanspec = mcp3564_channel_template; 1003 + struct iio_chan_spec temp_chanspec = mcp3564_temp_channel_template; 1004 + struct iio_chan_spec burnout_chanspec = mcp3564_burnout_channel_template; 1005 + int chan_idx = 0; 1006 + unsigned int num_ch; 1007 + u32 inputs[2]; 1008 + const char *node_name; 1009 + const char *label; 1010 + int ret; 1011 + 1012 + num_ch = device_get_child_node_count(dev); 1013 + if (num_ch == 0) 1014 + return dev_err_probe(&indio_dev->dev, -ENODEV, 1015 + "FW has no channels defined\n"); 1016 + 1017 + /* Reserve space for burnout and temperature channel */ 1018 + num_ch += 2; 1019 + 1020 + if (num_ch > adc->chip_info->num_channels) 1021 + return dev_err_probe(dev, -EINVAL, "Too many channels %d > %d\n", 1022 + num_ch, adc->chip_info->num_channels); 1023 + 1024 + channels = devm_kcalloc(dev, num_ch, sizeof(*channels), GFP_KERNEL); 1025 + if (!channels) 1026 + return dev_err_probe(dev, -ENOMEM, "Can't allocate memory\n"); 1027 + 1028 + device_for_each_child_node(dev, child) { 1029 + node_name = fwnode_get_name(child); 1030 + 1031 + if (fwnode_property_present(child, "diff-channels")) { 1032 + ret = fwnode_property_read_u32_array(child, 1033 + "diff-channels", 1034 + inputs, 1035 + ARRAY_SIZE(inputs)); 1036 + chanspec.differential = 1; 1037 + } else { 1038 + ret = fwnode_property_read_u32(child, "reg", &inputs[0]); 1039 + 1040 + chanspec.differential = 0; 1041 + inputs[1] = MCP3564_AGND; 1042 + } 1043 + if (ret) { 1044 + fwnode_handle_put(child); 1045 + return ret; 1046 + } 1047 + 1048 + if (inputs[0] > MCP3564_INTERNAL_VCM || 1049 + inputs[1] > MCP3564_INTERNAL_VCM) { 1050 + fwnode_handle_put(child); 1051 + return dev_err_probe(&indio_dev->dev, -EINVAL, 1052 + "Channel index > %d, for %s\n", 1053 + MCP3564_INTERNAL_VCM + 1, 1054 + node_name); 1055 + } 1056 + 1057 + chanspec.address = (inputs[0] << 4) | inputs[1]; 1058 + chanspec.channel = inputs[0]; 1059 + chanspec.channel2 = inputs[1]; 1060 + chanspec.scan_index = chan_idx; 1061 + 1062 + if (fwnode_property_present(child, "label")) { 1063 + fwnode_property_read_string(child, "label", &label); 1064 + adc->labels[chan_idx] = label; 1065 + } 1066 + 1067 + channels[chan_idx] = chanspec; 1068 + chan_idx++; 1069 + } 1070 + 1071 + /* Add burnout current channel */ 1072 + burnout_chanspec.scan_index = chan_idx; 1073 + channels[chan_idx] = burnout_chanspec; 1074 + adc->labels[chan_idx] = mcp3564_channel_labels[0]; 1075 + chanspec.scan_index = chan_idx; 1076 + chan_idx++; 1077 + 1078 + /* Add temperature channel */ 1079 + temp_chanspec.scan_index = chan_idx; 1080 + channels[chan_idx] = temp_chanspec; 1081 + adc->labels[chan_idx] = mcp3564_channel_labels[1]; 1082 + chan_idx++; 1083 + 1084 + indio_dev->num_channels = chan_idx; 1085 + indio_dev->channels = channels; 1086 + 1087 + return 0; 1088 + } 1089 + 1090 + static void mcp3564_disable_reg(void *reg) 1091 + { 1092 + regulator_disable(reg); 1093 + } 1094 + 1095 + static void mcp3564_fill_scale_tbls(struct mcp3564_state *adc) 1096 + { 1097 + unsigned int pow = adc->chip_info->resolution - 1; 1098 + int ref; 1099 + unsigned int i; 1100 + int tmp0; 1101 + u64 tmp1; 1102 + 1103 + for (i = 0; i < MCP3564_MAX_PGA; i++) { 1104 + ref = adc->vref_mv; 1105 + tmp1 = ((u64)ref * NANO) >> pow; 1106 + div_u64_rem(tmp1, NANO, &tmp0); 1107 + 1108 + tmp1 = tmp1 * mcp3564_hwgain_frac[(2 * i) + 1]; 1109 + tmp0 = (int)div_u64(tmp1, mcp3564_hwgain_frac[2 * i]); 1110 + 1111 + adc->scale_tbls[i][1] = tmp0; 1112 + } 1113 + } 1114 + 1115 + static int mcp3564_config(struct iio_dev *indio_dev) 1116 + { 1117 + struct mcp3564_state *adc = iio_priv(indio_dev); 1118 + struct device *dev = &adc->spi->dev; 1119 + const struct spi_device_id *dev_id; 1120 + u8 tmp_reg; 1121 + u16 tmp_u16; 1122 + enum mcp3564_ids ids; 1123 + int ret = 0; 1124 + unsigned int tmp = 0x01; 1125 + bool err = true; 1126 + 1127 + /* 1128 + * The address is set on a per-device basis by fuses in the factory, 1129 + * configured on request. If not requested, the fuses are set for 0x1. 1130 + * The device address is part of the device markings to avoid 1131 + * potential confusion. This address is coded on two bits, so four possible 1132 + * addresses are available when multiple devices are present on the same 1133 + * SPI bus with only one Chip Select line for all devices. 1134 + */ 1135 + device_property_read_u32(dev, "microchip,hw-device-address", &tmp); 1136 + 1137 + if (tmp > 3) { 1138 + dev_err_probe(dev, tmp, 1139 + "invalid device address. Must be in range 0-3.\n"); 1140 + return -EINVAL; 1141 + } 1142 + 1143 + adc->dev_addr = FIELD_GET(MCP3564_HW_ADDR_MASK, tmp); 1144 + 1145 + dev_dbg(dev, "use HW device address %i\n", adc->dev_addr); 1146 + 1147 + ret = mcp3564_read_8bits(adc, MCP3564_RESERVED_C_REG, &tmp_reg); 1148 + if (ret < 0) 1149 + return ret; 1150 + 1151 + switch (tmp_reg) { 1152 + case MCP3564_C_REG_DEFAULT: 1153 + adc->have_vref = false; 1154 + break; 1155 + case MCP3564R_C_REG_DEFAULT: 1156 + adc->have_vref = true; 1157 + break; 1158 + default: 1159 + dev_info(dev, "Unknown chip found: %d\n", tmp_reg); 1160 + err = true; 1161 + } 1162 + 1163 + if (!err) { 1164 + ret = mcp3564_read_16bits(adc, MCP3564_RESERVED_E_REG, &tmp_u16); 1165 + if (ret < 0) 1166 + return ret; 1167 + 1168 + switch (tmp_u16 & MCP3564_HW_ID_MASK) { 1169 + case MCP3461_HW_ID: 1170 + if (adc->have_vref) 1171 + ids = mcp3461r; 1172 + else 1173 + ids = mcp3461; 1174 + break; 1175 + case MCP3462_HW_ID: 1176 + if (adc->have_vref) 1177 + ids = mcp3462r; 1178 + else 1179 + ids = mcp3462; 1180 + break; 1181 + case MCP3464_HW_ID: 1182 + if (adc->have_vref) 1183 + ids = mcp3464r; 1184 + else 1185 + ids = mcp3464; 1186 + break; 1187 + case MCP3561_HW_ID: 1188 + if (adc->have_vref) 1189 + ids = mcp3561r; 1190 + else 1191 + ids = mcp3561; 1192 + break; 1193 + case MCP3562_HW_ID: 1194 + if (adc->have_vref) 1195 + ids = mcp3562r; 1196 + else 1197 + ids = mcp3562; 1198 + break; 1199 + case MCP3564_HW_ID: 1200 + if (adc->have_vref) 1201 + ids = mcp3564r; 1202 + else 1203 + ids = mcp3564; 1204 + break; 1205 + default: 1206 + dev_info(dev, "Unknown chip found: %d\n", tmp_u16); 1207 + err = true; 1208 + } 1209 + } 1210 + 1211 + if (err) { 1212 + /* 1213 + * If failed to identify the hardware based on internal registers, 1214 + * try using fallback compatible in device tree to deal with some newer part number. 1215 + */ 1216 + adc->chip_info = spi_get_device_match_data(adc->spi); 1217 + if (!adc->chip_info) { 1218 + dev_id = spi_get_device_id(adc->spi); 1219 + adc->chip_info = (const struct mcp3564_chip_info *)dev_id->driver_data; 1220 + } 1221 + 1222 + adc->have_vref = adc->chip_info->have_vref; 1223 + } else { 1224 + adc->chip_info = &mcp3564_chip_infos_tbl[ids]; 1225 + } 1226 + 1227 + dev_dbg(dev, "Found %s chip\n", adc->chip_info->name); 1228 + 1229 + adc->vref = devm_regulator_get_optional(dev, "vref"); 1230 + if (IS_ERR(adc->vref)) { 1231 + if (PTR_ERR(adc->vref) != -ENODEV) 1232 + return dev_err_probe(dev, PTR_ERR(adc->vref), 1233 + "failed to get regulator\n"); 1234 + 1235 + /* Check if chip has internal vref */ 1236 + if (!adc->have_vref) 1237 + return dev_err_probe(dev, PTR_ERR(adc->vref), 1238 + "Unknown Vref\n"); 1239 + adc->vref = NULL; 1240 + dev_dbg(dev, "%s: Using internal Vref\n", __func__); 1241 + } else { 1242 + ret = regulator_enable(adc->vref); 1243 + if (ret) 1244 + return ret; 1245 + 1246 + ret = devm_add_action_or_reset(dev, mcp3564_disable_reg, 1247 + adc->vref); 1248 + if (ret) 1249 + return ret; 1250 + 1251 + dev_dbg(dev, "%s: Using External Vref\n", __func__); 1252 + 1253 + ret = regulator_get_voltage(adc->vref); 1254 + if (ret < 0) 1255 + return dev_err_probe(dev, ret, 1256 + "Failed to read vref regulator\n"); 1257 + 1258 + adc->vref_mv = ret / MILLI; 1259 + } 1260 + 1261 + ret = mcp3564_parse_fw_children(indio_dev); 1262 + if (ret) 1263 + return ret; 1264 + 1265 + /* 1266 + * Command sequence that ensures a recovery with the desired settings 1267 + * in any cases of loss-of-power scenario (Full Chip Reset): 1268 + * - Write LOCK register to 0xA5 1269 + * - Write IRQ register to 0x03 1270 + * - Send "Device Full Reset" fast command 1271 + * - Wait 1ms for "Full Reset" to complete 1272 + */ 1273 + ret = mcp3564_write_8bits(adc, MCP3564_LOCK_REG, MCP3564_LOCK_WRITE_ACCESS_PASSWORD); 1274 + if (ret) 1275 + return ret; 1276 + 1277 + ret = mcp3564_write_8bits(adc, MCP3564_IRQ_REG, 0x03); 1278 + if (ret) 1279 + return ret; 1280 + 1281 + ret = mcp3564_fast_cmd(adc, MCP3564_FASTCMD_RESET); 1282 + if (ret) 1283 + return ret; 1284 + 1285 + /* 1286 + * After Full reset wait some time to be able to fully reset the part and place 1287 + * it back in a default configuration. 1288 + * From datasheet: POR (Power On Reset Time) is ~1us 1289 + * 1ms should be enough. 1290 + */ 1291 + mdelay(1); 1292 + 1293 + /* set a gain of 1x for GAINCAL */ 1294 + ret = mcp3564_write_24bits(adc, MCP3564_GAINCAL_REG, MCP3564_DEFAULT_GAINCAL); 1295 + if (ret) 1296 + return ret; 1297 + 1298 + adc->calib_scale = MCP3564_DEFAULT_GAINCAL; 1299 + 1300 + ret = mcp3564_write_24bits(adc, MCP3564_OFFSETCAL_REG, MCP3564_DEFAULT_OFFSETCAL); 1301 + if (ret) 1302 + return ret; 1303 + 1304 + ret = mcp3564_write_24bits(adc, MCP3564_TIMER_REG, MCP3564_TIMER_DEFAULT_VALUE); 1305 + if (ret) 1306 + return ret; 1307 + 1308 + ret = mcp3564_write_24bits(adc, MCP3564_SCAN_REG, 1309 + MCP3564_SCAN_DELAY_TIME_SET(MCP3564_NO_DELAY) | 1310 + MCP3564_SCAN_CH_SEL_SET(MCP3564_SCAN_DEFAULT_VALUE)); 1311 + if (ret) 1312 + return ret; 1313 + 1314 + ret = mcp3564_write_8bits(adc, MCP3564_MUX_REG, MCP3564_MUX_SET(MCP3564_CH0, MCP3564_CH1)); 1315 + if (ret) 1316 + return ret; 1317 + 1318 + ret = mcp3564_write_8bits(adc, MCP3564_IRQ_REG, 1319 + FIELD_PREP(MCP3464_EN_FASTCMD_MASK, 1) | 1320 + FIELD_PREP(MCP3464_EN_STP_MASK, 1)); 1321 + if (ret) 1322 + return ret; 1323 + 1324 + tmp_reg = FIELD_PREP(MCP3464_CONFIG3_CONV_MODE_MASK, 1325 + MCP3464_CONFIG3_CONV_MODE_ONE_SHOT_STANDBY); 1326 + tmp_reg |= FIELD_PREP(MCP3464_CONFIG3_DATA_FORMAT_MASK, 1327 + MCP3464_CONFIG3_DATA_FMT_32B_SGN_EXT); 1328 + tmp_reg |= MCP3464_CONFIG3_EN_OFFCAL_MASK; 1329 + tmp_reg |= MCP3464_CONFIG3_EN_GAINCAL_MASK; 1330 + 1331 + ret = mcp3564_write_8bits(adc, MCP3564_CONFIG3_REG, tmp_reg); 1332 + if (ret) 1333 + return ret; 1334 + 1335 + tmp_reg = FIELD_PREP(MCP3564_CONFIG2_BOOST_CURRENT_MASK, MCP3564_BOOST_CURRENT_x1_00); 1336 + tmp_reg |= FIELD_PREP(MCP3564_CONFIG2_HARDWARE_GAIN_MASK, 0x01); 1337 + tmp_reg |= FIELD_PREP(MCP3564_CONFIG2_AZ_MUX_MASK, 1); 1338 + 1339 + ret = mcp3564_write_8bits(adc, MCP3564_CONFIG2_REG, tmp_reg); 1340 + if (ret) 1341 + return ret; 1342 + 1343 + adc->hwgain = 0x01; 1344 + adc->auto_zeroing_mux = true; 1345 + adc->auto_zeroing_ref = false; 1346 + adc->current_boost_mode = MCP3564_BOOST_CURRENT_x1_00; 1347 + 1348 + tmp_reg = FIELD_PREP(MCP3564_CONFIG1_OVERSPL_RATIO_MASK, MCP3564_OVERSAMPLING_RATIO_98304); 1349 + 1350 + ret = mcp3564_write_8bits(adc, MCP3564_CONFIG1_REG, tmp_reg); 1351 + if (ret) 1352 + return ret; 1353 + 1354 + adc->oversampling = MCP3564_OVERSAMPLING_RATIO_98304; 1355 + 1356 + tmp_reg = FIELD_PREP(MCP3564_CONFIG0_ADC_MODE_MASK, MCP3564_ADC_MODE_STANDBY); 1357 + tmp_reg |= FIELD_PREP(MCP3564_CONFIG0_CS_SEL_MASK, MCP3564_CONFIG0_CS_SEL_0_0_uA); 1358 + tmp_reg |= FIELD_PREP(MCP3564_CONFIG0_CLK_SEL_MASK, MCP3564_CONFIG0_USE_INT_CLK); 1359 + tmp_reg |= MCP3456_CONFIG0_BIT6_DEFAULT; 1360 + 1361 + if (!adc->vref) { 1362 + tmp_reg |= FIELD_PREP(MCP3456_CONFIG0_VREF_MASK, 1); 1363 + adc->vref_mv = MCP3564R_INT_VREF_MV; 1364 + } 1365 + 1366 + ret = mcp3564_write_8bits(adc, MCP3564_CONFIG0_REG, tmp_reg); 1367 + 1368 + adc->burnout_mode = MCP3564_CONFIG0_CS_SEL_0_0_uA; 1369 + 1370 + return ret; 1371 + } 1372 + 1373 + static IIO_DEVICE_ATTR(auto_zeroing_ref_enable, 0644, 1374 + mcp3564_auto_zeroing_ref_show, 1375 + mcp3564_auto_zeroing_ref_store, 0); 1376 + 1377 + static IIO_DEVICE_ATTR(auto_zeroing_mux_enable, 0644, 1378 + mcp3564_auto_zeroing_mux_show, 1379 + mcp3564_auto_zeroing_mux_store, 0); 1380 + 1381 + static struct attribute *mcp3564_attributes[] = { 1382 + &iio_dev_attr_auto_zeroing_mux_enable.dev_attr.attr, 1383 + NULL 1384 + }; 1385 + 1386 + static struct attribute *mcp3564r_attributes[] = { 1387 + &iio_dev_attr_auto_zeroing_mux_enable.dev_attr.attr, 1388 + &iio_dev_attr_auto_zeroing_ref_enable.dev_attr.attr, 1389 + NULL 1390 + }; 1391 + 1392 + static struct attribute_group mcp3564_attribute_group = { 1393 + .attrs = mcp3564_attributes, 1394 + }; 1395 + 1396 + static struct attribute_group mcp3564r_attribute_group = { 1397 + .attrs = mcp3564r_attributes, 1398 + }; 1399 + 1400 + static const struct iio_info mcp3564_info = { 1401 + .read_raw = mcp3564_read_raw, 1402 + .read_avail = mcp3564_read_avail, 1403 + .write_raw = mcp3564_write_raw, 1404 + .write_raw_get_fmt = mcp3564_write_raw_get_fmt, 1405 + .read_label = mcp3564_read_label, 1406 + .attrs = &mcp3564_attribute_group, 1407 + }; 1408 + 1409 + static const struct iio_info mcp3564r_info = { 1410 + .read_raw = mcp3564_read_raw, 1411 + .read_avail = mcp3564_read_avail, 1412 + .write_raw = mcp3564_write_raw, 1413 + .write_raw_get_fmt = mcp3564_write_raw_get_fmt, 1414 + .read_label = mcp3564_read_label, 1415 + .attrs = &mcp3564r_attribute_group, 1416 + }; 1417 + 1418 + static int mcp3564_probe(struct spi_device *spi) 1419 + { 1420 + int ret; 1421 + struct iio_dev *indio_dev; 1422 + struct mcp3564_state *adc; 1423 + 1424 + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); 1425 + if (!indio_dev) 1426 + return -ENOMEM; 1427 + 1428 + adc = iio_priv(indio_dev); 1429 + adc->spi = spi; 1430 + 1431 + dev_dbg(&spi->dev, "%s: probe(spi = 0x%p)\n", __func__, spi); 1432 + 1433 + /* 1434 + * Do any chip specific initialization, e.g: 1435 + * read/write some registers 1436 + * enable/disable certain channels 1437 + * change the sampling rate to the requested value 1438 + */ 1439 + ret = mcp3564_config(indio_dev); 1440 + if (ret) 1441 + return dev_err_probe(&spi->dev, ret, 1442 + "Can't configure MCP356X device\n"); 1443 + 1444 + dev_dbg(&spi->dev, "%s: Vref (mV): %d\n", __func__, adc->vref_mv); 1445 + 1446 + mcp3564_fill_scale_tbls(adc); 1447 + 1448 + indio_dev->name = adc->chip_info->name; 1449 + indio_dev->modes = INDIO_DIRECT_MODE; 1450 + 1451 + if (!adc->vref) 1452 + indio_dev->info = &mcp3564r_info; 1453 + else 1454 + indio_dev->info = &mcp3564_info; 1455 + 1456 + mutex_init(&adc->lock); 1457 + 1458 + ret = devm_iio_device_register(&spi->dev, indio_dev); 1459 + if (ret) 1460 + return dev_err_probe(&spi->dev, ret, 1461 + "Can't register IIO device\n"); 1462 + 1463 + return 0; 1464 + } 1465 + 1466 + static const struct of_device_id mcp3564_dt_ids[] = { 1467 + { .compatible = "microchip,mcp3461", .data = &mcp3564_chip_infos_tbl[mcp3461] }, 1468 + { .compatible = "microchip,mcp3462", .data = &mcp3564_chip_infos_tbl[mcp3462] }, 1469 + { .compatible = "microchip,mcp3464", .data = &mcp3564_chip_infos_tbl[mcp3464] }, 1470 + { .compatible = "microchip,mcp3561", .data = &mcp3564_chip_infos_tbl[mcp3561] }, 1471 + { .compatible = "microchip,mcp3562", .data = &mcp3564_chip_infos_tbl[mcp3562] }, 1472 + { .compatible = "microchip,mcp3564", .data = &mcp3564_chip_infos_tbl[mcp3564] }, 1473 + { .compatible = "microchip,mcp3461r", .data = &mcp3564_chip_infos_tbl[mcp3461r] }, 1474 + { .compatible = "microchip,mcp3462r", .data = &mcp3564_chip_infos_tbl[mcp3462r] }, 1475 + { .compatible = "microchip,mcp3464r", .data = &mcp3564_chip_infos_tbl[mcp3464r] }, 1476 + { .compatible = "microchip,mcp3561r", .data = &mcp3564_chip_infos_tbl[mcp3561r] }, 1477 + { .compatible = "microchip,mcp3562r", .data = &mcp3564_chip_infos_tbl[mcp3562r] }, 1478 + { .compatible = "microchip,mcp3564r", .data = &mcp3564_chip_infos_tbl[mcp3564r] }, 1479 + { } 1480 + }; 1481 + MODULE_DEVICE_TABLE(of, mcp3564_dt_ids); 1482 + 1483 + static const struct spi_device_id mcp3564_id[] = { 1484 + { "mcp3461", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3461] }, 1485 + { "mcp3462", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3462] }, 1486 + { "mcp3464", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3464] }, 1487 + { "mcp3561", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3561] }, 1488 + { "mcp3562", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3562] }, 1489 + { "mcp3564", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3564] }, 1490 + { "mcp3461r", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3461r] }, 1491 + { "mcp3462r", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3462r] }, 1492 + { "mcp3464r", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3464r] }, 1493 + { "mcp3561r", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3561r] }, 1494 + { "mcp3562r", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3562r] }, 1495 + { "mcp3564r", (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3564r] }, 1496 + { } 1497 + }; 1498 + MODULE_DEVICE_TABLE(spi, mcp3564_id); 1499 + 1500 + static struct spi_driver mcp3564_driver = { 1501 + .driver = { 1502 + .name = "mcp3564", 1503 + .of_match_table = mcp3564_dt_ids, 1504 + }, 1505 + .probe = mcp3564_probe, 1506 + .id_table = mcp3564_id, 1507 + }; 1508 + 1509 + module_spi_driver(mcp3564_driver); 1510 + 1511 + MODULE_AUTHOR("Marius Cristea <marius.cristea@microchip.com>"); 1512 + MODULE_DESCRIPTION("Microchip MCP346x/MCP346xR and MCP356x/MCP346xR ADCs"); 1513 + MODULE_LICENSE("GPL v2");

+452 -110

drivers/iio/adc/mcp3911.c

··· 29 29 #define MCP3911_REG_MOD 0x06 30 30 #define MCP3911_REG_PHASE 0x07 31 31 #define MCP3911_REG_GAIN 0x09 32 - #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * ch) 33 - #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * ch) & MCP3911_GAIN_MASK(ch)) 32 + #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch)) 33 + #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch)) 34 34 35 35 #define MCP3911_REG_STATUSCOM 0x0a 36 - #define MCP3911_STATUSCOM_DRHIZ BIT(12) 36 + #define MCP3911_STATUSCOM_DRHIZ BIT(12) 37 37 #define MCP3911_STATUSCOM_READ GENMASK(7, 6) 38 38 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) 39 39 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) ··· 51 51 #define MCP3911_REG_GAINCAL_CH1 0x17 52 52 #define MCP3911_REG_VREFCAL 0x1a 53 53 54 - #define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3) 55 - #define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6) 54 + #define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3) 55 + #define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6) 56 56 57 57 /* Internal voltage reference in mV */ 58 58 #define MCP3911_INT_VREF_MV 1200 ··· 61 61 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff) 62 62 #define MCP3911_REG_MASK GENMASK(4, 1) 63 63 64 - #define MCP3911_NUM_CHANNELS 2 65 64 #define MCP3911_NUM_SCALES 6 65 + 66 + /* Registers compatible with MCP3910 */ 67 + #define MCP3910_REG_STATUSCOM 0x0c 68 + #define MCP3910_STATUSCOM_READ GENMASK(23, 22) 69 + #define MCP3910_STATUSCOM_DRHIZ BIT(20) 70 + 71 + #define MCP3910_REG_GAIN 0x0b 72 + 73 + #define MCP3910_REG_CONFIG0 0x0d 74 + #define MCP3910_CONFIG0_EN_OFFCAL BIT(23) 75 + #define MCP3910_CONFIG0_OSR GENMASK(15, 13) 76 + 77 + #define MCP3910_REG_CONFIG1 0x0e 78 + #define MCP3910_CONFIG1_CLKEXT BIT(6) 79 + #define MCP3910_CONFIG1_VREFEXT BIT(7) 80 + 81 + #define MCP3910_REG_OFFCAL_CH0 0x0f 82 + #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6) 83 + 84 + /* Maximal number of channels used by the MCP39XX family */ 85 + #define MCP39XX_MAX_NUM_CHANNELS 8 66 86 67 87 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; 68 88 static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2]; 89 + 90 + enum mcp3911_id { 91 + MCP3910, 92 + MCP3911, 93 + MCP3912, 94 + MCP3913, 95 + MCP3914, 96 + MCP3918, 97 + MCP3919, 98 + }; 99 + 100 + struct mcp3911; 101 + struct mcp3911_chip_info { 102 + const struct iio_chan_spec *channels; 103 + unsigned int num_channels; 104 + 105 + int (*config)(struct mcp3911 *adc); 106 + int (*get_osr)(struct mcp3911 *adc, u32 *val); 107 + int (*set_osr)(struct mcp3911 *adc, u32 val); 108 + int (*enable_offset)(struct mcp3911 *adc, bool enable); 109 + int (*get_offset)(struct mcp3911 *adc, int channel, int *val); 110 + int (*set_offset)(struct mcp3911 *adc, int channel, int val); 111 + int (*set_scale)(struct mcp3911 *adc, int channel, u32 val); 112 + }; 69 113 70 114 struct mcp3911 { 71 115 struct spi_device *spi; ··· 118 74 struct clk *clki; 119 75 u32 dev_addr; 120 76 struct iio_trigger *trig; 121 - u32 gain[MCP3911_NUM_CHANNELS]; 77 + u32 gain[MCP39XX_MAX_NUM_CHANNELS]; 78 + const struct mcp3911_chip_info *chip; 122 79 struct { 123 - u32 channels[MCP3911_NUM_CHANNELS]; 80 + u32 channels[MCP39XX_MAX_NUM_CHANNELS]; 124 81 s64 ts __aligned(8); 125 82 } scan; 126 83 127 84 u8 tx_buf __aligned(IIO_DMA_MINALIGN); 128 - u8 rx_buf[MCP3911_NUM_CHANNELS * 3]; 85 + u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3]; 129 86 }; 130 87 131 88 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) ··· 156 111 return spi_write(adc->spi, &val, len + 1); 157 112 } 158 113 159 - static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, 160 - u32 val, u8 len) 114 + static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len) 161 115 { 162 116 u32 tmp; 163 117 int ret; ··· 170 126 return mcp3911_write(adc, reg, val, len); 171 127 } 172 128 129 + static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) 130 + { 131 + unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL; 132 + unsigned int value = enable ? mask : 0; 133 + 134 + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); 135 + } 136 + 137 + static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) 138 + { 139 + return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3); 140 + } 141 + 142 + static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) 143 + { 144 + int ret; 145 + 146 + ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3); 147 + if (ret) 148 + return ret; 149 + 150 + return adc->chip->enable_offset(adc, 1); 151 + } 152 + 153 + static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) 154 + { 155 + unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL; 156 + unsigned int value = enable ? mask : 0; 157 + 158 + return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2); 159 + } 160 + 161 + static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) 162 + { 163 + return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3); 164 + } 165 + 166 + static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) 167 + { 168 + int ret; 169 + 170 + ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3); 171 + if (ret) 172 + return ret; 173 + 174 + return adc->chip->enable_offset(adc, 1); 175 + } 176 + 177 + static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) 178 + { 179 + int ret; 180 + unsigned int osr; 181 + 182 + ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); 183 + if (ret) 184 + return ret; 185 + 186 + osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val); 187 + *val = 32 << osr; 188 + return 0; 189 + } 190 + 191 + static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) 192 + { 193 + unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val); 194 + unsigned int mask = MCP3910_CONFIG0_OSR; 195 + 196 + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); 197 + } 198 + 199 + static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) 200 + { 201 + unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val); 202 + unsigned int mask = MCP3911_CONFIG_OSR; 203 + 204 + return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); 205 + } 206 + 207 + static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) 208 + { 209 + int ret; 210 + unsigned int osr; 211 + 212 + ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 213 + if (ret) 214 + return ret; 215 + 216 + osr = FIELD_GET(MCP3911_CONFIG_OSR, *val); 217 + *val = 32 << osr; 218 + return ret; 219 + } 220 + 221 + static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) 222 + { 223 + return mcp3911_update(adc, MCP3910_REG_GAIN, 224 + MCP3911_GAIN_MASK(channel), 225 + MCP3911_GAIN_VAL(channel, val), 3); 226 + } 227 + 228 + static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) 229 + { 230 + return mcp3911_update(adc, MCP3911_REG_GAIN, 231 + MCP3911_GAIN_MASK(channel), 232 + MCP3911_GAIN_VAL(channel, val), 1); 233 + } 234 + 173 235 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, 174 - struct iio_chan_spec const *chan, 175 - long mask) 236 + struct iio_chan_spec const *chan, 237 + long mask) 176 238 { 177 239 switch (mask) { 178 240 case IIO_CHAN_INFO_SCALE: ··· 291 141 } 292 142 293 143 static int mcp3911_read_avail(struct iio_dev *indio_dev, 294 - struct iio_chan_spec const *chan, 295 - const int **vals, int *type, int *length, 296 - long info) 144 + struct iio_chan_spec const *chan, 145 + const int **vals, int *type, int *length, 146 + long info) 297 147 { 298 148 switch (info) { 299 149 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: ··· 332 182 break; 333 183 334 184 case IIO_CHAN_INFO_OFFSET: 335 - ret = mcp3911_read(adc, 336 - MCP3911_OFFCAL(channel->channel), val, 3); 185 + 186 + ret = adc->chip->get_offset(adc, channel->channel, val); 337 187 if (ret) 338 188 goto out; 339 189 340 190 ret = IIO_VAL_INT; 341 191 break; 342 192 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 343 - ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 193 + ret = adc->chip->get_osr(adc, val); 344 194 if (ret) 345 195 goto out; 346 196 347 - *val = FIELD_GET(MCP3911_CONFIG_OSR, *val); 348 - *val = 32 << *val; 349 197 ret = IIO_VAL_INT; 350 198 break; 351 199 ··· 360 212 } 361 213 362 214 static int mcp3911_write_raw(struct iio_dev *indio_dev, 363 - struct iio_chan_spec const *channel, int val, 364 - int val2, long mask) 215 + struct iio_chan_spec const *channel, int val, 216 + int val2, long mask) 365 217 { 366 218 struct mcp3911 *adc = iio_priv(indio_dev); 367 219 int ret = -EINVAL; ··· 371 223 case IIO_CHAN_INFO_SCALE: 372 224 for (int i = 0; i < MCP3911_NUM_SCALES; i++) { 373 225 if (val == mcp3911_scale_table[i][0] && 374 - val2 == mcp3911_scale_table[i][1]) { 226 + val2 == mcp3911_scale_table[i][1]) { 375 227 376 228 adc->gain[channel->channel] = BIT(i); 377 - ret = mcp3911_update(adc, MCP3911_REG_GAIN, 378 - MCP3911_GAIN_MASK(channel->channel), 379 - MCP3911_GAIN_VAL(channel->channel, i), 1); 229 + ret = adc->chip->set_scale(adc, channel->channel, i); 380 230 } 381 231 } 382 232 break; ··· 384 238 goto out; 385 239 } 386 240 387 - /* Write offset */ 388 - ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val, 389 - 3); 390 - if (ret) 391 - goto out; 392 - 393 - /* Enable offset*/ 394 - ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, 395 - MCP3911_STATUSCOM_EN_OFFCAL, 396 - MCP3911_STATUSCOM_EN_OFFCAL, 2); 241 + ret = adc->chip->set_offset(adc, channel->channel, val); 397 242 break; 398 243 399 244 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 400 245 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) { 401 246 if (val == mcp3911_osr_table[i]) { 402 - val = FIELD_PREP(MCP3911_CONFIG_OSR, i); 403 - ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR, 404 - val, 2); 247 + ret = adc->chip->set_osr(adc, i); 405 248 break; 406 249 } 407 250 } ··· 404 269 405 270 static int mcp3911_calc_scale_table(struct mcp3911 *adc) 406 271 { 272 + struct device *dev = &adc->spi->dev; 407 273 u32 ref = MCP3911_INT_VREF_MV; 408 274 u32 div; 409 275 int ret; ··· 413 277 if (adc->vref) { 414 278 ret = regulator_get_voltage(adc->vref); 415 279 if (ret < 0) { 416 - dev_err(&adc->spi->dev, 417 - "failed to get vref voltage: %d\n", 418 - ret); 419 - return ret; 280 + return dev_err_probe(dev, ret, "failed to get vref voltage\n"); 420 281 } 421 282 422 283 ref = ret / 1000; ··· 459 326 }, \ 460 327 } 461 328 329 + static const struct iio_chan_spec mcp3910_channels[] = { 330 + MCP3911_CHAN(0), 331 + MCP3911_CHAN(1), 332 + IIO_CHAN_SOFT_TIMESTAMP(2), 333 + }; 334 + 462 335 static const struct iio_chan_spec mcp3911_channels[] = { 463 336 MCP3911_CHAN(0), 464 337 MCP3911_CHAN(1), 465 338 IIO_CHAN_SOFT_TIMESTAMP(2), 339 + }; 340 + 341 + static const struct iio_chan_spec mcp3912_channels[] = { 342 + MCP3911_CHAN(0), 343 + MCP3911_CHAN(1), 344 + MCP3911_CHAN(2), 345 + MCP3911_CHAN(3), 346 + IIO_CHAN_SOFT_TIMESTAMP(4), 347 + }; 348 + 349 + static const struct iio_chan_spec mcp3913_channels[] = { 350 + MCP3911_CHAN(0), 351 + MCP3911_CHAN(1), 352 + MCP3911_CHAN(2), 353 + MCP3911_CHAN(3), 354 + MCP3911_CHAN(4), 355 + MCP3911_CHAN(5), 356 + IIO_CHAN_SOFT_TIMESTAMP(6), 357 + }; 358 + 359 + static const struct iio_chan_spec mcp3914_channels[] = { 360 + MCP3911_CHAN(0), 361 + MCP3911_CHAN(1), 362 + MCP3911_CHAN(2), 363 + MCP3911_CHAN(3), 364 + MCP3911_CHAN(4), 365 + MCP3911_CHAN(5), 366 + MCP3911_CHAN(6), 367 + MCP3911_CHAN(7), 368 + IIO_CHAN_SOFT_TIMESTAMP(8), 369 + }; 370 + 371 + static const struct iio_chan_spec mcp3918_channels[] = { 372 + MCP3911_CHAN(0), 373 + IIO_CHAN_SOFT_TIMESTAMP(1), 374 + }; 375 + 376 + static const struct iio_chan_spec mcp3919_channels[] = { 377 + MCP3911_CHAN(0), 378 + MCP3911_CHAN(1), 379 + MCP3911_CHAN(2), 380 + IIO_CHAN_SOFT_TIMESTAMP(3), 466 381 }; 467 382 468 383 static irqreturn_t mcp3911_trigger_handler(int irq, void *p) ··· 518 337 struct iio_poll_func *pf = p; 519 338 struct iio_dev *indio_dev = pf->indio_dev; 520 339 struct mcp3911 *adc = iio_priv(indio_dev); 340 + struct device *dev = &adc->spi->dev; 521 341 struct spi_transfer xfer[] = { 522 342 { 523 343 .tx_buf = &adc->tx_buf, 524 344 .len = 1, 525 345 }, { 526 346 .rx_buf = adc->rx_buf, 527 - .len = sizeof(adc->rx_buf), 347 + .len = (adc->chip->num_channels - 1) * 3, 528 348 }, 529 349 }; 530 350 int scan_index; ··· 536 354 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); 537 355 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer)); 538 356 if (ret < 0) { 539 - dev_warn(&adc->spi->dev, 540 - "failed to get conversion data\n"); 357 + dev_warn(dev, "failed to get conversion data\n"); 541 358 goto out; 542 359 } 543 360 ··· 568 387 u32 regval; 569 388 int ret; 570 389 571 - ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 572 - 573 - /* 574 - * Fallback to "device-addr" due to historical mismatch between 575 - * dt-bindings and implementation 576 - */ 577 - if (ret) 578 - device_property_read_u32(dev, "device-addr", &adc->dev_addr); 579 - if (adc->dev_addr > 3) { 580 - dev_err(&adc->spi->dev, 581 - "invalid device address (%i). Must be in range 0-3.\n", 582 - adc->dev_addr); 583 - return -EINVAL; 584 - } 585 - dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr); 586 - 587 390 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &regval, 2); 588 391 if (ret) 589 392 return ret; 590 393 591 394 regval &= ~MCP3911_CONFIG_VREFEXT; 592 395 if (adc->vref) { 593 - dev_dbg(&adc->spi->dev, "use external voltage reference\n"); 396 + dev_dbg(dev, "use external voltage reference\n"); 594 397 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1); 595 398 } else { 596 - dev_dbg(&adc->spi->dev, 597 - "use internal voltage reference (1.2V)\n"); 399 + dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 598 400 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0); 599 401 } 600 402 601 403 regval &= ~MCP3911_CONFIG_CLKEXT; 602 404 if (adc->clki) { 603 - dev_dbg(&adc->spi->dev, "use external clock as clocksource\n"); 405 + dev_dbg(dev, "use external clock as clocksource\n"); 604 406 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1); 605 407 } else { 606 - dev_dbg(&adc->spi->dev, 607 - "use crystal oscillator as clocksource\n"); 408 + dev_dbg(dev, "use crystal oscillator as clocksource\n"); 608 409 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0); 609 410 } 610 411 ··· 602 439 regval &= ~MCP3911_STATUSCOM_READ; 603 440 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02); 604 441 605 - return mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 442 + regval &= ~MCP3911_STATUSCOM_DRHIZ; 443 + if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 444 + regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0); 445 + else 446 + regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1); 447 + 448 + /* Disable offset to ignore any old values in offset register */ 449 + regval &= ~MCP3911_STATUSCOM_EN_OFFCAL; 450 + 451 + ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 452 + if (ret) 453 + return ret; 454 + 455 + /* Set gain to 1 for all channels */ 456 + ret = mcp3911_read(adc, MCP3911_REG_GAIN, &regval, 1); 457 + if (ret) 458 + return ret; 459 + 460 + for (int i = 0; i < adc->chip->num_channels - 1; i++) { 461 + adc->gain[i] = 1; 462 + regval &= ~MCP3911_GAIN_MASK(i); 463 + } 464 + 465 + return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1); 466 + } 467 + 468 + static int mcp3910_config(struct mcp3911 *adc) 469 + { 470 + struct device *dev = &adc->spi->dev; 471 + u32 regval; 472 + int ret; 473 + 474 + ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, &regval, 3); 475 + if (ret) 476 + return ret; 477 + 478 + regval &= ~MCP3910_CONFIG1_VREFEXT; 479 + if (adc->vref) { 480 + dev_dbg(dev, "use external voltage reference\n"); 481 + regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1); 482 + } else { 483 + dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 484 + regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0); 485 + } 486 + 487 + regval &= ~MCP3910_CONFIG1_CLKEXT; 488 + if (adc->clki) { 489 + dev_dbg(dev, "use external clock as clocksource\n"); 490 + regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1); 491 + } else { 492 + dev_dbg(dev, "use crystal oscillator as clocksource\n"); 493 + regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0); 494 + } 495 + 496 + ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3); 497 + if (ret) 498 + return ret; 499 + 500 + ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, &regval, 3); 501 + if (ret) 502 + return ret; 503 + 504 + /* Address counter incremented, cycle through register types */ 505 + regval &= ~MCP3910_STATUSCOM_READ; 506 + regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02); 507 + 508 + regval &= ~MCP3910_STATUSCOM_DRHIZ; 509 + if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 510 + regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0); 511 + else 512 + regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1); 513 + 514 + ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3); 515 + if (ret) 516 + return ret; 517 + 518 + /* Set gain to 1 for all channels */ 519 + ret = mcp3911_read(adc, MCP3910_REG_GAIN, &regval, 3); 520 + if (ret) 521 + return ret; 522 + 523 + for (int i = 0; i < adc->chip->num_channels - 1; i++) { 524 + adc->gain[i] = 1; 525 + regval &= ~MCP3911_GAIN_MASK(i); 526 + } 527 + ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3); 528 + if (ret) 529 + return ret; 530 + 531 + /* Disable offset to ignore any old values in offset register */ 532 + return adc->chip->enable_offset(adc, 0); 606 533 } 607 534 608 535 static void mcp3911_cleanup_regulator(void *vref) ··· 719 466 720 467 static int mcp3911_probe(struct spi_device *spi) 721 468 { 469 + struct device *dev = &spi->dev; 722 470 struct iio_dev *indio_dev; 723 471 struct mcp3911 *adc; 724 472 int ret; 725 473 726 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); 474 + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 727 475 if (!indio_dev) 728 476 return -ENOMEM; 729 477 730 478 adc = iio_priv(indio_dev); 731 479 adc->spi = spi; 480 + adc->chip = spi_get_device_match_data(spi); 732 481 733 - adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref"); 482 + adc->vref = devm_regulator_get_optional(dev, "vref"); 734 483 if (IS_ERR(adc->vref)) { 735 484 if (PTR_ERR(adc->vref) == -ENODEV) { 736 485 adc->vref = NULL; 737 486 } else { 738 - dev_err(&adc->spi->dev, 739 - "failed to get regulator (%ld)\n", 740 - PTR_ERR(adc->vref)); 741 - return PTR_ERR(adc->vref); 487 + return dev_err_probe(dev, PTR_ERR(adc->vref), "failed to get regulator\n"); 742 488 } 743 489 744 490 } else { ··· 745 493 if (ret) 746 494 return ret; 747 495 748 - ret = devm_add_action_or_reset(&spi->dev, 749 - mcp3911_cleanup_regulator, adc->vref); 496 + ret = devm_add_action_or_reset(dev, mcp3911_cleanup_regulator, adc->vref); 750 497 if (ret) 751 498 return ret; 752 499 } 753 500 754 - adc->clki = devm_clk_get_enabled(&adc->spi->dev, NULL); 501 + adc->clki = devm_clk_get_enabled(dev, NULL); 755 502 if (IS_ERR(adc->clki)) { 756 503 if (PTR_ERR(adc->clki) == -ENOENT) { 757 504 adc->clki = NULL; 758 505 } else { 759 - dev_err(&adc->spi->dev, 760 - "failed to get adc clk (%ld)\n", 761 - PTR_ERR(adc->clki)); 762 - return PTR_ERR(adc->clki); 506 + return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n"); 763 507 } 764 508 } 765 509 766 - ret = mcp3911_config(adc); 510 + /* 511 + * Fallback to "device-addr" due to historical mismatch between 512 + * dt-bindings and implementation. 513 + */ 514 + ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 767 515 if (ret) 768 - return ret; 516 + device_property_read_u32(dev, "device-addr", &adc->dev_addr); 517 + if (adc->dev_addr > 3) { 518 + return dev_err_probe(dev, -EINVAL, 519 + "invalid device address (%i). Must be in range 0-3.\n", 520 + adc->dev_addr); 521 + } 522 + dev_dbg(dev, "use device address %i\n", adc->dev_addr); 769 523 770 - if (device_property_read_bool(&adc->spi->dev, "microchip,data-ready-hiz")) 771 - ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ, 772 - 0, 2); 773 - else 774 - ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ, 775 - MCP3911_STATUSCOM_DRHIZ, 2); 524 + ret = adc->chip->config(adc); 776 525 if (ret) 777 526 return ret; 778 527 ··· 781 528 if (ret) 782 529 return ret; 783 530 784 - /* Set gain to 1 for all channels */ 785 - for (int i = 0; i < MCP3911_NUM_CHANNELS; i++) { 531 + /* Set gain to 1 for all channels */ 532 + for (int i = 0; i < adc->chip->num_channels - 1; i++) { 786 533 adc->gain[i] = 1; 787 534 ret = mcp3911_update(adc, MCP3911_REG_GAIN, 788 - MCP3911_GAIN_MASK(i), 789 - MCP3911_GAIN_VAL(i, 0), 1); 535 + MCP3911_GAIN_MASK(i), 536 + MCP3911_GAIN_VAL(i, 0), 1); 790 537 if (ret) 791 538 return ret; 792 539 } ··· 796 543 indio_dev->info = &mcp3911_info; 797 544 spi_set_drvdata(spi, indio_dev); 798 545 799 - indio_dev->channels = mcp3911_channels; 800 - indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels); 546 + indio_dev->channels = adc->chip->channels; 547 + indio_dev->num_channels = adc->chip->num_channels; 801 548 802 549 mutex_init(&adc->lock); 803 550 804 551 if (spi->irq > 0) { 805 - adc->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", 806 - indio_dev->name, 807 - iio_device_id(indio_dev)); 552 + adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 553 + iio_device_id(indio_dev)); 808 554 if (!adc->trig) 809 555 return -ENOMEM; 810 556 811 557 adc->trig->ops = &mcp3911_trigger_ops; 812 558 iio_trigger_set_drvdata(adc->trig, adc); 813 - ret = devm_iio_trigger_register(&spi->dev, adc->trig); 559 + ret = devm_iio_trigger_register(dev, adc->trig); 814 560 if (ret) 815 561 return ret; 816 562 ··· 818 566 * Some platforms might not allow the option to power it down so 819 567 * don't enable the interrupt to avoid extra load on the system. 820 568 */ 821 - ret = devm_request_irq(&spi->dev, spi->irq, 822 - &iio_trigger_generic_data_rdy_poll, IRQF_NO_AUTOEN | IRQF_ONESHOT, 823 - indio_dev->name, adc->trig); 569 + ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll, 570 + IRQF_NO_AUTOEN | IRQF_ONESHOT, 571 + indio_dev->name, adc->trig); 824 572 if (ret) 825 573 return ret; 826 574 } 827 575 828 - ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 829 - NULL, 830 - mcp3911_trigger_handler, NULL); 576 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 577 + mcp3911_trigger_handler, NULL); 831 578 if (ret) 832 579 return ret; 833 580 834 - return devm_iio_device_register(&adc->spi->dev, indio_dev); 581 + return devm_iio_device_register(dev, indio_dev); 835 582 } 836 583 584 + static const struct mcp3911_chip_info mcp3911_chip_info[] = { 585 + [MCP3910] = { 586 + .channels = mcp3910_channels, 587 + .num_channels = ARRAY_SIZE(mcp3910_channels), 588 + .config = mcp3910_config, 589 + .get_osr = mcp3910_get_osr, 590 + .set_osr = mcp3910_set_osr, 591 + .enable_offset = mcp3910_enable_offset, 592 + .get_offset = mcp3910_get_offset, 593 + .set_offset = mcp3910_set_offset, 594 + .set_scale = mcp3910_set_scale, 595 + }, 596 + [MCP3911] = { 597 + .channels = mcp3911_channels, 598 + .num_channels = ARRAY_SIZE(mcp3911_channels), 599 + .config = mcp3911_config, 600 + .get_osr = mcp3911_get_osr, 601 + .set_osr = mcp3911_set_osr, 602 + .enable_offset = mcp3911_enable_offset, 603 + .get_offset = mcp3911_get_offset, 604 + .set_offset = mcp3911_set_offset, 605 + .set_scale = mcp3911_set_scale, 606 + }, 607 + [MCP3912] = { 608 + .channels = mcp3912_channels, 609 + .num_channels = ARRAY_SIZE(mcp3912_channels), 610 + .config = mcp3910_config, 611 + .get_osr = mcp3910_get_osr, 612 + .set_osr = mcp3910_set_osr, 613 + .enable_offset = mcp3910_enable_offset, 614 + .get_offset = mcp3910_get_offset, 615 + .set_offset = mcp3910_set_offset, 616 + .set_scale = mcp3910_set_scale, 617 + }, 618 + [MCP3913] = { 619 + .channels = mcp3913_channels, 620 + .num_channels = ARRAY_SIZE(mcp3913_channels), 621 + .config = mcp3910_config, 622 + .get_osr = mcp3910_get_osr, 623 + .set_osr = mcp3910_set_osr, 624 + .enable_offset = mcp3910_enable_offset, 625 + .get_offset = mcp3910_get_offset, 626 + .set_offset = mcp3910_set_offset, 627 + .set_scale = mcp3910_set_scale, 628 + }, 629 + [MCP3914] = { 630 + .channels = mcp3914_channels, 631 + .num_channels = ARRAY_SIZE(mcp3914_channels), 632 + .config = mcp3910_config, 633 + .get_osr = mcp3910_get_osr, 634 + .set_osr = mcp3910_set_osr, 635 + .enable_offset = mcp3910_enable_offset, 636 + .get_offset = mcp3910_get_offset, 637 + .set_offset = mcp3910_set_offset, 638 + .set_scale = mcp3910_set_scale, 639 + }, 640 + [MCP3918] = { 641 + .channels = mcp3918_channels, 642 + .num_channels = ARRAY_SIZE(mcp3918_channels), 643 + .config = mcp3910_config, 644 + .get_osr = mcp3910_get_osr, 645 + .set_osr = mcp3910_set_osr, 646 + .enable_offset = mcp3910_enable_offset, 647 + .get_offset = mcp3910_get_offset, 648 + .set_offset = mcp3910_set_offset, 649 + .set_scale = mcp3910_set_scale, 650 + }, 651 + [MCP3919] = { 652 + .channels = mcp3919_channels, 653 + .num_channels = ARRAY_SIZE(mcp3919_channels), 654 + .config = mcp3910_config, 655 + .get_osr = mcp3910_get_osr, 656 + .set_osr = mcp3910_set_osr, 657 + .enable_offset = mcp3910_enable_offset, 658 + .get_offset = mcp3910_get_offset, 659 + .set_offset = mcp3910_set_offset, 660 + .set_scale = mcp3910_set_scale, 661 + }, 662 + }; 837 663 static const struct of_device_id mcp3911_dt_ids[] = { 838 - { .compatible = "microchip,mcp3911" }, 664 + { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] }, 665 + { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] }, 666 + { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] }, 667 + { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] }, 668 + { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] }, 669 + { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] }, 670 + { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] }, 839 671 { } 840 672 }; 841 673 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); 842 674 843 675 static const struct spi_device_id mcp3911_id[] = { 844 - { "mcp3911", 0 }, 676 + { "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] }, 677 + { "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] }, 678 + { "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] }, 679 + { "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] }, 680 + { "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] }, 681 + { "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] }, 682 + { "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] }, 845 683 { } 846 684 }; 847 685 MODULE_DEVICE_TABLE(spi, mcp3911_id);

+12 -10

drivers/iio/adc/meson_saradc.c

··· 1045 1045 u32 regval; 1046 1046 1047 1047 ret = meson_sar_adc_lock(indio_dev); 1048 - if (ret) 1048 + if (ret) { 1049 + dev_err(dev, "failed to lock adc\n"); 1049 1050 goto err_lock; 1051 + } 1050 1052 1051 1053 ret = regulator_enable(priv->vref); 1052 1054 if (ret < 0) { ··· 1356 1354 1357 1355 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); 1358 1356 if (IS_ERR(priv->regmap)) 1359 - return PTR_ERR(priv->regmap); 1357 + return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n"); 1360 1358 1361 1359 irq = irq_of_parse_and_map(dev->of_node, 0); 1362 1360 if (!irq) 1363 - return -EINVAL; 1361 + return dev_err_probe(dev, -EINVAL, "failed to get irq\n"); 1364 1362 1365 1363 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev); 1366 1364 if (ret) 1367 - return ret; 1365 + return dev_err_probe(dev, ret, "failed to request irq\n"); 1368 1366 1369 1367 priv->clkin = devm_clk_get(dev, "clkin"); 1370 1368 if (IS_ERR(priv->clkin)) ··· 1386 1384 if (!priv->adc_clk) { 1387 1385 ret = meson_sar_adc_clk_init(indio_dev, base); 1388 1386 if (ret) 1389 - return ret; 1387 + return dev_err_probe(dev, ret, "failed to init internal clk\n"); 1390 1388 } 1391 1389 1392 1390 priv->vref = devm_regulator_get(dev, "vref"); ··· 1428 1426 platform_set_drvdata(pdev, indio_dev); 1429 1427 1430 1428 ret = iio_device_register(indio_dev); 1431 - if (ret) 1429 + if (ret) { 1430 + dev_err_probe(dev, ret, "failed to register iio device\n"); 1432 1431 goto err_hw; 1432 + } 1433 1433 1434 1434 return 0; 1435 1435 ··· 1441 1437 return ret; 1442 1438 } 1443 1439 1444 - static int meson_sar_adc_remove(struct platform_device *pdev) 1440 + static void meson_sar_adc_remove(struct platform_device *pdev) 1445 1441 { 1446 1442 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1447 1443 1448 1444 iio_device_unregister(indio_dev); 1449 1445 1450 1446 meson_sar_adc_hw_disable(indio_dev); 1451 - 1452 - return 0; 1453 1447 } 1454 1448 1455 1449 static int meson_sar_adc_suspend(struct device *dev) ··· 1482 1480 1483 1481 static struct platform_driver meson_sar_adc_driver = { 1484 1482 .probe = meson_sar_adc_probe, 1485 - .remove = meson_sar_adc_remove, 1483 + .remove_new = meson_sar_adc_remove, 1486 1484 .driver = { 1487 1485 .name = "meson-saradc", 1488 1486 .of_match_table = meson_sar_adc_of_match,

+2 -4

drivers/iio/adc/mp2629_adc.c

··· 171 171 return ret; 172 172 } 173 173 174 - static int mp2629_adc_remove(struct platform_device *pdev) 174 + static void mp2629_adc_remove(struct platform_device *pdev) 175 175 { 176 176 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 177 177 struct mp2629_adc *info = iio_priv(indio_dev); ··· 184 184 MP2629_ADC_CONTINUOUS, 0); 185 185 regmap_update_bits(info->regmap, MP2629_REG_ADC_CTRL, 186 186 MP2629_ADC_START, 0); 187 - 188 - return 0; 189 187 } 190 188 191 189 static const struct of_device_id mp2629_adc_of_match[] = { ··· 198 200 .of_match_table = mp2629_adc_of_match, 199 201 }, 200 202 .probe = mp2629_adc_probe, 201 - .remove = mp2629_adc_remove, 203 + .remove_new = mp2629_adc_remove, 202 204 }; 203 205 module_platform_driver(mp2629_adc_driver); 204 206

+24 -48

drivers/iio/adc/mt6577_auxadc.c

··· 246 246 return 0; 247 247 } 248 248 249 + static void mt6577_power_off(void *data) 250 + { 251 + struct mt6577_auxadc_device *adc_dev = data; 252 + 253 + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 254 + 0, MT6577_AUXADC_PDN_EN); 255 + } 256 + 249 257 static int mt6577_auxadc_probe(struct platform_device *pdev) 250 258 { 251 259 struct mt6577_auxadc_device *adc_dev; ··· 273 265 indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels); 274 266 275 267 adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0); 276 - if (IS_ERR(adc_dev->reg_base)) { 277 - dev_err(&pdev->dev, "failed to get auxadc base address\n"); 278 - return PTR_ERR(adc_dev->reg_base); 279 - } 268 + if (IS_ERR(adc_dev->reg_base)) 269 + return dev_err_probe(&pdev->dev, PTR_ERR(adc_dev->reg_base), 270 + "failed to get auxadc base address\n"); 280 271 281 - adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main"); 282 - if (IS_ERR(adc_dev->adc_clk)) { 283 - dev_err(&pdev->dev, "failed to get auxadc clock\n"); 284 - return PTR_ERR(adc_dev->adc_clk); 285 - } 286 - 287 - ret = clk_prepare_enable(adc_dev->adc_clk); 288 - if (ret) { 289 - dev_err(&pdev->dev, "failed to enable auxadc clock\n"); 290 - return ret; 291 - } 272 + adc_dev->adc_clk = devm_clk_get_enabled(&pdev->dev, "main"); 273 + if (IS_ERR(adc_dev->adc_clk)) 274 + return dev_err_probe(&pdev->dev, PTR_ERR(adc_dev->adc_clk), 275 + "failed to enable auxadc clock\n"); 292 276 293 277 adc_clk_rate = clk_get_rate(adc_dev->adc_clk); 294 - if (!adc_clk_rate) { 295 - ret = -EINVAL; 296 - dev_err(&pdev->dev, "null clock rate\n"); 297 - goto err_disable_clk; 298 - } 278 + if (!adc_clk_rate) 279 + return dev_err_probe(&pdev->dev, -EINVAL, "null clock rate\n"); 299 280 300 281 adc_dev->dev_comp = device_get_match_data(&pdev->dev); 301 282 ··· 293 296 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 294 297 MT6577_AUXADC_PDN_EN, 0); 295 298 mdelay(MT6577_AUXADC_POWER_READY_MS); 296 - 297 299 platform_set_drvdata(pdev, indio_dev); 298 300 299 - ret = iio_device_register(indio_dev); 300 - if (ret < 0) { 301 - dev_err(&pdev->dev, "failed to register iio device\n"); 302 - goto err_power_off; 303 - } 301 + ret = devm_add_action_or_reset(&pdev->dev, mt6577_power_off, adc_dev); 302 + if (ret) 303 + return dev_err_probe(&pdev->dev, ret, 304 + "Failed to add action to managed power off\n"); 304 305 305 - return 0; 306 - 307 - err_power_off: 308 - mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 309 - 0, MT6577_AUXADC_PDN_EN); 310 - err_disable_clk: 311 - clk_disable_unprepare(adc_dev->adc_clk); 312 - return ret; 313 - } 314 - 315 - static int mt6577_auxadc_remove(struct platform_device *pdev) 316 - { 317 - struct iio_dev *indio_dev = platform_get_drvdata(pdev); 318 - struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 319 - 320 - iio_device_unregister(indio_dev); 321 - 322 - mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 323 - 0, MT6577_AUXADC_PDN_EN); 324 - 325 - clk_disable_unprepare(adc_dev->adc_clk); 306 + ret = devm_iio_device_register(&pdev->dev, indio_dev); 307 + if (ret < 0) 308 + return dev_err_probe(&pdev->dev, ret, "failed to register iio device\n"); 326 309 327 310 return 0; 328 311 } ··· 329 352 .pm = pm_sleep_ptr(&mt6577_auxadc_pm_ops), 330 353 }, 331 354 .probe = mt6577_auxadc_probe, 332 - .remove = mt6577_auxadc_remove, 333 355 }; 334 356 module_platform_driver(mt6577_auxadc_driver); 335 357

+2 -4

drivers/iio/adc/mxs-lradc-adc.c

··· 807 807 return ret; 808 808 } 809 809 810 - static int mxs_lradc_adc_remove(struct platform_device *pdev) 810 + static void mxs_lradc_adc_remove(struct platform_device *pdev) 811 811 { 812 812 struct iio_dev *iio = platform_get_drvdata(pdev); 813 813 struct mxs_lradc_adc *adc = iio_priv(iio); ··· 816 816 mxs_lradc_adc_hw_stop(adc); 817 817 iio_triggered_buffer_cleanup(iio); 818 818 mxs_lradc_adc_trigger_remove(iio); 819 - 820 - return 0; 821 819 } 822 820 823 821 static struct platform_driver mxs_lradc_adc_driver = { ··· 823 825 .name = "mxs-lradc-adc", 824 826 }, 825 827 .probe = mxs_lradc_adc_probe, 826 - .remove = mxs_lradc_adc_remove, 828 + .remove_new = mxs_lradc_adc_remove, 827 829 }; 828 830 module_platform_driver(mxs_lradc_adc_driver); 829 831

+2 -4

drivers/iio/adc/npcm_adc.c

··· 320 320 return ret; 321 321 } 322 322 323 - static int npcm_adc_remove(struct platform_device *pdev) 323 + static void npcm_adc_remove(struct platform_device *pdev) 324 324 { 325 325 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 326 326 struct npcm_adc *info = iio_priv(indio_dev); ··· 333 333 if (!IS_ERR(info->vref)) 334 334 regulator_disable(info->vref); 335 335 clk_disable_unprepare(info->adc_clk); 336 - 337 - return 0; 338 336 } 339 337 340 338 static struct platform_driver npcm_adc_driver = { 341 339 .probe = npcm_adc_probe, 342 - .remove = npcm_adc_remove, 340 + .remove_new = npcm_adc_remove, 343 341 .driver = { 344 342 .name = "npcm_adc", 345 343 .of_match_table = npcm_adc_match,

+1 -1

drivers/iio/adc/palmas_gpadc.c

··· 457 457 * 458 458 * The gain error include both gain error, as specified in the datasheet, and 459 459 * the gain error drift. These paramenters vary depending on device and whether 460 - * the the channel is calibrated (trimmed) or not. 460 + * the channel is calibrated (trimmed) or not. 461 461 */ 462 462 static int palmas_gpadc_threshold_with_tolerance(int val, const int INL, 463 463 const int gain_error,

+2 -4

drivers/iio/adc/qcom-pm8xxx-xoadc.c

··· 957 957 return ret; 958 958 } 959 959 960 - static int pm8xxx_xoadc_remove(struct platform_device *pdev) 960 + static void pm8xxx_xoadc_remove(struct platform_device *pdev) 961 961 { 962 962 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 963 963 struct pm8xxx_xoadc *adc = iio_priv(indio_dev); ··· 965 965 iio_device_unregister(indio_dev); 966 966 967 967 regulator_disable(adc->vref); 968 - 969 - return 0; 970 968 } 971 969 972 970 static const struct xoadc_variant pm8018_variant = { ··· 1017 1019 .of_match_table = pm8xxx_xoadc_id_table, 1018 1020 }, 1019 1021 .probe = pm8xxx_xoadc_probe, 1020 - .remove = pm8xxx_xoadc_remove, 1022 + .remove_new = pm8xxx_xoadc_remove, 1021 1023 }; 1022 1024 module_platform_driver(pm8xxx_xoadc_driver); 1023 1025

+2 -4

drivers/iio/adc/rcar-gyroadc.c

··· 559 559 return ret; 560 560 } 561 561 562 - static int rcar_gyroadc_remove(struct platform_device *pdev) 562 + static void rcar_gyroadc_remove(struct platform_device *pdev) 563 563 { 564 564 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 565 565 struct rcar_gyroadc *priv = iio_priv(indio_dev); ··· 573 573 pm_runtime_set_suspended(dev); 574 574 clk_disable_unprepare(priv->clk); 575 575 rcar_gyroadc_deinit_supplies(indio_dev); 576 - 577 - return 0; 578 576 } 579 577 580 578 static int rcar_gyroadc_suspend(struct device *dev) ··· 601 603 602 604 static struct platform_driver rcar_gyroadc_driver = { 603 605 .probe = rcar_gyroadc_probe, 604 - .remove = rcar_gyroadc_remove, 606 + .remove_new = rcar_gyroadc_remove, 605 607 .driver = { 606 608 .name = DRIVER_NAME, 607 609 .of_match_table = rcar_gyroadc_match,

+16 -48

drivers/iio/adc/spear_adc.c

··· 274 274 int irq; 275 275 276 276 indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state)); 277 - if (!indio_dev) { 278 - dev_err(dev, "failed allocating iio device\n"); 279 - return -ENOMEM; 280 - } 277 + if (!indio_dev) 278 + return dev_err_probe(dev, -ENOMEM, 279 + "failed allocating iio device\n"); 281 280 282 281 st = iio_priv(indio_dev); 283 282 ··· 296 297 st->adc_base_spear3xx = 297 298 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx; 298 299 299 - st->clk = devm_clk_get(dev, NULL); 300 - if (IS_ERR(st->clk)) { 301 - dev_err(dev, "failed getting clock\n"); 302 - return PTR_ERR(st->clk); 303 - } 304 - 305 - ret = clk_prepare_enable(st->clk); 306 - if (ret) { 307 - dev_err(dev, "failed enabling clock\n"); 308 - return ret; 309 - } 300 + st->clk = devm_clk_get_enabled(dev, NULL); 301 + if (IS_ERR(st->clk)) 302 + return dev_err_probe(dev, PTR_ERR(st->clk), 303 + "failed enabling clock\n"); 310 304 311 305 irq = platform_get_irq(pdev, 0); 312 - if (irq < 0) { 313 - ret = irq; 314 - goto errout2; 315 - } 306 + if (irq < 0) 307 + return irq; 316 308 317 309 ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME, 318 310 st); 319 - if (ret < 0) { 320 - dev_err(dev, "failed requesting interrupt\n"); 321 - goto errout2; 322 - } 311 + if (ret < 0) 312 + return dev_err_probe(dev, ret, "failed requesting interrupt\n"); 323 313 324 314 if (of_property_read_u32(np, "sampling-frequency", 325 - &st->sampling_freq)) { 326 - dev_err(dev, "sampling-frequency missing in DT\n"); 327 - ret = -EINVAL; 328 - goto errout2; 329 - } 315 + &st->sampling_freq)) 316 + return dev_err_probe(dev, -EINVAL, 317 + "sampling-frequency missing in DT\n"); 330 318 331 319 /* 332 320 * Optional avg_samples defaults to 0, resulting in single data ··· 329 343 330 344 spear_adc_configure(st); 331 345 332 - platform_set_drvdata(pdev, indio_dev); 333 - 334 346 init_completion(&st->completion); 335 347 336 348 indio_dev->name = SPEAR_ADC_MOD_NAME; ··· 337 353 indio_dev->channels = spear_adc_iio_channels; 338 354 indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels); 339 355 340 - ret = iio_device_register(indio_dev); 356 + ret = devm_iio_device_register(dev, indio_dev); 341 357 if (ret) 342 - goto errout2; 358 + return ret; 343 359 344 360 dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq); 345 - 346 - return 0; 347 - 348 - errout2: 349 - clk_disable_unprepare(st->clk); 350 - return ret; 351 - } 352 - 353 - static int spear_adc_remove(struct platform_device *pdev) 354 - { 355 - struct iio_dev *indio_dev = platform_get_drvdata(pdev); 356 - struct spear_adc_state *st = iio_priv(indio_dev); 357 - 358 - iio_device_unregister(indio_dev); 359 - clk_disable_unprepare(st->clk); 360 361 361 362 return 0; 362 363 } ··· 356 387 357 388 static struct platform_driver spear_adc_driver = { 358 389 .probe = spear_adc_probe, 359 - .remove = spear_adc_remove, 360 390 .driver = { 361 391 .name = SPEAR_ADC_MOD_NAME, 362 392 .of_match_table = of_match_ptr(spear_adc_dt_ids),

+5 -7

drivers/iio/adc/stm32-adc-core.c

··· 17 17 #include <linux/irqdomain.h> 18 18 #include <linux/mfd/syscon.h> 19 19 #include <linux/module.h> 20 - #include <linux/of_device.h> 20 + #include <linux/of.h> 21 21 #include <linux/of_platform.h> 22 22 #include <linux/platform_device.h> 23 23 #include <linux/pm_runtime.h> 24 + #include <linux/property.h> 24 25 #include <linux/regmap.h> 25 26 #include <linux/regulator/consumer.h> 26 27 #include <linux/slab.h> ··· 721 720 return -ENOMEM; 722 721 platform_set_drvdata(pdev, &priv->common); 723 722 724 - priv->cfg = (const struct stm32_adc_priv_cfg *) 725 - of_match_device(dev->driver->of_match_table, dev)->data; 723 + priv->cfg = device_get_match_data(dev); 726 724 priv->nb_adc_max = priv->cfg->num_adcs; 727 725 spin_lock_init(&priv->common.lock); 728 726 ··· 814 814 return ret; 815 815 } 816 816 817 - static int stm32_adc_remove(struct platform_device *pdev) 817 + static void stm32_adc_remove(struct platform_device *pdev) 818 818 { 819 819 struct stm32_adc_common *common = platform_get_drvdata(pdev); 820 820 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); ··· 826 826 pm_runtime_disable(&pdev->dev); 827 827 pm_runtime_set_suspended(&pdev->dev); 828 828 pm_runtime_put_noidle(&pdev->dev); 829 - 830 - return 0; 831 829 } 832 830 833 831 static int stm32_adc_core_runtime_suspend(struct device *dev) ··· 906 908 907 909 static struct platform_driver stm32_adc_driver = { 908 910 .probe = stm32_adc_probe, 909 - .remove = stm32_adc_remove, 911 + .remove_new = stm32_adc_remove, 910 912 .driver = { 911 913 .name = "stm32-adc-core", 912 914 .of_match_table = stm32_adc_of_match,

+3 -5

drivers/iio/adc/stm32-adc.c

··· 2209 2209 ret = -EINVAL; 2210 2210 goto err; 2211 2211 } 2212 - strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); 2212 + strscpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); 2213 2213 ret = stm32_adc_populate_int_ch(indio_dev, name, val); 2214 2214 if (ret == -ENOENT) 2215 2215 continue; ··· 2513 2513 return ret; 2514 2514 } 2515 2515 2516 - static int stm32_adc_remove(struct platform_device *pdev) 2516 + static void stm32_adc_remove(struct platform_device *pdev) 2517 2517 { 2518 2518 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2519 2519 struct stm32_adc *adc = iio_priv(indio_dev); ··· 2532 2532 adc->rx_buf, adc->rx_dma_buf); 2533 2533 dma_release_channel(adc->dma_chan); 2534 2534 } 2535 - 2536 - return 0; 2537 2535 } 2538 2536 2539 2537 static int stm32_adc_suspend(struct device *dev) ··· 2657 2659 2658 2660 static struct platform_driver stm32_adc_driver = { 2659 2661 .probe = stm32_adc_probe, 2660 - .remove = stm32_adc_remove, 2662 + .remove_new = stm32_adc_remove, 2661 2663 .driver = { 2662 2664 .name = "stm32-adc", 2663 2665 .of_match_table = stm32_adc_of_match,

+2 -4

drivers/iio/adc/stm32-dfsdm-adc.c

··· 1620 1620 return ret; 1621 1621 } 1622 1622 1623 - static int stm32_dfsdm_adc_remove(struct platform_device *pdev) 1623 + static void stm32_dfsdm_adc_remove(struct platform_device *pdev) 1624 1624 { 1625 1625 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1626 1626 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); ··· 1629 1629 of_platform_depopulate(&pdev->dev); 1630 1630 iio_device_unregister(indio_dev); 1631 1631 stm32_dfsdm_dma_release(indio_dev); 1632 - 1633 - return 0; 1634 1632 } 1635 1633 1636 1634 static int stm32_dfsdm_adc_suspend(struct device *dev) ··· 1675 1677 .pm = pm_sleep_ptr(&stm32_dfsdm_adc_pm_ops), 1676 1678 }, 1677 1679 .probe = stm32_dfsdm_adc_probe, 1678 - .remove = stm32_dfsdm_adc_remove, 1680 + .remove_new = stm32_dfsdm_adc_remove, 1679 1681 }; 1680 1682 module_platform_driver(stm32_dfsdm_adc_driver); 1681 1683

+2 -4

drivers/iio/adc/stm32-dfsdm-core.c

··· 436 436 return ret; 437 437 } 438 438 439 - static int stm32_dfsdm_core_remove(struct platform_device *pdev) 439 + static void stm32_dfsdm_core_remove(struct platform_device *pdev) 440 440 { 441 441 struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev); 442 442 ··· 446 446 pm_runtime_set_suspended(&pdev->dev); 447 447 pm_runtime_put_noidle(&pdev->dev); 448 448 stm32_dfsdm_clk_disable_unprepare(dfsdm); 449 - 450 - return 0; 451 449 } 452 450 453 451 static int stm32_dfsdm_core_suspend(struct device *dev) ··· 506 508 507 509 static struct platform_driver stm32_dfsdm_driver = { 508 510 .probe = stm32_dfsdm_probe, 509 - .remove = stm32_dfsdm_core_remove, 511 + .remove_new = stm32_dfsdm_core_remove, 510 512 .driver = { 511 513 .name = "stm32-dfsdm", 512 514 .of_match_table = stm32_dfsdm_of_match,

+3 -5

drivers/iio/adc/sun4i-gpadc-iio.c

··· 669 669 return ret; 670 670 } 671 671 672 - static int sun4i_gpadc_remove(struct platform_device *pdev) 672 + static void sun4i_gpadc_remove(struct platform_device *pdev) 673 673 { 674 674 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 675 675 struct sun4i_gpadc_iio *info = iio_priv(indio_dev); ··· 678 678 pm_runtime_disable(&pdev->dev); 679 679 680 680 if (!IS_ENABLED(CONFIG_THERMAL_OF)) 681 - return 0; 681 + return; 682 682 683 683 if (!info->no_irq) 684 684 iio_map_array_unregister(indio_dev); 685 - 686 - return 0; 687 685 } 688 686 689 687 static const struct platform_device_id sun4i_gpadc_id[] = { ··· 700 702 }, 701 703 .id_table = sun4i_gpadc_id, 702 704 .probe = sun4i_gpadc_probe, 703 - .remove = sun4i_gpadc_remove, 705 + .remove_new = sun4i_gpadc_remove, 704 706 }; 705 707 MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_id); 706 708

+4 -8

drivers/iio/adc/ti-adc081c.c

··· 154 154 155 155 static int adc081c_probe(struct i2c_client *client) 156 156 { 157 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 158 157 struct iio_dev *iio; 159 158 struct adc081c *adc; 160 159 const struct adcxx1c_model *model; ··· 162 163 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA)) 163 164 return -EOPNOTSUPP; 164 165 165 - if (dev_fwnode(&client->dev)) 166 - model = device_get_match_data(&client->dev); 167 - else 168 - model = &adcxx1c_models[id->driver_data]; 166 + model = i2c_get_match_data(client); 169 167 170 168 iio = devm_iio_device_alloc(&client->dev, sizeof(*adc)); 171 169 if (!iio) ··· 203 207 } 204 208 205 209 static const struct i2c_device_id adc081c_id[] = { 206 - { "adc081c", ADC081C }, 207 - { "adc101c", ADC101C }, 208 - { "adc121c", ADC121C }, 210 + { "adc081c", (kernel_ulong_t)&adcxx1c_models[ADC081C] }, 211 + { "adc101c", (kernel_ulong_t)&adcxx1c_models[ADC101C] }, 212 + { "adc121c", (kernel_ulong_t)&adcxx1c_models[ADC121C] }, 209 213 { } 210 214 }; 211 215 MODULE_DEVICE_TABLE(i2c, adc081c_id);

+3 -4

drivers/iio/adc/ti-ads1015.c

··· 976 976 977 977 static int ads1015_probe(struct i2c_client *client) 978 978 { 979 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 980 979 const struct ads1015_chip_data *chip; 981 980 struct iio_dev *indio_dev; 982 981 struct ads1015_data *data; 983 982 int ret; 984 983 int i; 985 984 986 - chip = device_get_match_data(&client->dev); 987 - if (!chip) 988 - chip = (const struct ads1015_chip_data *)id->driver_data; 985 + chip = i2c_get_match_data(client); 989 986 if (!chip) 990 987 return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n"); 991 988 ··· 1044 1047 1 << ADS1015_CFG_COMP_LAT_SHIFT; 1045 1048 1046 1049 switch (irq_trig) { 1050 + case IRQF_TRIGGER_FALLING: 1047 1051 case IRQF_TRIGGER_LOW: 1048 1052 cfg_comp |= ADS1015_CFG_COMP_POL_LOW << 1049 1053 ADS1015_CFG_COMP_POL_SHIFT; 1050 1054 break; 1051 1055 case IRQF_TRIGGER_HIGH: 1056 + case IRQF_TRIGGER_RISING: 1052 1057 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH << 1053 1058 ADS1015_CFG_COMP_POL_SHIFT; 1054 1059 break;

+2 -4

drivers/iio/adc/ti_am335x_adc.c

··· 681 681 return err; 682 682 } 683 683 684 - static int tiadc_remove(struct platform_device *pdev) 684 + static void tiadc_remove(struct platform_device *pdev) 685 685 { 686 686 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 687 687 struct tiadc_device *adc_dev = iio_priv(indio_dev); ··· 697 697 698 698 step_en = get_adc_step_mask(adc_dev); 699 699 am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); 700 - 701 - return 0; 702 700 } 703 701 704 702 static int tiadc_suspend(struct device *dev) ··· 745 747 .of_match_table = ti_adc_dt_ids, 746 748 }, 747 749 .probe = tiadc_probe, 748 - .remove = tiadc_remove, 750 + .remove_new = tiadc_remove, 749 751 }; 750 752 module_platform_driver(tiadc_driver); 751 753

+2 -4

drivers/iio/adc/twl4030-madc.c

··· 892 892 return ret; 893 893 } 894 894 895 - static int twl4030_madc_remove(struct platform_device *pdev) 895 + static void twl4030_madc_remove(struct platform_device *pdev) 896 896 { 897 897 struct iio_dev *iio_dev = platform_get_drvdata(pdev); 898 898 struct twl4030_madc_data *madc = iio_priv(iio_dev); ··· 903 903 twl4030_madc_set_power(madc, 0); 904 904 905 905 regulator_disable(madc->usb3v1); 906 - 907 - return 0; 908 906 } 909 907 910 908 #ifdef CONFIG_OF ··· 915 917 916 918 static struct platform_driver twl4030_madc_driver = { 917 919 .probe = twl4030_madc_probe, 918 - .remove = twl4030_madc_remove, 920 + .remove_new = twl4030_madc_remove, 919 921 .driver = { 920 922 .name = "twl4030_madc", 921 923 .of_match_table = of_match_ptr(twl_madc_of_match),

+6 -10

drivers/iio/adc/twl6030-gpadc.c

··· 16 16 */ 17 17 #include <linux/interrupt.h> 18 18 #include <linux/kernel.h> 19 + #include <linux/mod_devicetable.h> 19 20 #include <linux/module.h> 20 21 #include <linux/platform_device.h> 21 - #include <linux/of_platform.h> 22 + #include <linux/property.h> 22 23 #include <linux/mfd/twl.h> 23 24 #include <linux/iio/iio.h> 24 25 #include <linux/iio/sysfs.h> ··· 880 879 struct device *dev = &pdev->dev; 881 880 struct twl6030_gpadc_data *gpadc; 882 881 const struct twl6030_gpadc_platform_data *pdata; 883 - const struct of_device_id *match; 884 882 struct iio_dev *indio_dev; 885 883 int irq; 886 884 int ret; 887 885 888 - match = of_match_device(of_twl6030_match_tbl, dev); 889 - if (!match) 886 + pdata = device_get_match_data(&pdev->dev); 887 + if (!pdata) 890 888 return -EINVAL; 891 - 892 - pdata = match->data; 893 889 894 890 indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc)); 895 891 if (!indio_dev) ··· 966 968 return iio_device_register(indio_dev); 967 969 } 968 970 969 - static int twl6030_gpadc_remove(struct platform_device *pdev) 971 + static void twl6030_gpadc_remove(struct platform_device *pdev) 970 972 { 971 973 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 972 974 973 975 twl6030_gpadc_disable_irq(TWL6030_GPADC_RT_SW1_EOC_MASK); 974 976 iio_device_unregister(indio_dev); 975 - 976 - return 0; 977 977 } 978 978 979 979 static int twl6030_gpadc_suspend(struct device *pdev) ··· 1003 1007 1004 1008 static struct platform_driver twl6030_gpadc_driver = { 1005 1009 .probe = twl6030_gpadc_probe, 1006 - .remove = twl6030_gpadc_remove, 1010 + .remove_new = twl6030_gpadc_remove, 1007 1011 .driver = { 1008 1012 .name = DRIVER_NAME, 1009 1013 .pm = pm_sleep_ptr(&twl6030_gpadc_pm_ops),

+2 -4

drivers/iio/adc/vf610_adc.c

··· 916 916 return ret; 917 917 } 918 918 919 - static int vf610_adc_remove(struct platform_device *pdev) 919 + static void vf610_adc_remove(struct platform_device *pdev) 920 920 { 921 921 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 922 922 struct vf610_adc *info = iio_priv(indio_dev); ··· 925 925 iio_triggered_buffer_cleanup(indio_dev); 926 926 regulator_disable(info->vref); 927 927 clk_disable_unprepare(info->clk); 928 - 929 - return 0; 930 928 } 931 929 932 930 static int vf610_adc_suspend(struct device *dev) ··· 972 974 973 975 static struct platform_driver vf610_adc_driver = { 974 976 .probe = vf610_adc_probe, 975 - .remove = vf610_adc_remove, 977 + .remove_new = vf610_adc_remove, 976 978 .driver = { 977 979 .name = DRIVER_NAME, 978 980 .of_match_table = vf610_adc_match,

+1

drivers/iio/addac/Kconfig

··· 40 40 select REGMAP_MMIO 41 41 select GPIOLIB 42 42 select GPIO_REGMAP 43 + select I8254 43 44 help 44 45 Say yes here to build support for the Apex Embedded Systems STX104 45 46 integrated analog PC/104 card.

+21 -3

drivers/iio/addac/ad74413r.c

··· 442 442 int ret; 443 443 444 444 ret = regmap_update_bits(st->regmap, 445 + AD74413R_REG_CH_FUNC_SETUP_X(channel), 446 + AD74413R_CH_FUNC_SETUP_MASK, 447 + CH_FUNC_HIGH_IMPEDANCE); 448 + if (ret) 449 + return ret; 450 + 451 + /* Set DAC code to 0 prior to changing channel function */ 452 + ret = ad74413r_set_channel_dac_code(st, channel, 0); 453 + if (ret) 454 + return ret; 455 + 456 + /* Delay required before transition to new desired mode */ 457 + usleep_range(130, 150); 458 + 459 + ret = regmap_update_bits(st->regmap, 445 460 AD74413R_REG_CH_FUNC_SETUP_X(channel), 446 461 AD74413R_CH_FUNC_SETUP_MASK, func); 447 462 if (ret) 448 463 return ret; 464 + 465 + /* Delay required before updating the new DAC code */ 466 + usleep_range(150, 170); 449 467 450 468 if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER) 451 469 ret = regmap_set_bits(st->regmap, ··· 723 705 return IIO_VAL_FRACTIONAL; 724 706 } 725 707 726 - static int ad74413_get_input_current_offset(struct ad74413r_state *st, 727 - unsigned int channel, int *val) 708 + static int ad74413r_get_input_current_offset(struct ad74413r_state *st, 709 + unsigned int channel, int *val) 728 710 { 729 711 unsigned int range; 730 712 int voltage_range; ··· 1009 991 return ad74413r_get_input_voltage_offset(st, 1010 992 chan->channel, val); 1011 993 case IIO_CURRENT: 1012 - return ad74413_get_input_current_offset(st, 994 + return ad74413r_get_input_current_offset(st, 1013 995 chan->channel, val); 1014 996 default: 1015 997 return -EINVAL;

+59 -2

drivers/iio/addac/stx104.c

··· 8 8 #include <linux/device.h> 9 9 #include <linux/err.h> 10 10 #include <linux/gpio/regmap.h> 11 + #include <linux/i8254.h> 11 12 #include <linux/iio/iio.h> 12 13 #include <linux/iio/types.h> 13 14 #include <linux/isa.h> ··· 56 55 #define STX104_ADC_STATUS (STX104_AIO_BASE + 0x8) 57 56 #define STX104_ADC_CONTROL (STX104_AIO_BASE + 0x9) 58 57 #define STX104_ADC_CONFIGURATION (STX104_AIO_BASE + 0x11) 58 + #define STX104_I8254_BASE (STX104_AIO_BASE + 0x12) 59 59 60 60 #define STX104_AIO_DATA_STRIDE 2 61 61 #define STX104_DAC_OFFSET(_channel) (STX104_DAC_BASE + STX104_AIO_DATA_STRIDE * (_channel)) ··· 79 77 /* ADC Configuration */ 80 78 #define STX104_GAIN GENMASK(1, 0) 81 79 #define STX104_ADBU BIT(2) 80 + #define STX104_RBK GENMASK(7, 4) 82 81 #define STX104_BIPOLAR 0 83 82 #define STX104_GAIN_X1 0 84 83 #define STX104_GAIN_X2 1 ··· 169 166 .reg_base = STX104_DIO_REG, 170 167 .val_bits = 8, 171 168 .io_port = true, 169 + }; 170 + 171 + static const struct regmap_range pit_wr_ranges[] = { 172 + regmap_reg_range(0x0, 0x3), 173 + }; 174 + static const struct regmap_range pit_rd_ranges[] = { 175 + regmap_reg_range(0x0, 0x2), 176 + }; 177 + static const struct regmap_access_table pit_wr_table = { 178 + .yes_ranges = pit_wr_ranges, 179 + .n_yes_ranges = ARRAY_SIZE(pit_wr_ranges), 180 + }; 181 + static const struct regmap_access_table pit_rd_table = { 182 + .yes_ranges = pit_rd_ranges, 183 + .n_yes_ranges = ARRAY_SIZE(pit_rd_ranges), 184 + }; 185 + 186 + static const struct regmap_config pit_regmap_config = { 187 + .name = "i8254", 188 + .reg_bits = 8, 189 + .reg_stride = 1, 190 + .reg_base = STX104_I8254_BASE, 191 + .val_bits = 8, 192 + .io_port = true, 193 + .wr_table = &pit_wr_table, 194 + .rd_table = &pit_rd_table, 172 195 }; 173 196 174 197 static int stx104_read_raw(struct iio_dev *indio_dev, ··· 368 339 "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3" 369 340 }; 370 341 342 + static int bank_select_i8254(struct regmap *map) 343 + { 344 + const u8 select_i8254[] = { 0x3, 0xB, 0xA }; 345 + size_t i; 346 + int err; 347 + 348 + for (i = 0; i < ARRAY_SIZE(select_i8254); i++) { 349 + err = regmap_write_bits(map, STX104_ADC_CONFIGURATION, STX104_RBK, select_i8254[i]); 350 + if (err) 351 + return err; 352 + } 353 + 354 + return 0; 355 + } 356 + 371 357 static int stx104_init_hw(struct stx104_iio *const priv) 372 358 { 373 359 int err; ··· 405 361 if (err) 406 362 return err; 407 363 408 - return 0; 364 + return bank_select_i8254(priv->aio_ctl_map); 409 365 } 410 366 411 367 static int stx104_probe(struct device *dev, unsigned int id) ··· 413 369 struct iio_dev *indio_dev; 414 370 struct stx104_iio *priv; 415 371 struct gpio_regmap_config gpio_config; 372 + struct i8254_regmap_config pit_config; 416 373 void __iomem *stx104_base; 417 374 struct regmap *aio_ctl_map; 418 375 struct regmap *aio_data_map; ··· 450 405 if (IS_ERR(dio_map)) 451 406 return dev_err_probe(dev, PTR_ERR(dio_map), 452 407 "Unable to initialize dio register map\n"); 408 + 409 + pit_config.map = devm_regmap_init_mmio(dev, stx104_base, &pit_regmap_config); 410 + if (IS_ERR(pit_config.map)) 411 + return dev_err_probe(dev, PTR_ERR(pit_config.map), 412 + "Unable to initialize i8254 register map\n"); 453 413 454 414 priv = iio_priv(indio_dev); 455 415 priv->aio_ctl_map = aio_ctl_map; ··· 499 449 .drvdata = dio_map, 500 450 }; 501 451 502 - return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); 452 + err = PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); 453 + if (err) 454 + return err; 455 + 456 + pit_config.parent = dev; 457 + 458 + return devm_i8254_regmap_register(dev, &pit_config); 503 459 } 504 460 505 461 static struct isa_driver stx104_driver = { ··· 520 464 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 521 465 MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver"); 522 466 MODULE_LICENSE("GPL v2"); 467 + MODULE_IMPORT_NS(I8254);

+17

drivers/iio/amplifiers/hmc425a.c

··· 21 21 22 22 enum hmc425a_type { 23 23 ID_HMC425A, 24 + ID_HMC540S, 24 25 }; 25 26 26 27 struct hmc425a_chip_info { ··· 71 70 case ID_HMC425A: 72 71 gain = ~code * -500; 73 72 break; 73 + case ID_HMC540S: 74 + gain = ~code * -1000; 75 + break; 74 76 } 75 77 76 78 *val = gain / 1000; ··· 109 105 switch (st->type) { 110 106 case ID_HMC425A: 111 107 code = ~((abs(gain) / 500) & 0x3F); 108 + break; 109 + case ID_HMC540S: 110 + code = ~((abs(gain) / 1000) & 0xF); 112 111 break; 113 112 } 114 113 ··· 164 157 /* Match table for of_platform binding */ 165 158 static const struct of_device_id hmc425a_of_match[] = { 166 159 { .compatible = "adi,hmc425a", .data = (void *)ID_HMC425A }, 160 + { .compatible = "adi,hmc540s", .data = (void *)ID_HMC540S }, 167 161 {}, 168 162 }; 169 163 MODULE_DEVICE_TABLE(of, hmc425a_of_match); ··· 178 170 .gain_min = -31500, 179 171 .gain_max = 0, 180 172 .default_gain = -0x40, /* set default gain -31.5db*/ 173 + }, 174 + [ID_HMC540S] = { 175 + .name = "hmc540s", 176 + .channels = hmc425a_channels, 177 + .num_channels = ARRAY_SIZE(hmc425a_channels), 178 + .num_gpios = 4, 179 + .gain_min = -15000, 180 + .gain_max = 0, 181 + .default_gain = -0x10, /* set default gain -15.0db*/ 181 182 }, 182 183 }; 183 184

+1 -5

drivers/iio/chemical/atlas-ezo-sensor.c

··· 203 203 204 204 static int atlas_ezo_probe(struct i2c_client *client) 205 205 { 206 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 207 206 const struct atlas_ezo_device *chip; 208 207 struct atlas_ezo_data *data; 209 208 struct iio_dev *indio_dev; ··· 211 212 if (!indio_dev) 212 213 return -ENOMEM; 213 214 214 - if (dev_fwnode(&client->dev)) 215 - chip = device_get_match_data(&client->dev); 216 - else 217 - chip = (const struct atlas_ezo_device *)id->driver_data; 215 + chip = i2c_get_match_data(client); 218 216 if (!chip) 219 217 return -EINVAL; 220 218

+14 -18

drivers/iio/chemical/atlas-sensor.c

··· 87 87 struct atlas_data { 88 88 struct i2c_client *client; 89 89 struct iio_trigger *trig; 90 - struct atlas_device *chip; 90 + const struct atlas_device *chip; 91 91 struct regmap *regmap; 92 92 struct irq_work work; 93 93 unsigned int interrupt_enabled; ··· 353 353 int delay; 354 354 }; 355 355 356 - static struct atlas_device atlas_devices[] = { 356 + static const struct atlas_device atlas_devices[] = { 357 357 [ATLAS_PH_SM] = { 358 358 .channels = atlas_ph_channels, 359 359 .num_channels = 3, ··· 589 589 }; 590 590 591 591 static const struct i2c_device_id atlas_id[] = { 592 - { "atlas-ph-sm", ATLAS_PH_SM }, 593 - { "atlas-ec-sm", ATLAS_EC_SM }, 594 - { "atlas-orp-sm", ATLAS_ORP_SM }, 595 - { "atlas-do-sm", ATLAS_DO_SM }, 596 - { "atlas-rtd-sm", ATLAS_RTD_SM }, 592 + { "atlas-ph-sm", (kernel_ulong_t)&atlas_devices[ATLAS_PH_SM] }, 593 + { "atlas-ec-sm", (kernel_ulong_t)&atlas_devices[ATLAS_EC_SM] }, 594 + { "atlas-orp-sm", (kernel_ulong_t)&atlas_devices[ATLAS_ORP_SM] }, 595 + { "atlas-do-sm", (kernel_ulong_t)&atlas_devices[ATLAS_DO_SM] }, 596 + { "atlas-rtd-sm", (kernel_ulong_t)&atlas_devices[ATLAS_RTD_SM] }, 597 597 {} 598 598 }; 599 599 MODULE_DEVICE_TABLE(i2c, atlas_id); 600 600 601 601 static const struct of_device_id atlas_dt_ids[] = { 602 - { .compatible = "atlas,ph-sm", .data = (void *)ATLAS_PH_SM, }, 603 - { .compatible = "atlas,ec-sm", .data = (void *)ATLAS_EC_SM, }, 604 - { .compatible = "atlas,orp-sm", .data = (void *)ATLAS_ORP_SM, }, 605 - { .compatible = "atlas,do-sm", .data = (void *)ATLAS_DO_SM, }, 606 - { .compatible = "atlas,rtd-sm", .data = (void *)ATLAS_RTD_SM, }, 602 + { .compatible = "atlas,ph-sm", .data = &atlas_devices[ATLAS_PH_SM] }, 603 + { .compatible = "atlas,ec-sm", .data = &atlas_devices[ATLAS_EC_SM] }, 604 + { .compatible = "atlas,orp-sm", .data = &atlas_devices[ATLAS_ORP_SM] }, 605 + { .compatible = "atlas,do-sm", .data = &atlas_devices[ATLAS_DO_SM] }, 606 + { .compatible = "atlas,rtd-sm", .data = &atlas_devices[ATLAS_RTD_SM] }, 607 607 { } 608 608 }; 609 609 MODULE_DEVICE_TABLE(of, atlas_dt_ids); 610 610 611 611 static int atlas_probe(struct i2c_client *client) 612 612 { 613 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 614 613 struct atlas_data *data; 615 - struct atlas_device *chip; 614 + const struct atlas_device *chip; 616 615 struct iio_trigger *trig; 617 616 struct iio_dev *indio_dev; 618 617 int ret; ··· 620 621 if (!indio_dev) 621 622 return -ENOMEM; 622 623 623 - if (!dev_fwnode(&client->dev)) 624 - chip = &atlas_devices[id->driver_data]; 625 - else 626 - chip = &atlas_devices[(unsigned long)device_get_match_data(&client->dev)]; 624 + chip = i2c_get_match_data(client); 627 625 628 626 indio_dev->info = &atlas_info; 629 627 indio_dev->name = ATLAS_DRV_NAME;

+12 -12

drivers/iio/chemical/sgp30.c

··· 114 114 }; 115 115 116 116 struct sgp_device { 117 + unsigned long product_id; 117 118 const struct iio_chan_spec *channels; 118 119 int num_channels; 119 120 }; ··· 183 182 184 183 static const struct sgp_device sgp_devices[] = { 185 184 [SGP30] = { 185 + .product_id = SGP30, 186 186 .channels = sgp30_channels, 187 187 .num_channels = ARRAY_SIZE(sgp30_channels), 188 188 }, 189 189 [SGPC3] = { 190 + .product_id = SGPC3, 190 191 .channels = sgpc3_channels, 191 192 .num_channels = ARRAY_SIZE(sgpc3_channels), 192 193 }, ··· 494 491 }; 495 492 496 493 static const struct of_device_id sgp_dt_ids[] = { 497 - { .compatible = "sensirion,sgp30", .data = (void *)SGP30 }, 498 - { .compatible = "sensirion,sgpc3", .data = (void *)SGPC3 }, 494 + { .compatible = "sensirion,sgp30", .data = &sgp_devices[SGP30] }, 495 + { .compatible = "sensirion,sgpc3", .data = &sgp_devices[SGPC3] }, 499 496 { } 500 497 }; 501 498 502 499 static int sgp_probe(struct i2c_client *client) 503 500 { 504 501 const struct i2c_device_id *id = i2c_client_get_device_id(client); 502 + const struct sgp_device *match_data; 505 503 struct device *dev = &client->dev; 506 504 struct iio_dev *indio_dev; 507 505 struct sgp_data *data; 508 - unsigned long product_id; 509 506 int ret; 510 507 511 508 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 512 509 if (!indio_dev) 513 510 return -ENOMEM; 514 511 515 - if (dev_fwnode(dev)) 516 - product_id = (unsigned long)device_get_match_data(dev); 517 - else 518 - product_id = id->driver_data; 512 + match_data = i2c_get_match_data(client); 519 513 520 514 data = iio_priv(indio_dev); 521 515 i2c_set_clientdata(client, indio_dev); ··· 528 528 529 529 data->feature_set = be16_to_cpu(data->buffer.raw_words[0].value); 530 530 531 - ret = sgp_check_compat(data, product_id); 531 + ret = sgp_check_compat(data, match_data->product_id); 532 532 if (ret) 533 533 return ret; 534 534 535 535 indio_dev->info = &sgp_info; 536 536 indio_dev->name = id->name; 537 537 indio_dev->modes = INDIO_DIRECT_MODE; 538 - indio_dev->channels = sgp_devices[product_id].channels; 539 - indio_dev->num_channels = sgp_devices[product_id].num_channels; 538 + indio_dev->channels = match_data->channels; 539 + indio_dev->num_channels = match_data->num_channels; 540 540 541 541 sgp_init(data); 542 542 ··· 562 562 } 563 563 564 564 static const struct i2c_device_id sgp_id[] = { 565 - { "sgp30", SGP30 }, 566 - { "sgpc3", SGPC3 }, 565 + { "sgp30", (kernel_ulong_t)&sgp_devices[SGP30] }, 566 + { "sgpc3", (kernel_ulong_t)&sgp_devices[SGPC3] }, 567 567 { } 568 568 }; 569 569

+5 -11

drivers/iio/chemical/vz89x.c

··· 342 342 }; 343 343 344 344 static const struct of_device_id vz89x_dt_ids[] = { 345 - { .compatible = "sgx,vz89x", .data = (void *) VZ89X }, 346 - { .compatible = "sgx,vz89te", .data = (void *) VZ89TE }, 345 + { .compatible = "sgx,vz89x", .data = &vz89x_chips[VZ89X] }, 346 + { .compatible = "sgx,vz89te", .data = &vz89x_chips[VZ89TE] }, 347 347 { } 348 348 }; 349 349 MODULE_DEVICE_TABLE(of, vz89x_dt_ids); 350 350 351 351 static int vz89x_probe(struct i2c_client *client) 352 352 { 353 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 354 353 struct device *dev = &client->dev; 355 354 struct iio_dev *indio_dev; 356 355 struct vz89x_data *data; 357 - int chip_id; 358 356 359 357 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 360 358 if (!indio_dev) ··· 367 369 else 368 370 return -EOPNOTSUPP; 369 371 370 - if (!dev_fwnode(dev)) 371 - chip_id = id->driver_data; 372 - else 373 - chip_id = (unsigned long)device_get_match_data(dev); 372 + data->chip = i2c_get_match_data(client); 374 373 375 374 i2c_set_clientdata(client, indio_dev); 376 375 data->client = client; 377 - data->chip = &vz89x_chips[chip_id]; 378 376 data->last_update = jiffies - HZ; 379 377 mutex_init(&data->lock); 380 378 ··· 385 391 } 386 392 387 393 static const struct i2c_device_id vz89x_id[] = { 388 - { "vz89x", VZ89X }, 389 - { "vz89te", VZ89TE }, 394 + { "vz89x", (kernel_ulong_t)&vz89x_chips[VZ89X] }, 395 + { "vz89te", (kernel_ulong_t)&vz89x_chips[VZ89TE] }, 390 396 { } 391 397 }; 392 398 MODULE_DEVICE_TABLE(i2c, vz89x_id);

+2 -4

drivers/iio/dac/dpot-dac.c

··· 226 226 return ret; 227 227 } 228 228 229 - static int dpot_dac_remove(struct platform_device *pdev) 229 + static void dpot_dac_remove(struct platform_device *pdev) 230 230 { 231 231 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 232 232 struct dpot_dac *dac = iio_priv(indio_dev); 233 233 234 234 iio_device_unregister(indio_dev); 235 235 regulator_disable(dac->vref); 236 - 237 - return 0; 238 236 } 239 237 240 238 static const struct of_device_id dpot_dac_match[] = { ··· 243 245 244 246 static struct platform_driver dpot_dac_driver = { 245 247 .probe = dpot_dac_probe, 246 - .remove = dpot_dac_remove, 248 + .remove_new = dpot_dac_remove, 247 249 .driver = { 248 250 .name = "iio-dpot-dac", 249 251 .of_match_table = dpot_dac_match,

+2 -4

drivers/iio/dac/lpc18xx_dac.c

··· 165 165 return ret; 166 166 } 167 167 168 - static int lpc18xx_dac_remove(struct platform_device *pdev) 168 + static void lpc18xx_dac_remove(struct platform_device *pdev) 169 169 { 170 170 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 171 171 struct lpc18xx_dac *dac = iio_priv(indio_dev); ··· 175 175 writel(0, dac->base + LPC18XX_DAC_CTRL); 176 176 clk_disable_unprepare(dac->clk); 177 177 regulator_disable(dac->vref); 178 - 179 - return 0; 180 178 } 181 179 182 180 static const struct of_device_id lpc18xx_dac_match[] = { ··· 185 187 186 188 static struct platform_driver lpc18xx_dac_driver = { 187 189 .probe = lpc18xx_dac_probe, 188 - .remove = lpc18xx_dac_remove, 190 + .remove_new = lpc18xx_dac_remove, 189 191 .driver = { 190 192 .name = "lpc18xx-dac", 191 193 .of_match_table = lpc18xx_dac_match,

+28 -14

drivers/iio/dac/mcp4725.c

··· 30 30 #define MCP472X_REF_VREF_UNBUFFERED 0x02 31 31 #define MCP472X_REF_VREF_BUFFERED 0x03 32 32 33 + struct mcp4725_chip_info { 34 + const struct iio_chan_spec *chan_spec; 35 + u8 dac_reg_offset; 36 + bool use_ext_ref_voltage; 37 + }; 38 + 33 39 struct mcp4725_data { 34 40 struct i2c_client *client; 35 - int id; 36 41 unsigned ref_mode; 37 42 bool vref_buffered; 38 43 u16 dac_value; ··· 389 384 static int mcp4725_probe(struct i2c_client *client) 390 385 { 391 386 const struct i2c_device_id *id = i2c_client_get_device_id(client); 387 + const struct mcp4725_chip_info *info; 392 388 struct mcp4725_data *data; 393 389 struct iio_dev *indio_dev; 394 390 struct mcp4725_platform_data *pdata, pdata_dt; ··· 404 398 data = iio_priv(indio_dev); 405 399 i2c_set_clientdata(client, indio_dev); 406 400 data->client = client; 407 - if (dev_fwnode(&client->dev)) 408 - data->id = (uintptr_t)device_get_match_data(&client->dev); 409 - else 410 - data->id = id->driver_data; 401 + info = i2c_get_match_data(client); 411 402 pdata = dev_get_platdata(&client->dev); 412 403 413 404 if (!pdata) { ··· 417 414 pdata = &pdata_dt; 418 415 } 419 416 420 - if (data->id == MCP4725 && pdata->use_vref) { 417 + if (info->use_ext_ref_voltage && pdata->use_vref) { 421 418 dev_err(&client->dev, 422 419 "external reference is unavailable on MCP4725"); 423 420 return -EINVAL; ··· 458 455 459 456 indio_dev->name = id->name; 460 457 indio_dev->info = &mcp4725_info; 461 - indio_dev->channels = &mcp472x_channel[id->driver_data]; 458 + indio_dev->channels = info->chan_spec; 462 459 indio_dev->num_channels = 1; 463 460 indio_dev->modes = INDIO_DIRECT_MODE; 464 461 465 462 /* read current DAC value and settings */ 466 - err = i2c_master_recv(client, inbuf, data->id == MCP4725 ? 3 : 4); 463 + err = i2c_master_recv(client, inbuf, info->dac_reg_offset); 467 464 468 465 if (err < 0) { 469 466 dev_err(&client->dev, "failed to read DAC value"); ··· 473 470 data->powerdown = pd > 0; 474 471 data->powerdown_mode = pd ? pd - 1 : 2; /* largest resistor to gnd */ 475 472 data->dac_value = (inbuf[1] << 4) | (inbuf[2] >> 4); 476 - if (data->id == MCP4726) 473 + if (!info->use_ext_ref_voltage) 477 474 ref = (inbuf[3] >> 3) & 0x3; 478 475 479 - if (data->id == MCP4726 && ref != data->ref_mode) { 476 + if (!info->use_ext_ref_voltage && ref != data->ref_mode) { 480 477 dev_info(&client->dev, 481 478 "voltage reference mode differs (conf: %u, eeprom: %u), setting %u", 482 479 data->ref_mode, ref, data->ref_mode); ··· 513 510 regulator_disable(data->vdd_reg); 514 511 } 515 512 513 + static const struct mcp4725_chip_info mcp4725 = { 514 + .chan_spec = &mcp472x_channel[MCP4725], 515 + .dac_reg_offset = 3, 516 + .use_ext_ref_voltage = true, 517 + }; 518 + 519 + static const struct mcp4725_chip_info mcp4726 = { 520 + .chan_spec = &mcp472x_channel[MCP4726], 521 + .dac_reg_offset = 4, 522 + }; 523 + 516 524 static const struct i2c_device_id mcp4725_id[] = { 517 - { "mcp4725", MCP4725 }, 518 - { "mcp4726", MCP4726 }, 525 + { "mcp4725", (kernel_ulong_t)&mcp4725 }, 526 + { "mcp4726", (kernel_ulong_t)&mcp4726 }, 519 527 { } 520 528 }; 521 529 MODULE_DEVICE_TABLE(i2c, mcp4725_id); ··· 534 520 static const struct of_device_id mcp4725_of_match[] = { 535 521 { 536 522 .compatible = "microchip,mcp4725", 537 - .data = (void *)MCP4725 523 + .data = &mcp4725 538 524 }, 539 525 { 540 526 .compatible = "microchip,mcp4726", 541 - .data = (void *)MCP4726 527 + .data = &mcp4726 542 528 }, 543 529 { } 544 530 };

+6 -9

drivers/iio/dac/stm32-dac-core.c

··· 9 9 10 10 #include <linux/clk.h> 11 11 #include <linux/delay.h> 12 + #include <linux/mod_devicetable.h> 12 13 #include <linux/module.h> 13 14 #include <linux/of_platform.h> 15 + #include <linux/platform_device.h> 14 16 #include <linux/pm_runtime.h> 17 + #include <linux/property.h> 15 18 #include <linux/regulator/consumer.h> 16 19 #include <linux/reset.h> 17 20 ··· 97 94 struct reset_control *rst; 98 95 int ret; 99 96 100 - if (!dev->of_node) 101 - return -ENODEV; 102 - 103 97 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 104 98 if (!priv) 105 99 return -ENOMEM; 106 100 platform_set_drvdata(pdev, &priv->common); 107 101 108 - cfg = (const struct stm32_dac_cfg *) 109 - of_match_device(dev->driver->of_match_table, dev)->data; 102 + cfg = device_get_match_data(dev); 110 103 111 104 mmio = devm_platform_ioremap_resource(pdev, 0); 112 105 if (IS_ERR(mmio)) ··· 182 183 return ret; 183 184 } 184 185 185 - static int stm32_dac_remove(struct platform_device *pdev) 186 + static void stm32_dac_remove(struct platform_device *pdev) 186 187 { 187 188 pm_runtime_get_sync(&pdev->dev); 188 189 of_platform_depopulate(&pdev->dev); ··· 190 191 pm_runtime_disable(&pdev->dev); 191 192 pm_runtime_set_suspended(&pdev->dev); 192 193 pm_runtime_put_noidle(&pdev->dev); 193 - 194 - return 0; 195 194 } 196 195 197 196 static int stm32_dac_core_resume(struct device *dev) ··· 246 249 247 250 static struct platform_driver stm32_dac_driver = { 248 251 .probe = stm32_dac_probe, 249 - .remove = stm32_dac_remove, 252 + .remove_new = stm32_dac_remove, 250 253 .driver = { 251 254 .name = "stm32-dac-core", 252 255 .of_match_table = stm32_dac_of_match,

+4 -5

drivers/iio/dac/stm32-dac.c

··· 11 11 #include <linux/delay.h> 12 12 #include <linux/iio/iio.h> 13 13 #include <linux/kernel.h> 14 + #include <linux/kstrtox.h> 14 15 #include <linux/module.h> 15 16 #include <linux/mod_devicetable.h> 16 17 #include <linux/of.h> 17 18 #include <linux/platform_device.h> 18 19 #include <linux/pm_runtime.h> 19 - #include <linux/string_helpers.h> 20 + #include <linux/string_choices.h> 20 21 21 22 #include "stm32-dac-core.h" 22 23 ··· 362 361 return ret; 363 362 } 364 363 365 - static int stm32_dac_remove(struct platform_device *pdev) 364 + static void stm32_dac_remove(struct platform_device *pdev) 366 365 { 367 366 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 368 367 ··· 371 370 pm_runtime_disable(&pdev->dev); 372 371 pm_runtime_set_suspended(&pdev->dev); 373 372 pm_runtime_put_noidle(&pdev->dev); 374 - 375 - return 0; 376 373 } 377 374 378 375 static int stm32_dac_suspend(struct device *dev) ··· 398 399 399 400 static struct platform_driver stm32_dac_driver = { 400 401 .probe = stm32_dac_probe, 401 - .remove = stm32_dac_remove, 402 + .remove_new = stm32_dac_remove, 402 403 .driver = { 403 404 .name = "stm32-dac", 404 405 .of_match_table = stm32_dac_of_match,

+21 -27

drivers/iio/dac/ti-dac5571.c

··· 313 313 const struct dac5571_spec *spec; 314 314 struct dac5571_data *data; 315 315 struct iio_dev *indio_dev; 316 - enum chip_id chip_id; 317 316 int ret, i; 318 317 319 318 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); ··· 328 329 indio_dev->modes = INDIO_DIRECT_MODE; 329 330 indio_dev->channels = dac5571_channels; 330 331 331 - if (dev_fwnode(dev)) 332 - chip_id = (uintptr_t)device_get_match_data(dev); 333 - else 334 - chip_id = id->driver_data; 335 - 336 - spec = &dac5571_spec[chip_id]; 332 + spec = i2c_get_match_data(client); 337 333 338 334 indio_dev->num_channels = spec->num_channels; 339 335 data->spec = spec; ··· 386 392 } 387 393 388 394 static const struct of_device_id dac5571_of_id[] = { 389 - {.compatible = "ti,dac5571", .data = (void *)single_8bit}, 390 - {.compatible = "ti,dac6571", .data = (void *)single_10bit}, 391 - {.compatible = "ti,dac7571", .data = (void *)single_12bit}, 392 - {.compatible = "ti,dac5574", .data = (void *)quad_8bit}, 393 - {.compatible = "ti,dac6574", .data = (void *)quad_10bit}, 394 - {.compatible = "ti,dac7574", .data = (void *)quad_12bit}, 395 - {.compatible = "ti,dac5573", .data = (void *)quad_8bit}, 396 - {.compatible = "ti,dac6573", .data = (void *)quad_10bit}, 397 - {.compatible = "ti,dac7573", .data = (void *)quad_12bit}, 398 - {.compatible = "ti,dac121c081", .data = (void *)single_12bit}, 395 + {.compatible = "ti,dac121c081", .data = &dac5571_spec[single_12bit] }, 396 + {.compatible = "ti,dac5571", .data = &dac5571_spec[single_8bit] }, 397 + {.compatible = "ti,dac6571", .data = &dac5571_spec[single_10bit] }, 398 + {.compatible = "ti,dac7571", .data = &dac5571_spec[single_12bit] }, 399 + {.compatible = "ti,dac5574", .data = &dac5571_spec[quad_8bit] }, 400 + {.compatible = "ti,dac6574", .data = &dac5571_spec[quad_10bit] }, 401 + {.compatible = "ti,dac7574", .data = &dac5571_spec[quad_12bit] }, 402 + {.compatible = "ti,dac5573", .data = &dac5571_spec[quad_8bit] }, 403 + {.compatible = "ti,dac6573", .data = &dac5571_spec[quad_10bit] }, 404 + {.compatible = "ti,dac7573", .data = &dac5571_spec[quad_12bit] }, 399 405 {} 400 406 }; 401 407 MODULE_DEVICE_TABLE(of, dac5571_of_id); 402 408 403 409 static const struct i2c_device_id dac5571_id[] = { 404 - {"dac5571", single_8bit}, 405 - {"dac6571", single_10bit}, 406 - {"dac7571", single_12bit}, 407 - {"dac5574", quad_8bit}, 408 - {"dac6574", quad_10bit}, 409 - {"dac7574", quad_12bit}, 410 - {"dac5573", quad_8bit}, 411 - {"dac6573", quad_10bit}, 412 - {"dac7573", quad_12bit}, 413 - {"dac121c081", single_12bit}, 410 + {"dac121c081", (kernel_ulong_t)&dac5571_spec[single_12bit] }, 411 + {"dac5571", (kernel_ulong_t)&dac5571_spec[single_8bit] }, 412 + {"dac6571", (kernel_ulong_t)&dac5571_spec[single_10bit] }, 413 + {"dac7571", (kernel_ulong_t)&dac5571_spec[single_12bit] }, 414 + {"dac5574", (kernel_ulong_t)&dac5571_spec[quad_8bit] }, 415 + {"dac6574", (kernel_ulong_t)&dac5571_spec[quad_10bit] }, 416 + {"dac7574", (kernel_ulong_t)&dac5571_spec[quad_12bit] }, 417 + {"dac5573", (kernel_ulong_t)&dac5571_spec[quad_8bit] }, 418 + {"dac6573", (kernel_ulong_t)&dac5571_spec[quad_10bit] }, 419 + {"dac7573", (kernel_ulong_t)&dac5571_spec[quad_12bit] }, 414 420 {} 415 421 }; 416 422 MODULE_DEVICE_TABLE(i2c, dac5571_id);

+2 -4

drivers/iio/dac/vf610_dac.c

··· 231 231 return ret; 232 232 } 233 233 234 - static int vf610_dac_remove(struct platform_device *pdev) 234 + static void vf610_dac_remove(struct platform_device *pdev) 235 235 { 236 236 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 237 237 struct vf610_dac *info = iio_priv(indio_dev); ··· 239 239 iio_device_unregister(indio_dev); 240 240 vf610_dac_exit(info); 241 241 clk_disable_unprepare(info->clk); 242 - 243 - return 0; 244 242 } 245 243 246 244 static int vf610_dac_suspend(struct device *dev) ··· 272 274 273 275 static struct platform_driver vf610_dac_driver = { 274 276 .probe = vf610_dac_probe, 275 - .remove = vf610_dac_remove, 277 + .remove_new = vf610_dac_remove, 276 278 .driver = { 277 279 .name = "vf610-dac", 278 280 .of_match_table = vf610_dac_match,

+23 -52

drivers/iio/frequency/adf4350.c

··· 33 33 34 34 struct adf4350_state { 35 35 struct spi_device *spi; 36 - struct regulator *reg; 37 36 struct gpio_desc *lock_detect_gpiod; 38 37 struct adf4350_platform_data *pdata; 39 38 struct clk *clk; ··· 468 469 return pdata; 469 470 } 470 471 472 + static void adf4350_power_down(void *data) 473 + { 474 + struct iio_dev *indio_dev = data; 475 + struct adf4350_state *st = iio_priv(indio_dev); 476 + 477 + st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 478 + adf4350_sync_config(st); 479 + } 480 + 471 481 static int adf4350_probe(struct spi_device *spi) 472 482 { 473 483 struct adf4350_platform_data *pdata; ··· 499 491 } 500 492 501 493 if (!pdata->clkin) { 502 - clk = devm_clk_get(&spi->dev, "clkin"); 494 + clk = devm_clk_get_enabled(&spi->dev, "clkin"); 503 495 if (IS_ERR(clk)) 504 - return -EPROBE_DEFER; 505 - 506 - ret = clk_prepare_enable(clk); 507 - if (ret < 0) 508 - return ret; 496 + return PTR_ERR(clk); 509 497 } 510 498 511 499 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 512 - if (indio_dev == NULL) { 513 - ret = -ENOMEM; 514 - goto error_disable_clk; 515 - } 500 + if (indio_dev == NULL) 501 + return -ENOMEM; 516 502 517 503 st = iio_priv(indio_dev); 518 504 519 - st->reg = devm_regulator_get(&spi->dev, "vcc"); 520 - if (!IS_ERR(st->reg)) { 521 - ret = regulator_enable(st->reg); 522 - if (ret) 523 - goto error_disable_clk; 524 - } 505 + ret = devm_regulator_get_enable(&spi->dev, "vcc"); 506 + if (ret) 507 + return ret; 525 508 526 - spi_set_drvdata(spi, indio_dev); 527 509 st->spi = spi; 528 510 st->pdata = pdata; 529 511 ··· 542 544 543 545 st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL, 544 546 GPIOD_IN); 545 - if (IS_ERR(st->lock_detect_gpiod)) { 546 - ret = PTR_ERR(st->lock_detect_gpiod); 547 - goto error_disable_reg; 548 - } 547 + if (IS_ERR(st->lock_detect_gpiod)) 548 + return PTR_ERR(st->lock_detect_gpiod); 549 549 550 550 if (pdata->power_up_frequency) { 551 551 ret = adf4350_set_freq(st, pdata->power_up_frequency); 552 552 if (ret) 553 - goto error_disable_reg; 553 + return ret; 554 554 } 555 555 556 - ret = iio_device_register(indio_dev); 556 + ret = devm_add_action_or_reset(&spi->dev, adf4350_power_down, indio_dev); 557 557 if (ret) 558 - goto error_disable_reg; 558 + return dev_err_probe(&spi->dev, ret, 559 + "Failed to add action to managed power down\n"); 559 560 560 - return 0; 561 - 562 - error_disable_reg: 563 - if (!IS_ERR(st->reg)) 564 - regulator_disable(st->reg); 565 - error_disable_clk: 566 - clk_disable_unprepare(clk); 567 - 568 - return ret; 569 - } 570 - 571 - static void adf4350_remove(struct spi_device *spi) 572 - { 573 - struct iio_dev *indio_dev = spi_get_drvdata(spi); 574 - struct adf4350_state *st = iio_priv(indio_dev); 575 - struct regulator *reg = st->reg; 576 - 577 - st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 578 - adf4350_sync_config(st); 579 - 580 - iio_device_unregister(indio_dev); 581 - 582 - clk_disable_unprepare(st->clk); 583 - 584 - if (!IS_ERR(reg)) 585 - regulator_disable(reg); 561 + return devm_iio_device_register(&spi->dev, indio_dev); 586 562 } 587 563 588 564 static const struct of_device_id adf4350_of_match[] = { ··· 579 607 .of_match_table = adf4350_of_match, 580 608 }, 581 609 .probe = adf4350_probe, 582 - .remove = adf4350_remove, 583 610 .id_table = adf4350_id, 584 611 }; 585 612 module_spi_driver(adf4350_driver);

+2 -4

drivers/iio/gyro/hid-sensor-gyro-3d.c

··· 359 359 } 360 360 361 361 /* Function to deinitialize the processing for usage id */ 362 - static int hid_gyro_3d_remove(struct platform_device *pdev) 362 + static void hid_gyro_3d_remove(struct platform_device *pdev) 363 363 { 364 364 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 365 365 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 368 368 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_GYRO_3D); 369 369 iio_device_unregister(indio_dev); 370 370 hid_sensor_remove_trigger(indio_dev, &gyro_state->common_attributes); 371 - 372 - return 0; 373 371 } 374 372 375 373 static const struct platform_device_id hid_gyro_3d_ids[] = { ··· 386 388 .pm = &hid_sensor_pm_ops, 387 389 }, 388 390 .probe = hid_gyro_3d_probe, 389 - .remove = hid_gyro_3d_remove, 391 + .remove_new = hid_gyro_3d_remove, 390 392 }; 391 393 module_platform_driver(hid_gyro_3d_platform_driver); 392 394

+2 -4

drivers/iio/humidity/hid-sensor-humidity.c

··· 260 260 } 261 261 262 262 /* Function to deinitialize the processing for usage id */ 263 - static int hid_humidity_remove(struct platform_device *pdev) 263 + static void hid_humidity_remove(struct platform_device *pdev) 264 264 { 265 265 struct hid_sensor_hub_device *hsdev = dev_get_platdata(&pdev->dev); 266 266 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 269 269 iio_device_unregister(indio_dev); 270 270 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_HUMIDITY); 271 271 hid_sensor_remove_trigger(indio_dev, &humid_st->common_attributes); 272 - 273 - return 0; 274 272 } 275 273 276 274 static const struct platform_device_id hid_humidity_ids[] = { ··· 287 289 .pm = &hid_sensor_pm_ops, 288 290 }, 289 291 .probe = hid_humidity_probe, 290 - .remove = hid_humidity_remove, 292 + .remove_new = hid_humidity_remove, 291 293 }; 292 294 module_platform_driver(hid_humidity_platform_driver); 293 295

+7

drivers/iio/humidity/si7005.c

··· 169 169 }; 170 170 MODULE_DEVICE_TABLE(i2c, si7005_id); 171 171 172 + static const struct of_device_id si7005_dt_ids[] = { 173 + { .compatible = "silabs,si7005" }, 174 + { } 175 + }; 176 + MODULE_DEVICE_TABLE(of, si7005_dt_ids); 177 + 172 178 static struct i2c_driver si7005_driver = { 173 179 .driver = { 174 180 .name = "si7005", 181 + .of_match_table = si7005_dt_ids, 175 182 }, 176 183 .probe = si7005_probe, 177 184 .id_table = si7005_id,

-3

drivers/iio/iio_core.h

··· 30 30 unsigned int cmd, unsigned long arg); 31 31 }; 32 32 33 - long iio_device_ioctl(struct iio_dev *indio_dev, struct file *filp, 34 - unsigned int cmd, unsigned long arg); 35 - 36 33 void iio_device_ioctl_handler_register(struct iio_dev *indio_dev, 37 34 struct iio_ioctl_handler *h); 38 35 void iio_device_ioctl_handler_unregister(struct iio_ioctl_handler *h);

+200 -38

drivers/iio/imu/adis16475.c

··· 31 31 #define ADIS16475_REG_Y_ACCEL_L 0x14 32 32 #define ADIS16475_REG_Z_ACCEL_L 0x18 33 33 #define ADIS16475_REG_TEMP_OUT 0x1c 34 + #define ADIS16475_REG_X_DELTANG_L 0x24 35 + #define ADIS16475_REG_Y_DELTANG_L 0x28 36 + #define ADIS16475_REG_Z_DELTANG_L 0x2C 37 + #define ADIS16475_REG_X_DELTVEL_L 0x30 38 + #define ADIS16475_REG_Y_DELTVEL_L 0x34 39 + #define ADIS16475_REG_Z_DELTVEL_L 0x38 34 40 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40 35 41 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 36 42 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 ··· 61 55 #define ADIS16475_REG_PROD_ID 0x72 62 56 #define ADIS16475_REG_SERIAL_NUM 0x74 63 57 #define ADIS16475_REG_FLASH_CNT 0x7c 58 + #define ADIS16500_BURST_DATA_SEL_MASK BIT(8) 64 59 #define ADIS16500_BURST32_MASK BIT(9) 65 60 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) 66 61 /* number of data elements in burst mode */ ··· 72 65 #define ADIS16475_BURST_MAX_SPEED 1000000 73 66 #define ADIS16475_LSB_DEC_MASK BIT(0) 74 67 #define ADIS16475_LSB_FIR_MASK BIT(1) 68 + #define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) 69 + #define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7) 75 70 76 71 enum { 77 72 ADIS16475_SYNC_DIRECT = 1, ··· 93 84 const struct adis16475_sync *sync; 94 85 const struct adis_data adis_data; 95 86 const char *name; 87 + #define ADIS16475_HAS_BURST32 BIT(0) 88 + #define ADIS16475_HAS_BURST_DELTA_DATA BIT(1) 89 + const long flags; 96 90 u32 num_channels; 97 91 u32 gyro_max_val; 98 92 u32 gyro_max_scale; 99 93 u32 accel_max_val; 100 94 u32 accel_max_scale; 101 95 u32 temp_scale; 96 + u32 deltang_max_val; 97 + u32 deltvel_max_val; 102 98 u32 int_clk; 103 99 u16 max_dec; 104 100 u8 num_sync; 105 - bool has_burst32; 106 101 }; 107 102 108 103 struct adis16475 { ··· 128 115 ADIS16475_SCAN_ACCEL_Y, 129 116 ADIS16475_SCAN_ACCEL_Z, 130 117 ADIS16475_SCAN_TEMP, 118 + ADIS16475_SCAN_DELTANG_X, 119 + ADIS16475_SCAN_DELTANG_Y, 120 + ADIS16475_SCAN_DELTANG_Z, 121 + ADIS16475_SCAN_DELTVEL_X, 122 + ADIS16475_SCAN_DELTVEL_Y, 123 + ADIS16475_SCAN_DELTVEL_Z, 131 124 }; 132 125 133 126 static bool low_rate_allow; ··· 470 451 case IIO_TEMP: 471 452 *val = st->info->temp_scale; 472 453 return IIO_VAL_INT; 454 + case IIO_DELTA_ANGL: 455 + *val = st->info->deltang_max_val; 456 + *val2 = 31; 457 + return IIO_VAL_FRACTIONAL_LOG2; 458 + case IIO_DELTA_VELOCITY: 459 + *val = st->info->deltvel_max_val; 460 + *val2 = 31; 461 + return IIO_VAL_FRACTIONAL_LOG2; 473 462 default: 474 463 return -EINVAL; 475 464 } ··· 578 551 }, \ 579 552 } 580 553 554 + #define ADIS16475_MOD_CHAN_DELTA(_type, _mod, _address, _si, _r_bits, _s_bits) { \ 555 + .type = (_type), \ 556 + .modified = 1, \ 557 + .channel2 = (_mod), \ 558 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 559 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 560 + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 561 + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 562 + .address = (_address), \ 563 + .scan_index = _si, \ 564 + .scan_type = { \ 565 + .sign = 's', \ 566 + .realbits = (_r_bits), \ 567 + .storagebits = (_s_bits), \ 568 + .endianness = IIO_BE, \ 569 + }, \ 570 + } 571 + 572 + #define ADIS16475_DELTANG_CHAN(_mod) \ 573 + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 574 + ADIS16475_REG_ ## _mod ## _DELTANG_L, ADIS16475_SCAN_DELTANG_ ## _mod, 32, 32) 575 + 576 + #define ADIS16475_DELTVEL_CHAN(_mod) \ 577 + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 578 + ADIS16475_REG_ ## _mod ## _DELTVEL_L, ADIS16475_SCAN_DELTVEL_ ## _mod, 32, 32) 579 + 580 + #define ADIS16475_DELTANG_CHAN_NO_SCAN(_mod) \ 581 + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 582 + ADIS16475_REG_ ## _mod ## _DELTANG_L, -1, 32, 32) 583 + 584 + #define ADIS16475_DELTVEL_CHAN_NO_SCAN(_mod) \ 585 + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 586 + ADIS16475_REG_ ## _mod ## _DELTVEL_L, -1, 32, 32) 587 + 588 + static const struct iio_chan_spec adis16477_channels[] = { 589 + ADIS16475_GYRO_CHANNEL(X), 590 + ADIS16475_GYRO_CHANNEL(Y), 591 + ADIS16475_GYRO_CHANNEL(Z), 592 + ADIS16475_ACCEL_CHANNEL(X), 593 + ADIS16475_ACCEL_CHANNEL(Y), 594 + ADIS16475_ACCEL_CHANNEL(Z), 595 + ADIS16475_TEMP_CHANNEL(), 596 + ADIS16475_DELTANG_CHAN(X), 597 + ADIS16475_DELTANG_CHAN(Y), 598 + ADIS16475_DELTANG_CHAN(Z), 599 + ADIS16475_DELTVEL_CHAN(X), 600 + ADIS16475_DELTVEL_CHAN(Y), 601 + ADIS16475_DELTVEL_CHAN(Z), 602 + IIO_CHAN_SOFT_TIMESTAMP(13) 603 + }; 604 + 581 605 static const struct iio_chan_spec adis16475_channels[] = { 582 606 ADIS16475_GYRO_CHANNEL(X), 583 607 ADIS16475_GYRO_CHANNEL(Y), ··· 637 559 ADIS16475_ACCEL_CHANNEL(Y), 638 560 ADIS16475_ACCEL_CHANNEL(Z), 639 561 ADIS16475_TEMP_CHANNEL(), 562 + ADIS16475_DELTANG_CHAN_NO_SCAN(X), 563 + ADIS16475_DELTANG_CHAN_NO_SCAN(Y), 564 + ADIS16475_DELTANG_CHAN_NO_SCAN(Z), 565 + ADIS16475_DELTVEL_CHAN_NO_SCAN(X), 566 + ADIS16475_DELTVEL_CHAN_NO_SCAN(Y), 567 + ADIS16475_DELTVEL_CHAN_NO_SCAN(Z), 640 568 IIO_CHAN_SOFT_TIMESTAMP(7) 641 569 }; 642 570 ··· 746 662 .accel_max_val = 1, 747 663 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 748 664 .temp_scale = 100, 665 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 666 + .deltvel_max_val = 400, 749 667 .int_clk = 2000, 750 668 .max_dec = 1999, 751 669 .sync = adis16475_sync_mode, ··· 763 677 .accel_max_val = 1, 764 678 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 765 679 .temp_scale = 100, 680 + .deltang_max_val = IIO_DEGREE_TO_RAD(360), 681 + .deltvel_max_val = 100, 766 682 .int_clk = 2000, 767 683 .max_dec = 1999, 768 684 .sync = adis16475_sync_mode, ··· 780 692 .accel_max_val = 1, 781 693 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 782 694 .temp_scale = 100, 695 + .deltang_max_val = IIO_DEGREE_TO_RAD(720), 696 + .deltvel_max_val = 100, 783 697 .int_clk = 2000, 784 698 .max_dec = 1999, 785 699 .sync = adis16475_sync_mode, ··· 797 707 .accel_max_val = 1, 798 708 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 799 709 .temp_scale = 100, 710 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 711 + .deltvel_max_val = 100, 800 712 .int_clk = 2000, 801 713 .max_dec = 1999, 802 714 .sync = adis16475_sync_mode, ··· 807 715 }, 808 716 [ADIS16477_1] = { 809 717 .name = "adis16477-1", 810 - .num_channels = ARRAY_SIZE(adis16475_channels), 811 - .channels = adis16475_channels, 718 + .num_channels = ARRAY_SIZE(adis16477_channels), 719 + .channels = adis16477_channels, 812 720 .gyro_max_val = 1, 813 721 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 814 722 .accel_max_val = 1, 815 723 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 816 724 .temp_scale = 100, 725 + .deltang_max_val = IIO_DEGREE_TO_RAD(360), 726 + .deltvel_max_val = 400, 817 727 .int_clk = 2000, 818 728 .max_dec = 1999, 819 729 .sync = adis16475_sync_mode, 820 730 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 821 - .has_burst32 = true, 731 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 822 732 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 823 733 }, 824 734 [ADIS16477_2] = { 825 735 .name = "adis16477-2", 826 - .num_channels = ARRAY_SIZE(adis16475_channels), 827 - .channels = adis16475_channels, 736 + .num_channels = ARRAY_SIZE(adis16477_channels), 737 + .channels = adis16477_channels, 828 738 .gyro_max_val = 1, 829 739 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 830 740 .accel_max_val = 1, 831 741 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 832 742 .temp_scale = 100, 743 + .deltang_max_val = IIO_DEGREE_TO_RAD(720), 744 + .deltvel_max_val = 400, 833 745 .int_clk = 2000, 834 746 .max_dec = 1999, 835 747 .sync = adis16475_sync_mode, 836 748 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 837 - .has_burst32 = true, 749 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 838 750 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 839 751 }, 840 752 [ADIS16477_3] = { 841 753 .name = "adis16477-3", 842 - .num_channels = ARRAY_SIZE(adis16475_channels), 843 - .channels = adis16475_channels, 754 + .num_channels = ARRAY_SIZE(adis16477_channels), 755 + .channels = adis16477_channels, 844 756 .gyro_max_val = 1, 845 757 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 846 758 .accel_max_val = 1, 847 759 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 848 760 .temp_scale = 100, 761 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 762 + .deltvel_max_val = 400, 849 763 .int_clk = 2000, 850 764 .max_dec = 1999, 851 765 .sync = adis16475_sync_mode, 852 766 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 853 - .has_burst32 = true, 767 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 854 768 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), 855 769 }, 856 770 [ADIS16465_1] = { ··· 868 770 .accel_max_val = 1, 869 771 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 870 772 .temp_scale = 100, 773 + .deltang_max_val = IIO_DEGREE_TO_RAD(360), 774 + .deltvel_max_val = 100, 871 775 .int_clk = 2000, 872 776 .max_dec = 1999, 873 777 .sync = adis16475_sync_mode, ··· 885 785 .accel_max_val = 1, 886 786 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 887 787 .temp_scale = 100, 788 + .deltang_max_val = IIO_DEGREE_TO_RAD(720), 789 + .deltvel_max_val = 100, 888 790 .int_clk = 2000, 889 791 .max_dec = 1999, 890 792 .sync = adis16475_sync_mode, ··· 902 800 .accel_max_val = 1, 903 801 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 904 802 .temp_scale = 100, 803 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 804 + .deltvel_max_val = 100, 905 805 .int_clk = 2000, 906 806 .max_dec = 1999, 907 807 .sync = adis16475_sync_mode, ··· 919 815 .accel_max_val = 1, 920 816 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 921 817 .temp_scale = 100, 818 + .deltang_max_val = IIO_DEGREE_TO_RAD(360), 819 + .deltvel_max_val = 400, 922 820 .int_clk = 2000, 923 821 .max_dec = 1999, 924 822 .sync = adis16475_sync_mode, ··· 936 830 .accel_max_val = 1, 937 831 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 938 832 .temp_scale = 100, 833 + .deltang_max_val = IIO_DEGREE_TO_RAD(720), 834 + .deltvel_max_val = 400, 939 835 .int_clk = 2000, 940 836 .max_dec = 1999, 941 837 .sync = adis16475_sync_mode, ··· 953 845 .accel_max_val = 1, 954 846 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 955 847 .temp_scale = 100, 848 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 849 + .deltvel_max_val = 400, 956 850 .int_clk = 2000, 957 851 .max_dec = 1999, 958 852 .sync = adis16475_sync_mode, ··· 963 853 }, 964 854 [ADIS16500] = { 965 855 .name = "adis16500", 966 - .num_channels = ARRAY_SIZE(adis16475_channels), 967 - .channels = adis16475_channels, 856 + .num_channels = ARRAY_SIZE(adis16477_channels), 857 + .channels = adis16477_channels, 968 858 .gyro_max_val = 1, 969 859 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 970 860 .accel_max_val = 392, 971 861 .accel_max_scale = 32000 << 16, 972 862 .temp_scale = 100, 863 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 864 + .deltvel_max_val = 400, 973 865 .int_clk = 2000, 974 866 .max_dec = 1999, 975 867 .sync = adis16475_sync_mode, 976 868 /* pulse sync not supported */ 977 869 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 978 - .has_burst32 = true, 870 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 979 871 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), 980 872 }, 981 873 [ADIS16505_1] = { 982 874 .name = "adis16505-1", 983 - .num_channels = ARRAY_SIZE(adis16475_channels), 984 - .channels = adis16475_channels, 875 + .num_channels = ARRAY_SIZE(adis16477_channels), 876 + .channels = adis16477_channels, 985 877 .gyro_max_val = 1, 986 878 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 987 879 .accel_max_val = 78, 988 880 .accel_max_scale = 32000 << 16, 989 881 .temp_scale = 100, 882 + .deltang_max_val = IIO_DEGREE_TO_RAD(360), 883 + .deltvel_max_val = 100, 990 884 .int_clk = 2000, 991 885 .max_dec = 1999, 992 886 .sync = adis16475_sync_mode, 993 887 /* pulse sync not supported */ 994 888 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 995 - .has_burst32 = true, 889 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 996 890 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 997 891 }, 998 892 [ADIS16505_2] = { 999 893 .name = "adis16505-2", 1000 - .num_channels = ARRAY_SIZE(adis16475_channels), 1001 - .channels = adis16475_channels, 894 + .num_channels = ARRAY_SIZE(adis16477_channels), 895 + .channels = adis16477_channels, 1002 896 .gyro_max_val = 1, 1003 897 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1004 898 .accel_max_val = 78, 1005 899 .accel_max_scale = 32000 << 16, 1006 900 .temp_scale = 100, 901 + .deltang_max_val = IIO_DEGREE_TO_RAD(720), 902 + .deltvel_max_val = 100, 1007 903 .int_clk = 2000, 1008 904 .max_dec = 1999, 1009 905 .sync = adis16475_sync_mode, 1010 906 /* pulse sync not supported */ 1011 907 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1012 - .has_burst32 = true, 908 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1013 909 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 1014 910 }, 1015 911 [ADIS16505_3] = { 1016 912 .name = "adis16505-3", 1017 - .num_channels = ARRAY_SIZE(adis16475_channels), 1018 - .channels = adis16475_channels, 913 + .num_channels = ARRAY_SIZE(adis16477_channels), 914 + .channels = adis16477_channels, 1019 915 .gyro_max_val = 1, 1020 916 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1021 917 .accel_max_val = 78, 1022 918 .accel_max_scale = 32000 << 16, 1023 919 .temp_scale = 100, 920 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 921 + .deltvel_max_val = 100, 1024 922 .int_clk = 2000, 1025 923 .max_dec = 1999, 1026 924 .sync = adis16475_sync_mode, 1027 925 /* pulse sync not supported */ 1028 926 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1029 - .has_burst32 = true, 927 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1030 928 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), 1031 929 }, 1032 930 [ADIS16507_1] = { 1033 931 .name = "adis16507-1", 1034 - .num_channels = ARRAY_SIZE(adis16475_channels), 1035 - .channels = adis16475_channels, 932 + .num_channels = ARRAY_SIZE(adis16477_channels), 933 + .channels = adis16477_channels, 1036 934 .gyro_max_val = 1, 1037 935 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1038 936 .accel_max_val = 392, 1039 937 .accel_max_scale = 32000 << 16, 1040 938 .temp_scale = 100, 939 + .deltang_max_val = IIO_DEGREE_TO_RAD(360), 940 + .deltvel_max_val = 400, 1041 941 .int_clk = 2000, 1042 942 .max_dec = 1999, 1043 943 .sync = adis16475_sync_mode, 1044 944 /* pulse sync not supported */ 1045 945 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1046 - .has_burst32 = true, 946 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1047 947 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 1048 948 }, 1049 949 [ADIS16507_2] = { 1050 950 .name = "adis16507-2", 1051 - .num_channels = ARRAY_SIZE(adis16475_channels), 1052 - .channels = adis16475_channels, 951 + .num_channels = ARRAY_SIZE(adis16477_channels), 952 + .channels = adis16477_channels, 1053 953 .gyro_max_val = 1, 1054 954 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1055 955 .accel_max_val = 392, 1056 956 .accel_max_scale = 32000 << 16, 1057 957 .temp_scale = 100, 958 + .deltang_max_val = IIO_DEGREE_TO_RAD(720), 959 + .deltvel_max_val = 400, 1058 960 .int_clk = 2000, 1059 961 .max_dec = 1999, 1060 962 .sync = adis16475_sync_mode, 1061 963 /* pulse sync not supported */ 1062 964 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1063 - .has_burst32 = true, 965 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1064 966 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 1065 967 }, 1066 968 [ADIS16507_3] = { 1067 969 .name = "adis16507-3", 1068 - .num_channels = ARRAY_SIZE(adis16475_channels), 1069 - .channels = adis16475_channels, 970 + .num_channels = ARRAY_SIZE(adis16477_channels), 971 + .channels = adis16477_channels, 1070 972 .gyro_max_val = 1, 1071 973 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1072 974 .accel_max_val = 392, 1073 975 .accel_max_scale = 32000 << 16, 1074 976 .temp_scale = 100, 977 + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 978 + .deltvel_max_val = 400, 1075 979 .int_clk = 2000, 1076 980 .max_dec = 1999, 1077 981 .sync = adis16475_sync_mode, 1078 982 /* pulse sync not supported */ 1079 983 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1080 - .has_burst32 = true, 984 + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1081 985 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), 1082 986 }, 1083 987 }; 1084 988 989 + static int adis16475_update_scan_mode(struct iio_dev *indio_dev, 990 + const unsigned long *scan_mask) 991 + { 992 + u16 en; 993 + int ret; 994 + struct adis16475 *st = iio_priv(indio_dev); 995 + 996 + if (st->info->flags & ADIS16475_HAS_BURST_DELTA_DATA) { 997 + if ((*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) && 998 + (*scan_mask & ADIS16500_BURST_DATA_SEL_1_CHN_MASK)) 999 + return -EINVAL; 1000 + if (*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) 1001 + en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 0); 1002 + else 1003 + en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 1); 1004 + 1005 + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1006 + ADIS16500_BURST_DATA_SEL_MASK, en); 1007 + if (ret) 1008 + return ret; 1009 + } 1010 + 1011 + return adis_update_scan_mode(indio_dev, scan_mask); 1012 + } 1013 + 1085 1014 static const struct iio_info adis16475_info = { 1086 1015 .read_raw = &adis16475_read_raw, 1087 1016 .write_raw = &adis16475_write_raw, 1088 - .update_scan_mode = adis_update_scan_mode, 1017 + .update_scan_mode = adis16475_update_scan_mode, 1089 1018 .debugfs_reg_access = adis_debugfs_reg_access, 1090 1019 }; 1091 1020 ··· 1147 998 int ret; 1148 999 struct adis *adis = &st->adis; 1149 1000 1150 - if (!st->info->has_burst32) 1001 + if (!(st->info->flags & ADIS16475_HAS_BURST32)) 1151 1002 return; 1152 1003 1153 1004 if (st->lsb_flag && !st->burst32) { ··· 1193 1044 struct iio_dev *indio_dev = pf->indio_dev; 1194 1045 struct adis16475 *st = iio_priv(indio_dev); 1195 1046 struct adis *adis = &st->adis; 1196 - int ret, bit, i = 0; 1047 + int ret, bit, buff_offset = 0, i = 0; 1197 1048 __be16 *buffer; 1198 1049 u16 crc; 1199 1050 bool valid; ··· 1222 1073 switch (bit) { 1223 1074 case ADIS16475_SCAN_TEMP: 1224 1075 st->data[i++] = buffer[offset]; 1076 + /* 1077 + * The temperature channel has 16-bit storage size. 1078 + * We need to perform the padding to have the buffer 1079 + * elements naturally aligned in case there are any 1080 + * 32-bit storage size channels enabled which have a 1081 + * scan index higher than the temperature channel scan 1082 + * index. 1083 + */ 1084 + if (*indio_dev->active_scan_mask & GENMASK(ADIS16475_SCAN_DELTVEL_Z, ADIS16475_SCAN_DELTANG_X)) 1085 + st->data[i++] = 0; 1225 1086 break; 1087 + case ADIS16475_SCAN_DELTANG_X ... ADIS16475_SCAN_DELTVEL_Z: 1088 + buff_offset = ADIS16475_SCAN_DELTANG_X; 1089 + fallthrough; 1226 1090 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: 1227 1091 /* 1228 1092 * The first 2 bytes on the received data are the ··· 1243 1081 */ 1244 1082 if (st->burst32) { 1245 1083 /* upper 16 */ 1246 - st->data[i++] = buffer[bit * 2 + 2]; 1084 + st->data[i++] = buffer[(bit - buff_offset) * 2 + 2]; 1247 1085 /* lower 16 */ 1248 - st->data[i++] = buffer[bit * 2 + 1]; 1086 + st->data[i++] = buffer[(bit - buff_offset) * 2 + 1]; 1249 1087 } else { 1250 - st->data[i++] = buffer[bit + 1]; 1088 + st->data[i++] = buffer[(bit - buff_offset) + 1]; 1251 1089 /* 1252 1090 * Don't bother in doing the manual read if the 1253 1091 * device supports burst32. burst32 will be 1254 1092 * enabled in the next call to 1255 1093 * adis16475_burst32_check()... 1256 1094 */ 1257 - if (st->lsb_flag && !st->info->has_burst32) { 1095 + if (st->lsb_flag && !(st->info->flags & ADIS16475_HAS_BURST32)) { 1258 1096 u16 val = 0; 1259 1097 const u32 reg = ADIS16475_REG_X_GYRO_L + 1260 1098 bit * 4;

+13

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

··· 71 71 unsigned int val; 72 72 int ret; 73 73 74 + /* 75 + * Code based on the vendor Linux kernel v3.0, 76 + * the exact meaning is unknown. 77 + */ 78 + if (st->chip_type == INV_MPU9150) { 79 + unsigned int mask = BIT(7); 80 + 81 + val = st->level_shifter ? mask : 0; 82 + ret = regmap_update_bits(st->map, 0x1, mask, val); 83 + if (ret) 84 + return ret; 85 + } 86 + 74 87 /* configure i2c master */ 75 88 val = INV_MPU6050_BITS_I2C_MST_CLK_400KHZ | 76 89 INV_MPU6050_BIT_WAIT_FOR_ES;

+3

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

··· 17 17 #include <linux/regulator/consumer.h> 18 18 #include <linux/pm.h> 19 19 #include <linux/pm_runtime.h> 20 + #include <linux/property.h> 20 21 21 22 #include <linux/iio/common/inv_sensors_timestamp.h> 22 23 #include <linux/iio/iio.h> ··· 1496 1495 st->irq = irq; 1497 1496 st->map = regmap; 1498 1497 1498 + st->level_shifter = device_property_read_bool(dev, 1499 + "invensense,level-shifter"); 1499 1500 pdata = dev_get_platdata(dev); 1500 1501 if (!pdata) { 1501 1502 result = iio_read_mount_matrix(dev, &st->orientation);

+1 -1

drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

··· 203 203 s32 magn_raw_to_gauss[3]; 204 204 struct iio_mount_matrix magn_orient; 205 205 unsigned int suspended_sensors; 206 + bool level_shifter; 206 207 u8 *data; 207 208 }; 208 209 ··· 465 464 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable); 466 465 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, 467 466 unsigned int mask); 468 - int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 469 467 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 470 468 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 471 469 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,

+4

drivers/iio/industrialio-core.c

··· 90 90 [IIO_POSITIONRELATIVE] = "positionrelative", 91 91 [IIO_PHASE] = "phase", 92 92 [IIO_MASSCONCENTRATION] = "massconcentration", 93 + [IIO_DELTA_ANGL] = "deltaangl", 94 + [IIO_DELTA_VELOCITY] = "deltavelocity", 95 + [IIO_COLORTEMP] = "colortemp", 96 + [IIO_CHROMATICITY] = "chromaticity", 93 97 }; 94 98 95 99 static const char * const iio_modifier_names[] = {

+55

drivers/iio/industrialio-event.c

··· 355 355 return len; 356 356 } 357 357 358 + static ssize_t iio_ev_label_show(struct device *dev, 359 + struct device_attribute *attr, 360 + char *buf) 361 + { 362 + struct iio_dev *indio_dev = dev_to_iio_dev(dev); 363 + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 364 + 365 + if (indio_dev->info->read_event_label) 366 + return indio_dev->info->read_event_label(indio_dev, 367 + this_attr->c, iio_ev_attr_type(this_attr), 368 + iio_ev_attr_dir(this_attr), buf); 369 + 370 + return -EINVAL; 371 + } 372 + 358 373 static int iio_device_add_event(struct iio_dev *indio_dev, 359 374 const struct iio_chan_spec *chan, unsigned int spec_index, 360 375 enum iio_event_type type, enum iio_event_direction dir, ··· 426 411 return attrcount; 427 412 } 428 413 414 + static int iio_device_add_event_label(struct iio_dev *indio_dev, 415 + const struct iio_chan_spec *chan, 416 + unsigned int spec_index, 417 + enum iio_event_type type, 418 + enum iio_event_direction dir) 419 + { 420 + struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); 421 + char *postfix; 422 + int ret; 423 + 424 + if (!indio_dev->info->read_event_label) 425 + return 0; 426 + 427 + if (dir != IIO_EV_DIR_NONE) 428 + postfix = kasprintf(GFP_KERNEL, "%s_%s_label", 429 + iio_ev_type_text[type], 430 + iio_ev_dir_text[dir]); 431 + else 432 + postfix = kasprintf(GFP_KERNEL, "%s_label", 433 + iio_ev_type_text[type]); 434 + if (postfix == NULL) 435 + return -ENOMEM; 436 + 437 + ret = __iio_add_chan_devattr(postfix, chan, &iio_ev_label_show, NULL, 438 + spec_index, IIO_SEPARATE, &indio_dev->dev, NULL, 439 + &iio_dev_opaque->event_interface->dev_attr_list); 440 + 441 + kfree(postfix); 442 + 443 + if (ret < 0) 444 + return ret; 445 + 446 + return 1; 447 + } 448 + 429 449 static int iio_device_add_event_sysfs(struct iio_dev *indio_dev, 430 450 struct iio_chan_spec const *chan) 431 451 { ··· 495 445 ret = iio_device_add_event(indio_dev, chan, i, type, dir, 496 446 IIO_SHARED_BY_ALL, 497 447 &chan->event_spec[i].mask_shared_by_all); 448 + if (ret < 0) 449 + return ret; 450 + attrcount += ret; 451 + 452 + ret = iio_device_add_event_label(indio_dev, chan, i, type, dir); 498 453 if (ret < 0) 499 454 return ret; 500 455 attrcount += ret;

+2 -4

drivers/iio/light/cm3605.c

··· 266 266 return ret; 267 267 } 268 268 269 - static int cm3605_remove(struct platform_device *pdev) 269 + static void cm3605_remove(struct platform_device *pdev) 270 270 { 271 271 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 272 272 struct cm3605 *cm3605 = iio_priv(indio_dev); ··· 276 276 gpiod_set_value_cansleep(cm3605->aset, 0); 277 277 iio_device_unregister(indio_dev); 278 278 regulator_disable(cm3605->vdd); 279 - 280 - return 0; 281 279 } 282 280 283 281 static int cm3605_pm_suspend(struct device *dev) ··· 318 320 .pm = pm_sleep_ptr(&cm3605_dev_pm_ops), 319 321 }, 320 322 .probe = cm3605_probe, 321 - .remove = cm3605_remove, 323 + .remove_new = cm3605_remove, 322 324 }; 323 325 module_platform_driver(cm3605_driver); 324 326

+115 -19

drivers/iio/light/hid-sensor-als.c

··· 14 14 #include "../common/hid-sensors/hid-sensor-trigger.h" 15 15 16 16 enum { 17 - CHANNEL_SCAN_INDEX_INTENSITY = 0, 18 - CHANNEL_SCAN_INDEX_ILLUM = 1, 17 + CHANNEL_SCAN_INDEX_INTENSITY, 18 + CHANNEL_SCAN_INDEX_ILLUM, 19 + CHANNEL_SCAN_INDEX_COLOR_TEMP, 20 + CHANNEL_SCAN_INDEX_CHROMATICITY_X, 21 + CHANNEL_SCAN_INDEX_CHROMATICITY_Y, 19 22 CHANNEL_SCAN_INDEX_MAX 20 23 }; 21 24 ··· 27 24 struct als_state { 28 25 struct hid_sensor_hub_callbacks callbacks; 29 26 struct hid_sensor_common common_attributes; 30 - struct hid_sensor_hub_attribute_info als_illum; 27 + struct hid_sensor_hub_attribute_info als[CHANNEL_SCAN_INDEX_MAX]; 31 28 struct { 32 29 u32 illum[CHANNEL_SCAN_INDEX_MAX]; 33 30 u64 timestamp __aligned(8); ··· 68 65 BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE), 69 66 .scan_index = CHANNEL_SCAN_INDEX_ILLUM, 70 67 }, 68 + { 69 + .type = IIO_COLORTEMP, 70 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 71 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | 72 + BIT(IIO_CHAN_INFO_SCALE) | 73 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | 74 + BIT(IIO_CHAN_INFO_HYSTERESIS) | 75 + BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE), 76 + .scan_index = CHANNEL_SCAN_INDEX_COLOR_TEMP, 77 + }, 78 + { 79 + .type = IIO_CHROMATICITY, 80 + .modified = 1, 81 + .channel2 = IIO_MOD_X, 82 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 83 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | 84 + BIT(IIO_CHAN_INFO_SCALE) | 85 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | 86 + BIT(IIO_CHAN_INFO_HYSTERESIS) | 87 + BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE), 88 + .scan_index = CHANNEL_SCAN_INDEX_CHROMATICITY_X, 89 + }, 90 + { 91 + .type = IIO_CHROMATICITY, 92 + .modified = 1, 93 + .channel2 = IIO_MOD_Y, 94 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 95 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | 96 + BIT(IIO_CHAN_INFO_SCALE) | 97 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | 98 + BIT(IIO_CHAN_INFO_HYSTERESIS) | 99 + BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE), 100 + .scan_index = CHANNEL_SCAN_INDEX_CHROMATICITY_Y, 101 + }, 71 102 IIO_CHAN_SOFT_TIMESTAMP(CHANNEL_SCAN_INDEX_TIMESTAMP) 72 103 }; 73 104 ··· 136 99 switch (chan->scan_index) { 137 100 case CHANNEL_SCAN_INDEX_INTENSITY: 138 101 case CHANNEL_SCAN_INDEX_ILLUM: 139 - report_id = als_state->als_illum.report_id; 140 - min = als_state->als_illum.logical_minimum; 102 + report_id = als_state->als[chan->scan_index].report_id; 103 + min = als_state->als[chan->scan_index].logical_minimum; 141 104 address = HID_USAGE_SENSOR_LIGHT_ILLUM; 105 + break; 106 + case CHANNEL_SCAN_INDEX_COLOR_TEMP: 107 + report_id = als_state->als[chan->scan_index].report_id; 108 + min = als_state->als[chan->scan_index].logical_minimum; 109 + address = HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE; 110 + break; 111 + case CHANNEL_SCAN_INDEX_CHROMATICITY_X: 112 + report_id = als_state->als[chan->scan_index].report_id; 113 + min = als_state->als[chan->scan_index].logical_minimum; 114 + address = HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X; 115 + break; 116 + case CHANNEL_SCAN_INDEX_CHROMATICITY_Y: 117 + report_id = als_state->als[chan->scan_index].report_id; 118 + min = als_state->als[chan->scan_index].logical_minimum; 119 + address = HID_USAGE_SENSOR_LIGHT_CHROMATICITY_Y; 142 120 break; 143 121 default: 144 122 report_id = -1; ··· 275 223 als_state->scan.illum[CHANNEL_SCAN_INDEX_ILLUM] = sample_data; 276 224 ret = 0; 277 225 break; 226 + case HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE: 227 + als_state->scan.illum[CHANNEL_SCAN_INDEX_COLOR_TEMP] = sample_data; 228 + ret = 0; 229 + break; 230 + case HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X: 231 + als_state->scan.illum[CHANNEL_SCAN_INDEX_CHROMATICITY_X] = sample_data; 232 + ret = 0; 233 + break; 234 + case HID_USAGE_SENSOR_LIGHT_CHROMATICITY_Y: 235 + als_state->scan.illum[CHANNEL_SCAN_INDEX_CHROMATICITY_Y] = sample_data; 236 + ret = 0; 237 + break; 278 238 case HID_USAGE_SENSOR_TIME_TIMESTAMP: 279 239 als_state->timestamp = hid_sensor_convert_timestamp(&als_state->common_attributes, 280 240 *(s64 *)raw_data); ··· 306 242 struct als_state *st) 307 243 { 308 244 int ret; 245 + int i; 246 + 247 + for (i = 0; i <= CHANNEL_SCAN_INDEX_ILLUM; ++i) { 248 + ret = sensor_hub_input_get_attribute_info(hsdev, 249 + HID_INPUT_REPORT, 250 + usage_id, 251 + HID_USAGE_SENSOR_LIGHT_ILLUM, 252 + &st->als[i]); 253 + if (ret < 0) 254 + return ret; 255 + als_adjust_channel_bit_mask(channels, i, st->als[i].size); 256 + 257 + dev_dbg(&pdev->dev, "als %x:%x\n", st->als[i].index, 258 + st->als[i].report_id); 259 + } 309 260 310 261 ret = sensor_hub_input_get_attribute_info(hsdev, HID_INPUT_REPORT, 311 - usage_id, 312 - HID_USAGE_SENSOR_LIGHT_ILLUM, 313 - &st->als_illum); 262 + usage_id, 263 + HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE, 264 + &st->als[CHANNEL_SCAN_INDEX_COLOR_TEMP]); 314 265 if (ret < 0) 315 266 return ret; 316 - als_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_INTENSITY, 317 - st->als_illum.size); 318 - als_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_ILLUM, 319 - st->als_illum.size); 267 + als_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_COLOR_TEMP, 268 + st->als[CHANNEL_SCAN_INDEX_COLOR_TEMP].size); 320 269 321 - dev_dbg(&pdev->dev, "als %x:%x\n", st->als_illum.index, 322 - st->als_illum.report_id); 270 + dev_dbg(&pdev->dev, "als %x:%x\n", 271 + st->als[CHANNEL_SCAN_INDEX_COLOR_TEMP].index, 272 + st->als[CHANNEL_SCAN_INDEX_COLOR_TEMP].report_id); 323 273 324 - st->scale_precision = hid_sensor_format_scale(usage_id, &st->als_illum, 274 + for (i = 0; i < 2; i++) { 275 + int next_scan_index = CHANNEL_SCAN_INDEX_CHROMATICITY_X + i; 276 + 277 + ret = sensor_hub_input_get_attribute_info(hsdev, 278 + HID_INPUT_REPORT, usage_id, 279 + HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X + i, 280 + &st->als[next_scan_index]); 281 + if (ret < 0) 282 + return ret; 283 + 284 + als_adjust_channel_bit_mask(channels, 285 + CHANNEL_SCAN_INDEX_CHROMATICITY_X + i, 286 + st->als[next_scan_index].size); 287 + 288 + dev_dbg(&pdev->dev, "als %x:%x\n", 289 + st->als[next_scan_index].index, 290 + st->als[next_scan_index].report_id); 291 + } 292 + 293 + st->scale_precision = hid_sensor_format_scale(usage_id, 294 + &st->als[CHANNEL_SCAN_INDEX_INTENSITY], 325 295 &st->scale_pre_decml, &st->scale_post_decml); 326 296 327 297 return ret; ··· 445 347 } 446 348 447 349 /* Function to deinitialize the processing for usage id */ 448 - static int hid_als_remove(struct platform_device *pdev) 350 + static void hid_als_remove(struct platform_device *pdev) 449 351 { 450 352 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 451 353 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 454 356 sensor_hub_remove_callback(hsdev, hsdev->usage); 455 357 iio_device_unregister(indio_dev); 456 358 hid_sensor_remove_trigger(indio_dev, &als_state->common_attributes); 457 - 458 - return 0; 459 359 } 460 360 461 361 static const struct platform_device_id hid_als_ids[] = { ··· 476 380 .pm = &hid_sensor_pm_ops, 477 381 }, 478 382 .probe = hid_als_probe, 479 - .remove = hid_als_remove, 383 + .remove_new = hid_als_remove, 480 384 }; 481 385 module_platform_driver(hid_als_platform_driver); 482 386

+2 -4

drivers/iio/light/hid-sensor-prox.c

··· 313 313 } 314 314 315 315 /* Function to deinitialize the processing for usage id */ 316 - static int hid_prox_remove(struct platform_device *pdev) 316 + static void hid_prox_remove(struct platform_device *pdev) 317 317 { 318 318 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 319 319 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 322 322 sensor_hub_remove_callback(hsdev, hsdev->usage); 323 323 iio_device_unregister(indio_dev); 324 324 hid_sensor_remove_trigger(indio_dev, &prox_state->common_attributes); 325 - 326 - return 0; 327 325 } 328 326 329 327 static const struct platform_device_id hid_prox_ids[] = { ··· 344 346 .pm = &hid_sensor_pm_ops, 345 347 }, 346 348 .probe = hid_prox_probe, 347 - .remove = hid_prox_remove, 349 + .remove_new = hid_prox_remove, 348 350 }; 349 351 module_platform_driver(hid_prox_platform_driver); 350 352

+2 -4

drivers/iio/light/lm3533-als.c

··· 895 895 return ret; 896 896 } 897 897 898 - static int lm3533_als_remove(struct platform_device *pdev) 898 + static void lm3533_als_remove(struct platform_device *pdev) 899 899 { 900 900 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 901 901 struct lm3533_als *als = iio_priv(indio_dev); ··· 905 905 lm3533_als_disable(als); 906 906 if (als->irq) 907 907 free_irq(als->irq, indio_dev); 908 - 909 - return 0; 910 908 } 911 909 912 910 static struct platform_driver lm3533_als_driver = { ··· 912 914 .name = "lm3533-als", 913 915 }, 914 916 .probe = lm3533_als_probe, 915 - .remove = lm3533_als_remove, 917 + .remove_new = lm3533_als_remove, 916 918 }; 917 919 module_platform_driver(lm3533_als_driver); 918 920

+1 -1

drivers/iio/light/opt4001.c

··· 412 412 if (dev_id != OPT4001_DEVICE_ID_VAL) 413 413 dev_warn(&client->dev, "Device ID: %#04x unknown\n", dev_id); 414 414 415 - chip->chip_info = device_get_match_data(&client->dev); 415 + chip->chip_info = i2c_get_match_data(client); 416 416 417 417 indio_dev->channels = opt4001_channels; 418 418 indio_dev->num_channels = ARRAY_SIZE(opt4001_channels);

+40 -57

drivers/iio/magnetometer/ak8975.c

··· 204 204 205 205 /* Compatible Asahi Kasei Compass parts */ 206 206 enum asahi_compass_chipset { 207 - AKXXXX = 0, 208 207 AK8975, 209 208 AK8963, 210 209 AK09911, ··· 247 248 }; 248 249 249 250 static const struct ak_def ak_def_array[] = { 250 - { 251 + [AK8975] = { 251 252 .type = AK8975, 252 253 .raw_to_gauss = ak8975_raw_to_gauss, 253 254 .range = 4096, ··· 272 273 AK8975_REG_HYL, 273 274 AK8975_REG_HZL}, 274 275 }, 275 - { 276 + [AK8963] = { 276 277 .type = AK8963, 277 278 .raw_to_gauss = ak8963_09911_raw_to_gauss, 278 279 .range = 8190, ··· 297 298 AK8975_REG_HYL, 298 299 AK8975_REG_HZL}, 299 300 }, 300 - { 301 + [AK09911] = { 301 302 .type = AK09911, 302 303 .raw_to_gauss = ak8963_09911_raw_to_gauss, 303 304 .range = 8192, ··· 322 323 AK09912_REG_HYL, 323 324 AK09912_REG_HZL}, 324 325 }, 325 - { 326 + [AK09912] = { 326 327 .type = AK09912, 327 328 .raw_to_gauss = ak09912_raw_to_gauss, 328 329 .range = 32752, ··· 347 348 AK09912_REG_HYL, 348 349 AK09912_REG_HZL}, 349 350 }, 350 - { 351 + [AK09916] = { 351 352 .type = AK09916, 352 353 .raw_to_gauss = ak09912_raw_to_gauss, 353 354 .range = 32752, ··· 811 812 .read_raw = &ak8975_read_raw, 812 813 }; 813 814 814 - static const struct acpi_device_id ak_acpi_match[] = { 815 - {"AK8975", AK8975}, 816 - {"AK8963", AK8963}, 817 - {"INVN6500", AK8963}, 818 - {"AK009911", AK09911}, 819 - {"AK09911", AK09911}, 820 - {"AKM9911", AK09911}, 821 - {"AK09912", AK09912}, 822 - { } 823 - }; 824 - MODULE_DEVICE_TABLE(acpi, ak_acpi_match); 825 - 826 815 static void ak8975_fill_buffer(struct iio_dev *indio_dev) 827 816 { 828 817 struct ak8975_data *data = iio_priv(indio_dev); ··· 870 883 struct iio_dev *indio_dev; 871 884 struct gpio_desc *eoc_gpiod; 872 885 struct gpio_desc *reset_gpiod; 873 - const void *match; 874 - unsigned int i; 875 886 int err; 876 - enum asahi_compass_chipset chipset; 877 887 const char *name = NULL; 878 888 879 889 /* ··· 912 928 return err; 913 929 914 930 /* id will be NULL when enumerated via ACPI */ 915 - match = device_get_match_data(&client->dev); 916 - if (match) { 917 - chipset = (uintptr_t)match; 918 - name = dev_name(&client->dev); 919 - } else if (id) { 920 - chipset = (enum asahi_compass_chipset)(id->driver_data); 921 - name = id->name; 922 - } else 923 - return -ENOSYS; 924 - 925 - for (i = 0; i < ARRAY_SIZE(ak_def_array); i++) 926 - if (ak_def_array[i].type == chipset) 927 - break; 928 - 929 - if (i == ARRAY_SIZE(ak_def_array)) { 930 - dev_err(&client->dev, "AKM device type unsupported: %d\n", 931 - chipset); 931 + data->def = i2c_get_match_data(client); 932 + if (!data->def) 932 933 return -ENODEV; 933 - } 934 934 935 - data->def = &ak_def_array[i]; 935 + /* If enumerated via firmware node, fix the ABI */ 936 + if (dev_fwnode(&client->dev)) 937 + name = dev_name(&client->dev); 938 + else 939 + name = id->name; 936 940 937 941 /* Fetch the regulators */ 938 942 data->vdd = devm_regulator_get(&client->dev, "vdd"); ··· 1048 1076 static DEFINE_RUNTIME_DEV_PM_OPS(ak8975_dev_pm_ops, ak8975_runtime_suspend, 1049 1077 ak8975_runtime_resume, NULL); 1050 1078 1079 + static const struct acpi_device_id ak_acpi_match[] = { 1080 + {"AK8963", (kernel_ulong_t)&ak_def_array[AK8963] }, 1081 + {"AK8975", (kernel_ulong_t)&ak_def_array[AK8975] }, 1082 + {"AK009911", (kernel_ulong_t)&ak_def_array[AK09911] }, 1083 + {"AK09911", (kernel_ulong_t)&ak_def_array[AK09911] }, 1084 + {"AK09912", (kernel_ulong_t)&ak_def_array[AK09912] }, 1085 + {"AKM9911", (kernel_ulong_t)&ak_def_array[AK09911] }, 1086 + {"INVN6500", (kernel_ulong_t)&ak_def_array[AK8963] }, 1087 + { } 1088 + }; 1089 + MODULE_DEVICE_TABLE(acpi, ak_acpi_match); 1090 + 1051 1091 static const struct i2c_device_id ak8975_id[] = { 1052 - {"ak8975", AK8975}, 1053 - {"ak8963", AK8963}, 1054 - {"AK8963", AK8963}, 1055 - {"ak09911", AK09911}, 1056 - {"ak09912", AK09912}, 1057 - {"ak09916", AK09916}, 1092 + {"AK8963", (kernel_ulong_t)&ak_def_array[AK8963] }, 1093 + {"ak8963", (kernel_ulong_t)&ak_def_array[AK8963] }, 1094 + {"ak8975", (kernel_ulong_t)&ak_def_array[AK8975] }, 1095 + {"ak09911", (kernel_ulong_t)&ak_def_array[AK09911] }, 1096 + {"ak09912", (kernel_ulong_t)&ak_def_array[AK09912] }, 1097 + {"ak09916", (kernel_ulong_t)&ak_def_array[AK09916] }, 1058 1098 {} 1059 1099 }; 1060 - 1061 1100 MODULE_DEVICE_TABLE(i2c, ak8975_id); 1062 1101 1063 1102 static const struct of_device_id ak8975_of_match[] = { 1064 - { .compatible = "asahi-kasei,ak8975", }, 1065 - { .compatible = "ak8975", }, 1066 - { .compatible = "asahi-kasei,ak8963", }, 1067 - { .compatible = "ak8963", }, 1068 - { .compatible = "asahi-kasei,ak09911", }, 1069 - { .compatible = "ak09911", }, 1070 - { .compatible = "asahi-kasei,ak09912", }, 1071 - { .compatible = "ak09912", }, 1072 - { .compatible = "asahi-kasei,ak09916", }, 1073 - { .compatible = "ak09916", }, 1103 + { .compatible = "asahi-kasei,ak8975", .data = &ak_def_array[AK8975] }, 1104 + { .compatible = "ak8975", .data = &ak_def_array[AK8975] }, 1105 + { .compatible = "asahi-kasei,ak8963", .data = &ak_def_array[AK8963] }, 1106 + { .compatible = "ak8963", .data = &ak_def_array[AK8963] }, 1107 + { .compatible = "asahi-kasei,ak09911", .data = &ak_def_array[AK09911] }, 1108 + { .compatible = "ak09911", .data = &ak_def_array[AK09911] }, 1109 + { .compatible = "asahi-kasei,ak09912", .data = &ak_def_array[AK09912] }, 1110 + { .compatible = "ak09912", .data = &ak_def_array[AK09912] }, 1111 + { .compatible = "asahi-kasei,ak09916", .data = &ak_def_array[AK09916] }, 1112 + { .compatible = "ak09916", .data = &ak_def_array[AK09916] }, 1074 1113 {} 1075 1114 }; 1076 1115 MODULE_DEVICE_TABLE(of, ak8975_of_match);

+2 -4

drivers/iio/magnetometer/hid-sensor-magn-3d.c

··· 547 547 } 548 548 549 549 /* Function to deinitialize the processing for usage id */ 550 - static int hid_magn_3d_remove(struct platform_device *pdev) 550 + static void hid_magn_3d_remove(struct platform_device *pdev) 551 551 { 552 552 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 553 553 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 556 556 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_COMPASS_3D); 557 557 iio_device_unregister(indio_dev); 558 558 hid_sensor_remove_trigger(indio_dev, &magn_state->magn_flux_attributes); 559 - 560 - return 0; 561 559 } 562 560 563 561 static const struct platform_device_id hid_magn_3d_ids[] = { ··· 574 576 .pm = &hid_sensor_pm_ops, 575 577 }, 576 578 .probe = hid_magn_3d_probe, 577 - .remove = hid_magn_3d_remove, 579 + .remove_new = hid_magn_3d_remove, 578 580 }; 579 581 module_platform_driver(hid_magn_3d_platform_driver); 580 582

+1 -3

drivers/iio/magnetometer/yamaha-yas530.c

··· 1434 1434 goto assert_reset; 1435 1435 } 1436 1436 1437 - ci = device_get_match_data(dev); 1438 - if (!ci) 1439 - ci = (const struct yas5xx_chip_info *)id->driver_data; 1437 + ci = i2c_get_match_data(i2c); 1440 1438 yas5xx->chip_info = ci; 1441 1439 1442 1440 ret = regmap_read(yas5xx->map, YAS5XX_DEVICE_ID, &id_check);

+2 -4

drivers/iio/orientation/hid-sensor-incl-3d.c

··· 383 383 } 384 384 385 385 /* Function to deinitialize the processing for usage id */ 386 - static int hid_incl_3d_remove(struct platform_device *pdev) 386 + static void hid_incl_3d_remove(struct platform_device *pdev) 387 387 { 388 388 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 389 389 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 392 392 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_INCLINOMETER_3D); 393 393 iio_device_unregister(indio_dev); 394 394 hid_sensor_remove_trigger(indio_dev, &incl_state->common_attributes); 395 - 396 - return 0; 397 395 } 398 396 399 397 static const struct platform_device_id hid_incl_3d_ids[] = { ··· 410 412 .pm = &hid_sensor_pm_ops, 411 413 }, 412 414 .probe = hid_incl_3d_probe, 413 - .remove = hid_incl_3d_remove, 415 + .remove_new = hid_incl_3d_remove, 414 416 }; 415 417 module_platform_driver(hid_incl_3d_platform_driver); 416 418

+2 -4

drivers/iio/orientation/hid-sensor-rotation.c

··· 327 327 } 328 328 329 329 /* Function to deinitialize the processing for usage id */ 330 - static int hid_dev_rot_remove(struct platform_device *pdev) 330 + static void hid_dev_rot_remove(struct platform_device *pdev) 331 331 { 332 332 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 333 333 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 336 336 sensor_hub_remove_callback(hsdev, hsdev->usage); 337 337 iio_device_unregister(indio_dev); 338 338 hid_sensor_remove_trigger(indio_dev, &rot_state->common_attributes); 339 - 340 - return 0; 341 339 } 342 340 343 341 static const struct platform_device_id hid_dev_rot_ids[] = { ··· 362 364 .pm = &hid_sensor_pm_ops, 363 365 }, 364 366 .probe = hid_dev_rot_probe, 365 - .remove = hid_dev_rot_remove, 367 + .remove_new = hid_dev_rot_remove, 366 368 }; 367 369 module_platform_driver(hid_dev_rot_platform_driver); 368 370

+2 -4

drivers/iio/position/hid-sensor-custom-intel-hinge.c

··· 342 342 } 343 343 344 344 /* Function to deinitialize the processing for usage id */ 345 - static int hid_hinge_remove(struct platform_device *pdev) 345 + static void hid_hinge_remove(struct platform_device *pdev) 346 346 { 347 347 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 348 348 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 351 351 iio_device_unregister(indio_dev); 352 352 sensor_hub_remove_callback(hsdev, hsdev->usage); 353 353 hid_sensor_remove_trigger(indio_dev, &st->common_attributes); 354 - 355 - return 0; 356 354 } 357 355 358 356 static const struct platform_device_id hid_hinge_ids[] = { ··· 369 371 .pm = &hid_sensor_pm_ops, 370 372 }, 371 373 .probe = hid_hinge_probe, 372 - .remove = hid_hinge_remove, 374 + .remove_new = hid_hinge_remove, 373 375 }; 374 376 module_platform_driver(hid_hinge_platform_driver); 375 377

+13 -8

drivers/iio/potentiometer/ad5110.c

··· 278 278 }; 279 279 MODULE_DEVICE_TABLE(of, ad5110_of_match); 280 280 281 + #define AD5110_ID_TABLE(_name, cfg) { \ 282 + .name = _name, \ 283 + .driver_data = (kernel_ulong_t)&ad5110_cfg[cfg], \ 284 + } 285 + 281 286 static const struct i2c_device_id ad5110_id[] = { 282 - { "ad5110-10", AD5110_10 }, 283 - { "ad5110-80", AD5110_80 }, 284 - { "ad5112-05", AD5112_05 }, 285 - { "ad5112-10", AD5112_10 }, 286 - { "ad5112-80", AD5112_80 }, 287 - { "ad5114-10", AD5114_10 }, 288 - { "ad5114-80", AD5114_80 }, 287 + AD5110_ID_TABLE("ad5110-10", AD5110_10), 288 + AD5110_ID_TABLE("ad5110-80", AD5110_80), 289 + AD5110_ID_TABLE("ad5112-05", AD5112_05), 290 + AD5110_ID_TABLE("ad5112-10", AD5112_10), 291 + AD5110_ID_TABLE("ad5112-80", AD5112_80), 292 + AD5110_ID_TABLE("ad5114-10", AD5114_10), 293 + AD5110_ID_TABLE("ad5114-80", AD5114_80), 289 294 { } 290 295 }; 291 296 MODULE_DEVICE_TABLE(i2c, ad5110_id); ··· 310 305 data->client = client; 311 306 mutex_init(&data->lock); 312 307 data->enable = 1; 313 - data->cfg = device_get_match_data(dev); 308 + data->cfg = i2c_get_match_data(client); 314 309 315 310 /* refresh RDAC register with EEPROM */ 316 311 ret = ad5110_write(data, AD5110_RESET, 0);

+5 -8

drivers/iio/potentiometer/ds1803.c

··· 204 204 205 205 static int ds1803_probe(struct i2c_client *client) 206 206 { 207 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 208 207 struct device *dev = &client->dev; 209 208 struct ds1803_data *data; 210 209 struct iio_dev *indio_dev; ··· 216 217 217 218 data = iio_priv(indio_dev); 218 219 data->client = client; 219 - data->cfg = device_get_match_data(dev); 220 - if (!data->cfg) 221 - data->cfg = &ds1803_cfg[id->driver_data]; 220 + data->cfg = i2c_get_match_data(client); 222 221 223 222 indio_dev->info = &ds1803_info; 224 223 indio_dev->channels = data->cfg->channels; ··· 236 239 MODULE_DEVICE_TABLE(of, ds1803_dt_ids); 237 240 238 241 static const struct i2c_device_id ds1803_id[] = { 239 - { "ds1803-010", DS1803_010 }, 240 - { "ds1803-050", DS1803_050 }, 241 - { "ds1803-100", DS1803_100 }, 242 - { "ds3502", DS3502 }, 242 + { "ds1803-010", (kernel_ulong_t)&ds1803_cfg[DS1803_010] }, 243 + { "ds1803-050", (kernel_ulong_t)&ds1803_cfg[DS1803_050] }, 244 + { "ds1803-100", (kernel_ulong_t)&ds1803_cfg[DS1803_100] }, 245 + { "ds3502", (kernel_ulong_t)&ds1803_cfg[DS3502] }, 243 246 {} 244 247 }; 245 248 MODULE_DEVICE_TABLE(i2c, ds1803_id);

+9

drivers/iio/pressure/Kconfig

··· 16 16 To compile this driver as a module, choose M here: the module 17 17 will be called abp060mg. 18 18 19 + config ROHM_BM1390 20 + tristate "ROHM BM1390GLV-Z pressure sensor driver" 21 + depends on I2C 22 + help 23 + Support for the ROHM BM1390 pressure sensor. The BM1390GLV-Z 24 + can measure pressures ranging from 300 hPa to 1300 hPa with 25 + configurable measurement averaging and internal FIFO. The 26 + sensor does also provide temperature measurements. 27 + 19 28 config BMP280 20 29 tristate "Bosch Sensortec BMP180/BMP280/BMP380/BMP580 pressure sensor driver" 21 30 depends on (I2C || SPI_MASTER)

+1

drivers/iio/pressure/Makefile

··· 5 5 6 6 # When adding new entries keep the list in alphabetical order 7 7 obj-$(CONFIG_ABP060MG) += abp060mg.o 8 + obj-$(CONFIG_ROHM_BM1390) += rohm-bm1390.o 8 9 obj-$(CONFIG_BMP280) += bmp280.o 9 10 bmp280-objs := bmp280-core.o bmp280-regmap.o 10 11 obj-$(CONFIG_BMP280_I2C) += bmp280-i2c.o

+2 -4

drivers/iio/pressure/hid-sensor-press.c

··· 323 323 } 324 324 325 325 /* Function to deinitialize the processing for usage id */ 326 - static int hid_press_remove(struct platform_device *pdev) 326 + static void hid_press_remove(struct platform_device *pdev) 327 327 { 328 328 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 329 329 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 332 332 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_PRESSURE); 333 333 iio_device_unregister(indio_dev); 334 334 hid_sensor_remove_trigger(indio_dev, &press_state->common_attributes); 335 - 336 - return 0; 337 335 } 338 336 339 337 static const struct platform_device_id hid_press_ids[] = { ··· 350 352 .pm = &hid_sensor_pm_ops, 351 353 }, 352 354 .probe = hid_press_probe, 353 - .remove = hid_press_remove, 355 + .remove_new = hid_press_remove, 354 356 }; 355 357 module_platform_driver(hid_press_platform_driver); 356 358

+1 -5

drivers/iio/pressure/ms5637.c

··· 144 144 145 145 static int ms5637_probe(struct i2c_client *client) 146 146 { 147 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 148 147 const struct ms_tp_data *data; 149 148 struct ms_tp_dev *dev_data; 150 149 struct iio_dev *indio_dev; ··· 158 159 return -EOPNOTSUPP; 159 160 } 160 161 161 - if (id) 162 - data = (const struct ms_tp_data *)id->driver_data; 163 - else 164 - data = device_get_match_data(&client->dev); 162 + data = i2c_get_match_data(client); 165 163 if (!data) 166 164 return -EINVAL; 167 165

+934

drivers/iio/pressure/rohm-bm1390.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * BM1390 ROHM pressure sensor 4 + * 5 + * Copyright (c) 2023, ROHM Semiconductor. 6 + * https://fscdn.rohm.com/en/products/databook/datasheet/ic/sensor/pressure/bm1390glv-z-e.pdf 7 + */ 8 + 9 + #include <linux/bitfield.h> 10 + #include <linux/bits.h> 11 + #include <linux/device.h> 12 + #include <linux/i2c.h> 13 + #include <linux/module.h> 14 + #include <linux/regmap.h> 15 + #include <linux/regulator/consumer.h> 16 + 17 + #include <linux/iio/iio.h> 18 + #include <linux/iio/trigger.h> 19 + #include <linux/iio/trigger_consumer.h> 20 + #include <linux/iio/triggered_buffer.h> 21 + 22 + #define BM1390_REG_MANUFACT_ID 0x0f 23 + #define BM1390_REG_PART_ID 0x10 24 + #define BM1390_REG_POWER 0x12 25 + #define BM1390_MASK_POWER BIT(0) 26 + #define BM1390_POWER_ON BM1390_MASK_POWER 27 + #define BM1390_POWER_OFF 0x00 28 + #define BM1390_REG_RESET 0x13 29 + #define BM1390_MASK_RESET BIT(0) 30 + #define BM1390_RESET_RELEASE BM1390_MASK_RESET 31 + #define BM1390_RESET 0x00 32 + #define BM1390_REG_MODE_CTRL 0x14 33 + #define BM1390_MASK_MEAS_MODE GENMASK(1, 0) 34 + #define BM1390_MASK_DRDY_EN BIT(4) 35 + #define BM1390_MASK_WMI_EN BIT(2) 36 + #define BM1390_MASK_AVE_NUM GENMASK(7, 5) 37 + 38 + /* 39 + * Data-sheet states that when the IIR is used, the AVE_NUM must be set to 40 + * value 110b 41 + */ 42 + #define BM1390_IIR_AVE_NUM 0x06 43 + #define BM1390_REG_FIFO_CTRL 0x15 44 + #define BM1390_MASK_IIR_MODE GENMASK(1, 0) 45 + #define BM1390_IIR_MODE_OFF 0x0 46 + #define BM1390_IIR_MODE_WEAK 0x1 47 + #define BM1390_IIR_MODE_MID 0x2 48 + #define BM1390_IIR_MODE_STRONG 0x3 49 + 50 + #define BM1390_MASK_FIFO_LEN BIT(6) 51 + #define BM1390_MASK_FIFO_EN BIT(7) 52 + #define BM1390_WMI_MIN 2 53 + #define BM1390_WMI_MAX 3 54 + 55 + #define BM1390_REG_FIFO_LVL 0x18 56 + #define BM1390_MASK_FIFO_LVL GENMASK(2, 0) 57 + #define BM1390_REG_STATUS 0x19 58 + #define BM1390_REG_PRESSURE_BASE 0x1a 59 + #define BM1390_REG_TEMP_HI 0x1d 60 + #define BM1390_REG_TEMP_LO 0x1e 61 + #define BM1390_MAX_REGISTER BM1390_REG_TEMP_LO 62 + 63 + #define BM1390_ID 0x34 64 + 65 + /* Regmap configs */ 66 + static const struct regmap_range bm1390_volatile_ranges[] = { 67 + { 68 + .range_min = BM1390_REG_STATUS, 69 + .range_max = BM1390_REG_STATUS, 70 + }, 71 + { 72 + .range_min = BM1390_REG_FIFO_LVL, 73 + .range_max = BM1390_REG_TEMP_LO, 74 + }, 75 + }; 76 + 77 + static const struct regmap_access_table bm1390_volatile_regs = { 78 + .yes_ranges = &bm1390_volatile_ranges[0], 79 + .n_yes_ranges = ARRAY_SIZE(bm1390_volatile_ranges), 80 + }; 81 + 82 + static const struct regmap_range bm1390_precious_ranges[] = { 83 + { 84 + .range_min = BM1390_REG_STATUS, 85 + .range_max = BM1390_REG_STATUS, 86 + }, 87 + }; 88 + 89 + static const struct regmap_access_table bm1390_precious_regs = { 90 + .yes_ranges = &bm1390_precious_ranges[0], 91 + .n_yes_ranges = ARRAY_SIZE(bm1390_precious_ranges), 92 + }; 93 + 94 + static const struct regmap_range bm1390_read_only_ranges[] = { 95 + { 96 + .range_min = BM1390_REG_MANUFACT_ID, 97 + .range_max = BM1390_REG_PART_ID, 98 + }, { 99 + .range_min = BM1390_REG_FIFO_LVL, 100 + .range_max = BM1390_REG_TEMP_LO, 101 + }, 102 + }; 103 + 104 + static const struct regmap_access_table bm1390_ro_regs = { 105 + .no_ranges = &bm1390_read_only_ranges[0], 106 + .n_no_ranges = ARRAY_SIZE(bm1390_read_only_ranges), 107 + }; 108 + 109 + static const struct regmap_range bm1390_noinc_read_ranges[] = { 110 + { 111 + .range_min = BM1390_REG_PRESSURE_BASE, 112 + .range_max = BM1390_REG_TEMP_LO, 113 + }, 114 + }; 115 + 116 + static const struct regmap_access_table bm1390_nir_regs = { 117 + .yes_ranges = &bm1390_noinc_read_ranges[0], 118 + .n_yes_ranges = ARRAY_SIZE(bm1390_noinc_read_ranges), 119 + }; 120 + 121 + static const struct regmap_config bm1390_regmap = { 122 + .reg_bits = 8, 123 + .val_bits = 8, 124 + .volatile_table = &bm1390_volatile_regs, 125 + .wr_table = &bm1390_ro_regs, 126 + .rd_noinc_table = &bm1390_nir_regs, 127 + .precious_table = &bm1390_precious_regs, 128 + .max_register = BM1390_MAX_REGISTER, 129 + .cache_type = REGCACHE_RBTREE, 130 + .disable_locking = true, 131 + }; 132 + 133 + enum { 134 + BM1390_STATE_SAMPLE, 135 + BM1390_STATE_FIFO, 136 + }; 137 + 138 + struct bm1390_data_buf { 139 + u32 pressure; 140 + __be16 temp; 141 + s64 ts __aligned(8); 142 + }; 143 + 144 + /* BM1390 has FIFO for 4 pressure samples */ 145 + #define BM1390_FIFO_LENGTH 4 146 + 147 + struct bm1390_data { 148 + s64 timestamp, old_timestamp; 149 + struct iio_trigger *trig; 150 + struct regmap *regmap; 151 + struct device *dev; 152 + struct bm1390_data_buf buf; 153 + int irq; 154 + unsigned int state; 155 + bool trigger_enabled; 156 + u8 watermark; 157 + 158 + /* Prevent accessing sensor during FIFO read sequence */ 159 + struct mutex mutex; 160 + }; 161 + 162 + enum { 163 + BM1390_CHAN_PRESSURE, 164 + BM1390_CHAN_TEMP, 165 + }; 166 + 167 + static const struct iio_chan_spec bm1390_channels[] = { 168 + { 169 + .type = IIO_PRESSURE, 170 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 171 + /* 172 + * When IIR is used, we must fix amount of averaged samples. 173 + * Thus we don't allow setting oversampling ratio. 174 + */ 175 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 176 + .scan_index = BM1390_CHAN_PRESSURE, 177 + .scan_type = { 178 + .sign = 'u', 179 + .realbits = 22, 180 + .storagebits = 32, 181 + .endianness = IIO_LE, 182 + }, 183 + }, 184 + { 185 + .type = IIO_TEMP, 186 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 187 + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 188 + .scan_index = BM1390_CHAN_TEMP, 189 + .scan_type = { 190 + .sign = 's', 191 + .realbits = 16, 192 + .storagebits = 16, 193 + .endianness = IIO_BE, 194 + }, 195 + }, 196 + IIO_CHAN_SOFT_TIMESTAMP(2), 197 + }; 198 + 199 + /* 200 + * We can't skip reading the pressure because the watermark IRQ is acked 201 + * only when the pressure data is read from the FIFO. 202 + */ 203 + static const unsigned long bm1390_scan_masks[] = { 204 + BIT(BM1390_CHAN_PRESSURE), 205 + BIT(BM1390_CHAN_PRESSURE) | BIT(BM1390_CHAN_TEMP), 206 + 0 207 + }; 208 + 209 + static int bm1390_read_temp(struct bm1390_data *data, int *temp) 210 + { 211 + __be16 temp_raw; 212 + int ret; 213 + 214 + ret = regmap_bulk_read(data->regmap, BM1390_REG_TEMP_HI, &temp_raw, 215 + sizeof(temp_raw)); 216 + if (ret) 217 + return ret; 218 + 219 + *temp = be16_to_cpu(temp_raw); 220 + 221 + return 0; 222 + } 223 + 224 + static int bm1390_pressure_read(struct bm1390_data *data, u32 *pressure) 225 + { 226 + /* Pressure data is in 3 8-bit registers */ 227 + u8 raw[3]; 228 + int ret; 229 + 230 + ret = regmap_bulk_read(data->regmap, BM1390_REG_PRESSURE_BASE, 231 + raw, sizeof(raw)); 232 + if (ret < 0) 233 + return ret; 234 + 235 + *pressure = (u32)(raw[2] >> 2 | raw[1] << 6 | raw[0] << 14); 236 + 237 + return 0; 238 + } 239 + 240 + /* The enum values map directly to register bits */ 241 + enum bm1390_meas_mode { 242 + BM1390_MEAS_MODE_STOP = 0x0, 243 + BM1390_MEAS_MODE_1SHOT = 0x1, 244 + BM1390_MEAS_MODE_CONTINUOUS = 0x2, 245 + }; 246 + 247 + static int bm1390_meas_set(struct bm1390_data *data, enum bm1390_meas_mode mode) 248 + { 249 + return regmap_update_bits(data->regmap, BM1390_REG_MODE_CTRL, 250 + BM1390_MASK_MEAS_MODE, mode); 251 + } 252 + 253 + /* 254 + * If the trigger is not used we just wait until the measurement has 255 + * completed. The data-sheet says maximum measurement cycle (regardless 256 + * the AVE_NUM) is 200 mS so let's just sleep at least that long. If speed 257 + * is needed the trigger should be used. 258 + */ 259 + #define BM1390_MAX_MEAS_TIME_MS 205 260 + 261 + static int bm1390_read_data(struct bm1390_data *data, 262 + struct iio_chan_spec const *chan, int *val, int *val2) 263 + { 264 + int ret, warn; 265 + 266 + mutex_lock(&data->mutex); 267 + /* 268 + * We use 'continuous mode' even for raw read because according to the 269 + * data-sheet an one-shot mode can't be used with IIR filter. 270 + */ 271 + ret = bm1390_meas_set(data, BM1390_MEAS_MODE_CONTINUOUS); 272 + if (ret) 273 + goto unlock_out; 274 + 275 + switch (chan->type) { 276 + case IIO_PRESSURE: 277 + msleep(BM1390_MAX_MEAS_TIME_MS); 278 + ret = bm1390_pressure_read(data, val); 279 + break; 280 + case IIO_TEMP: 281 + msleep(BM1390_MAX_MEAS_TIME_MS); 282 + ret = bm1390_read_temp(data, val); 283 + break; 284 + default: 285 + ret = -EINVAL; 286 + } 287 + warn = bm1390_meas_set(data, BM1390_MEAS_MODE_STOP); 288 + if (warn) 289 + dev_warn(data->dev, "Failed to stop measurement (%d)\n", warn); 290 + unlock_out: 291 + mutex_unlock(&data->mutex); 292 + 293 + return ret; 294 + } 295 + 296 + static int bm1390_read_raw(struct iio_dev *idev, 297 + struct iio_chan_spec const *chan, 298 + int *val, int *val2, long mask) 299 + { 300 + struct bm1390_data *data = iio_priv(idev); 301 + int ret; 302 + 303 + switch (mask) { 304 + case IIO_CHAN_INFO_SCALE: 305 + if (chan->type == IIO_TEMP) { 306 + *val = 31; 307 + *val2 = 250000; 308 + 309 + return IIO_VAL_INT_PLUS_MICRO; 310 + } else if (chan->type == IIO_PRESSURE) { 311 + /* 312 + * pressure in hPa is register value divided by 2048. 313 + * This means kPa is 1/20480 times the register value, 314 + */ 315 + *val = 1; 316 + *val2 = 2048; 317 + 318 + return IIO_VAL_FRACTIONAL; 319 + } 320 + 321 + return -EINVAL; 322 + case IIO_CHAN_INFO_RAW: 323 + ret = iio_device_claim_direct_mode(idev); 324 + if (ret) 325 + return ret; 326 + 327 + ret = bm1390_read_data(data, chan, val, val2); 328 + iio_device_release_direct_mode(idev); 329 + if (ret) 330 + return ret; 331 + 332 + return IIO_VAL_INT; 333 + default: 334 + return -EINVAL; 335 + } 336 + } 337 + 338 + static int __bm1390_fifo_flush(struct iio_dev *idev, unsigned int samples, 339 + s64 timestamp) 340 + { 341 + /* BM1390_FIFO_LENGTH is small so we shouldn't run out of stack */ 342 + struct bm1390_data_buf buffer[BM1390_FIFO_LENGTH]; 343 + struct bm1390_data *data = iio_priv(idev); 344 + int smp_lvl, ret, i, warn, dummy; 345 + u64 sample_period; 346 + __be16 temp = 0; 347 + 348 + ret = regmap_read(data->regmap, BM1390_REG_FIFO_LVL, &smp_lvl); 349 + if (ret) 350 + return ret; 351 + 352 + smp_lvl = FIELD_GET(BM1390_MASK_FIFO_LVL, smp_lvl); 353 + if (!smp_lvl) 354 + return 0; 355 + 356 + if (smp_lvl > BM1390_FIFO_LENGTH) { 357 + /* 358 + * The fifo holds maximum of 4 samples so valid values 359 + * should be 0, 1, 2, 3, 4 - rest are probably bit errors 360 + * in I2C line. Don't overflow if this happens. 361 + */ 362 + dev_err(data->dev, "bad FIFO level %d\n", smp_lvl); 363 + smp_lvl = BM1390_FIFO_LENGTH; 364 + } 365 + 366 + sample_period = timestamp - data->old_timestamp; 367 + do_div(sample_period, smp_lvl); 368 + 369 + if (samples && smp_lvl > samples) 370 + smp_lvl = samples; 371 + 372 + 373 + /* 374 + * After some testing it appears that the temperature is not readable 375 + * until the FIFO access has been done after the WMI. Thus, we need 376 + * to read the all pressure values to memory and read the temperature 377 + * only after that. 378 + */ 379 + for (i = 0; i < smp_lvl; i++) { 380 + /* 381 + * When we start reading data from the FIFO the sensor goes to 382 + * special FIFO reading mode. If any other register is accessed 383 + * during the FIFO read, samples can be dropped. Prevent access 384 + * until FIFO_LVL is read. We have mutex locked and we do also 385 + * go performing reading of FIFO_LVL even if this read fails. 386 + */ 387 + if (test_bit(BM1390_CHAN_PRESSURE, idev->active_scan_mask)) { 388 + ret = bm1390_pressure_read(data, &buffer[i].pressure); 389 + if (ret) 390 + break; 391 + } 392 + 393 + /* 394 + * Old timestamp is either the previous sample IRQ time, 395 + * previous flush-time or, if this was first sample, the enable 396 + * time. When we add a sample period to that we should get the 397 + * best approximation of the time-stamp we are handling. 398 + * 399 + * Idea is to always keep the "old_timestamp" matching the 400 + * timestamp which we are currently handling. 401 + */ 402 + data->old_timestamp += sample_period; 403 + buffer[i].ts = data->old_timestamp; 404 + } 405 + /* Reading the FIFO_LVL closes the FIFO access sequence */ 406 + warn = regmap_read(data->regmap, BM1390_REG_FIFO_LVL, &dummy); 407 + if (warn) 408 + dev_warn(data->dev, "Closing FIFO sequence failed\n"); 409 + 410 + if (ret) 411 + return ret; 412 + 413 + if (test_bit(BM1390_CHAN_TEMP, idev->active_scan_mask)) { 414 + ret = regmap_bulk_read(data->regmap, BM1390_REG_TEMP_HI, &temp, 415 + sizeof(temp)); 416 + if (ret) 417 + return ret; 418 + } 419 + 420 + if (ret) 421 + return ret; 422 + 423 + for (i = 0; i < smp_lvl; i++) { 424 + buffer[i].temp = temp; 425 + iio_push_to_buffers(idev, &buffer[i]); 426 + } 427 + 428 + return smp_lvl; 429 + } 430 + 431 + static int bm1390_fifo_flush(struct iio_dev *idev, unsigned int samples) 432 + { 433 + struct bm1390_data *data = iio_priv(idev); 434 + s64 timestamp; 435 + int ret; 436 + 437 + /* 438 + * If fifo_flush is being called from IRQ handler we know the stored 439 + * timestamp is fairly accurate for the last stored sample. If we are 440 + * called as a result of a read operation from userspace and hence 441 + * before the watermark interrupt was triggered, take a timestamp 442 + * now. We can fall anywhere in between two samples so the error in this 443 + * case is at most one sample period. 444 + * We need to have the IRQ disabled or we risk of messing-up 445 + * the timestamps. If we are ran from IRQ, then the 446 + * IRQF_ONESHOT has us covered - but if we are ran by the 447 + * user-space read we need to disable the IRQ to be on a safe 448 + * side. We do this usng synchronous disable so that if the 449 + * IRQ thread is being ran on other CPU we wait for it to be 450 + * finished. 451 + */ 452 + 453 + timestamp = iio_get_time_ns(idev); 454 + mutex_lock(&data->mutex); 455 + ret = __bm1390_fifo_flush(idev, samples, timestamp); 456 + mutex_unlock(&data->mutex); 457 + 458 + return ret; 459 + } 460 + 461 + static int bm1390_set_watermark(struct iio_dev *idev, unsigned int val) 462 + { 463 + struct bm1390_data *data = iio_priv(idev); 464 + 465 + if (val < BM1390_WMI_MIN || val > BM1390_WMI_MAX) 466 + return -EINVAL; 467 + 468 + mutex_lock(&data->mutex); 469 + data->watermark = val; 470 + mutex_unlock(&data->mutex); 471 + 472 + return 0; 473 + } 474 + 475 + static const struct iio_info bm1390_noirq_info = { 476 + .read_raw = &bm1390_read_raw, 477 + }; 478 + 479 + static const struct iio_info bm1390_info = { 480 + .read_raw = &bm1390_read_raw, 481 + .hwfifo_set_watermark = bm1390_set_watermark, 482 + .hwfifo_flush_to_buffer = bm1390_fifo_flush, 483 + }; 484 + 485 + static int bm1390_chip_init(struct bm1390_data *data) 486 + { 487 + int ret; 488 + 489 + ret = regmap_write_bits(data->regmap, BM1390_REG_POWER, 490 + BM1390_MASK_POWER, BM1390_POWER_ON); 491 + if (ret) 492 + return ret; 493 + 494 + msleep(1); 495 + 496 + ret = regmap_write_bits(data->regmap, BM1390_REG_RESET, 497 + BM1390_MASK_RESET, BM1390_RESET); 498 + if (ret) 499 + return ret; 500 + 501 + msleep(1); 502 + 503 + ret = regmap_write_bits(data->regmap, BM1390_REG_RESET, 504 + BM1390_MASK_RESET, BM1390_RESET_RELEASE); 505 + if (ret) 506 + return ret; 507 + 508 + msleep(1); 509 + 510 + ret = regmap_reinit_cache(data->regmap, &bm1390_regmap); 511 + if (ret) { 512 + dev_err(data->dev, "Failed to reinit reg cache\n"); 513 + return ret; 514 + } 515 + 516 + /* 517 + * Default to use IIR filter in "middle" mode. Also the AVE_NUM must 518 + * be fixed when IIR is in use. 519 + */ 520 + ret = regmap_update_bits(data->regmap, BM1390_REG_MODE_CTRL, 521 + BM1390_MASK_AVE_NUM, BM1390_IIR_AVE_NUM); 522 + if (ret) 523 + return ret; 524 + 525 + return regmap_update_bits(data->regmap, BM1390_REG_FIFO_CTRL, 526 + BM1390_MASK_IIR_MODE, BM1390_IIR_MODE_MID); 527 + } 528 + 529 + static int bm1390_fifo_set_wmi(struct bm1390_data *data) 530 + { 531 + u8 regval; 532 + 533 + regval = FIELD_PREP(BM1390_MASK_FIFO_LEN, 534 + data->watermark - BM1390_WMI_MIN); 535 + 536 + return regmap_update_bits(data->regmap, BM1390_REG_FIFO_CTRL, 537 + BM1390_MASK_FIFO_LEN, regval); 538 + } 539 + 540 + static int bm1390_fifo_enable(struct iio_dev *idev) 541 + { 542 + struct bm1390_data *data = iio_priv(idev); 543 + int ret; 544 + 545 + /* We can't do buffered stuff without IRQ as we never get WMI */ 546 + if (data->irq <= 0) 547 + return -EINVAL; 548 + 549 + mutex_lock(&data->mutex); 550 + if (data->trigger_enabled) { 551 + ret = -EBUSY; 552 + goto unlock_out; 553 + } 554 + 555 + /* Update watermark to HW */ 556 + ret = bm1390_fifo_set_wmi(data); 557 + if (ret) 558 + goto unlock_out; 559 + 560 + /* Enable WMI_IRQ */ 561 + ret = regmap_set_bits(data->regmap, BM1390_REG_MODE_CTRL, 562 + BM1390_MASK_WMI_EN); 563 + if (ret) 564 + goto unlock_out; 565 + 566 + /* Enable FIFO */ 567 + ret = regmap_set_bits(data->regmap, BM1390_REG_FIFO_CTRL, 568 + BM1390_MASK_FIFO_EN); 569 + if (ret) 570 + goto unlock_out; 571 + 572 + data->state = BM1390_STATE_FIFO; 573 + 574 + data->old_timestamp = iio_get_time_ns(idev); 575 + ret = bm1390_meas_set(data, BM1390_MEAS_MODE_CONTINUOUS); 576 + 577 + unlock_out: 578 + mutex_unlock(&data->mutex); 579 + 580 + return ret; 581 + } 582 + 583 + static int bm1390_fifo_disable(struct iio_dev *idev) 584 + { 585 + struct bm1390_data *data = iio_priv(idev); 586 + int ret; 587 + 588 + msleep(1); 589 + 590 + mutex_lock(&data->mutex); 591 + ret = bm1390_meas_set(data, BM1390_MEAS_MODE_STOP); 592 + if (ret) 593 + goto unlock_out; 594 + 595 + /* Disable FIFO */ 596 + ret = regmap_clear_bits(data->regmap, BM1390_REG_FIFO_CTRL, 597 + BM1390_MASK_FIFO_EN); 598 + if (ret) 599 + goto unlock_out; 600 + 601 + data->state = BM1390_STATE_SAMPLE; 602 + 603 + /* Disable WMI_IRQ */ 604 + ret = regmap_clear_bits(data->regmap, BM1390_REG_MODE_CTRL, 605 + BM1390_MASK_WMI_EN); 606 + 607 + unlock_out: 608 + mutex_unlock(&data->mutex); 609 + 610 + return ret; 611 + } 612 + 613 + static int bm1390_buffer_postenable(struct iio_dev *idev) 614 + { 615 + /* 616 + * If we use data-ready trigger, then the IRQ masks should be handled by 617 + * trigger enable and the hardware buffer is not used but we just update 618 + * results to the IIO FIFO when data-ready triggers. 619 + */ 620 + if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED) 621 + return 0; 622 + 623 + return bm1390_fifo_enable(idev); 624 + } 625 + 626 + static int bm1390_buffer_predisable(struct iio_dev *idev) 627 + { 628 + if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED) 629 + return 0; 630 + 631 + return bm1390_fifo_disable(idev); 632 + } 633 + 634 + static const struct iio_buffer_setup_ops bm1390_buffer_ops = { 635 + .postenable = bm1390_buffer_postenable, 636 + .predisable = bm1390_buffer_predisable, 637 + }; 638 + 639 + static irqreturn_t bm1390_trigger_handler(int irq, void *p) 640 + { 641 + struct iio_poll_func *pf = p; 642 + struct iio_dev *idev = pf->indio_dev; 643 + struct bm1390_data *data = iio_priv(idev); 644 + int ret, status; 645 + 646 + /* DRDY is acked by reading status reg */ 647 + ret = regmap_read(data->regmap, BM1390_REG_STATUS, &status); 648 + if (ret || !status) 649 + return IRQ_NONE; 650 + 651 + dev_dbg(data->dev, "DRDY trig status 0x%x\n", status); 652 + 653 + if (test_bit(BM1390_CHAN_PRESSURE, idev->active_scan_mask)) { 654 + ret = bm1390_pressure_read(data, &data->buf.pressure); 655 + if (ret) { 656 + dev_warn(data->dev, "sample read failed %d\n", ret); 657 + return IRQ_NONE; 658 + } 659 + } 660 + 661 + if (test_bit(BM1390_CHAN_TEMP, idev->active_scan_mask)) { 662 + ret = regmap_bulk_read(data->regmap, BM1390_REG_TEMP_HI, 663 + &data->buf.temp, sizeof(data->buf.temp)); 664 + if (ret) { 665 + dev_warn(data->dev, "temp read failed %d\n", ret); 666 + return IRQ_HANDLED; 667 + } 668 + } 669 + 670 + iio_push_to_buffers_with_timestamp(idev, &data->buf, data->timestamp); 671 + iio_trigger_notify_done(idev->trig); 672 + 673 + return IRQ_HANDLED; 674 + } 675 + 676 + /* Get timestamps and wake the thread if we need to read data */ 677 + static irqreturn_t bm1390_irq_handler(int irq, void *private) 678 + { 679 + struct iio_dev *idev = private; 680 + struct bm1390_data *data = iio_priv(idev); 681 + 682 + data->timestamp = iio_get_time_ns(idev); 683 + 684 + if (data->state == BM1390_STATE_FIFO || data->trigger_enabled) 685 + return IRQ_WAKE_THREAD; 686 + 687 + return IRQ_NONE; 688 + } 689 + 690 + static irqreturn_t bm1390_irq_thread_handler(int irq, void *private) 691 + { 692 + struct iio_dev *idev = private; 693 + struct bm1390_data *data = iio_priv(idev); 694 + int ret = IRQ_NONE; 695 + 696 + mutex_lock(&data->mutex); 697 + 698 + if (data->trigger_enabled) { 699 + iio_trigger_poll_nested(data->trig); 700 + ret = IRQ_HANDLED; 701 + } else if (data->state == BM1390_STATE_FIFO) { 702 + int ok; 703 + 704 + ok = __bm1390_fifo_flush(idev, BM1390_FIFO_LENGTH, 705 + data->timestamp); 706 + if (ok > 0) 707 + ret = IRQ_HANDLED; 708 + } 709 + 710 + mutex_unlock(&data->mutex); 711 + 712 + return ret; 713 + } 714 + 715 + static int bm1390_set_drdy_irq(struct bm1390_data *data, bool en) 716 + { 717 + if (en) 718 + return regmap_set_bits(data->regmap, BM1390_REG_MODE_CTRL, 719 + BM1390_MASK_DRDY_EN); 720 + return regmap_clear_bits(data->regmap, BM1390_REG_MODE_CTRL, 721 + BM1390_MASK_DRDY_EN); 722 + } 723 + 724 + static int bm1390_trigger_set_state(struct iio_trigger *trig, 725 + bool state) 726 + { 727 + struct bm1390_data *data = iio_trigger_get_drvdata(trig); 728 + int ret = 0; 729 + 730 + mutex_lock(&data->mutex); 731 + 732 + if (data->trigger_enabled == state) 733 + goto unlock_out; 734 + 735 + if (data->state == BM1390_STATE_FIFO) { 736 + dev_warn(data->dev, "Can't set trigger when FIFO enabled\n"); 737 + ret = -EBUSY; 738 + goto unlock_out; 739 + } 740 + 741 + data->trigger_enabled = state; 742 + 743 + if (state) { 744 + ret = bm1390_meas_set(data, BM1390_MEAS_MODE_CONTINUOUS); 745 + if (ret) 746 + goto unlock_out; 747 + } else { 748 + int dummy; 749 + 750 + ret = bm1390_meas_set(data, BM1390_MEAS_MODE_STOP); 751 + if (ret) 752 + goto unlock_out; 753 + 754 + /* 755 + * We need to read the status register in order to ACK the 756 + * data-ready which may have been generated just before we 757 + * disabled the measurement. 758 + */ 759 + ret = regmap_read(data->regmap, BM1390_REG_STATUS, &dummy); 760 + if (ret) 761 + dev_warn(data->dev, "status read failed\n"); 762 + } 763 + 764 + ret = bm1390_set_drdy_irq(data, state); 765 + 766 + unlock_out: 767 + mutex_unlock(&data->mutex); 768 + 769 + return ret; 770 + } 771 + 772 + static const struct iio_trigger_ops bm1390_trigger_ops = { 773 + .set_trigger_state = bm1390_trigger_set_state, 774 + }; 775 + 776 + static int bm1390_setup_buffer(struct bm1390_data *data, struct iio_dev *idev) 777 + { 778 + int ret; 779 + 780 + ret = devm_iio_triggered_buffer_setup(data->dev, idev, 781 + &iio_pollfunc_store_time, 782 + &bm1390_trigger_handler, 783 + &bm1390_buffer_ops); 784 + 785 + if (ret) 786 + return dev_err_probe(data->dev, ret, 787 + "iio_triggered_buffer_setup FAIL\n"); 788 + 789 + idev->available_scan_masks = bm1390_scan_masks; 790 + 791 + return 0; 792 + } 793 + 794 + static int bm1390_setup_trigger(struct bm1390_data *data, struct iio_dev *idev, 795 + int irq) 796 + { 797 + struct iio_trigger *itrig; 798 + char *name; 799 + int ret; 800 + 801 + itrig = devm_iio_trigger_alloc(data->dev, "%sdata-rdy-dev%d", idev->name, 802 + iio_device_id(idev)); 803 + if (!itrig) 804 + return -ENOMEM; 805 + 806 + data->trig = itrig; 807 + 808 + itrig->ops = &bm1390_trigger_ops; 809 + iio_trigger_set_drvdata(itrig, data); 810 + 811 + name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-bm1390", 812 + dev_name(data->dev)); 813 + if (name == NULL) 814 + return -ENOMEM; 815 + 816 + ret = devm_request_threaded_irq(data->dev, irq, bm1390_irq_handler, 817 + &bm1390_irq_thread_handler, 818 + IRQF_ONESHOT, name, idev); 819 + if (ret) 820 + return dev_err_probe(data->dev, ret, "Could not request IRQ\n"); 821 + 822 + 823 + ret = devm_iio_trigger_register(data->dev, itrig); 824 + if (ret) 825 + return dev_err_probe(data->dev, ret, 826 + "Trigger registration failed\n"); 827 + 828 + return 0; 829 + } 830 + 831 + static int bm1390_probe(struct i2c_client *i2c) 832 + { 833 + struct bm1390_data *data; 834 + struct regmap *regmap; 835 + struct iio_dev *idev; 836 + struct device *dev; 837 + unsigned int part_id; 838 + int ret; 839 + 840 + dev = &i2c->dev; 841 + 842 + regmap = devm_regmap_init_i2c(i2c, &bm1390_regmap); 843 + if (IS_ERR(regmap)) 844 + return dev_err_probe(dev, PTR_ERR(regmap), 845 + "Failed to initialize Regmap\n"); 846 + 847 + ret = devm_regulator_get_enable(dev, "vdd"); 848 + if (ret) 849 + return dev_err_probe(dev, ret, "Failed to get regulator\n"); 850 + 851 + ret = regmap_read(regmap, BM1390_REG_PART_ID, &part_id); 852 + if (ret) 853 + return dev_err_probe(dev, ret, "Failed to access sensor\n"); 854 + 855 + if (part_id != BM1390_ID) 856 + dev_warn(dev, "unknown device 0x%x\n", part_id); 857 + 858 + idev = devm_iio_device_alloc(dev, sizeof(*data)); 859 + if (!idev) 860 + return -ENOMEM; 861 + 862 + data = iio_priv(idev); 863 + data->regmap = regmap; 864 + data->dev = dev; 865 + data->irq = i2c->irq; 866 + /* 867 + * For now we just allow BM1390_WMI_MIN to BM1390_WMI_MAX and 868 + * discard every other configuration when triggered mode is not used. 869 + */ 870 + data->watermark = BM1390_WMI_MAX; 871 + mutex_init(&data->mutex); 872 + 873 + idev->channels = bm1390_channels; 874 + idev->num_channels = ARRAY_SIZE(bm1390_channels); 875 + idev->name = "bm1390"; 876 + idev->modes = INDIO_DIRECT_MODE; 877 + 878 + ret = bm1390_chip_init(data); 879 + if (ret) 880 + return dev_err_probe(dev, ret, "sensor init failed\n"); 881 + 882 + ret = bm1390_setup_buffer(data, idev); 883 + if (ret) 884 + return ret; 885 + 886 + /* No trigger if we don't have IRQ for data-ready and WMI */ 887 + if (i2c->irq > 0) { 888 + idev->info = &bm1390_info; 889 + idev->modes |= INDIO_BUFFER_SOFTWARE; 890 + ret = bm1390_setup_trigger(data, idev, i2c->irq); 891 + if (ret) 892 + return ret; 893 + } else { 894 + idev->info = &bm1390_noirq_info; 895 + } 896 + 897 + ret = devm_iio_device_register(dev, idev); 898 + if (ret < 0) 899 + return dev_err_probe(dev, ret, 900 + "Unable to register iio device\n"); 901 + 902 + return 0; 903 + } 904 + 905 + static const struct of_device_id bm1390_of_match[] = { 906 + { .compatible = "rohm,bm1390glv-z" }, 907 + {} 908 + }; 909 + MODULE_DEVICE_TABLE(of, bm1390_of_match); 910 + 911 + static const struct i2c_device_id bm1390_id[] = { 912 + { "bm1390glv-z", }, 913 + {} 914 + }; 915 + MODULE_DEVICE_TABLE(i2c, bm1390_id); 916 + 917 + static struct i2c_driver bm1390_driver = { 918 + .driver = { 919 + .name = "bm1390", 920 + .of_match_table = bm1390_of_match, 921 + /* 922 + * Probing explicitly requires a few millisecond of sleep. 923 + * Enabling the VDD regulator may include ramp up rates. 924 + */ 925 + .probe_type = PROBE_PREFER_ASYNCHRONOUS, 926 + }, 927 + .probe = bm1390_probe, 928 + .id_table = bm1390_id, 929 + }; 930 + module_i2c_driver(bm1390_driver); 931 + 932 + MODULE_AUTHOR("Matti Vaittinen <mazziesaccount@gmail.com>"); 933 + MODULE_DESCRIPTION("Driver for ROHM BM1390 pressure sensor"); 934 + MODULE_LICENSE("GPL");

+2 -4

drivers/iio/proximity/cros_ec_mkbp_proximity.c

··· 239 239 return 0; 240 240 } 241 241 242 - static int cros_ec_mkbp_proximity_remove(struct platform_device *pdev) 242 + static void cros_ec_mkbp_proximity_remove(struct platform_device *pdev) 243 243 { 244 244 struct cros_ec_mkbp_proximity_data *data = platform_get_drvdata(pdev); 245 245 struct cros_ec_device *ec = data->ec; 246 246 247 247 blocking_notifier_chain_unregister(&ec->event_notifier, 248 248 &data->notifier); 249 - 250 - return 0; 251 249 } 252 250 253 251 static const struct of_device_id cros_ec_mkbp_proximity_of_match[] = { ··· 261 263 .pm = pm_sleep_ptr(&cros_ec_mkbp_proximity_pm_ops), 262 264 }, 263 265 .probe = cros_ec_mkbp_proximity_probe, 264 - .remove = cros_ec_mkbp_proximity_remove, 266 + .remove_new = cros_ec_mkbp_proximity_remove, 265 267 }; 266 268 module_platform_driver(cros_ec_mkbp_proximity_driver); 267 269

+2 -4

drivers/iio/proximity/srf04.c

··· 344 344 return ret; 345 345 } 346 346 347 - static int srf04_remove(struct platform_device *pdev) 347 + static void srf04_remove(struct platform_device *pdev) 348 348 { 349 349 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 350 350 struct srf04_data *data = iio_priv(indio_dev); ··· 355 355 pm_runtime_disable(data->dev); 356 356 pm_runtime_set_suspended(data->dev); 357 357 } 358 - 359 - return 0; 360 358 } 361 359 362 360 static int srf04_pm_runtime_suspend(struct device *dev) ··· 389 391 390 392 static struct platform_driver srf04_driver = { 391 393 .probe = srf04_probe, 392 - .remove = srf04_remove, 394 + .remove_new = srf04_remove, 393 395 .driver = { 394 396 .name = "srf04-gpio", 395 397 .of_match_table = of_srf04_match,

+26 -20

drivers/iio/proximity/sx9310.c

··· 159 159 } 160 160 #define SX9310_CHANNEL(idx) SX9310_NAMED_CHANNEL(idx, NULL) 161 161 162 + struct sx931x_info { 163 + const char *name; 164 + unsigned int whoami; 165 + }; 166 + 162 167 static const struct iio_chan_spec sx9310_channels[] = { 163 168 SX9310_CHANNEL(0), /* CS0 */ 164 169 SX9310_CHANNEL(1), /* CS1 */ ··· 907 902 struct iio_dev *indio_dev) 908 903 { 909 904 struct sx_common_data *data = iio_priv(indio_dev); 910 - unsigned int long ddata; 905 + const struct sx931x_info *ddata; 911 906 unsigned int whoami; 912 907 int ret; 913 908 ··· 915 910 if (ret) 916 911 return ret; 917 912 918 - ddata = (uintptr_t)device_get_match_data(dev); 919 - if (ddata != whoami) 920 - return -EINVAL; 921 - 922 - switch (whoami) { 923 - case SX9310_WHOAMI_VALUE: 924 - indio_dev->name = "sx9310"; 925 - break; 926 - case SX9311_WHOAMI_VALUE: 927 - indio_dev->name = "sx9311"; 928 - break; 929 - default: 913 + ddata = device_get_match_data(dev); 914 + if (ddata->whoami != whoami) 930 915 return -ENODEV; 931 - } 916 + 917 + indio_dev->name = ddata->name; 932 918 933 919 return 0; 934 920 } ··· 1011 1015 1012 1016 static DEFINE_SIMPLE_DEV_PM_OPS(sx9310_pm_ops, sx9310_suspend, sx9310_resume); 1013 1017 1018 + static const struct sx931x_info sx9310_info = { 1019 + .name = "sx9310", 1020 + .whoami = SX9310_WHOAMI_VALUE, 1021 + }; 1022 + 1023 + static const struct sx931x_info sx9311_info = { 1024 + .name = "sx9311", 1025 + .whoami = SX9311_WHOAMI_VALUE, 1026 + }; 1027 + 1014 1028 static const struct acpi_device_id sx9310_acpi_match[] = { 1015 - { "STH9310", SX9310_WHOAMI_VALUE }, 1016 - { "STH9311", SX9311_WHOAMI_VALUE }, 1029 + { "STH9310", (kernel_ulong_t)&sx9310_info }, 1030 + { "STH9311", (kernel_ulong_t)&sx9311_info }, 1017 1031 {} 1018 1032 }; 1019 1033 MODULE_DEVICE_TABLE(acpi, sx9310_acpi_match); 1020 1034 1021 1035 static const struct of_device_id sx9310_of_match[] = { 1022 - { .compatible = "semtech,sx9310", (void *)SX9310_WHOAMI_VALUE }, 1023 - { .compatible = "semtech,sx9311", (void *)SX9311_WHOAMI_VALUE }, 1036 + { .compatible = "semtech,sx9310", &sx9310_info }, 1037 + { .compatible = "semtech,sx9311", &sx9311_info }, 1024 1038 {} 1025 1039 }; 1026 1040 MODULE_DEVICE_TABLE(of, sx9310_of_match); 1027 1041 1028 1042 static const struct i2c_device_id sx9310_id[] = { 1029 - { "sx9310", SX9310_WHOAMI_VALUE }, 1030 - { "sx9311", SX9311_WHOAMI_VALUE }, 1043 + { "sx9310", (kernel_ulong_t)&sx9310_info }, 1044 + { "sx9311", (kernel_ulong_t)&sx9311_info }, 1031 1045 {} 1032 1046 }; 1033 1047 MODULE_DEVICE_TABLE(i2c, sx9310_id);

+13

drivers/iio/resolver/Kconfig

··· 25 25 26 26 To compile this driver as a module, choose M here: the 27 27 module will be called ad2s1200. 28 + 29 + config AD2S1210 30 + tristate "Analog Devices ad2s1210 driver" 31 + depends on SPI 32 + depends on COMMON_CLK 33 + depends on GPIOLIB || COMPILE_TEST 34 + help 35 + Say yes here to build support for Analog Devices spi resolver 36 + to digital converters, ad2s1210, provides direct access via sysfs. 37 + 38 + To compile this driver as a module, choose M here: the 39 + module will be called ad2s1210. 40 + 28 41 endmenu

+1

drivers/iio/resolver/Makefile

··· 5 5 6 6 obj-$(CONFIG_AD2S90) += ad2s90.o 7 7 obj-$(CONFIG_AD2S1200) += ad2s1200.o 8 + obj-$(CONFIG_AD2S1210) += ad2s1210.o

+1519

drivers/iio/resolver/ad2s1210.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * ad2s1210.c support for the ADI Resolver to Digital Converters: AD2S1210 4 + * 5 + * Copyright (c) 2010-2010 Analog Devices Inc. 6 + * Copyright (c) 2023 BayLibre, SAS 7 + * 8 + * Device register to IIO ABI mapping: 9 + * 10 + * Register | Addr | IIO ABI (sysfs) 11 + * ----------------------------|------|------------------------------------------- 12 + * DOS Overrange Threshold | 0x89 | events/in_altvoltage0_thresh_rising_value 13 + * DOS Mismatch Threshold | 0x8A | events/in_altvoltage0_mag_rising_value 14 + * DOS Reset Maximum Threshold | 0x8B | events/in_altvoltage0_mag_rising_reset_max 15 + * DOS Reset Minimum Threshold | 0x8C | events/in_altvoltage0_mag_rising_reset_min 16 + * LOT High Threshold | 0x8D | events/in_angl1_thresh_rising_value 17 + * LOT Low Threshold [1] | 0x8E | events/in_angl1_thresh_rising_hysteresis 18 + * Excitation Frequency | 0x91 | out_altvoltage0_frequency 19 + * Control | 0x92 | *as bit fields* 20 + * Phase lock range | D5 | events/in_phase0_mag_rising_value 21 + * Hysteresis | D4 | in_angl0_hysteresis 22 + * Encoder resolution | D3:2 | *not implemented* 23 + * Resolution | D1:0 | *device tree: assigned-resolution-bits* 24 + * Soft Reset | 0xF0 | [2] 25 + * Fault | 0xFF | *not implemented* 26 + * 27 + * [1]: The value written to the LOT low register is high value minus the 28 + * hysteresis. 29 + * [2]: Soft reset is performed when `out_altvoltage0_frequency` is written. 30 + * 31 + * Fault to event mapping: 32 + * 33 + * Fault | | Channel | Type | Direction 34 + * ----------------------------------------|----|--------------------------------- 35 + * Sine/cosine inputs clipped [3] | D7 | altvoltage1 | mag | either 36 + * Sine/cosine inputs below LOS | D6 | altvoltage0 | thresh | falling 37 + * Sine/cosine inputs exceed DOS overrange | D5 | altvoltage0 | thresh | rising 38 + * Sine/cosine inputs exceed DOS mismatch | D4 | altvoltage0 | mag | rising 39 + * Tracking error exceeds LOT | D3 | angl1 | thresh | rising 40 + * Velocity exceeds maximum tracking rate | D2 | anglvel0 | mag | rising 41 + * Phase error exceeds phase lock range | D1 | phase0 | mag | rising 42 + * Configuration parity error | D0 | *writes to kernel log* 43 + * 44 + * [3]: The chip does not differentiate between fault on sine vs. cosine so 45 + * there will also be an event on the altvoltage2 channel. 46 + */ 47 + 48 + #include <linux/bitfield.h> 49 + #include <linux/bits.h> 50 + #include <linux/cleanup.h> 51 + #include <linux/clk.h> 52 + #include <linux/delay.h> 53 + #include <linux/device.h> 54 + #include <linux/gpio/consumer.h> 55 + #include <linux/module.h> 56 + #include <linux/mutex.h> 57 + #include <linux/regmap.h> 58 + #include <linux/slab.h> 59 + #include <linux/spi/spi.h> 60 + #include <linux/sysfs.h> 61 + #include <linux/types.h> 62 + 63 + #include <linux/iio/buffer.h> 64 + #include <linux/iio/events.h> 65 + #include <linux/iio/iio.h> 66 + #include <linux/iio/sysfs.h> 67 + #include <linux/iio/trigger_consumer.h> 68 + #include <linux/iio/triggered_buffer.h> 69 + 70 + /* control register flags */ 71 + #define AD2S1210_ADDRESS_DATA BIT(7) 72 + #define AD2S1210_PHASE_LOCK_RANGE_44 BIT(5) 73 + #define AD2S1210_ENABLE_HYSTERESIS BIT(4) 74 + #define AD2S1210_SET_ENRES GENMASK(3, 2) 75 + #define AD2S1210_SET_RES GENMASK(1, 0) 76 + 77 + /* fault register flags */ 78 + #define AD2S1210_FAULT_CLIP BIT(7) 79 + #define AD2S1210_FAULT_LOS BIT(6) 80 + #define AD2S1210_FAULT_DOS_OVR BIT(5) 81 + #define AD2S1210_FAULT_DOS_MIS BIT(4) 82 + #define AD2S1210_FAULT_LOT BIT(3) 83 + #define AD2S1210_FAULT_VELOCITY BIT(2) 84 + #define AD2S1210_FAULT_PHASE BIT(1) 85 + #define AD2S1210_FAULT_CONFIG_PARITY BIT(0) 86 + 87 + #define AD2S1210_REG_POSITION_MSB 0x80 88 + #define AD2S1210_REG_POSITION_LSB 0x81 89 + #define AD2S1210_REG_VELOCITY_MSB 0x82 90 + #define AD2S1210_REG_VELOCITY_LSB 0x83 91 + #define AD2S1210_REG_LOS_THRD 0x88 92 + #define AD2S1210_REG_DOS_OVR_THRD 0x89 93 + #define AD2S1210_REG_DOS_MIS_THRD 0x8A 94 + #define AD2S1210_REG_DOS_RST_MAX_THRD 0x8B 95 + #define AD2S1210_REG_DOS_RST_MIN_THRD 0x8C 96 + #define AD2S1210_REG_LOT_HIGH_THRD 0x8D 97 + #define AD2S1210_REG_LOT_LOW_THRD 0x8E 98 + #define AD2S1210_REG_EXCIT_FREQ 0x91 99 + #define AD2S1210_REG_CONTROL 0x92 100 + #define AD2S1210_REG_SOFT_RESET 0xF0 101 + #define AD2S1210_REG_FAULT 0xFF 102 + 103 + #define AD2S1210_MIN_CLKIN 6144000 104 + #define AD2S1210_MAX_CLKIN 10240000 105 + #define AD2S1210_MIN_EXCIT 2000 106 + #define AD2S1210_DEF_EXCIT 10000 107 + #define AD2S1210_MAX_EXCIT 20000 108 + #define AD2S1210_MIN_FCW 0x4 109 + #define AD2S1210_MAX_FCW 0x50 110 + 111 + /* 44 degrees ~= 0.767945 radians */ 112 + #define PHASE_44_DEG_TO_RAD_INT 0 113 + #define PHASE_44_DEG_TO_RAD_MICRO 767945 114 + /* 360 degrees ~= 6.283185 radians */ 115 + #define PHASE_360_DEG_TO_RAD_INT 6 116 + #define PHASE_360_DEG_TO_RAD_MICRO 283185 117 + 118 + /* Threshold voltage registers have 1 LSB == 38 mV */ 119 + #define THRESHOLD_MILLIVOLT_PER_LSB 38 120 + /* max voltage for threshold registers is 0x7F * 38 mV */ 121 + #define THRESHOLD_RANGE_STR "[0 38 4826]" 122 + 123 + #define FAULT_ONESHOT(bit, new, old) (new & bit && !(old & bit)) 124 + 125 + enum ad2s1210_mode { 126 + MOD_POS = 0b00, 127 + MOD_VEL = 0b01, 128 + MOD_RESERVED = 0b10, 129 + MOD_CONFIG = 0b11, 130 + }; 131 + 132 + enum ad2s1210_resolution { 133 + AD2S1210_RES_10 = 0b00, 134 + AD2S1210_RES_12 = 0b01, 135 + AD2S1210_RES_14 = 0b10, 136 + AD2S1210_RES_16 = 0b11, 137 + }; 138 + 139 + struct ad2s1210_state { 140 + struct mutex lock; 141 + struct spi_device *sdev; 142 + /** GPIO pin connected to SAMPLE line. */ 143 + struct gpio_desc *sample_gpio; 144 + /** GPIO pins connected to A0 and A1 lines. */ 145 + struct gpio_descs *mode_gpios; 146 + /** Used to access config registers. */ 147 + struct regmap *regmap; 148 + /** The external oscillator frequency in Hz. */ 149 + unsigned long clkin_hz; 150 + /** Available raw hysteresis values based on resolution. */ 151 + int hysteresis_available[2]; 152 + /** The selected resolution */ 153 + enum ad2s1210_resolution resolution; 154 + /** Copy of fault register from the previous read. */ 155 + u8 prev_fault_flags; 156 + /** For reading raw sample value via SPI. */ 157 + struct { 158 + __be16 raw; 159 + u8 fault; 160 + } sample __aligned(IIO_DMA_MINALIGN); 161 + /** Scan buffer */ 162 + struct { 163 + __be16 chan[2]; 164 + /* Ensure timestamp is naturally aligned. */ 165 + s64 timestamp __aligned(8); 166 + } scan; 167 + /** SPI transmit buffer. */ 168 + u8 rx[2]; 169 + /** SPI receive buffer. */ 170 + u8 tx[2]; 171 + }; 172 + 173 + static int ad2s1210_set_mode(struct ad2s1210_state *st, enum ad2s1210_mode mode) 174 + { 175 + struct gpio_descs *gpios = st->mode_gpios; 176 + DECLARE_BITMAP(bitmap, 2); 177 + 178 + bitmap[0] = mode; 179 + 180 + return gpiod_set_array_value(gpios->ndescs, gpios->desc, gpios->info, 181 + bitmap); 182 + } 183 + 184 + /* 185 + * Writes the given data to the given register address. 186 + * 187 + * If the mode is configurable, the device will first be placed in 188 + * configuration mode. 189 + */ 190 + static int ad2s1210_regmap_reg_write(void *context, unsigned int reg, 191 + unsigned int val) 192 + { 193 + struct ad2s1210_state *st = context; 194 + struct spi_transfer xfers[] = { 195 + { 196 + .len = 1, 197 + .rx_buf = &st->rx[0], 198 + .tx_buf = &st->tx[0], 199 + .cs_change = 1, 200 + }, { 201 + .len = 1, 202 + .rx_buf = &st->rx[1], 203 + .tx_buf = &st->tx[1], 204 + }, 205 + }; 206 + int ret; 207 + 208 + /* values can only be 7 bits, the MSB indicates an address */ 209 + if (val & ~0x7F) 210 + return -EINVAL; 211 + 212 + st->tx[0] = reg; 213 + st->tx[1] = val; 214 + 215 + ret = ad2s1210_set_mode(st, MOD_CONFIG); 216 + if (ret < 0) 217 + return ret; 218 + 219 + ret = spi_sync_transfer(st->sdev, xfers, ARRAY_SIZE(xfers)); 220 + if (ret < 0) 221 + return ret; 222 + 223 + /* soft reset also clears the fault register */ 224 + if (reg == AD2S1210_REG_SOFT_RESET) 225 + st->prev_fault_flags = 0; 226 + 227 + return 0; 228 + } 229 + 230 + /* 231 + * Reads value from one of the registers. 232 + * 233 + * If the mode is configurable, the device will first be placed in 234 + * configuration mode. 235 + */ 236 + static int ad2s1210_regmap_reg_read(void *context, unsigned int reg, 237 + unsigned int *val) 238 + { 239 + struct ad2s1210_state *st = context; 240 + struct spi_transfer xfers[] = { 241 + { 242 + .len = 1, 243 + .rx_buf = &st->rx[0], 244 + .tx_buf = &st->tx[0], 245 + .cs_change = 1, 246 + }, { 247 + .len = 1, 248 + .rx_buf = &st->rx[1], 249 + .tx_buf = &st->tx[1], 250 + }, 251 + }; 252 + int ret; 253 + 254 + ret = ad2s1210_set_mode(st, MOD_CONFIG); 255 + if (ret < 0) 256 + return ret; 257 + 258 + st->tx[0] = reg; 259 + /* 260 + * Must be valid register address here otherwise this could write data. 261 + * It doesn't matter which one as long as reading doesn't have side- 262 + * effects. 263 + */ 264 + st->tx[1] = AD2S1210_REG_CONTROL; 265 + 266 + ret = spi_sync_transfer(st->sdev, xfers, ARRAY_SIZE(xfers)); 267 + if (ret < 0) 268 + return ret; 269 + 270 + /* reading the fault register also clears it */ 271 + if (reg == AD2S1210_REG_FAULT) 272 + st->prev_fault_flags = 0; 273 + 274 + /* 275 + * If the D7 bit is set on any read/write register, it indicates a 276 + * parity error. The fault register is read-only and the D7 bit means 277 + * something else there. 278 + */ 279 + if (reg != AD2S1210_REG_FAULT && st->rx[1] & AD2S1210_ADDRESS_DATA) 280 + return -EBADMSG; 281 + 282 + *val = st->rx[1]; 283 + 284 + return 0; 285 + } 286 + 287 + /* 288 + * Toggles the SAMPLE line on the AD2S1210 to latch in the current position, 289 + * velocity, and faults. 290 + * 291 + * Must be called with lock held. 292 + */ 293 + static void ad2s1210_toggle_sample_line(struct ad2s1210_state *st) 294 + { 295 + /* 296 + * Datasheet specifies minimum hold time t16 = 2 * tck + 20 ns. So the 297 + * longest time needed is when CLKIN is 6.144 MHz, in which case t16 298 + * ~= 350 ns. The same delay is also needed before re-asserting the 299 + * SAMPLE line. 300 + */ 301 + gpiod_set_value(st->sample_gpio, 1); 302 + ndelay(350); 303 + gpiod_set_value(st->sample_gpio, 0); 304 + ndelay(350); 305 + } 306 + 307 + /* 308 + * Sets the excitation frequency and performs software reset. 309 + * 310 + * Must be called with lock held. 311 + */ 312 + static int ad2s1210_reinit_excitation_frequency(struct ad2s1210_state *st, 313 + u16 fexcit) 314 + { 315 + /* Map resolution to settle time in milliseconds. */ 316 + static const int track_time_ms[] = { 10, 20, 25, 60 }; 317 + unsigned int ignored; 318 + int ret; 319 + u8 fcw; 320 + 321 + fcw = fexcit * (1 << 15) / st->clkin_hz; 322 + if (fcw < AD2S1210_MIN_FCW || fcw > AD2S1210_MAX_FCW) 323 + return -ERANGE; 324 + 325 + ret = regmap_write(st->regmap, AD2S1210_REG_EXCIT_FREQ, fcw); 326 + if (ret < 0) 327 + return ret; 328 + 329 + /* 330 + * Software reset reinitializes the excitation frequency output. 331 + * It does not reset any of the configuration registers. 332 + */ 333 + ret = regmap_write(st->regmap, AD2S1210_REG_SOFT_RESET, 0); 334 + if (ret < 0) 335 + return ret; 336 + 337 + /* 338 + * Soft reset always triggers some faults due the change in the output 339 + * signal so clear the faults too. We need to delay for some time 340 + * (what datasheet calls t[track]) to allow things to settle before 341 + * clearing the faults. 342 + */ 343 + msleep(track_time_ms[st->resolution] * 8192000 / st->clkin_hz); 344 + 345 + /* Reading the fault register clears the faults. */ 346 + ret = regmap_read(st->regmap, AD2S1210_REG_FAULT, &ignored); 347 + if (ret < 0) 348 + return ret; 349 + 350 + /* Have to toggle sample line to get fault output pins to reset. */ 351 + ad2s1210_toggle_sample_line(st); 352 + 353 + return 0; 354 + } 355 + 356 + static void ad2s1210_push_events(struct iio_dev *indio_dev, 357 + u8 flags, s64 timestamp) 358 + { 359 + struct ad2s1210_state *st = iio_priv(indio_dev); 360 + 361 + /* Sine/cosine inputs clipped */ 362 + if (FAULT_ONESHOT(AD2S1210_FAULT_CLIP, flags, st->prev_fault_flags)) { 363 + /* 364 + * The chip does not differentiate between fault on sine vs. 365 + * cosine channel so we just send an event on both channels. 366 + */ 367 + iio_push_event(indio_dev, 368 + IIO_UNMOD_EVENT_CODE(IIO_ALTVOLTAGE, 1, 369 + IIO_EV_TYPE_MAG, 370 + IIO_EV_DIR_EITHER), 371 + timestamp); 372 + iio_push_event(indio_dev, 373 + IIO_UNMOD_EVENT_CODE(IIO_ALTVOLTAGE, 2, 374 + IIO_EV_TYPE_MAG, 375 + IIO_EV_DIR_EITHER), 376 + timestamp); 377 + } 378 + 379 + /* Sine/cosine inputs below LOS threshold */ 380 + if (FAULT_ONESHOT(AD2S1210_FAULT_LOS, flags, st->prev_fault_flags)) 381 + iio_push_event(indio_dev, 382 + IIO_UNMOD_EVENT_CODE(IIO_ALTVOLTAGE, 0, 383 + IIO_EV_TYPE_THRESH, 384 + IIO_EV_DIR_FALLING), 385 + timestamp); 386 + 387 + /* Sine/cosine inputs exceed DOS overrange threshold */ 388 + if (FAULT_ONESHOT(AD2S1210_FAULT_DOS_OVR, flags, st->prev_fault_flags)) 389 + iio_push_event(indio_dev, 390 + IIO_UNMOD_EVENT_CODE(IIO_ALTVOLTAGE, 0, 391 + IIO_EV_TYPE_THRESH, 392 + IIO_EV_DIR_RISING), 393 + timestamp); 394 + 395 + /* Sine/cosine inputs exceed DOS mismatch threshold */ 396 + if (FAULT_ONESHOT(AD2S1210_FAULT_DOS_MIS, flags, st->prev_fault_flags)) 397 + iio_push_event(indio_dev, 398 + IIO_UNMOD_EVENT_CODE(IIO_ALTVOLTAGE, 0, 399 + IIO_EV_TYPE_MAG, 400 + IIO_EV_DIR_RISING), 401 + timestamp); 402 + 403 + /* Tracking error exceeds LOT threshold */ 404 + if (FAULT_ONESHOT(AD2S1210_FAULT_LOT, flags, st->prev_fault_flags)) 405 + iio_push_event(indio_dev, 406 + IIO_UNMOD_EVENT_CODE(IIO_ANGL, 1, 407 + IIO_EV_TYPE_THRESH, 408 + IIO_EV_DIR_RISING), 409 + timestamp); 410 + 411 + /* Velocity exceeds maximum tracking rate */ 412 + if (FAULT_ONESHOT(AD2S1210_FAULT_VELOCITY, flags, st->prev_fault_flags)) 413 + iio_push_event(indio_dev, 414 + IIO_UNMOD_EVENT_CODE(IIO_ANGL_VEL, 0, 415 + IIO_EV_TYPE_THRESH, 416 + IIO_EV_DIR_RISING), 417 + timestamp); 418 + 419 + /* Phase error exceeds phase lock range */ 420 + if (FAULT_ONESHOT(AD2S1210_FAULT_PHASE, flags, st->prev_fault_flags)) 421 + iio_push_event(indio_dev, 422 + IIO_UNMOD_EVENT_CODE(IIO_PHASE, 0, 423 + IIO_EV_TYPE_MAG, 424 + IIO_EV_DIR_RISING), 425 + timestamp); 426 + 427 + /* Configuration parity error */ 428 + if (FAULT_ONESHOT(AD2S1210_FAULT_CONFIG_PARITY, flags, 429 + st->prev_fault_flags)) 430 + /* 431 + * Userspace should also get notified of this via error return 432 + * when trying to write to any attribute that writes a register. 433 + */ 434 + dev_err_ratelimited(&indio_dev->dev, 435 + "Configuration parity error\n"); 436 + 437 + st->prev_fault_flags = flags; 438 + } 439 + 440 + static int ad2s1210_single_conversion(struct iio_dev *indio_dev, 441 + struct iio_chan_spec const *chan, 442 + int *val) 443 + { 444 + struct ad2s1210_state *st = iio_priv(indio_dev); 445 + s64 timestamp; 446 + int ret; 447 + 448 + guard(mutex)(&st->lock); 449 + 450 + ad2s1210_toggle_sample_line(st); 451 + timestamp = iio_get_time_ns(indio_dev); 452 + 453 + switch (chan->type) { 454 + case IIO_ANGL: 455 + ret = ad2s1210_set_mode(st, MOD_POS); 456 + break; 457 + case IIO_ANGL_VEL: 458 + ret = ad2s1210_set_mode(st, MOD_VEL); 459 + break; 460 + default: 461 + return -EINVAL; 462 + } 463 + if (ret < 0) 464 + return ret; 465 + ret = spi_read(st->sdev, &st->sample, 3); 466 + if (ret < 0) 467 + return ret; 468 + 469 + switch (chan->type) { 470 + case IIO_ANGL: 471 + *val = be16_to_cpu(st->sample.raw); 472 + ret = IIO_VAL_INT; 473 + break; 474 + case IIO_ANGL_VEL: 475 + *val = (s16)be16_to_cpu(st->sample.raw); 476 + ret = IIO_VAL_INT; 477 + break; 478 + default: 479 + return -EINVAL; 480 + } 481 + 482 + ad2s1210_push_events(indio_dev, st->sample.fault, timestamp); 483 + 484 + return ret; 485 + } 486 + 487 + static int ad2s1210_get_hysteresis(struct ad2s1210_state *st, int *val) 488 + { 489 + int ret; 490 + 491 + guard(mutex)(&st->lock); 492 + ret = regmap_test_bits(st->regmap, AD2S1210_REG_CONTROL, 493 + AD2S1210_ENABLE_HYSTERESIS); 494 + if (ret < 0) 495 + return ret; 496 + 497 + *val = ret << (2 * (AD2S1210_RES_16 - st->resolution)); 498 + return IIO_VAL_INT; 499 + } 500 + 501 + static int ad2s1210_set_hysteresis(struct ad2s1210_state *st, int val) 502 + { 503 + guard(mutex)(&st->lock); 504 + return regmap_update_bits(st->regmap, AD2S1210_REG_CONTROL, 505 + AD2S1210_ENABLE_HYSTERESIS, 506 + val ? AD2S1210_ENABLE_HYSTERESIS : 0); 507 + } 508 + 509 + static int ad2s1210_get_phase_lock_range(struct ad2s1210_state *st, 510 + int *val, int *val2) 511 + { 512 + int ret; 513 + 514 + guard(mutex)(&st->lock); 515 + ret = regmap_test_bits(st->regmap, AD2S1210_REG_CONTROL, 516 + AD2S1210_PHASE_LOCK_RANGE_44); 517 + if (ret < 0) 518 + return ret; 519 + 520 + if (ret) { 521 + /* 44 degrees as radians */ 522 + *val = PHASE_44_DEG_TO_RAD_INT; 523 + *val2 = PHASE_44_DEG_TO_RAD_MICRO; 524 + } else { 525 + /* 360 degrees as radians */ 526 + *val = PHASE_360_DEG_TO_RAD_INT; 527 + *val2 = PHASE_360_DEG_TO_RAD_MICRO; 528 + } 529 + 530 + return IIO_VAL_INT_PLUS_MICRO; 531 + } 532 + 533 + static int ad2s1210_set_phase_lock_range(struct ad2s1210_state *st, 534 + int val, int val2) 535 + { 536 + int deg; 537 + 538 + /* convert radians to degrees - only two allowable values */ 539 + if (val == PHASE_44_DEG_TO_RAD_INT && val2 == PHASE_44_DEG_TO_RAD_MICRO) 540 + deg = 44; 541 + else if (val == PHASE_360_DEG_TO_RAD_INT && 542 + val2 == PHASE_360_DEG_TO_RAD_MICRO) 543 + deg = 360; 544 + else 545 + return -EINVAL; 546 + 547 + guard(mutex)(&st->lock); 548 + return regmap_update_bits(st->regmap, AD2S1210_REG_CONTROL, 549 + AD2S1210_PHASE_LOCK_RANGE_44, 550 + deg == 44 ? AD2S1210_PHASE_LOCK_RANGE_44 : 0); 551 + } 552 + 553 + /* map resolution to microradians/LSB for LOT registers */ 554 + static const int ad2s1210_lot_threshold_urad_per_lsb[] = { 555 + 6184, /* 10-bit: ~0.35 deg/LSB, 45 deg max */ 556 + 2473, /* 12-bit: ~0.14 deg/LSB, 18 deg max */ 557 + 1237, /* 14-bit: ~0.07 deg/LSB, 9 deg max */ 558 + 1237, /* 16-bit: same as 14-bit */ 559 + }; 560 + 561 + static int ad2s1210_get_voltage_threshold(struct ad2s1210_state *st, 562 + unsigned int reg, int *val) 563 + { 564 + unsigned int reg_val; 565 + int ret; 566 + 567 + guard(mutex)(&st->lock); 568 + ret = regmap_read(st->regmap, reg, &reg_val); 569 + if (ret < 0) 570 + return ret; 571 + 572 + *val = reg_val * THRESHOLD_MILLIVOLT_PER_LSB; 573 + return IIO_VAL_INT; 574 + } 575 + 576 + static int ad2s1210_set_voltage_threshold(struct ad2s1210_state *st, 577 + unsigned int reg, int val) 578 + { 579 + unsigned int reg_val; 580 + 581 + reg_val = val / THRESHOLD_MILLIVOLT_PER_LSB; 582 + 583 + guard(mutex)(&st->lock); 584 + return regmap_write(st->regmap, reg, reg_val); 585 + } 586 + 587 + static int ad2s1210_get_lot_high_threshold(struct ad2s1210_state *st, 588 + int *val, int *val2) 589 + { 590 + unsigned int reg_val; 591 + int ret; 592 + 593 + guard(mutex)(&st->lock); 594 + ret = regmap_read(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, &reg_val); 595 + if (ret < 0) 596 + return ret; 597 + 598 + *val = 0; 599 + *val2 = reg_val * ad2s1210_lot_threshold_urad_per_lsb[st->resolution]; 600 + return IIO_VAL_INT_PLUS_MICRO; 601 + } 602 + 603 + static int ad2s1210_set_lot_high_threshold(struct ad2s1210_state *st, 604 + int val, int val2) 605 + { 606 + unsigned int high_reg_val, low_reg_val, hysteresis; 607 + int ret; 608 + 609 + /* all valid values are between 0 and pi/4 radians */ 610 + if (val != 0) 611 + return -EINVAL; 612 + 613 + guard(mutex)(&st->lock); 614 + /* 615 + * We need to read both high and low registers first so we can preserve 616 + * the hysteresis. 617 + */ 618 + ret = regmap_read(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, &high_reg_val); 619 + if (ret < 0) 620 + return ret; 621 + 622 + ret = regmap_read(st->regmap, AD2S1210_REG_LOT_LOW_THRD, &low_reg_val); 623 + if (ret < 0) 624 + return ret; 625 + 626 + hysteresis = high_reg_val - low_reg_val; 627 + high_reg_val = val2 / ad2s1210_lot_threshold_urad_per_lsb[st->resolution]; 628 + low_reg_val = high_reg_val - hysteresis; 629 + 630 + ret = regmap_write(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, high_reg_val); 631 + if (ret < 0) 632 + return ret; 633 + 634 + return regmap_write(st->regmap, AD2S1210_REG_LOT_LOW_THRD, low_reg_val); 635 + } 636 + 637 + static int ad2s1210_get_lot_low_threshold(struct ad2s1210_state *st, 638 + int *val, int *val2) 639 + { 640 + unsigned int high_reg_val, low_reg_val; 641 + int ret; 642 + 643 + guard(mutex)(&st->lock); 644 + 645 + ret = regmap_read(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, &high_reg_val); 646 + if (ret < 0) 647 + return ret; 648 + 649 + ret = regmap_read(st->regmap, AD2S1210_REG_LOT_LOW_THRD, &low_reg_val); 650 + if (ret < 0) 651 + return ret; 652 + 653 + /* sysfs value is hysteresis rather than actual low value */ 654 + *val = 0; 655 + *val2 = (high_reg_val - low_reg_val) * 656 + ad2s1210_lot_threshold_urad_per_lsb[st->resolution]; 657 + return IIO_VAL_INT_PLUS_MICRO; 658 + } 659 + 660 + static int ad2s1210_set_lot_low_threshold(struct ad2s1210_state *st, 661 + int val, int val2) 662 + { 663 + unsigned int reg_val, hysteresis; 664 + int ret; 665 + 666 + /* all valid values are between 0 and pi/4 radians */ 667 + if (val != 0) 668 + return -EINVAL; 669 + 670 + hysteresis = val2 / ad2s1210_lot_threshold_urad_per_lsb[st->resolution]; 671 + 672 + guard(mutex)(&st->lock); 673 + 674 + ret = regmap_read(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, &reg_val); 675 + if (ret < 0) 676 + return ret; 677 + 678 + return regmap_write(st->regmap, AD2S1210_REG_LOT_LOW_THRD, 679 + reg_val - hysteresis); 680 + } 681 + 682 + static int ad2s1210_get_excitation_frequency(struct ad2s1210_state *st, int *val) 683 + { 684 + unsigned int reg_val; 685 + int ret; 686 + 687 + guard(mutex)(&st->lock); 688 + 689 + ret = regmap_read(st->regmap, AD2S1210_REG_EXCIT_FREQ, &reg_val); 690 + if (ret < 0) 691 + return ret; 692 + 693 + *val = reg_val * st->clkin_hz / (1 << 15); 694 + return IIO_VAL_INT; 695 + } 696 + 697 + static int ad2s1210_set_excitation_frequency(struct ad2s1210_state *st, int val) 698 + { 699 + if (val < AD2S1210_MIN_EXCIT || val > AD2S1210_MAX_EXCIT) 700 + return -EINVAL; 701 + 702 + guard(mutex)(&st->lock); 703 + return ad2s1210_reinit_excitation_frequency(st, val); 704 + } 705 + 706 + static const int ad2s1210_velocity_scale[] = { 707 + 17089132, /* 8.192MHz / (2*pi * 2500 / 2^15) */ 708 + 42722830, /* 8.192MHz / (2*pi * 1000 / 2^15) */ 709 + 85445659, /* 8.192MHz / (2*pi * 500 / 2^15) */ 710 + 341782638, /* 8.192MHz / (2*pi * 125 / 2^15) */ 711 + }; 712 + 713 + static int ad2s1210_read_raw(struct iio_dev *indio_dev, 714 + struct iio_chan_spec const *chan, 715 + int *val, 716 + int *val2, 717 + long mask) 718 + { 719 + struct ad2s1210_state *st = iio_priv(indio_dev); 720 + 721 + switch (mask) { 722 + case IIO_CHAN_INFO_RAW: 723 + return ad2s1210_single_conversion(indio_dev, chan, val); 724 + case IIO_CHAN_INFO_SCALE: 725 + switch (chan->type) { 726 + case IIO_ANGL: 727 + /* approx 0.3 arc min converted to radians */ 728 + *val = 0; 729 + *val2 = 95874; 730 + return IIO_VAL_INT_PLUS_NANO; 731 + case IIO_ANGL_VEL: 732 + *val = st->clkin_hz; 733 + *val2 = ad2s1210_velocity_scale[st->resolution]; 734 + return IIO_VAL_FRACTIONAL; 735 + default: 736 + return -EINVAL; 737 + } 738 + case IIO_CHAN_INFO_FREQUENCY: 739 + switch (chan->type) { 740 + case IIO_ALTVOLTAGE: 741 + return ad2s1210_get_excitation_frequency(st, val); 742 + default: 743 + return -EINVAL; 744 + } 745 + case IIO_CHAN_INFO_HYSTERESIS: 746 + switch (chan->type) { 747 + case IIO_ANGL: 748 + return ad2s1210_get_hysteresis(st, val); 749 + default: 750 + return -EINVAL; 751 + } 752 + default: 753 + return -EINVAL; 754 + } 755 + } 756 + 757 + static int ad2s1210_read_avail(struct iio_dev *indio_dev, 758 + struct iio_chan_spec const *chan, 759 + const int **vals, int *type, 760 + int *length, long mask) 761 + { 762 + static const int excitation_frequency_available[] = { 763 + AD2S1210_MIN_EXCIT, 764 + 250, /* step */ 765 + AD2S1210_MAX_EXCIT, 766 + }; 767 + 768 + struct ad2s1210_state *st = iio_priv(indio_dev); 769 + 770 + switch (mask) { 771 + case IIO_CHAN_INFO_FREQUENCY: 772 + switch (chan->type) { 773 + case IIO_ALTVOLTAGE: 774 + *type = IIO_VAL_INT; 775 + *vals = excitation_frequency_available; 776 + return IIO_AVAIL_RANGE; 777 + default: 778 + return -EINVAL; 779 + } 780 + case IIO_CHAN_INFO_HYSTERESIS: 781 + switch (chan->type) { 782 + case IIO_ANGL: 783 + *vals = st->hysteresis_available; 784 + *type = IIO_VAL_INT; 785 + *length = ARRAY_SIZE(st->hysteresis_available); 786 + return IIO_AVAIL_LIST; 787 + default: 788 + return -EINVAL; 789 + } 790 + default: 791 + return -EINVAL; 792 + } 793 + } 794 + 795 + static int ad2s1210_write_raw(struct iio_dev *indio_dev, 796 + struct iio_chan_spec const *chan, 797 + int val, int val2, long mask) 798 + { 799 + struct ad2s1210_state *st = iio_priv(indio_dev); 800 + 801 + switch (mask) { 802 + case IIO_CHAN_INFO_FREQUENCY: 803 + switch (chan->type) { 804 + case IIO_ALTVOLTAGE: 805 + return ad2s1210_set_excitation_frequency(st, val); 806 + default: 807 + return -EINVAL; 808 + } 809 + case IIO_CHAN_INFO_HYSTERESIS: 810 + switch (chan->type) { 811 + case IIO_ANGL: 812 + return ad2s1210_set_hysteresis(st, val); 813 + default: 814 + return -EINVAL; 815 + } 816 + default: 817 + return -EINVAL; 818 + } 819 + } 820 + 821 + static const struct iio_event_spec ad2s1210_position_event_spec[] = { 822 + { 823 + /* Tracking error exceeds LOT threshold fault. */ 824 + .type = IIO_EV_TYPE_THRESH, 825 + .dir = IIO_EV_DIR_RISING, 826 + .mask_separate = 827 + /* Loss of tracking high threshold. */ 828 + BIT(IIO_EV_INFO_VALUE) | 829 + /* Loss of tracking low threshold. */ 830 + BIT(IIO_EV_INFO_HYSTERESIS), 831 + }, 832 + }; 833 + 834 + static const struct iio_event_spec ad2s1210_velocity_event_spec[] = { 835 + { 836 + /* Velocity exceeds maximum tracking rate fault. */ 837 + .type = IIO_EV_TYPE_MAG, 838 + .dir = IIO_EV_DIR_RISING, 839 + }, 840 + }; 841 + 842 + static const struct iio_event_spec ad2s1210_phase_event_spec[] = { 843 + { 844 + /* Phase error fault. */ 845 + .type = IIO_EV_TYPE_MAG, 846 + .dir = IIO_EV_DIR_RISING, 847 + /* Phase lock range. */ 848 + .mask_separate = BIT(IIO_EV_INFO_VALUE), 849 + }, 850 + }; 851 + 852 + static const struct iio_event_spec ad2s1210_monitor_signal_event_spec[] = { 853 + { 854 + /* Sine/cosine below LOS threshold fault. */ 855 + .type = IIO_EV_TYPE_THRESH, 856 + .dir = IIO_EV_DIR_FALLING, 857 + /* Loss of signal threshold. */ 858 + .mask_separate = BIT(IIO_EV_INFO_VALUE), 859 + }, 860 + { 861 + /* Sine/cosine DOS overrange fault.*/ 862 + .type = IIO_EV_TYPE_THRESH, 863 + .dir = IIO_EV_DIR_RISING, 864 + /* Degredation of signal overrange threshold. */ 865 + .mask_separate = BIT(IIO_EV_INFO_VALUE), 866 + }, 867 + { 868 + /* Sine/cosine DOS mismatch fault.*/ 869 + .type = IIO_EV_TYPE_MAG, 870 + .dir = IIO_EV_DIR_RISING, 871 + .mask_separate = BIT(IIO_EV_INFO_VALUE), 872 + }, 873 + }; 874 + 875 + static const struct iio_event_spec ad2s1210_sin_cos_event_spec[] = { 876 + { 877 + /* Sine/cosine clipping fault. */ 878 + .type = IIO_EV_TYPE_MAG, 879 + .dir = IIO_EV_DIR_EITHER, 880 + }, 881 + }; 882 + 883 + static const struct iio_chan_spec ad2s1210_channels[] = { 884 + { 885 + .type = IIO_ANGL, 886 + .indexed = 1, 887 + .channel = 0, 888 + .scan_index = 0, 889 + .scan_type = { 890 + .sign = 'u', 891 + .realbits = 16, 892 + .storagebits = 16, 893 + .endianness = IIO_BE, 894 + }, 895 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 896 + BIT(IIO_CHAN_INFO_SCALE) | 897 + BIT(IIO_CHAN_INFO_HYSTERESIS), 898 + .info_mask_separate_available = 899 + BIT(IIO_CHAN_INFO_HYSTERESIS), 900 + }, { 901 + .type = IIO_ANGL_VEL, 902 + .indexed = 1, 903 + .channel = 0, 904 + .scan_index = 1, 905 + .scan_type = { 906 + .sign = 's', 907 + .realbits = 16, 908 + .storagebits = 16, 909 + .endianness = IIO_BE, 910 + }, 911 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 912 + BIT(IIO_CHAN_INFO_SCALE), 913 + .event_spec = ad2s1210_velocity_event_spec, 914 + .num_event_specs = ARRAY_SIZE(ad2s1210_velocity_event_spec), 915 + }, 916 + IIO_CHAN_SOFT_TIMESTAMP(2), 917 + { 918 + /* used to configure LOT thresholds and get tracking error */ 919 + .type = IIO_ANGL, 920 + .indexed = 1, 921 + .channel = 1, 922 + .scan_index = -1, 923 + .event_spec = ad2s1210_position_event_spec, 924 + .num_event_specs = ARRAY_SIZE(ad2s1210_position_event_spec), 925 + }, 926 + { 927 + /* used to configure phase lock range and get phase lock error */ 928 + .type = IIO_PHASE, 929 + .indexed = 1, 930 + .channel = 0, 931 + .scan_index = -1, 932 + .event_spec = ad2s1210_phase_event_spec, 933 + .num_event_specs = ARRAY_SIZE(ad2s1210_phase_event_spec), 934 + }, { 935 + /* excitation frequency output */ 936 + .type = IIO_ALTVOLTAGE, 937 + .indexed = 1, 938 + .channel = 0, 939 + .output = 1, 940 + .scan_index = -1, 941 + .info_mask_separate = BIT(IIO_CHAN_INFO_FREQUENCY), 942 + .info_mask_separate_available = BIT(IIO_CHAN_INFO_FREQUENCY), 943 + }, { 944 + /* monitor signal */ 945 + .type = IIO_ALTVOLTAGE, 946 + .indexed = 1, 947 + .channel = 0, 948 + .scan_index = -1, 949 + .event_spec = ad2s1210_monitor_signal_event_spec, 950 + .num_event_specs = ARRAY_SIZE(ad2s1210_monitor_signal_event_spec), 951 + }, { 952 + /* sine input */ 953 + .type = IIO_ALTVOLTAGE, 954 + .indexed = 1, 955 + .channel = 1, 956 + .scan_index = -1, 957 + .event_spec = ad2s1210_sin_cos_event_spec, 958 + .num_event_specs = ARRAY_SIZE(ad2s1210_sin_cos_event_spec), 959 + }, { 960 + /* cosine input */ 961 + .type = IIO_ALTVOLTAGE, 962 + .indexed = 1, 963 + .channel = 2, 964 + .scan_index = -1, 965 + .event_spec = ad2s1210_sin_cos_event_spec, 966 + .num_event_specs = ARRAY_SIZE(ad2s1210_sin_cos_event_spec), 967 + }, 968 + }; 969 + 970 + static ssize_t event_attr_voltage_reg_show(struct device *dev, 971 + struct device_attribute *attr, 972 + char *buf) 973 + { 974 + struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 975 + struct iio_dev_attr *iattr = to_iio_dev_attr(attr); 976 + unsigned int value; 977 + int ret; 978 + 979 + guard(mutex)(&st->lock); 980 + ret = regmap_read(st->regmap, iattr->address, &value); 981 + if (ret < 0) 982 + return ret; 983 + 984 + return sprintf(buf, "%d\n", value * THRESHOLD_MILLIVOLT_PER_LSB); 985 + } 986 + 987 + static ssize_t event_attr_voltage_reg_store(struct device *dev, 988 + struct device_attribute *attr, 989 + const char *buf, size_t len) 990 + { 991 + struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 992 + struct iio_dev_attr *iattr = to_iio_dev_attr(attr); 993 + u16 data; 994 + int ret; 995 + 996 + ret = kstrtou16(buf, 10, &data); 997 + if (ret) 998 + return -EINVAL; 999 + 1000 + guard(mutex)(&st->lock); 1001 + ret = regmap_write(st->regmap, iattr->address, 1002 + data / THRESHOLD_MILLIVOLT_PER_LSB); 1003 + if (ret < 0) 1004 + return ret; 1005 + 1006 + return len; 1007 + } 1008 + 1009 + static ssize_t 1010 + in_angl1_thresh_rising_value_available_show(struct device *dev, 1011 + struct device_attribute *attr, 1012 + char *buf) 1013 + { 1014 + struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 1015 + int step = ad2s1210_lot_threshold_urad_per_lsb[st->resolution]; 1016 + 1017 + return sysfs_emit(buf, "[0 0.%06d 0.%06d]\n", step, step * 0x7F); 1018 + } 1019 + 1020 + static ssize_t 1021 + in_angl1_thresh_rising_hysteresis_available_show(struct device *dev, 1022 + struct device_attribute *attr, 1023 + char *buf) 1024 + { 1025 + struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 1026 + int step = ad2s1210_lot_threshold_urad_per_lsb[st->resolution]; 1027 + 1028 + return sysfs_emit(buf, "[0 0.%06d 0.%06d]\n", step, step * 0x7F); 1029 + } 1030 + 1031 + static IIO_CONST_ATTR(in_phase0_mag_rising_value_available, 1032 + __stringify(PHASE_44_DEG_TO_RAD_INT) "." 1033 + __stringify(PHASE_44_DEG_TO_RAD_MICRO) " " 1034 + __stringify(PHASE_360_DEG_TO_RAD_INT) "." 1035 + __stringify(PHASE_360_DEG_TO_RAD_MICRO)); 1036 + static IIO_CONST_ATTR(in_altvoltage0_thresh_falling_value_available, 1037 + THRESHOLD_RANGE_STR); 1038 + static IIO_CONST_ATTR(in_altvoltage0_thresh_rising_value_available, 1039 + THRESHOLD_RANGE_STR); 1040 + static IIO_CONST_ATTR(in_altvoltage0_mag_rising_value_available, 1041 + THRESHOLD_RANGE_STR); 1042 + static IIO_DEVICE_ATTR(in_altvoltage0_mag_rising_reset_max, 0644, 1043 + event_attr_voltage_reg_show, event_attr_voltage_reg_store, 1044 + AD2S1210_REG_DOS_RST_MAX_THRD); 1045 + static IIO_CONST_ATTR(in_altvoltage0_mag_rising_reset_max_available, THRESHOLD_RANGE_STR); 1046 + static IIO_DEVICE_ATTR(in_altvoltage0_mag_rising_reset_min, 0644, 1047 + event_attr_voltage_reg_show, event_attr_voltage_reg_store, 1048 + AD2S1210_REG_DOS_RST_MIN_THRD); 1049 + static IIO_CONST_ATTR(in_altvoltage0_mag_rising_reset_min_available, THRESHOLD_RANGE_STR); 1050 + static IIO_DEVICE_ATTR_RO(in_angl1_thresh_rising_value_available, 0); 1051 + static IIO_DEVICE_ATTR_RO(in_angl1_thresh_rising_hysteresis_available, 0); 1052 + 1053 + static struct attribute *ad2s1210_event_attributes[] = { 1054 + &iio_const_attr_in_phase0_mag_rising_value_available.dev_attr.attr, 1055 + &iio_const_attr_in_altvoltage0_thresh_falling_value_available.dev_attr.attr, 1056 + &iio_const_attr_in_altvoltage0_thresh_rising_value_available.dev_attr.attr, 1057 + &iio_const_attr_in_altvoltage0_mag_rising_value_available.dev_attr.attr, 1058 + &iio_dev_attr_in_altvoltage0_mag_rising_reset_max.dev_attr.attr, 1059 + &iio_const_attr_in_altvoltage0_mag_rising_reset_max_available.dev_attr.attr, 1060 + &iio_dev_attr_in_altvoltage0_mag_rising_reset_min.dev_attr.attr, 1061 + &iio_const_attr_in_altvoltage0_mag_rising_reset_min_available.dev_attr.attr, 1062 + &iio_dev_attr_in_angl1_thresh_rising_value_available.dev_attr.attr, 1063 + &iio_dev_attr_in_angl1_thresh_rising_hysteresis_available.dev_attr.attr, 1064 + NULL, 1065 + }; 1066 + 1067 + static const struct attribute_group ad2s1210_event_attribute_group = { 1068 + .attrs = ad2s1210_event_attributes, 1069 + }; 1070 + 1071 + static int ad2s1210_initial(struct ad2s1210_state *st) 1072 + { 1073 + unsigned int data; 1074 + int ret; 1075 + 1076 + guard(mutex)(&st->lock); 1077 + 1078 + /* Use default config register value plus resolution from devicetree. */ 1079 + data = FIELD_PREP(AD2S1210_PHASE_LOCK_RANGE_44, 1); 1080 + data |= FIELD_PREP(AD2S1210_ENABLE_HYSTERESIS, 1); 1081 + data |= FIELD_PREP(AD2S1210_SET_ENRES, 0x3); 1082 + data |= FIELD_PREP(AD2S1210_SET_RES, st->resolution); 1083 + 1084 + ret = regmap_write(st->regmap, AD2S1210_REG_CONTROL, data); 1085 + if (ret < 0) 1086 + return ret; 1087 + 1088 + return ad2s1210_reinit_excitation_frequency(st, AD2S1210_DEF_EXCIT); 1089 + } 1090 + 1091 + static int ad2s1210_read_label(struct iio_dev *indio_dev, 1092 + struct iio_chan_spec const *chan, 1093 + char *label) 1094 + { 1095 + if (chan->type == IIO_ANGL) { 1096 + if (chan->channel == 0) 1097 + return sprintf(label, "position\n"); 1098 + if (chan->channel == 1) 1099 + return sprintf(label, "tracking error\n"); 1100 + } 1101 + if (chan->type == IIO_ANGL_VEL) 1102 + return sprintf(label, "velocity\n"); 1103 + if (chan->type == IIO_PHASE) 1104 + return sprintf(label, "synthetic reference\n"); 1105 + if (chan->type == IIO_ALTVOLTAGE) { 1106 + if (chan->output) 1107 + return sprintf(label, "excitation\n"); 1108 + if (chan->channel == 0) 1109 + return sprintf(label, "monitor signal\n"); 1110 + if (chan->channel == 1) 1111 + return sprintf(label, "cosine\n"); 1112 + if (chan->channel == 2) 1113 + return sprintf(label, "sine\n"); 1114 + } 1115 + 1116 + return -EINVAL; 1117 + } 1118 + 1119 + static int ad2s1210_read_event_value(struct iio_dev *indio_dev, 1120 + const struct iio_chan_spec *chan, 1121 + enum iio_event_type type, 1122 + enum iio_event_direction dir, 1123 + enum iio_event_info info, 1124 + int *val, int *val2) 1125 + { 1126 + struct ad2s1210_state *st = iio_priv(indio_dev); 1127 + 1128 + switch (chan->type) { 1129 + case IIO_ANGL: 1130 + switch (info) { 1131 + case IIO_EV_INFO_VALUE: 1132 + return ad2s1210_get_lot_high_threshold(st, val, val2); 1133 + case IIO_EV_INFO_HYSTERESIS: 1134 + return ad2s1210_get_lot_low_threshold(st, val, val2); 1135 + default: 1136 + return -EINVAL; 1137 + } 1138 + case IIO_ALTVOLTAGE: 1139 + if (chan->output) 1140 + return -EINVAL; 1141 + if (type == IIO_EV_TYPE_THRESH && dir == IIO_EV_DIR_FALLING) 1142 + return ad2s1210_get_voltage_threshold(st, 1143 + AD2S1210_REG_LOS_THRD, val); 1144 + if (type == IIO_EV_TYPE_THRESH && dir == IIO_EV_DIR_RISING) 1145 + return ad2s1210_get_voltage_threshold(st, 1146 + AD2S1210_REG_DOS_OVR_THRD, val); 1147 + if (type == IIO_EV_TYPE_MAG) 1148 + return ad2s1210_get_voltage_threshold(st, 1149 + AD2S1210_REG_DOS_MIS_THRD, val); 1150 + return -EINVAL; 1151 + case IIO_PHASE: 1152 + return ad2s1210_get_phase_lock_range(st, val, val2); 1153 + default: 1154 + return -EINVAL; 1155 + } 1156 + } 1157 + 1158 + static int ad2s1210_write_event_value(struct iio_dev *indio_dev, 1159 + const struct iio_chan_spec *chan, 1160 + enum iio_event_type type, 1161 + enum iio_event_direction dir, 1162 + enum iio_event_info info, 1163 + int val, int val2) 1164 + { 1165 + struct ad2s1210_state *st = iio_priv(indio_dev); 1166 + 1167 + switch (chan->type) { 1168 + case IIO_ANGL: 1169 + switch (info) { 1170 + case IIO_EV_INFO_VALUE: 1171 + return ad2s1210_set_lot_high_threshold(st, val, val2); 1172 + case IIO_EV_INFO_HYSTERESIS: 1173 + return ad2s1210_set_lot_low_threshold(st, val, val2); 1174 + default: 1175 + return -EINVAL; 1176 + } 1177 + case IIO_ALTVOLTAGE: 1178 + if (chan->output) 1179 + return -EINVAL; 1180 + if (type == IIO_EV_TYPE_THRESH && dir == IIO_EV_DIR_FALLING) 1181 + return ad2s1210_set_voltage_threshold(st, 1182 + AD2S1210_REG_LOS_THRD, val); 1183 + if (type == IIO_EV_TYPE_THRESH && dir == IIO_EV_DIR_RISING) 1184 + return ad2s1210_set_voltage_threshold(st, 1185 + AD2S1210_REG_DOS_OVR_THRD, val); 1186 + if (type == IIO_EV_TYPE_MAG) 1187 + return ad2s1210_set_voltage_threshold(st, 1188 + AD2S1210_REG_DOS_MIS_THRD, val); 1189 + return -EINVAL; 1190 + case IIO_PHASE: 1191 + return ad2s1210_set_phase_lock_range(st, val, val2); 1192 + default: 1193 + return -EINVAL; 1194 + } 1195 + } 1196 + 1197 + static int ad2s1210_read_event_label(struct iio_dev *indio_dev, 1198 + struct iio_chan_spec const *chan, 1199 + enum iio_event_type type, 1200 + enum iio_event_direction dir, 1201 + char *label) 1202 + { 1203 + if (chan->type == IIO_ANGL) 1204 + return sprintf(label, "LOT\n"); 1205 + if (chan->type == IIO_ANGL_VEL) 1206 + return sprintf(label, "max tracking rate\n"); 1207 + if (chan->type == IIO_PHASE) 1208 + return sprintf(label, "phase lock\n"); 1209 + if (chan->type == IIO_ALTVOLTAGE) { 1210 + if (chan->channel == 0) { 1211 + if (type == IIO_EV_TYPE_THRESH && 1212 + dir == IIO_EV_DIR_FALLING) 1213 + return sprintf(label, "LOS\n"); 1214 + if (type == IIO_EV_TYPE_THRESH && 1215 + dir == IIO_EV_DIR_RISING) 1216 + return sprintf(label, "DOS overrange\n"); 1217 + if (type == IIO_EV_TYPE_MAG) 1218 + return sprintf(label, "DOS mismatch\n"); 1219 + } 1220 + if (chan->channel == 1 || chan->channel == 2) 1221 + return sprintf(label, "clipped\n"); 1222 + } 1223 + 1224 + return -EINVAL; 1225 + } 1226 + 1227 + static int ad2s1210_debugfs_reg_access(struct iio_dev *indio_dev, 1228 + unsigned int reg, unsigned int writeval, 1229 + unsigned int *readval) 1230 + { 1231 + struct ad2s1210_state *st = iio_priv(indio_dev); 1232 + 1233 + guard(mutex)(&st->lock); 1234 + 1235 + if (readval) 1236 + return regmap_read(st->regmap, reg, readval); 1237 + 1238 + return regmap_write(st->regmap, reg, writeval); 1239 + } 1240 + 1241 + static irqreturn_t ad2s1210_trigger_handler(int irq, void *p) 1242 + { 1243 + struct iio_poll_func *pf = p; 1244 + struct iio_dev *indio_dev = pf->indio_dev; 1245 + struct ad2s1210_state *st = iio_priv(indio_dev); 1246 + size_t chan = 0; 1247 + int ret; 1248 + 1249 + guard(mutex)(&st->lock); 1250 + 1251 + memset(&st->scan, 0, sizeof(st->scan)); 1252 + ad2s1210_toggle_sample_line(st); 1253 + 1254 + if (test_bit(0, indio_dev->active_scan_mask)) { 1255 + ret = ad2s1210_set_mode(st, MOD_POS); 1256 + if (ret < 0) 1257 + goto error_ret; 1258 + 1259 + ret = spi_read(st->sdev, &st->sample, 3); 1260 + if (ret < 0) 1261 + goto error_ret; 1262 + 1263 + memcpy(&st->scan.chan[chan++], &st->sample.raw, 2); 1264 + } 1265 + 1266 + if (test_bit(1, indio_dev->active_scan_mask)) { 1267 + ret = ad2s1210_set_mode(st, MOD_VEL); 1268 + if (ret < 0) 1269 + goto error_ret; 1270 + 1271 + ret = spi_read(st->sdev, &st->sample, 3); 1272 + if (ret < 0) 1273 + goto error_ret; 1274 + 1275 + memcpy(&st->scan.chan[chan++], &st->sample.raw, 2); 1276 + } 1277 + 1278 + ad2s1210_push_events(indio_dev, st->sample.fault, pf->timestamp); 1279 + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan, pf->timestamp); 1280 + 1281 + error_ret: 1282 + iio_trigger_notify_done(indio_dev->trig); 1283 + 1284 + return IRQ_HANDLED; 1285 + } 1286 + 1287 + static const struct iio_info ad2s1210_info = { 1288 + .event_attrs = &ad2s1210_event_attribute_group, 1289 + .read_raw = ad2s1210_read_raw, 1290 + .read_avail = ad2s1210_read_avail, 1291 + .write_raw = ad2s1210_write_raw, 1292 + .read_label = ad2s1210_read_label, 1293 + .read_event_value = ad2s1210_read_event_value, 1294 + .write_event_value = ad2s1210_write_event_value, 1295 + .read_event_label = ad2s1210_read_event_label, 1296 + .debugfs_reg_access = &ad2s1210_debugfs_reg_access, 1297 + }; 1298 + 1299 + static int ad2s1210_setup_properties(struct ad2s1210_state *st) 1300 + { 1301 + struct device *dev = &st->sdev->dev; 1302 + u32 val; 1303 + int ret; 1304 + 1305 + ret = device_property_read_u32(dev, "assigned-resolution-bits", &val); 1306 + if (ret < 0) 1307 + return dev_err_probe(dev, ret, 1308 + "failed to read assigned-resolution-bits property\n"); 1309 + 1310 + if (val < 10 || val > 16) 1311 + return dev_err_probe(dev, -EINVAL, 1312 + "resolution out of range: %u\n", val); 1313 + 1314 + st->resolution = (val - 10) >> 1; 1315 + /* 1316 + * These are values that correlate to the hysteresis bit in the Control 1317 + * register. 0 = disabled, 1 = enabled. When enabled, the actual 1318 + * hysteresis is +/- 1 LSB of the raw position value. Which bit is the 1319 + * LSB depends on the specified resolution. 1320 + */ 1321 + st->hysteresis_available[0] = 0; 1322 + st->hysteresis_available[1] = 1 << (2 * (AD2S1210_RES_16 - 1323 + st->resolution)); 1324 + 1325 + return 0; 1326 + } 1327 + 1328 + static int ad2s1210_setup_clocks(struct ad2s1210_state *st) 1329 + { 1330 + struct device *dev = &st->sdev->dev; 1331 + struct clk *clk; 1332 + 1333 + clk = devm_clk_get_enabled(dev, NULL); 1334 + if (IS_ERR(clk)) 1335 + return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); 1336 + 1337 + st->clkin_hz = clk_get_rate(clk); 1338 + if (st->clkin_hz < AD2S1210_MIN_CLKIN || st->clkin_hz > AD2S1210_MAX_CLKIN) 1339 + return dev_err_probe(dev, -EINVAL, 1340 + "clock frequency out of range: %lu\n", 1341 + st->clkin_hz); 1342 + 1343 + return 0; 1344 + } 1345 + 1346 + static int ad2s1210_setup_gpios(struct ad2s1210_state *st) 1347 + { 1348 + struct device *dev = &st->sdev->dev; 1349 + struct gpio_descs *resolution_gpios; 1350 + DECLARE_BITMAP(bitmap, 2); 1351 + int ret; 1352 + 1353 + /* should not be sampling on startup */ 1354 + st->sample_gpio = devm_gpiod_get(dev, "sample", GPIOD_OUT_LOW); 1355 + if (IS_ERR(st->sample_gpio)) 1356 + return dev_err_probe(dev, PTR_ERR(st->sample_gpio), 1357 + "failed to request sample GPIO\n"); 1358 + 1359 + /* both pins high means that we start in config mode */ 1360 + st->mode_gpios = devm_gpiod_get_array(dev, "mode", GPIOD_OUT_HIGH); 1361 + if (IS_ERR(st->mode_gpios)) 1362 + return dev_err_probe(dev, PTR_ERR(st->mode_gpios), 1363 + "failed to request mode GPIOs\n"); 1364 + 1365 + if (st->mode_gpios->ndescs != 2) 1366 + return dev_err_probe(dev, -EINVAL, 1367 + "requires exactly 2 mode-gpios\n"); 1368 + 1369 + /* 1370 + * If resolution gpios are provided, they get set to the required 1371 + * resolution, otherwise it is assumed the RES0 and RES1 pins are 1372 + * hard-wired to match the resolution indicated in the devicetree. 1373 + */ 1374 + resolution_gpios = devm_gpiod_get_array_optional(dev, "resolution", 1375 + GPIOD_ASIS); 1376 + if (IS_ERR(resolution_gpios)) 1377 + return dev_err_probe(dev, PTR_ERR(resolution_gpios), 1378 + "failed to request resolution GPIOs\n"); 1379 + 1380 + if (resolution_gpios) { 1381 + if (resolution_gpios->ndescs != 2) 1382 + return dev_err_probe(dev, -EINVAL, 1383 + "requires exactly 2 resolution-gpios\n"); 1384 + 1385 + bitmap[0] = st->resolution; 1386 + 1387 + ret = gpiod_set_array_value(resolution_gpios->ndescs, 1388 + resolution_gpios->desc, 1389 + resolution_gpios->info, 1390 + bitmap); 1391 + if (ret < 0) 1392 + return dev_err_probe(dev, ret, 1393 + "failed to set resolution gpios\n"); 1394 + } 1395 + 1396 + return 0; 1397 + } 1398 + 1399 + static const struct regmap_range ad2s1210_regmap_readable_ranges[] = { 1400 + regmap_reg_range(AD2S1210_REG_POSITION_MSB, AD2S1210_REG_VELOCITY_LSB), 1401 + regmap_reg_range(AD2S1210_REG_LOS_THRD, AD2S1210_REG_LOT_LOW_THRD), 1402 + regmap_reg_range(AD2S1210_REG_EXCIT_FREQ, AD2S1210_REG_CONTROL), 1403 + regmap_reg_range(AD2S1210_REG_FAULT, AD2S1210_REG_FAULT), 1404 + }; 1405 + 1406 + static const struct regmap_access_table ad2s1210_regmap_rd_table = { 1407 + .yes_ranges = ad2s1210_regmap_readable_ranges, 1408 + .n_yes_ranges = ARRAY_SIZE(ad2s1210_regmap_readable_ranges), 1409 + }; 1410 + 1411 + static const struct regmap_range ad2s1210_regmap_writeable_ranges[] = { 1412 + regmap_reg_range(AD2S1210_REG_LOS_THRD, AD2S1210_REG_LOT_LOW_THRD), 1413 + regmap_reg_range(AD2S1210_REG_EXCIT_FREQ, AD2S1210_REG_CONTROL), 1414 + regmap_reg_range(AD2S1210_REG_SOFT_RESET, AD2S1210_REG_SOFT_RESET), 1415 + regmap_reg_range(AD2S1210_REG_FAULT, AD2S1210_REG_FAULT), 1416 + }; 1417 + 1418 + static const struct regmap_access_table ad2s1210_regmap_wr_table = { 1419 + .yes_ranges = ad2s1210_regmap_writeable_ranges, 1420 + .n_yes_ranges = ARRAY_SIZE(ad2s1210_regmap_writeable_ranges), 1421 + }; 1422 + 1423 + static int ad2s1210_setup_regmap(struct ad2s1210_state *st) 1424 + { 1425 + struct device *dev = &st->sdev->dev; 1426 + const struct regmap_config config = { 1427 + .reg_bits = 8, 1428 + .val_bits = 8, 1429 + .disable_locking = true, 1430 + .reg_read = ad2s1210_regmap_reg_read, 1431 + .reg_write = ad2s1210_regmap_reg_write, 1432 + .rd_table = &ad2s1210_regmap_rd_table, 1433 + .wr_table = &ad2s1210_regmap_wr_table, 1434 + .can_sleep = true, 1435 + }; 1436 + 1437 + st->regmap = devm_regmap_init(dev, NULL, st, &config); 1438 + if (IS_ERR(st->regmap)) 1439 + return dev_err_probe(dev, PTR_ERR(st->regmap), 1440 + "failed to allocate register map\n"); 1441 + 1442 + return 0; 1443 + } 1444 + 1445 + static int ad2s1210_probe(struct spi_device *spi) 1446 + { 1447 + struct iio_dev *indio_dev; 1448 + struct ad2s1210_state *st; 1449 + int ret; 1450 + 1451 + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1452 + if (!indio_dev) 1453 + return -ENOMEM; 1454 + st = iio_priv(indio_dev); 1455 + 1456 + mutex_init(&st->lock); 1457 + st->sdev = spi; 1458 + 1459 + ret = ad2s1210_setup_properties(st); 1460 + if (ret < 0) 1461 + return ret; 1462 + 1463 + ret = ad2s1210_setup_clocks(st); 1464 + if (ret < 0) 1465 + return ret; 1466 + 1467 + ret = ad2s1210_setup_gpios(st); 1468 + if (ret < 0) 1469 + return ret; 1470 + 1471 + ret = ad2s1210_setup_regmap(st); 1472 + if (ret < 0) 1473 + return ret; 1474 + 1475 + ret = ad2s1210_initial(st); 1476 + if (ret < 0) 1477 + return ret; 1478 + 1479 + indio_dev->info = &ad2s1210_info; 1480 + indio_dev->modes = INDIO_DIRECT_MODE; 1481 + indio_dev->channels = ad2s1210_channels; 1482 + indio_dev->num_channels = ARRAY_SIZE(ad2s1210_channels); 1483 + indio_dev->name = spi_get_device_id(spi)->name; 1484 + 1485 + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 1486 + &iio_pollfunc_store_time, 1487 + &ad2s1210_trigger_handler, NULL); 1488 + if (ret < 0) 1489 + return dev_err_probe(&spi->dev, ret, 1490 + "iio triggered buffer setup failed\n"); 1491 + 1492 + return devm_iio_device_register(&spi->dev, indio_dev); 1493 + } 1494 + 1495 + static const struct of_device_id ad2s1210_of_match[] = { 1496 + { .compatible = "adi,ad2s1210", }, 1497 + { } 1498 + }; 1499 + MODULE_DEVICE_TABLE(of, ad2s1210_of_match); 1500 + 1501 + static const struct spi_device_id ad2s1210_id[] = { 1502 + { "ad2s1210" }, 1503 + {} 1504 + }; 1505 + MODULE_DEVICE_TABLE(spi, ad2s1210_id); 1506 + 1507 + static struct spi_driver ad2s1210_driver = { 1508 + .driver = { 1509 + .name = "ad2s1210", 1510 + .of_match_table = ad2s1210_of_match, 1511 + }, 1512 + .probe = ad2s1210_probe, 1513 + .id_table = ad2s1210_id, 1514 + }; 1515 + module_spi_driver(ad2s1210_driver); 1516 + 1517 + MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>"); 1518 + MODULE_DESCRIPTION("Analog Devices AD2S1210 Resolver to Digital SPI driver"); 1519 + MODULE_LICENSE("GPL v2");

+2 -4

drivers/iio/temperature/hid-sensor-temperature.c

··· 257 257 } 258 258 259 259 /* Function to deinitialize the processing for usage id */ 260 - static int hid_temperature_remove(struct platform_device *pdev) 260 + static void hid_temperature_remove(struct platform_device *pdev) 261 261 { 262 262 struct hid_sensor_hub_device *hsdev = dev_get_platdata(&pdev->dev); 263 263 struct iio_dev *indio_dev = platform_get_drvdata(pdev); ··· 265 265 266 266 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_TEMPERATURE); 267 267 hid_sensor_remove_trigger(indio_dev, &temp_st->common_attributes); 268 - 269 - return 0; 270 268 } 271 269 272 270 static const struct platform_device_id hid_temperature_ids[] = { ··· 283 285 .pm = &hid_sensor_pm_ops, 284 286 }, 285 287 .probe = hid_temperature_probe, 286 - .remove = hid_temperature_remove, 288 + .remove_new = hid_temperature_remove, 287 289 }; 288 290 module_platform_driver(hid_temperature_platform_driver); 289 291

+1 -1

drivers/iio/temperature/mlx90614.c

··· 600 600 data->client = client; 601 601 mutex_init(&data->lock); 602 602 data->wakeup_gpio = mlx90614_probe_wakeup(client); 603 - data->chip_info = device_get_match_data(&client->dev); 603 + data->chip_info = i2c_get_match_data(client); 604 604 605 605 mlx90614_wakeup(data); 606 606

+44 -50

drivers/iio/temperature/tmp117.c

··· 42 42 s16 calibbias; 43 43 }; 44 44 45 + struct tmp11x_info { 46 + const char *name; 47 + struct iio_chan_spec const *channels; 48 + int num_channels; 49 + }; 50 + 45 51 static int tmp117_read_raw(struct iio_dev *indio_dev, 46 52 struct iio_chan_spec const *channel, int *val, 47 53 int *val2, long mask) ··· 125 119 }, 126 120 }; 127 121 122 + static const struct tmp11x_info tmp116_channels_info = { 123 + .name = "tmp116", 124 + .channels = tmp116_channels, 125 + .num_channels = ARRAY_SIZE(tmp116_channels) 126 + }; 127 + 128 + static const struct tmp11x_info tmp117_channels_info = { 129 + .name = "tmp117", 130 + .channels = tmp117_channels, 131 + .num_channels = ARRAY_SIZE(tmp117_channels) 132 + }; 133 + 128 134 static const struct iio_info tmp117_info = { 129 135 .read_raw = tmp117_read_raw, 130 136 .write_raw = tmp117_write_raw, 131 137 }; 132 138 133 - static int tmp117_identify(struct i2c_client *client) 139 + static int tmp117_probe(struct i2c_client *client) 134 140 { 135 - const struct i2c_device_id *id; 136 - unsigned long match_data; 141 + const struct tmp11x_info *match_data; 142 + struct tmp117_data *data; 143 + struct iio_dev *indio_dev; 137 144 int dev_id; 145 + 146 + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA)) 147 + return -EOPNOTSUPP; 138 148 139 149 dev_id = i2c_smbus_read_word_swapped(client, TMP117_REG_DEVICE_ID); 140 150 if (dev_id < 0) ··· 158 136 159 137 switch (dev_id) { 160 138 case TMP116_DEVICE_ID: 139 + match_data = &tmp116_channels_info; 140 + break; 161 141 case TMP117_DEVICE_ID: 162 - return dev_id; 142 + match_data = &tmp117_channels_info; 143 + break; 144 + default: 145 + dev_info(&client->dev, 146 + "Unknown device id (0x%x), use fallback compatible\n", 147 + dev_id); 148 + match_data = i2c_get_match_data(client); 163 149 } 164 150 165 - dev_info(&client->dev, "Unknown device id (0x%x), use fallback compatible\n", 166 - dev_id); 167 - 168 - match_data = (uintptr_t)device_get_match_data(&client->dev); 169 - if (match_data) 170 - return match_data; 171 - 172 - id = i2c_client_get_device_id(client); 173 - if (id) 174 - return id->driver_data; 175 - 176 - dev_err(&client->dev, "Failed to identify unsupported device\n"); 177 - 178 - return -ENODEV; 179 - } 180 - 181 - static int tmp117_probe(struct i2c_client *client) 182 - { 183 - struct tmp117_data *data; 184 - struct iio_dev *indio_dev; 185 - int ret, dev_id; 186 - 187 - if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA)) 188 - return -EOPNOTSUPP; 189 - 190 - ret = tmp117_identify(client); 191 - if (ret < 0) 192 - return ret; 193 - 194 - dev_id = ret; 151 + if (!match_data) 152 + return dev_err_probe(&client->dev, -ENODEV, 153 + "Failed to identify unsupported device\n"); 195 154 196 155 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 197 156 if (!indio_dev) ··· 184 181 185 182 indio_dev->modes = INDIO_DIRECT_MODE; 186 183 indio_dev->info = &tmp117_info; 184 + indio_dev->channels = match_data->channels; 185 + indio_dev->num_channels = match_data->num_channels; 186 + indio_dev->name = match_data->name; 187 187 188 - switch (dev_id) { 189 - case TMP116_DEVICE_ID: 190 - indio_dev->channels = tmp116_channels; 191 - indio_dev->num_channels = ARRAY_SIZE(tmp116_channels); 192 - indio_dev->name = "tmp116"; 193 - break; 194 - case TMP117_DEVICE_ID: 195 - indio_dev->channels = tmp117_channels; 196 - indio_dev->num_channels = ARRAY_SIZE(tmp117_channels); 197 - indio_dev->name = "tmp117"; 198 - break; 199 - } 200 188 201 189 return devm_iio_device_register(&client->dev, indio_dev); 202 190 } 203 191 204 192 static const struct of_device_id tmp117_of_match[] = { 205 - { .compatible = "ti,tmp116", .data = (void *)TMP116_DEVICE_ID }, 206 - { .compatible = "ti,tmp117", .data = (void *)TMP117_DEVICE_ID }, 193 + { .compatible = "ti,tmp116", .data = &tmp116_channels_info }, 194 + { .compatible = "ti,tmp117", .data = &tmp117_channels_info }, 207 195 { } 208 196 }; 209 197 MODULE_DEVICE_TABLE(of, tmp117_of_match); 210 198 211 199 static const struct i2c_device_id tmp117_id[] = { 212 - { "tmp116", TMP116_DEVICE_ID }, 213 - { "tmp117", TMP117_DEVICE_ID }, 200 + { "tmp116", (kernel_ulong_t)&tmp116_channels_info }, 201 + { "tmp117", (kernel_ulong_t)&tmp117_channels_info }, 214 202 { } 215 203 }; 216 204 MODULE_DEVICE_TABLE(i2c, tmp117_id);

+2 -4

drivers/iio/trigger/iio-trig-interrupt.c

··· 81 81 return ret; 82 82 } 83 83 84 - static int iio_interrupt_trigger_remove(struct platform_device *pdev) 84 + static void iio_interrupt_trigger_remove(struct platform_device *pdev) 85 85 { 86 86 struct iio_trigger *trig; 87 87 struct iio_interrupt_trigger_info *trig_info; ··· 92 92 free_irq(trig_info->irq, trig); 93 93 kfree(trig_info); 94 94 iio_trigger_free(trig); 95 - 96 - return 0; 97 95 } 98 96 99 97 static struct platform_driver iio_interrupt_trigger_driver = { 100 98 .probe = iio_interrupt_trigger_probe, 101 - .remove = iio_interrupt_trigger_remove, 99 + .remove_new = iio_interrupt_trigger_remove, 102 100 .driver = { 103 101 .name = "iio_interrupt_trigger", 104 102 },

+2 -4

drivers/iio/trigger/stm32-timer-trigger.c

··· 809 809 return 0; 810 810 } 811 811 812 - static int stm32_timer_trigger_remove(struct platform_device *pdev) 812 + static void stm32_timer_trigger_remove(struct platform_device *pdev) 813 813 { 814 814 struct stm32_timer_trigger *priv = platform_get_drvdata(pdev); 815 815 u32 val; ··· 824 824 825 825 if (priv->enabled) 826 826 clk_disable(priv->clk); 827 - 828 - return 0; 829 827 } 830 828 831 829 static int stm32_timer_trigger_suspend(struct device *dev) ··· 902 904 903 905 static struct platform_driver stm32_timer_trigger_driver = { 904 906 .probe = stm32_timer_trigger_probe, 905 - .remove = stm32_timer_trigger_remove, 907 + .remove_new = stm32_timer_trigger_remove, 906 908 .driver = { 907 909 .name = "stm32-timer-trigger", 908 910 .of_match_table = stm32_trig_of_match,

-1

drivers/staging/iio/Kconfig

··· 10 10 source "drivers/staging/iio/addac/Kconfig" 11 11 source "drivers/staging/iio/frequency/Kconfig" 12 12 source "drivers/staging/iio/impedance-analyzer/Kconfig" 13 - source "drivers/staging/iio/resolver/Kconfig" 14 13 15 14 endmenu

-1

drivers/staging/iio/Makefile

··· 8 8 obj-y += addac/ 9 9 obj-y += frequency/ 10 10 obj-y += impedance-analyzer/ 11 - obj-y += resolver/

+1 -14

drivers/staging/iio/frequency/ad9832.c

··· 299 299 regulator_disable(reg); 300 300 } 301 301 302 - static void ad9832_clk_disable(void *clk) 303 - { 304 - clk_disable_unprepare(clk); 305 - } 306 - 307 302 static int ad9832_probe(struct spi_device *spi) 308 303 { 309 304 struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev); ··· 345 350 if (ret) 346 351 return ret; 347 352 348 - st->mclk = devm_clk_get(&spi->dev, "mclk"); 353 + st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 349 354 if (IS_ERR(st->mclk)) 350 355 return PTR_ERR(st->mclk); 351 - 352 - ret = clk_prepare_enable(st->mclk); 353 - if (ret < 0) 354 - return ret; 355 - 356 - ret = devm_add_action_or_reset(&spi->dev, ad9832_clk_disable, st->mclk); 357 - if (ret) 358 - return ret; 359 356 360 357 st->spi = spi; 361 358 mutex_init(&st->lock);

+2 -19

drivers/staging/iio/frequency/ad9834.c

··· 394 394 regulator_disable(reg); 395 395 } 396 396 397 - static void ad9834_disable_clk(void *data) 398 - { 399 - struct clk *clk = data; 400 - 401 - clk_disable_unprepare(clk); 402 - } 403 - 404 397 static int ad9834_probe(struct spi_device *spi) 405 398 { 406 399 struct ad9834_state *st; ··· 422 429 } 423 430 st = iio_priv(indio_dev); 424 431 mutex_init(&st->lock); 425 - st->mclk = devm_clk_get(&spi->dev, NULL); 432 + st->mclk = devm_clk_get_enabled(&spi->dev, NULL); 426 433 if (IS_ERR(st->mclk)) { 427 - ret = PTR_ERR(st->mclk); 428 - return ret; 429 - } 430 - 431 - ret = clk_prepare_enable(st->mclk); 432 - if (ret) { 433 434 dev_err(&spi->dev, "Failed to enable master clock\n"); 434 - return ret; 435 + return PTR_ERR(st->mclk); 435 436 } 436 - 437 - ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_clk, st->mclk); 438 - if (ret) 439 - return ret; 440 437 441 438 st->spi = spi; 442 439 st->devid = spi_get_device_id(spi)->driver_data;

+2 -20

drivers/staging/iio/impedance-analyzer/ad5933.c

··· 667 667 regulator_disable(st->reg); 668 668 } 669 669 670 - static void ad5933_clk_disable(void *data) 671 - { 672 - struct ad5933_state *st = data; 673 - 674 - clk_disable_unprepare(st->mclk); 675 - } 676 - 677 670 static int ad5933_probe(struct i2c_client *client) 678 671 { 679 672 const struct i2c_device_id *id = i2c_client_get_device_id(client); ··· 705 712 706 713 st->vref_mv = ret / 1000; 707 714 708 - st->mclk = devm_clk_get(&client->dev, "mclk"); 715 + st->mclk = devm_clk_get_enabled(&client->dev, "mclk"); 709 716 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) 710 717 return PTR_ERR(st->mclk); 711 718 712 - if (!IS_ERR(st->mclk)) { 713 - ret = clk_prepare_enable(st->mclk); 714 - if (ret < 0) 715 - return ret; 716 - 717 - ret = devm_add_action_or_reset(&client->dev, 718 - ad5933_clk_disable, 719 - st); 720 - if (ret) 721 - return ret; 722 - 719 + if (!IS_ERR(st->mclk)) 723 720 ext_clk_hz = clk_get_rate(st->mclk); 724 - } 725 721 726 722 if (ext_clk_hz) { 727 723 st->mclk_hz = ext_clk_hz;

-18

drivers/staging/iio/resolver/Kconfig

··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # Resolver/Synchro drivers 4 - # 5 - menu "Resolver to digital converters" 6 - 7 - config AD2S1210 8 - tristate "Analog Devices ad2s1210 driver" 9 - depends on SPI 10 - depends on GPIOLIB || COMPILE_TEST 11 - help 12 - Say yes here to build support for Analog Devices spi resolver 13 - to digital converters, ad2s1210, provides direct access via sysfs. 14 - 15 - To compile this driver as a module, choose M here: the 16 - module will be called ad2s1210. 17 - 18 - endmenu

-6

drivers/staging/iio/resolver/Makefile

··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # Makefile for Resolver/Synchro drivers 4 - # 5 - 6 - obj-$(CONFIG_AD2S1210) += ad2s1210.o

-716

drivers/staging/iio/resolver/ad2s1210.c

··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * ad2s1210.c support for the ADI Resolver to Digital Converters: AD2S1210 4 - * 5 - * Copyright (c) 2010-2010 Analog Devices Inc. 6 - */ 7 - #include <linux/types.h> 8 - #include <linux/mutex.h> 9 - #include <linux/device.h> 10 - #include <linux/of.h> 11 - #include <linux/spi/spi.h> 12 - #include <linux/slab.h> 13 - #include <linux/sysfs.h> 14 - #include <linux/delay.h> 15 - #include <linux/gpio/consumer.h> 16 - #include <linux/module.h> 17 - 18 - #include <linux/iio/iio.h> 19 - #include <linux/iio/sysfs.h> 20 - 21 - #define DRV_NAME "ad2s1210" 22 - 23 - #define AD2S1210_DEF_CONTROL 0x7E 24 - 25 - #define AD2S1210_MSB_IS_HIGH 0x80 26 - #define AD2S1210_MSB_IS_LOW 0x7F 27 - #define AD2S1210_PHASE_LOCK_RANGE_44 0x20 28 - #define AD2S1210_ENABLE_HYSTERESIS 0x10 29 - #define AD2S1210_SET_ENRES1 0x08 30 - #define AD2S1210_SET_ENRES0 0x04 31 - #define AD2S1210_SET_RES1 0x02 32 - #define AD2S1210_SET_RES0 0x01 33 - 34 - #define AD2S1210_SET_RESOLUTION (AD2S1210_SET_RES1 | AD2S1210_SET_RES0) 35 - 36 - #define AD2S1210_REG_POSITION 0x80 37 - #define AD2S1210_REG_VELOCITY 0x82 38 - #define AD2S1210_REG_LOS_THRD 0x88 39 - #define AD2S1210_REG_DOS_OVR_THRD 0x89 40 - #define AD2S1210_REG_DOS_MIS_THRD 0x8A 41 - #define AD2S1210_REG_DOS_RST_MAX_THRD 0x8B 42 - #define AD2S1210_REG_DOS_RST_MIN_THRD 0x8C 43 - #define AD2S1210_REG_LOT_HIGH_THRD 0x8D 44 - #define AD2S1210_REG_LOT_LOW_THRD 0x8E 45 - #define AD2S1210_REG_EXCIT_FREQ 0x91 46 - #define AD2S1210_REG_CONTROL 0x92 47 - #define AD2S1210_REG_SOFT_RESET 0xF0 48 - #define AD2S1210_REG_FAULT 0xFF 49 - 50 - #define AD2S1210_MIN_CLKIN 6144000 51 - #define AD2S1210_MAX_CLKIN 10240000 52 - #define AD2S1210_MIN_EXCIT 2000 53 - #define AD2S1210_MAX_EXCIT 20000 54 - #define AD2S1210_MIN_FCW 0x4 55 - #define AD2S1210_MAX_FCW 0x50 56 - 57 - #define AD2S1210_DEF_EXCIT 10000 58 - 59 - enum ad2s1210_mode { 60 - MOD_POS = 0, 61 - MOD_VEL, 62 - MOD_CONFIG, 63 - MOD_RESERVED, 64 - }; 65 - 66 - enum ad2s1210_gpios { 67 - AD2S1210_SAMPLE, 68 - AD2S1210_A0, 69 - AD2S1210_A1, 70 - AD2S1210_RES0, 71 - AD2S1210_RES1, 72 - }; 73 - 74 - struct ad2s1210_gpio { 75 - const char *name; 76 - unsigned long flags; 77 - }; 78 - 79 - static const struct ad2s1210_gpio gpios[] = { 80 - [AD2S1210_SAMPLE] = { .name = "adi,sample", .flags = GPIOD_OUT_LOW }, 81 - [AD2S1210_A0] = { .name = "adi,a0", .flags = GPIOD_OUT_LOW }, 82 - [AD2S1210_A1] = { .name = "adi,a1", .flags = GPIOD_OUT_LOW }, 83 - [AD2S1210_RES0] = { .name = "adi,res0", .flags = GPIOD_OUT_LOW }, 84 - [AD2S1210_RES1] = { .name = "adi,res1", .flags = GPIOD_OUT_LOW }, 85 - }; 86 - 87 - static const unsigned int ad2s1210_resolution_value[] = { 10, 12, 14, 16 }; 88 - 89 - struct ad2s1210_state { 90 - struct mutex lock; 91 - struct spi_device *sdev; 92 - struct gpio_desc *gpios[5]; 93 - unsigned int fclkin; 94 - unsigned int fexcit; 95 - bool hysteresis; 96 - u8 resolution; 97 - enum ad2s1210_mode mode; 98 - u8 rx[2] __aligned(IIO_DMA_MINALIGN); 99 - u8 tx[2]; 100 - }; 101 - 102 - static const int ad2s1210_mode_vals[4][2] = { 103 - [MOD_POS] = { 0, 0 }, 104 - [MOD_VEL] = { 0, 1 }, 105 - [MOD_CONFIG] = { 1, 1 }, 106 - }; 107 - 108 - static inline void ad2s1210_set_mode(enum ad2s1210_mode mode, 109 - struct ad2s1210_state *st) 110 - { 111 - gpiod_set_value(st->gpios[AD2S1210_A0], ad2s1210_mode_vals[mode][0]); 112 - gpiod_set_value(st->gpios[AD2S1210_A1], ad2s1210_mode_vals[mode][1]); 113 - st->mode = mode; 114 - } 115 - 116 - /* write 1 bytes (address or data) to the chip */ 117 - static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data) 118 - { 119 - int ret; 120 - 121 - ad2s1210_set_mode(MOD_CONFIG, st); 122 - st->tx[0] = data; 123 - ret = spi_write(st->sdev, st->tx, 1); 124 - if (ret < 0) 125 - return ret; 126 - 127 - return 0; 128 - } 129 - 130 - /* read value from one of the registers */ 131 - static int ad2s1210_config_read(struct ad2s1210_state *st, 132 - unsigned char address) 133 - { 134 - struct spi_transfer xfers[] = { 135 - { 136 - .len = 1, 137 - .rx_buf = &st->rx[0], 138 - .tx_buf = &st->tx[0], 139 - .cs_change = 1, 140 - }, { 141 - .len = 1, 142 - .rx_buf = &st->rx[1], 143 - .tx_buf = &st->tx[1], 144 - }, 145 - }; 146 - int ret = 0; 147 - 148 - ad2s1210_set_mode(MOD_CONFIG, st); 149 - st->tx[0] = address | AD2S1210_MSB_IS_HIGH; 150 - st->tx[1] = AD2S1210_REG_FAULT; 151 - ret = spi_sync_transfer(st->sdev, xfers, 2); 152 - if (ret < 0) 153 - return ret; 154 - 155 - return st->rx[1]; 156 - } 157 - 158 - static inline 159 - int ad2s1210_update_frequency_control_word(struct ad2s1210_state *st) 160 - { 161 - int ret; 162 - unsigned char fcw; 163 - 164 - fcw = (unsigned char)(st->fexcit * (1 << 15) / st->fclkin); 165 - if (fcw < AD2S1210_MIN_FCW || fcw > AD2S1210_MAX_FCW) { 166 - dev_err(&st->sdev->dev, "ad2s1210: FCW out of range\n"); 167 - return -ERANGE; 168 - } 169 - 170 - ret = ad2s1210_config_write(st, AD2S1210_REG_EXCIT_FREQ); 171 - if (ret < 0) 172 - return ret; 173 - 174 - return ad2s1210_config_write(st, fcw); 175 - } 176 - 177 - static const int ad2s1210_res_pins[4][2] = { 178 - { 0, 0 }, {0, 1}, {1, 0}, {1, 1} 179 - }; 180 - 181 - static inline void ad2s1210_set_resolution_pin(struct ad2s1210_state *st) 182 - { 183 - gpiod_set_value(st->gpios[AD2S1210_RES0], 184 - ad2s1210_res_pins[(st->resolution - 10) / 2][0]); 185 - gpiod_set_value(st->gpios[AD2S1210_RES1], 186 - ad2s1210_res_pins[(st->resolution - 10) / 2][1]); 187 - } 188 - 189 - static inline int ad2s1210_soft_reset(struct ad2s1210_state *st) 190 - { 191 - int ret; 192 - 193 - ret = ad2s1210_config_write(st, AD2S1210_REG_SOFT_RESET); 194 - if (ret < 0) 195 - return ret; 196 - 197 - return ad2s1210_config_write(st, 0x0); 198 - } 199 - 200 - static ssize_t ad2s1210_show_fclkin(struct device *dev, 201 - struct device_attribute *attr, 202 - char *buf) 203 - { 204 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 205 - 206 - return sprintf(buf, "%u\n", st->fclkin); 207 - } 208 - 209 - static ssize_t ad2s1210_store_fclkin(struct device *dev, 210 - struct device_attribute *attr, 211 - const char *buf, 212 - size_t len) 213 - { 214 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 215 - unsigned int fclkin; 216 - int ret; 217 - 218 - ret = kstrtouint(buf, 10, &fclkin); 219 - if (ret) 220 - return ret; 221 - if (fclkin < AD2S1210_MIN_CLKIN || fclkin > AD2S1210_MAX_CLKIN) { 222 - dev_err(dev, "ad2s1210: fclkin out of range\n"); 223 - return -EINVAL; 224 - } 225 - 226 - mutex_lock(&st->lock); 227 - st->fclkin = fclkin; 228 - 229 - ret = ad2s1210_update_frequency_control_word(st); 230 - if (ret < 0) 231 - goto error_ret; 232 - ret = ad2s1210_soft_reset(st); 233 - error_ret: 234 - mutex_unlock(&st->lock); 235 - 236 - return ret < 0 ? ret : len; 237 - } 238 - 239 - static ssize_t ad2s1210_show_fexcit(struct device *dev, 240 - struct device_attribute *attr, 241 - char *buf) 242 - { 243 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 244 - 245 - return sprintf(buf, "%u\n", st->fexcit); 246 - } 247 - 248 - static ssize_t ad2s1210_store_fexcit(struct device *dev, 249 - struct device_attribute *attr, 250 - const char *buf, size_t len) 251 - { 252 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 253 - unsigned int fexcit; 254 - int ret; 255 - 256 - ret = kstrtouint(buf, 10, &fexcit); 257 - if (ret < 0) 258 - return ret; 259 - if (fexcit < AD2S1210_MIN_EXCIT || fexcit > AD2S1210_MAX_EXCIT) { 260 - dev_err(dev, 261 - "ad2s1210: excitation frequency out of range\n"); 262 - return -EINVAL; 263 - } 264 - mutex_lock(&st->lock); 265 - st->fexcit = fexcit; 266 - ret = ad2s1210_update_frequency_control_word(st); 267 - if (ret < 0) 268 - goto error_ret; 269 - ret = ad2s1210_soft_reset(st); 270 - error_ret: 271 - mutex_unlock(&st->lock); 272 - 273 - return ret < 0 ? ret : len; 274 - } 275 - 276 - static ssize_t ad2s1210_show_control(struct device *dev, 277 - struct device_attribute *attr, 278 - char *buf) 279 - { 280 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 281 - int ret; 282 - 283 - mutex_lock(&st->lock); 284 - ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL); 285 - mutex_unlock(&st->lock); 286 - return ret < 0 ? ret : sprintf(buf, "0x%x\n", ret); 287 - } 288 - 289 - static ssize_t ad2s1210_store_control(struct device *dev, 290 - struct device_attribute *attr, 291 - const char *buf, size_t len) 292 - { 293 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 294 - unsigned char udata; 295 - unsigned char data; 296 - int ret; 297 - 298 - ret = kstrtou8(buf, 16, &udata); 299 - if (ret) 300 - return -EINVAL; 301 - 302 - mutex_lock(&st->lock); 303 - ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL); 304 - if (ret < 0) 305 - goto error_ret; 306 - data = udata & AD2S1210_MSB_IS_LOW; 307 - ret = ad2s1210_config_write(st, data); 308 - if (ret < 0) 309 - goto error_ret; 310 - 311 - ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL); 312 - if (ret < 0) 313 - goto error_ret; 314 - if (ret & AD2S1210_MSB_IS_HIGH) { 315 - ret = -EIO; 316 - dev_err(dev, 317 - "ad2s1210: write control register fail\n"); 318 - goto error_ret; 319 - } 320 - st->resolution = 321 - ad2s1210_resolution_value[data & AD2S1210_SET_RESOLUTION]; 322 - ad2s1210_set_resolution_pin(st); 323 - ret = len; 324 - st->hysteresis = !!(data & AD2S1210_ENABLE_HYSTERESIS); 325 - 326 - error_ret: 327 - mutex_unlock(&st->lock); 328 - return ret; 329 - } 330 - 331 - static ssize_t ad2s1210_show_resolution(struct device *dev, 332 - struct device_attribute *attr, 333 - char *buf) 334 - { 335 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 336 - 337 - return sprintf(buf, "%d\n", st->resolution); 338 - } 339 - 340 - static ssize_t ad2s1210_store_resolution(struct device *dev, 341 - struct device_attribute *attr, 342 - const char *buf, size_t len) 343 - { 344 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 345 - unsigned char data; 346 - unsigned char udata; 347 - int ret; 348 - 349 - ret = kstrtou8(buf, 10, &udata); 350 - if (ret || udata < 10 || udata > 16) { 351 - dev_err(dev, "ad2s1210: resolution out of range\n"); 352 - return -EINVAL; 353 - } 354 - mutex_lock(&st->lock); 355 - ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL); 356 - if (ret < 0) 357 - goto error_ret; 358 - data = ret; 359 - data &= ~AD2S1210_SET_RESOLUTION; 360 - data |= (udata - 10) >> 1; 361 - ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL); 362 - if (ret < 0) 363 - goto error_ret; 364 - ret = ad2s1210_config_write(st, data & AD2S1210_MSB_IS_LOW); 365 - if (ret < 0) 366 - goto error_ret; 367 - ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL); 368 - if (ret < 0) 369 - goto error_ret; 370 - data = ret; 371 - if (data & AD2S1210_MSB_IS_HIGH) { 372 - ret = -EIO; 373 - dev_err(dev, "ad2s1210: setting resolution fail\n"); 374 - goto error_ret; 375 - } 376 - st->resolution = 377 - ad2s1210_resolution_value[data & AD2S1210_SET_RESOLUTION]; 378 - ad2s1210_set_resolution_pin(st); 379 - ret = len; 380 - error_ret: 381 - mutex_unlock(&st->lock); 382 - return ret; 383 - } 384 - 385 - /* read the fault register since last sample */ 386 - static ssize_t ad2s1210_show_fault(struct device *dev, 387 - struct device_attribute *attr, char *buf) 388 - { 389 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 390 - int ret; 391 - 392 - mutex_lock(&st->lock); 393 - ret = ad2s1210_config_read(st, AD2S1210_REG_FAULT); 394 - mutex_unlock(&st->lock); 395 - 396 - return ret ? ret : sprintf(buf, "0x%x\n", ret); 397 - } 398 - 399 - static ssize_t ad2s1210_clear_fault(struct device *dev, 400 - struct device_attribute *attr, 401 - const char *buf, 402 - size_t len) 403 - { 404 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 405 - int ret; 406 - 407 - mutex_lock(&st->lock); 408 - gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 0); 409 - /* delay (2 * tck + 20) nano seconds */ 410 - udelay(1); 411 - gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 1); 412 - ret = ad2s1210_config_read(st, AD2S1210_REG_FAULT); 413 - if (ret < 0) 414 - goto error_ret; 415 - gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 0); 416 - gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 1); 417 - error_ret: 418 - mutex_unlock(&st->lock); 419 - 420 - return ret < 0 ? ret : len; 421 - } 422 - 423 - static ssize_t ad2s1210_show_reg(struct device *dev, 424 - struct device_attribute *attr, 425 - char *buf) 426 - { 427 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 428 - struct iio_dev_attr *iattr = to_iio_dev_attr(attr); 429 - int ret; 430 - 431 - mutex_lock(&st->lock); 432 - ret = ad2s1210_config_read(st, iattr->address); 433 - mutex_unlock(&st->lock); 434 - 435 - return ret < 0 ? ret : sprintf(buf, "%d\n", ret); 436 - } 437 - 438 - static ssize_t ad2s1210_store_reg(struct device *dev, 439 - struct device_attribute *attr, 440 - const char *buf, size_t len) 441 - { 442 - struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); 443 - unsigned char data; 444 - int ret; 445 - struct iio_dev_attr *iattr = to_iio_dev_attr(attr); 446 - 447 - ret = kstrtou8(buf, 10, &data); 448 - if (ret) 449 - return -EINVAL; 450 - mutex_lock(&st->lock); 451 - ret = ad2s1210_config_write(st, iattr->address); 452 - if (ret < 0) 453 - goto error_ret; 454 - ret = ad2s1210_config_write(st, data & AD2S1210_MSB_IS_LOW); 455 - error_ret: 456 - mutex_unlock(&st->lock); 457 - return ret < 0 ? ret : len; 458 - } 459 - 460 - static int ad2s1210_read_raw(struct iio_dev *indio_dev, 461 - struct iio_chan_spec const *chan, 462 - int *val, 463 - int *val2, 464 - long m) 465 - { 466 - struct ad2s1210_state *st = iio_priv(indio_dev); 467 - u16 negative; 468 - int ret = 0; 469 - u16 pos; 470 - s16 vel; 471 - 472 - mutex_lock(&st->lock); 473 - gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 0); 474 - /* delay (6 * tck + 20) nano seconds */ 475 - udelay(1); 476 - 477 - switch (chan->type) { 478 - case IIO_ANGL: 479 - ad2s1210_set_mode(MOD_POS, st); 480 - break; 481 - case IIO_ANGL_VEL: 482 - ad2s1210_set_mode(MOD_VEL, st); 483 - break; 484 - default: 485 - ret = -EINVAL; 486 - break; 487 - } 488 - if (ret < 0) 489 - goto error_ret; 490 - ret = spi_read(st->sdev, st->rx, 2); 491 - if (ret < 0) 492 - goto error_ret; 493 - 494 - switch (chan->type) { 495 - case IIO_ANGL: 496 - pos = be16_to_cpup((__be16 *)st->rx); 497 - if (st->hysteresis) 498 - pos >>= 16 - st->resolution; 499 - *val = pos; 500 - ret = IIO_VAL_INT; 501 - break; 502 - case IIO_ANGL_VEL: 503 - vel = be16_to_cpup((__be16 *)st->rx); 504 - vel >>= 16 - st->resolution; 505 - if (vel & 0x8000) { 506 - negative = (0xffff >> st->resolution) << st->resolution; 507 - vel |= negative; 508 - } 509 - *val = vel; 510 - ret = IIO_VAL_INT; 511 - break; 512 - default: 513 - mutex_unlock(&st->lock); 514 - return -EINVAL; 515 - } 516 - 517 - error_ret: 518 - gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 1); 519 - /* delay (2 * tck + 20) nano seconds */ 520 - udelay(1); 521 - mutex_unlock(&st->lock); 522 - return ret; 523 - } 524 - 525 - static IIO_DEVICE_ATTR(fclkin, 0644, 526 - ad2s1210_show_fclkin, ad2s1210_store_fclkin, 0); 527 - static IIO_DEVICE_ATTR(fexcit, 0644, 528 - ad2s1210_show_fexcit, ad2s1210_store_fexcit, 0); 529 - static IIO_DEVICE_ATTR(control, 0644, 530 - ad2s1210_show_control, ad2s1210_store_control, 0); 531 - static IIO_DEVICE_ATTR(bits, 0644, 532 - ad2s1210_show_resolution, ad2s1210_store_resolution, 0); 533 - static IIO_DEVICE_ATTR(fault, 0644, 534 - ad2s1210_show_fault, ad2s1210_clear_fault, 0); 535 - 536 - static IIO_DEVICE_ATTR(los_thrd, 0644, 537 - ad2s1210_show_reg, ad2s1210_store_reg, 538 - AD2S1210_REG_LOS_THRD); 539 - static IIO_DEVICE_ATTR(dos_ovr_thrd, 0644, 540 - ad2s1210_show_reg, ad2s1210_store_reg, 541 - AD2S1210_REG_DOS_OVR_THRD); 542 - static IIO_DEVICE_ATTR(dos_mis_thrd, 0644, 543 - ad2s1210_show_reg, ad2s1210_store_reg, 544 - AD2S1210_REG_DOS_MIS_THRD); 545 - static IIO_DEVICE_ATTR(dos_rst_max_thrd, 0644, 546 - ad2s1210_show_reg, ad2s1210_store_reg, 547 - AD2S1210_REG_DOS_RST_MAX_THRD); 548 - static IIO_DEVICE_ATTR(dos_rst_min_thrd, 0644, 549 - ad2s1210_show_reg, ad2s1210_store_reg, 550 - AD2S1210_REG_DOS_RST_MIN_THRD); 551 - static IIO_DEVICE_ATTR(lot_high_thrd, 0644, 552 - ad2s1210_show_reg, ad2s1210_store_reg, 553 - AD2S1210_REG_LOT_HIGH_THRD); 554 - static IIO_DEVICE_ATTR(lot_low_thrd, 0644, 555 - ad2s1210_show_reg, ad2s1210_store_reg, 556 - AD2S1210_REG_LOT_LOW_THRD); 557 - 558 - static const struct iio_chan_spec ad2s1210_channels[] = { 559 - { 560 - .type = IIO_ANGL, 561 - .indexed = 1, 562 - .channel = 0, 563 - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 564 - }, { 565 - .type = IIO_ANGL_VEL, 566 - .indexed = 1, 567 - .channel = 0, 568 - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 569 - } 570 - }; 571 - 572 - static struct attribute *ad2s1210_attributes[] = { 573 - &iio_dev_attr_fclkin.dev_attr.attr, 574 - &iio_dev_attr_fexcit.dev_attr.attr, 575 - &iio_dev_attr_control.dev_attr.attr, 576 - &iio_dev_attr_bits.dev_attr.attr, 577 - &iio_dev_attr_fault.dev_attr.attr, 578 - &iio_dev_attr_los_thrd.dev_attr.attr, 579 - &iio_dev_attr_dos_ovr_thrd.dev_attr.attr, 580 - &iio_dev_attr_dos_mis_thrd.dev_attr.attr, 581 - &iio_dev_attr_dos_rst_max_thrd.dev_attr.attr, 582 - &iio_dev_attr_dos_rst_min_thrd.dev_attr.attr, 583 - &iio_dev_attr_lot_high_thrd.dev_attr.attr, 584 - &iio_dev_attr_lot_low_thrd.dev_attr.attr, 585 - NULL, 586 - }; 587 - 588 - static const struct attribute_group ad2s1210_attribute_group = { 589 - .attrs = ad2s1210_attributes, 590 - }; 591 - 592 - static int ad2s1210_initial(struct ad2s1210_state *st) 593 - { 594 - unsigned char data; 595 - int ret; 596 - 597 - mutex_lock(&st->lock); 598 - ad2s1210_set_resolution_pin(st); 599 - 600 - ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL); 601 - if (ret < 0) 602 - goto error_ret; 603 - data = AD2S1210_DEF_CONTROL & ~(AD2S1210_SET_RESOLUTION); 604 - data |= (st->resolution - 10) >> 1; 605 - ret = ad2s1210_config_write(st, data); 606 - if (ret < 0) 607 - goto error_ret; 608 - ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL); 609 - if (ret < 0) 610 - goto error_ret; 611 - 612 - if (ret & AD2S1210_MSB_IS_HIGH) { 613 - ret = -EIO; 614 - goto error_ret; 615 - } 616 - 617 - ret = ad2s1210_update_frequency_control_word(st); 618 - if (ret < 0) 619 - goto error_ret; 620 - ret = ad2s1210_soft_reset(st); 621 - error_ret: 622 - mutex_unlock(&st->lock); 623 - return ret; 624 - } 625 - 626 - static const struct iio_info ad2s1210_info = { 627 - .read_raw = ad2s1210_read_raw, 628 - .attrs = &ad2s1210_attribute_group, 629 - }; 630 - 631 - static int ad2s1210_setup_gpios(struct ad2s1210_state *st) 632 - { 633 - struct spi_device *spi = st->sdev; 634 - int i, ret; 635 - 636 - for (i = 0; i < ARRAY_SIZE(gpios); i++) { 637 - st->gpios[i] = devm_gpiod_get(&spi->dev, gpios[i].name, 638 - gpios[i].flags); 639 - if (IS_ERR(st->gpios[i])) { 640 - ret = PTR_ERR(st->gpios[i]); 641 - dev_err(&spi->dev, 642 - "ad2s1210: failed to request %s GPIO: %d\n", 643 - gpios[i].name, ret); 644 - return ret; 645 - } 646 - } 647 - 648 - return 0; 649 - } 650 - 651 - static int ad2s1210_probe(struct spi_device *spi) 652 - { 653 - struct iio_dev *indio_dev; 654 - struct ad2s1210_state *st; 655 - int ret; 656 - 657 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 658 - if (!indio_dev) 659 - return -ENOMEM; 660 - st = iio_priv(indio_dev); 661 - ret = ad2s1210_setup_gpios(st); 662 - if (ret < 0) 663 - return ret; 664 - 665 - spi_set_drvdata(spi, indio_dev); 666 - 667 - mutex_init(&st->lock); 668 - st->sdev = spi; 669 - st->hysteresis = true; 670 - st->mode = MOD_CONFIG; 671 - st->resolution = 12; 672 - st->fexcit = AD2S1210_DEF_EXCIT; 673 - 674 - indio_dev->info = &ad2s1210_info; 675 - indio_dev->modes = INDIO_DIRECT_MODE; 676 - indio_dev->channels = ad2s1210_channels; 677 - indio_dev->num_channels = ARRAY_SIZE(ad2s1210_channels); 678 - indio_dev->name = spi_get_device_id(spi)->name; 679 - 680 - ret = devm_iio_device_register(&spi->dev, indio_dev); 681 - if (ret) 682 - return ret; 683 - 684 - st->fclkin = spi->max_speed_hz; 685 - spi->mode = SPI_MODE_3; 686 - spi_setup(spi); 687 - ad2s1210_initial(st); 688 - 689 - return 0; 690 - } 691 - 692 - static const struct of_device_id ad2s1210_of_match[] = { 693 - { .compatible = "adi,ad2s1210", }, 694 - { } 695 - }; 696 - MODULE_DEVICE_TABLE(of, ad2s1210_of_match); 697 - 698 - static const struct spi_device_id ad2s1210_id[] = { 699 - { "ad2s1210" }, 700 - {} 701 - }; 702 - MODULE_DEVICE_TABLE(spi, ad2s1210_id); 703 - 704 - static struct spi_driver ad2s1210_driver = { 705 - .driver = { 706 - .name = DRV_NAME, 707 - .of_match_table = of_match_ptr(ad2s1210_of_match), 708 - }, 709 - .probe = ad2s1210_probe, 710 - .id_table = ad2s1210_id, 711 - }; 712 - module_spi_driver(ad2s1210_driver); 713 - 714 - MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>"); 715 - MODULE_DESCRIPTION("Analog Devices AD2S1210 Resolver to Digital SPI driver"); 716 - MODULE_LICENSE("GPL v2");

+4

include/linux/hid-sensor-ids.h

··· 21 21 #define HID_USAGE_SENSOR_ALS 0x200041 22 22 #define HID_USAGE_SENSOR_DATA_LIGHT 0x2004d0 23 23 #define HID_USAGE_SENSOR_LIGHT_ILLUM 0x2004d1 24 + #define HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE 0x2004d2 25 + #define HID_USAGE_SENSOR_LIGHT_CHROMATICITY 0x2004d3 26 + #define HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X 0x2004d4 27 + #define HID_USAGE_SENSOR_LIGHT_CHROMATICITY_Y 0x2004d5 24 28 25 29 /* PROX (200011) */ 26 30 #define HID_USAGE_SENSOR_PROX 0x200011

+11 -1

include/linux/iio/iio.h

··· 427 427 * @write_event_config: set if the event is enabled. 428 428 * @read_event_value: read a configuration value associated with the event. 429 429 * @write_event_value: write a configuration value for the event. 430 + * @read_event_label: function to request label name for a specified label, 431 + * for better event identification. 430 432 * @validate_trigger: function to validate the trigger when the 431 433 * current trigger gets changed. 432 434 * @update_scan_mode: function to configure device and scan buffer when ··· 513 511 enum iio_event_direction dir, 514 512 enum iio_event_info info, int val, int val2); 515 513 514 + int (*read_event_label)(struct iio_dev *indio_dev, 515 + struct iio_chan_spec const *chan, 516 + enum iio_event_type type, 517 + enum iio_event_direction dir, 518 + char *label); 519 + 516 520 int (*validate_trigger)(struct iio_dev *indio_dev, 517 521 struct iio_trigger *trig); 518 522 int (*update_scan_mode)(struct iio_dev *indio_dev, ··· 564 556 * and owner 565 557 * @buffer: [DRIVER] any buffer present 566 558 * @scan_bytes: [INTERN] num bytes captured to be fed to buffer demux 567 - * @available_scan_masks: [DRIVER] optional array of allowed bitmasks 559 + * @available_scan_masks: [DRIVER] optional array of allowed bitmasks. Sort the 560 + * array in order of preference, the most preferred 561 + * masks first. 568 562 * @masklength: [INTERN] the length of the mask established from 569 563 * channels 570 564 * @active_scan_mask: [INTERN] union of all scan masks requested by buffers

-3

include/linux/iio/sw_device.h

··· 51 51 struct iio_sw_device *iio_sw_device_create(const char *, const char *); 52 52 void iio_sw_device_destroy(struct iio_sw_device *); 53 53 54 - int iio_sw_device_type_configfs_register(struct iio_sw_device_type *dt); 55 - void iio_sw_device_type_configfs_unregister(struct iio_sw_device_type *dt); 56 - 57 54 static inline 58 55 void iio_swd_group_init_type_name(struct iio_sw_device *d, 59 56 const char *name,

-3

include/linux/iio/sw_trigger.h

··· 51 51 struct iio_sw_trigger *iio_sw_trigger_create(const char *, const char *); 52 52 void iio_sw_trigger_destroy(struct iio_sw_trigger *); 53 53 54 - int iio_sw_trigger_type_configfs_register(struct iio_sw_trigger_type *tt); 55 - void iio_sw_trigger_type_configfs_unregister(struct iio_sw_trigger_type *tt); 56 - 57 54 static inline 58 55 void iio_swt_group_init_type_name(struct iio_sw_trigger *t, 59 56 const char *name,

+4

include/uapi/linux/iio/types.h

··· 47 47 IIO_POSITIONRELATIVE, 48 48 IIO_PHASE, 49 49 IIO_MASSCONCENTRATION, 50 + IIO_DELTA_ANGL, 51 + IIO_DELTA_VELOCITY, 52 + IIO_COLORTEMP, 53 + IIO_CHROMATICITY, 50 54 }; 51 55 52 56 enum iio_modifier {

+8

tools/iio/iio_event_monitor.c

··· 59 59 [IIO_POSITIONRELATIVE] = "positionrelative", 60 60 [IIO_PHASE] = "phase", 61 61 [IIO_MASSCONCENTRATION] = "massconcentration", 62 + [IIO_DELTA_ANGL] = "deltaangl", 63 + [IIO_DELTA_VELOCITY] = "deltavelocity", 64 + [IIO_COLORTEMP] = "colortemp", 65 + [IIO_CHROMATICITY] = "chromaticity", 62 66 }; 63 67 64 68 static const char * const iio_ev_type_text[] = { ··· 177 173 case IIO_POSITIONRELATIVE: 178 174 case IIO_PHASE: 179 175 case IIO_MASSCONCENTRATION: 176 + case IIO_DELTA_ANGL: 177 + case IIO_DELTA_VELOCITY: 178 + case IIO_COLORTEMP: 179 + case IIO_CHROMATICITY: 180 180 break; 181 181 default: 182 182 return false;

+12 -1

tools/iio/iio_generic_buffer.c

··· 54 54 static unsigned int size_from_channelarray(struct iio_channel_info *channels, int num_channels) 55 55 { 56 56 unsigned int bytes = 0; 57 - int i = 0; 57 + int i = 0, max = 0; 58 + unsigned int misalignment; 58 59 59 60 while (i < num_channels) { 61 + if (channels[i].bytes > max) 62 + max = channels[i].bytes; 60 63 if (bytes % channels[i].bytes == 0) 61 64 channels[i].location = bytes; 62 65 else ··· 69 66 bytes = channels[i].location + channels[i].bytes; 70 67 i++; 71 68 } 69 + /* 70 + * We want the data in next sample to also be properly aligned so 71 + * we'll add padding at the end if needed. Adding padding only 72 + * works for channel data which size is 2^n bytes. 73 + */ 74 + misalignment = bytes % max; 75 + if (misalignment) 76 + bytes += max - misalignment; 72 77 73 78 return bytes; 74 79 }

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