Merge branch 'icc-sdx75' into icc-next

Drop the QPIC interconnect and BCM nodes for the SDX75 SoC. The reason
is that this QPIC BCM resource is already defined as a RPMh clock in
clk-rpmh driver as like other SDX SoCs. So it is wrong to describe the
same resource in two different providers.

Also, without this series, the NAND driver fails to probe on SDX75 as
the interconnect sync state disables the QPIC nodes as there were no
clients voting for this ICC resource. However, the NAND driver had already
voted for this BCM resource through the clk-rpmh driver. Since both votes
come from Linux, RPMh was unable to distinguish between these two and ends
up disabling the resource during sync state.

* icc-sdx75
interconnect: qcom: sdx75: Drop QPIC interconnect and BCM nodes
dt-bindings: interconnect: qcom: Drop QPIC_CORE IDs

Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-0-20d6820e455c@oss.qualcomm.com>
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Georgi Djakov 7 months ago b4e8b0f2 a1f295a1

-30

3 changed files

expand all

drivers

interconnect

qcom

sdx75.c

sdx75.h

include

dt-bindings

interconnect

qcom,sdx75.h

-26

drivers/interconnect/qcom/sdx75.c

··· 16 16 #include "icc-rpmh.h" 17 17 #include "sdx75.h" 18 18 19 - static struct qcom_icc_node qpic_core_master = { 20 - .name = "qpic_core_master", 21 - .id = SDX75_MASTER_QPIC_CORE, 22 - .channels = 1, 23 - .buswidth = 4, 24 - .num_links = 1, 25 - .links = { SDX75_SLAVE_QPIC_CORE }, 26 - }; 27 - 28 19 static struct qcom_icc_node qup0_core_master = { 29 20 .name = "qup0_core_master", 30 21 .id = SDX75_MASTER_QUP_CORE_0, ··· 364 373 .buswidth = 8, 365 374 .num_links = 1, 366 375 .links = { SDX75_SLAVE_A1NOC_CFG }, 367 - }; 368 - 369 - static struct qcom_icc_node qpic_core_slave = { 370 - .name = "qpic_core_slave", 371 - .id = SDX75_SLAVE_QPIC_CORE, 372 - .channels = 1, 373 - .buswidth = 4, 374 - .num_links = 0, 375 376 }; 376 377 377 378 static struct qcom_icc_node qup0_core_slave = { ··· 814 831 .nodes = { &ebi }, 815 832 }; 816 833 817 - static struct qcom_icc_bcm bcm_qp0 = { 818 - .name = "QP0", 819 - .num_nodes = 1, 820 - .nodes = { &qpic_core_slave }, 821 - }; 822 - 823 834 static struct qcom_icc_bcm bcm_qup0 = { 824 835 .name = "QUP0", 825 836 .keepalive = true, ··· 875 898 }; 876 899 877 900 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 878 - &bcm_qp0, 879 901 &bcm_qup0, 880 902 }; 881 903 882 904 static struct qcom_icc_node * const clk_virt_nodes[] = { 883 - [MASTER_QPIC_CORE] = &qpic_core_master, 884 905 [MASTER_QUP_CORE_0] = &qup0_core_master, 885 - [SLAVE_QPIC_CORE] = &qpic_core_slave, 886 906 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 887 907 }; 888 908

-2

drivers/interconnect/qcom/sdx75.h

··· 33 33 #define SDX75_MASTER_QDSS_ETR 24 34 34 #define SDX75_MASTER_QDSS_ETR_1 25 35 35 #define SDX75_MASTER_QPIC 26 36 - #define SDX75_MASTER_QPIC_CORE 27 37 36 #define SDX75_MASTER_QUP_0 28 38 37 #define SDX75_MASTER_QUP_CORE_0 29 39 38 #define SDX75_MASTER_SDCC_1 30 ··· 75 76 #define SDX75_SLAVE_QDSS_CFG 67 76 77 #define SDX75_SLAVE_QDSS_STM 68 77 78 #define SDX75_SLAVE_QPIC 69 78 - #define SDX75_SLAVE_QPIC_CORE 70 79 79 #define SDX75_SLAVE_QUP_0 71 80 80 #define SDX75_SLAVE_QUP_CORE_0 72 81 81 #define SDX75_SLAVE_SDCC_1 73

-2

include/dt-bindings/interconnect/qcom,sdx75.h

··· 6 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H 7 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H 8 8 9 - #define MASTER_QPIC_CORE 0 10 9 #define MASTER_QUP_CORE_0 1 11 - #define SLAVE_QPIC_CORE 2 12 10 #define SLAVE_QUP_CORE_0 3 13 11 14 12 #define MASTER_LLCC 0

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