Merge branch 'net-stmmac-cleanup-stmmac_xmit'

+52 -51

1 changed file

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drivers

net

ethernet

stmicro

stmmac

stmmac_main.c

+52 -51

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

··· 4678 4678 int gso = skb_shinfo(skb)->gso_type; 4679 4679 struct stmmac_txq_stats *txq_stats; 4680 4680 struct dma_desc *desc, *first_desc; 4681 - struct dma_edesc *tbs_desc = NULL; 4682 4681 struct stmmac_tx_queue *tx_q; 4683 4682 int i, csum_insertion = 0; 4684 4683 int entry, first_tx; 4685 4684 dma_addr_t dma_addr; 4686 4685 u32 sdu_len; 4687 - 4688 - tx_q = &priv->dma_conf.tx_queue[queue]; 4689 - txq_stats = &priv->xstats.txq_stats[queue]; 4690 - first_tx = tx_q->cur_tx; 4691 4686 4692 4687 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4693 4688 stmmac_stop_sw_lpi(priv); ··· 4720 4725 return NETDEV_TX_BUSY; 4721 4726 } 4722 4727 4728 + tx_q = &priv->dma_conf.tx_queue[queue]; 4729 + first_tx = tx_q->cur_tx; 4730 + 4723 4731 /* Check if VLAN can be inserted by HW */ 4724 4732 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4725 - 4726 - entry = tx_q->cur_tx; 4727 - first_entry = entry; 4728 - WARN_ON(tx_q->tx_skbuff[first_entry]); 4729 4733 4730 4734 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4731 4735 /* DWMAC IPs can be synthesized to support tx coe only for a few tx ··· 4742 4748 csum_insertion = !csum_insertion; 4743 4749 } 4744 4750 4751 + entry = tx_q->cur_tx; 4752 + first_entry = entry; 4753 + WARN_ON(tx_q->tx_skbuff[first_entry]); 4754 + 4745 4755 desc = stmmac_get_tx_desc(priv, tx_q, entry); 4746 4756 first_desc = desc; 4747 4757 ··· 4761 4763 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4762 4764 if (unlikely(entry < 0) && (entry != -EINVAL)) 4763 4765 goto dma_map_err; 4766 + } else { 4767 + bool last_segment = (nfrags == 0); 4768 + 4769 + dma_addr = dma_map_single(priv->device, skb->data, 4770 + nopaged_len, DMA_TO_DEVICE); 4771 + if (dma_mapping_error(priv->device, dma_addr)) 4772 + goto dma_map_err; 4773 + 4774 + stmmac_set_tx_skb_dma_entry(tx_q, first_entry, dma_addr, 4775 + nopaged_len, false); 4776 + 4777 + stmmac_set_desc_addr(priv, first_desc, dma_addr); 4778 + 4779 + if (last_segment) 4780 + stmmac_set_tx_dma_last_segment(tx_q, first_entry); 4781 + 4782 + if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4783 + priv->hwts_tx_en)) { 4784 + /* declare that device is doing timestamping */ 4785 + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4786 + stmmac_enable_tx_timestamp(priv, first_desc); 4787 + } 4788 + 4789 + /* Prepare the first descriptor without setting the OWN bit */ 4790 + stmmac_prepare_tx_desc(priv, first_desc, 1, nopaged_len, 4791 + csum_insertion, priv->descriptor_mode, 4792 + 0, last_segment, skb->len); 4793 + } 4794 + 4795 + if (priv->sarc_type) 4796 + stmmac_set_desc_sarc(priv, first_desc, priv->sarc_type); 4797 + 4798 + /* STMMAC_TBS_EN can only be set if STMMAC_TBS_AVAIL has already 4799 + * been set, which means the underlying type of the descriptors 4800 + * will be struct stmmac_edesc. Therefore, it is safe to convert 4801 + * the basic descriptor to the enhanced descriptor here. 4802 + */ 4803 + if (tx_q->tbs & STMMAC_TBS_EN) { 4804 + struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4805 + 4806 + stmmac_set_desc_tbs(priv, dma_desc_to_edesc(first_desc), 4807 + ts.tv_sec, ts.tv_nsec); 4764 4808 } 4765 4809 4766 4810 for (i = 0; i < nfrags; i++) { ··· 4885 4845 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4886 4846 } 4887 4847 4848 + txq_stats = &priv->xstats.txq_stats[queue]; 4888 4849 u64_stats_update_begin(&txq_stats->q_syncp); 4889 4850 u64_stats_add(&txq_stats->q.tx_bytes, skb->len); 4890 4851 if (set_ic) 4891 4852 u64_stats_inc(&txq_stats->q.tx_set_ic_bit); 4892 4853 u64_stats_update_end(&txq_stats->q_syncp); 4893 4854 4894 - if (priv->sarc_type) 4895 - stmmac_set_desc_sarc(priv, first_desc, priv->sarc_type); 4896 - 4897 - /* Ready to fill the first descriptor and set the OWN bit w/o any 4898 - * problems because all the descriptors are actually ready to be 4899 - * passed to the DMA engine. 4855 + /* Set the OWN bit on the first descriptor now that all descriptors 4856 + * for this skb are populated. 4900 4857 */ 4901 - if (likely(!is_jumbo)) { 4902 - bool last_segment = (nfrags == 0); 4903 - 4904 - dma_addr = dma_map_single(priv->device, skb->data, 4905 - nopaged_len, DMA_TO_DEVICE); 4906 - if (dma_mapping_error(priv->device, dma_addr)) 4907 - goto dma_map_err; 4908 - 4909 - stmmac_set_tx_skb_dma_entry(tx_q, first_entry, dma_addr, 4910 - nopaged_len, false); 4911 - 4912 - stmmac_set_desc_addr(priv, first_desc, dma_addr); 4913 - 4914 - if (last_segment) 4915 - stmmac_set_tx_dma_last_segment(tx_q, first_entry); 4916 - 4917 - if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4918 - priv->hwts_tx_en)) { 4919 - /* declare that device is doing timestamping */ 4920 - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4921 - stmmac_enable_tx_timestamp(priv, first_desc); 4922 - } 4923 - 4924 - /* Prepare the first descriptor setting the OWN bit too */ 4925 - stmmac_prepare_tx_desc(priv, first_desc, 1, nopaged_len, 4926 - csum_insertion, priv->descriptor_mode, 4927 - 0, last_segment, skb->len); 4928 - } 4929 - 4930 - if (tx_q->tbs & STMMAC_TBS_EN) { 4931 - struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4932 - 4933 - tbs_desc = &tx_q->dma_entx[first_entry]; 4934 - stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4935 - } 4936 - 4937 4858 stmmac_set_tx_owner(priv, first_desc); 4938 4859 4939 4860 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);

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