+4 -6

Documentation/arch/x86/pti.rst

reviewed

··· 81 81 and exit (it can be skipped when the kernel is interrupted, 82 82 though.) Moves to CR3 are on the order of a hundred 83 83 cycles, and are required at every entry and exit. 84 84 - b. A "trampoline" must be used for SYSCALL entry. This 85 85 - trampoline depends on a smaller set of resources than the 86 86 - non-PTI SYSCALL entry code, so requires mapping fewer 87 87 - things into the userspace page tables. The downside is 88 88 - that stacks must be switched at entry time. 84 84 + b. Percpu TSS is mapped into the user page tables to allow SYSCALL64 path 85 85 + to work under PTI. This doesn't have a direct runtime cost but it can 86 86 + be argued it opens certain timing attack scenarios. 89 87 c. Global pages are disabled for all kernel structures not 90 88 mapped into both kernel and userspace page tables. This 91 89 feature of the MMU allows different processes to share TLB ··· 165 167 * Failures of the selftests/x86 code. Usually a bug in one of the 166 168 more obscure corners of entry_64.S 167 169 * Crashes in early boot, especially around CPU bringup. Bugs 168 168 - in the trampoline code or mappings cause these. 170 170 + in the mappings cause these. 169 171 * Crashes at the first interrupt. Caused by bugs in entry_64.S, 170 172 like screwing up a page table switch. Also caused by 171 173 incorrectly mapping the IRQ handler entry code.

-4

arch/x86/Kconfig

reviewed

··· 384 384 def_bool y 385 385 depends on INTEL_IOMMU && ACPI 386 386 387 387 - config X86_32_SMP 388 388 - def_bool y 389 389 - depends on X86_32 && SMP 390 390 - 391 387 config X86_64_SMP 392 388 def_bool y 393 389 depends on X86_64 && SMP

+1 -1

arch/x86/boot/compressed/Makefile

reviewed

··· 53 53 KBUILD_CFLAGS += $(call cc-option,-Wa$(comma)-mrelax-relocations=no) 54 54 KBUILD_CFLAGS += -include $(srctree)/include/linux/hidden.h 55 55 56 56 - # sev.c indirectly inludes inat-table.h which is generated during 56 56 + # sev.c indirectly includes inat-table.h which is generated during 57 57 # compilation and stored in $(objtree). Add the directory to the includes so 58 58 # that the compiler finds it even with out-of-tree builds (make O=/some/path). 59 59 CFLAGS_sev.o += -I$(objtree)/arch/x86/lib/

+1 -1

arch/x86/boot/compressed/mem.c

reviewed

··· 8 8 9 9 /* 10 10 * accept_memory() and process_unaccepted_memory() called from EFI stub which 11 11 - * runs before decompresser and its early_tdx_detect(). 11 11 + * runs before decompressor and its early_tdx_detect(). 12 12 * 13 13 * Enumerate TDX directly from the early users. 14 14 */

+1 -1

arch/x86/coco/tdx/tdx.c

reviewed

··· 887 887 * there. 888 888 * 889 889 * Intel-TDX has a secure RDMSR hypercall, but that needs to be 890 890 - * implemented seperately in the low level startup ASM code. 890 890 + * implemented separately in the low level startup ASM code. 891 891 * Until that is in place, disable parallel bringup for TDX. 892 892 */ 893 893 x86_cpuinit.parallel_bringup = false;

+1 -1

arch/x86/crypto/aesni-intel_asm.S

reviewed

··· 666 666 667 667 .ifc \operation, dec 668 668 movdqa %xmm1, %xmm3 669 669 - pxor %xmm1, %xmm9 # Cyphertext XOR E(K, Yn) 669 669 + pxor %xmm1, %xmm9 # Ciphertext XOR E(K, Yn) 670 670 671 671 mov \PLAIN_CYPH_LEN, %r10 672 672 add %r13, %r10

+1 -1

arch/x86/crypto/aesni-intel_avx-x86_64.S

reviewed

··· 747 747 748 748 .if \ENC_DEC == DEC 749 749 vmovdqa %xmm1, %xmm3 750 750 - pxor %xmm1, %xmm9 # Cyphertext XOR E(K, Yn) 750 750 + pxor %xmm1, %xmm9 # Ciphertext XOR E(K, Yn) 751 751 752 752 mov \PLAIN_CYPH_LEN, %r10 753 753 add %r13, %r10

+1 -1

arch/x86/crypto/crc32c-pcl-intel-asm_64.S

reviewed

··· 184 184 xor crc1,crc1 185 185 xor crc2,crc2 186 186 187 187 - # Fall thruogh into top of crc array (crc_128) 187 187 + # Fall through into top of crc array (crc_128) 188 188 189 189 ################################################################ 190 190 ## 3) CRC Array:

+1 -1

arch/x86/crypto/sha512-avx-asm.S

reviewed

··· 84 84 85 85 # Useful QWORD "arrays" for simpler memory references 86 86 # MSG, DIGEST, K_t, W_t are arrays 87 87 - # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even 87 87 + # WK_2(t) points to 1 of 2 qwords at frame.WK depending on t being odd/even 88 88 89 89 # Input message (arg1) 90 90 #define MSG(i) 8*i(msg)

+1 -1

arch/x86/crypto/sha512-ssse3-asm.S

reviewed

··· 82 82 83 83 # Useful QWORD "arrays" for simpler memory references 84 84 # MSG, DIGEST, K_t, W_t are arrays 85 85 - # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even 85 85 + # WK_2(t) points to 1 of 2 qwords at frame.WK depending on t being odd/even 86 86 87 87 # Input message (arg1) 88 88 #define MSG(i) 8*i(msg)

+1 -1

arch/x86/events/amd/brs.c

reviewed

··· 125 125 * Where X is the number of taken branches due to interrupt 126 126 * skid. Skid is large. 127 127 * 128 128 - * Where Y is the occurences of the event while BRS is 128 128 + * Where Y is the occurrences of the event while BRS is 129 129 * capturing the lbr_nr entries. 130 130 * 131 131 * By using retired taken branches, we limit the impact on the

+1 -1

arch/x86/events/amd/core.c

reviewed

··· 1184 1184 * period of each one and given that the BRS saturates, it would not be possible 1185 1185 * to guarantee correlated content for all events. Therefore, in situations 1186 1186 * where multiple events want to use BRS, the kernel enforces mutual exclusion. 1187 1187 - * Exclusion is enforced by chosing only one counter for events using BRS. 1187 1187 + * Exclusion is enforced by choosing only one counter for events using BRS. 1188 1188 * The event scheduling logic will then automatically multiplex the 1189 1189 * events and ensure that at most one event is actively using BRS. 1190 1190 *

+1 -1

arch/x86/events/intel/core.c

reviewed

··· 4027 4027 4028 4028 /* 4029 4029 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4030 4030 - * The host perf conext helps to prepare the values of the real hardware for 4030 4030 + * The host perf context helps to prepare the values of the real hardware for 4031 4031 * a set of msrs that need to be switched atomically in a vmx transaction. 4032 4032 * 4033 4033 * For example, the pseudocode needed to add a new msr should look like:

+1 -1

arch/x86/hyperv/hv_apic.c

reviewed

··· 209 209 210 210 /* 211 211 * This particular version of the IPI hypercall can 212 212 - * only target upto 64 CPUs. 212 212 + * only target up to 64 CPUs. 213 213 */ 214 214 if (vcpu >= 64) 215 215 goto do_ex_hypercall;

+1 -1

arch/x86/hyperv/irqdomain.c

reviewed

··· 212 212 * This interrupt is already mapped. Let's unmap first. 213 213 * 214 214 * We don't use retarget interrupt hypercalls here because 215 215 - * Microsoft Hypervisor doens't allow root to change the vector 215 215 + * Microsoft Hypervisor doesn't allow root to change the vector 216 216 * or specify VPs outside of the set that is initially used 217 217 * during mapping. 218 218 */

+1 -1

arch/x86/hyperv/ivm.c

reviewed

··· 144 144 /* Tell the hypervisor what went wrong. */ 145 145 val |= GHCB_SEV_TERM_REASON(set, reason); 146 146 147 147 - /* Request Guest Termination from Hypvervisor */ 147 147 + /* Request Guest Termination from Hypervisor */ 148 148 wr_ghcb_msr(val); 149 149 VMGEXIT(); 150 150

+1 -1

arch/x86/include/asm/amd_nb.h

reviewed

··· 104 104 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 105 105 return false; 106 106 107 107 - /* GART present only on Fam15h, upto model 0fh */ 107 107 + /* GART present only on Fam15h, up to model 0fh */ 108 108 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || 109 109 (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) 110 110 return true;

+1 -1

arch/x86/include/asm/extable_fixup_types.h

reviewed

··· 4 4 5 5 /* 6 6 * Our IMM is signed, as such it must live at the top end of the word. Also, 7 7 - * since C99 hex constants are of ambigious type, force cast the mask to 'int' 7 7 + * since C99 hex constants are of ambiguous type, force cast the mask to 'int' 8 8 * so that FIELD_GET() will DTRT and sign extend the value when it extracts it. 9 9 */ 10 10 #define EX_DATA_TYPE_MASK ((int)0x000000FF)

+1 -1

arch/x86/include/asm/fpu/types.h

reviewed

··· 415 415 * 416 416 * This master permission field is only to be used when 417 417 * task.fpu.fpstate based checks fail to validate whether the task 418 418 - * is allowed to expand it's xfeatures set which requires to 418 418 + * is allowed to expand its xfeatures set which requires to 419 419 * allocate a larger sized fpstate buffer. 420 420 * 421 421 * Do not access this field directly. Use the provided helper

+4 -4

arch/x86/include/asm/io.h

reviewed

··· 242 242 243 243 #endif 244 244 245 245 - #define BUILDIO(bwl, bw, type) \ 245 245 + #define BUILDIO(bwl, type) \ 246 246 static inline void out##bwl##_p(type value, u16 port) \ 247 247 { \ 248 248 out##bwl(value, port); \ ··· 288 288 } \ 289 289 } 290 290 291 291 - BUILDIO(b, b, u8) 292 292 - BUILDIO(w, w, u16) 293 293 - BUILDIO(l, , u32) 291 291 + BUILDIO(b, u8) 292 292 + BUILDIO(w, u16) 293 293 + BUILDIO(l, u32) 294 294 #undef BUILDIO 295 295 296 296 #define inb_p inb_p

+1 -1

arch/x86/include/asm/iosf_mbi.h

reviewed

··· 111 111 * This function will block all kernel access to the PMIC I2C bus, so that the 112 112 * P-Unit can safely access the PMIC over the shared I2C bus. 113 113 * 114 114 - * Note on these systems the i2c-bus driver will request a sempahore from the 114 114 + * Note on these systems the i2c-bus driver will request a semaphore from the 115 115 * P-Unit for exclusive access to the PMIC bus when i2c drivers are accessing 116 116 * it, but this does not appear to be sufficient, we still need to avoid making 117 117 * certain P-Unit requests during the access window to avoid problems.

+1 -1

arch/x86/include/asm/kvm_host.h

reviewed

··· 1652 1652 /* Whether or not a virtual NMI is pending in hardware. */ 1653 1653 bool (*is_vnmi_pending)(struct kvm_vcpu *vcpu); 1654 1654 /* 1655 1655 - * Attempt to pend a virtual NMI in harware. Returns %true on success 1655 1655 + * Attempt to pend a virtual NMI in hardware. Returns %true on success 1656 1656 * to allow using static_call_ret0 as the fallback. 1657 1657 */ 1658 1658 bool (*set_vnmi_pending)(struct kvm_vcpu *vcpu);

+2 -2

arch/x86/include/asm/nospec-branch.h

reviewed

··· 49 49 * but there is still a cushion vs. the RSB depth. The algorithm does not 50 50 * claim to be perfect and it can be speculated around by the CPU, but it 51 51 * is considered that it obfuscates the problem enough to make exploitation 52 52 - * extremly difficult. 52 52 + * extremely difficult. 53 53 */ 54 54 #define RET_DEPTH_SHIFT 5 55 55 #define RSB_RET_STUFF_LOOPS 16 ··· 208 208 209 209 /* 210 210 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should 211 211 - * eventually turn into it's own annotation. 211 211 + * eventually turn into its own annotation. 212 212 */ 213 213 .macro VALIDATE_UNRET_END 214 214 #if defined(CONFIG_NOINSTR_VALIDATION) && \

+1 -1

arch/x86/include/asm/pgtable_64.h

reviewed

··· 203 203 * F (2) in swp entry is used to record when a pagetable is 204 204 * writeprotected by userfaultfd WP support. 205 205 * 206 206 - * E (3) in swp entry is used to rememeber PG_anon_exclusive. 206 206 + * E (3) in swp entry is used to remember PG_anon_exclusive. 207 207 * 208 208 * Bit 7 in swp entry should be 0 because pmd_present checks not only P, 209 209 * but also L and G.

-2

arch/x86/include/asm/setup.h

reviewed

··· 31 31 #include <asm/bootparam.h> 32 32 #include <asm/x86_init.h> 33 33 34 34 - extern u64 relocated_ramdisk; 35 35 - 36 34 /* Interrupt control for vSMPowered x86_64 systems */ 37 35 #ifdef CONFIG_X86_64 38 36 void vsmp_init(void);

+1 -1

arch/x86/include/asm/uv/uv_hub.h

reviewed

··· 653 653 return uv_socket_to_node(blade); 654 654 } 655 655 656 656 - /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 656 656 + /* Blade number of current cpu. Numbered 0 .. <#blades -1> */ 657 657 static inline int uv_numa_blade_id(void) 658 658 { 659 659 return uv_hub_info->numa_blade_id;

+1 -1

arch/x86/include/asm/vdso/gettimeofday.h

reviewed

··· 321 321 u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult) 322 322 { 323 323 /* 324 324 - * Due to the MSB/Sign-bit being used as invald marker (see 324 324 + * Due to the MSB/Sign-bit being used as invalid marker (see 325 325 * arch_vdso_cycles_valid() above), the effective mask is S64_MAX. 326 326 */ 327 327 u64 delta = (cycles - last) & S64_MAX;

+1 -1

arch/x86/include/asm/xen/interface_64.h

reviewed

··· 61 61 * RING1 -> RING3 kernel mode. 62 62 * RING2 -> RING3 kernel mode. 63 63 * RING3 -> RING3 user mode. 64 64 - * However RING0 indicates that the guest kernel should return to iteself 64 64 + * However RING0 indicates that the guest kernel should return to itself 65 65 * directly with 66 66 * orb $3,1*8(%rsp) 67 67 * iretq

+1 -1

arch/x86/include/uapi/asm/amd_hsmp.h

reviewed

··· 238 238 /* 239 239 * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1 240 240 * input: args[0] = DIMM address[7:0] 241 241 - * output: args[0] = temperature in degree celcius[31:21] + update rate in ms[16:8] + 241 241 + * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] + 242 242 * DIMM address[7:0] 243 243 */ 244 244 {1, 1, HSMP_GET},

+1 -1

arch/x86/kernel/alternative.c

reviewed

··· 1906 1906 * Note that the caller must ensure that if the modified code is part of a 1907 1907 * module, the module would not be removed during poking. This can be achieved 1908 1908 * by registering a module notifier, and ordering module removal and patching 1909 1909 - * trough a mutex. 1909 1909 + * through a mutex. 1910 1910 */ 1911 1911 void *text_poke(void *addr, const void *opcode, size_t len) 1912 1912 {

+1 -1

arch/x86/kernel/amd_gart_64.c

reviewed

··· 776 776 iommu_size >> PAGE_SHIFT); 777 777 /* 778 778 * Tricky. The GART table remaps the physical memory range, 779 779 - * so the CPU wont notice potential aliases and if the memory 779 779 + * so the CPU won't notice potential aliases and if the memory 780 780 * is remapped to UC later on, we might surprise the PCI devices 781 781 * with a stray writeout of a cacheline. So play it sure and 782 782 * do an explicit, full-scale wbinvd() _after_ having marked all

+1 -1

arch/x86/kernel/apic/Makefile

reviewed

··· 4 4 # 5 5 6 6 # Leads to non-deterministic coverage that is not a function of syscall inputs. 7 7 - # In particualr, smp_apic_timer_interrupt() is called in random places. 7 7 + # In particular, smp_apic_timer_interrupt() is called in random places. 8 8 KCOV_INSTRUMENT := n 9 9 10 10 obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o init.o

+1 -1

arch/x86/kernel/apic/apic.c

reviewed

··· 782 782 783 783 /* 784 784 * If interrupt delivery mode is legacy PIC or virtual wire without 785 785 - * configuration, the local APIC timer wont be set up. Make sure 785 785 + * configuration, the local APIC timer won't be set up. Make sure 786 786 * that the PIT is initialized. 787 787 */ 788 788 if (apic_intr_mode == APIC_PIC ||

+2 -2

arch/x86/kernel/apic/vector.c

reviewed

··· 738 738 void lapic_assign_legacy_vector(unsigned int irq, bool replace) 739 739 { 740 740 /* 741 741 - * Use assign system here so it wont get accounted as allocated 742 742 - * and moveable in the cpu hotplug check and it prevents managed 741 741 + * Use assign system here so it won't get accounted as allocated 742 742 + * and movable in the cpu hotplug check and it prevents managed 743 743 * irq reservation from touching it. 744 744 */ 745 745 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);

+10 -4

arch/x86/kernel/cpu/mtrr/generic.c

reviewed

··· 428 428 * from the x86_init.hyper.init_platform() hook. It can be called only once. 429 429 * The MTRR state can't be changed afterwards. To ensure that, X86_FEATURE_MTRR 430 430 * is cleared. 431 431 + * 432 432 + * @var: MTRR variable range array to use 433 433 + * @num_var: length of the @var array 434 434 + * @def_type: default caching type 431 435 */ 432 436 void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, 433 437 mtrr_type def_type) ··· 496 492 /** 497 493 * mtrr_type_lookup - look up memory type in MTRR 498 494 * 495 495 + * @start: Begin of the physical address range 496 496 + * @end: End of the physical address range 497 497 + * @uniform: output argument: 498 498 + * - 1: the returned MTRR type is valid for the whole region 499 499 + * - 0: otherwise 500 500 + * 499 501 * Return Values: 500 502 * MTRR_TYPE_(type) - The effective MTRR type for the region 501 503 * MTRR_TYPE_INVALID - MTRR is disabled 502 502 - * 503 503 - * Output Argument: 504 504 - * uniform - Set to 1 when the returned MTRR type is valid for the whole 505 505 - * region, set to 0 else. 506 504 */ 507 505 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 508 506 {

+1 -1

arch/x86/kernel/cpu/sgx/ioctl.c

reviewed

··· 581 581 * 582 582 * Flush any outstanding enqueued EADD operations and perform EINIT. The 583 583 * Launch Enclave Public Key Hash MSRs are rewritten as necessary to match 584 584 - * the enclave's MRSIGNER, which is caculated from the provided sigstruct. 584 584 + * the enclave's MRSIGNER, which is calculated from the provided sigstruct. 585 585 * 586 586 * Return: 587 587 * - 0: Success.

+1 -1

arch/x86/kernel/fpu/core.c

reviewed

··· 308 308 * Must be invoked from KVM after a VMEXIT before enabling interrupts when 309 309 * XFD write emulation is disabled. This is required because the guest can 310 310 * freely modify XFD and the state at VMEXIT is not guaranteed to be the 311 311 - * same as the state on VMENTER. So software state has to be udpated before 311 311 + * same as the state on VMENTER. So software state has to be updated before 312 312 * any operation which depends on it can take place. 313 313 * 314 314 * Note: It can be invoked unconditionally even when write emulation is

+3 -3

arch/x86/kernel/head_64.S

reviewed

··· 204 204 /* Enable PAE mode, PSE, PGE and LA57 */ 205 205 orl $(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx 206 206 #ifdef CONFIG_X86_5LEVEL 207 207 - testl $1, __pgtable_l5_enabled(%rip) 207 207 + testb $1, __pgtable_l5_enabled(%rip) 208 208 jz 1f 209 209 orl $X86_CR4_LA57, %ecx 210 210 1: ··· 218 218 * Switch to new page-table 219 219 * 220 220 * For the boot CPU this switches to early_top_pgt which still has the 221 221 - * indentity mappings present. The secondary CPUs will switch to the 221 221 + * identity mappings present. The secondary CPUs will switch to the 222 222 * init_top_pgt here, away from the trampoline_pgd and unmap the 223 223 - * indentity mapped ranges. 223 223 + * identity mapped ranges. 224 224 */ 225 225 movq %rax, %cr3 226 226

+2 -2

arch/x86/kernel/hpet.c

reviewed

··· 707 707 708 708 hpet_base.nr_clockevents = 0; 709 709 710 710 - /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */ 710 710 + /* No point if MSI is disabled or CPU has an Always Running APIC Timer */ 711 711 if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT)) 712 712 return; 713 713 ··· 965 965 * and per CPU timer interrupts. 966 966 * 967 967 * The probability that this problem is going to be solved in the 968 968 - * forseeable future is close to zero, so the kernel has to be cluttered 968 968 + * foreseeable future is close to zero, so the kernel has to be cluttered 969 969 * with heuristics to keep up with the ever growing amount of hardware and 970 970 * firmware trainwrecks. Hopefully some day hardware people will understand 971 971 * that the approach of "This can be fixed in software" is not sustainable.

+1 -1

arch/x86/kernel/kvm.c

reviewed

··· 942 942 * Reset the host's shared pages list related to kernel 943 943 * specific page encryption status settings before we load a 944 944 * new kernel by kexec. Reset the page encryption status 945 945 - * during early boot intead of just before kexec to avoid SMP 945 945 + * during early boot instead of just before kexec to avoid SMP 946 946 * races during kvm_pv_guest_cpu_reboot(). 947 947 * NOTE: We cannot reset the complete shared pages list 948 948 * here as we need to retain the UEFI/OVMF firmware

+1 -1

arch/x86/kernel/kvmclock.c

reviewed

··· 42 42 } 43 43 early_param("no-kvmclock-vsyscall", parse_no_kvmclock_vsyscall); 44 44 45 45 - /* Aligned to page sizes to match whats mapped via vsyscalls to userspace */ 45 45 + /* Aligned to page sizes to match what's mapped via vsyscalls to userspace */ 46 46 #define HVC_BOOT_ARRAY_SIZE \ 47 47 (PAGE_SIZE / sizeof(struct pvclock_vsyscall_time_info)) 48 48

+3 -3

arch/x86/kernel/ldt.c

reviewed

··· 7 7 * This handles calls from both 32bit and 64bit mode. 8 8 * 9 9 * Lock order: 10 10 - * contex.ldt_usr_sem 10 10 + * context.ldt_usr_sem 11 11 * mmap_lock 12 12 * context.lock 13 13 */ ··· 49 49 /* 50 50 * Any change to mm->context.ldt is followed by an IPI to all 51 51 * CPUs with the mm active. The LDT will not be freed until 52 52 - * after the IPI is handled by all such CPUs. This means that, 52 52 + * after the IPI is handled by all such CPUs. This means that 53 53 * if the ldt_struct changes before we return, the values we see 54 54 * will be safe, and the new values will be loaded before we run 55 55 * any user code. ··· 685 685 } 686 686 /* 687 687 * The SYSCALL_DEFINE() macros give us an 'unsigned long' 688 688 - * return type, but tht ABI for sys_modify_ldt() expects 688 688 + * return type, but the ABI for sys_modify_ldt() expects 689 689 * 'int'. This cast gives us an int-sized value in %rax 690 690 * for the return code. The 'unsigned' is necessary so 691 691 * the compiler does not try to sign-extend the negative

+1 -1

arch/x86/kernel/process.c

reviewed

··· 477 477 /* 478 478 * Make sure that the TSS limit is covering the IO bitmap. It might have 479 479 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 480 480 - * access from user space to trigger a #GP because tbe bitmap is outside 480 480 + * access from user space to trigger a #GP because the bitmap is outside 481 481 * the TSS limit. 482 482 */ 483 483 refresh_tss_limit();

+1 -3

arch/x86/kernel/setup.c

reviewed

··· 226 226 _brk_start = 0; 227 227 } 228 228 229 229 - u64 relocated_ramdisk; 230 230 - 231 229 #ifdef CONFIG_BLK_DEV_INITRD 232 230 233 231 static u64 __init get_ramdisk_image(void) ··· 259 261 u64 area_size = PAGE_ALIGN(ramdisk_size); 260 262 261 263 /* We need to move the initrd down into directly mapped mem */ 262 262 - relocated_ramdisk = memblock_phys_alloc_range(area_size, PAGE_SIZE, 0, 264 264 + u64 relocated_ramdisk = memblock_phys_alloc_range(area_size, PAGE_SIZE, 0, 263 265 PFN_PHYS(max_pfn_mapped)); 264 266 if (!relocated_ramdisk) 265 267 panic("Cannot find place for new RAMDISK of size %lld\n",

+1 -1

arch/x86/kernel/sev-shared.c

reviewed

··· 96 96 /* Tell the hypervisor what went wrong. */ 97 97 val |= GHCB_SEV_TERM_REASON(set, reason); 98 98 99 99 - /* Request Guest Termination from Hypvervisor */ 99 99 + /* Request Guest Termination from Hypervisor */ 100 100 sev_es_wr_ghcb_msr(val); 101 101 VMGEXIT(); 102 102

+1 -1

arch/x86/kvm/cpuid.c

reviewed

··· 105 105 106 106 /* 107 107 * If the index isn't significant, use the first entry with a 108 108 - * matching function. It's userspace's responsibilty to not 108 108 + * matching function. It's userspace's responsibility to not 109 109 * provide "duplicate" entries in all cases. 110 110 */ 111 111 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)

+2 -2

arch/x86/kvm/mmu/mmu.c

reviewed

··· 987 987 988 988 /* 989 989 * The head descriptor is empty. If there are no tail descriptors, 990 990 - * nullify the rmap head to mark the list as emtpy, else point the rmap 990 990 + * nullify the rmap head to mark the list as empty, else point the rmap 991 991 * head at the next descriptor, i.e. the new head. 992 992 */ 993 993 if (!head_desc->more) ··· 6544 6544 kvm_tdp_mmu_try_split_huge_pages(kvm, memslot, start, end, target_level, false); 6545 6545 6546 6546 /* 6547 6547 - * A TLB flush is unnecessary at this point for the same resons as in 6547 6547 + * A TLB flush is unnecessary at this point for the same reasons as in 6548 6548 * kvm_mmu_slot_try_split_huge_pages(). 6549 6549 */ 6550 6550 }

+1 -1

arch/x86/kvm/mmu/tdp_iter.c

reviewed

··· 146 146 * Step to the next SPTE in a pre-order traversal of the paging structure. 147 147 * To get to the next SPTE, the iterator either steps down towards the goal 148 148 * GFN, if at a present, non-last-level SPTE, or over to a SPTE mapping a 149 149 - * highter GFN. 149 149 + * higher GFN. 150 150 * 151 151 * The basic algorithm is as follows: 152 152 * 1. If the current SPTE is a non-last-level SPTE, step down into the page

+1 -1

arch/x86/kvm/svm/svm.c

reviewed

··· 4744 4744 * Emulation is possible for SEV guests if and only if a prefilled 4745 4745 * buffer containing the bytes of the intercepted instruction is 4746 4746 * available. SEV guest memory is encrypted with a guest specific key 4747 4747 - * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and 4747 4747 + * and cannot be decrypted by KVM, i.e. KVM would read ciphertext and 4748 4748 * decode garbage. 4749 4749 * 4750 4750 * If KVM is NOT trying to simply skip an instruction, inject #UD if

+1 -1

arch/x86/kvm/vmx/nested.c

reviewed

··· 6561 6561 * code was changed such that flag signals vmcs12 should 6562 6562 * be copied into eVMCS in guest memory. 6563 6563 * 6564 6564 - * To preserve backwards compatability, allow user 6564 6564 + * To preserve backwards compatibility, allow user 6565 6565 * to set this flag even when there is no VMXON region. 6566 6566 */ 6567 6567 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS)

+1 -1

arch/x86/kvm/vmx/vmx.c

reviewed

··· 1809 1809 * do generate error codes with bits 31:16 set, and so KVM's 1810 1810 * ABI lets userspace shove in arbitrary 32-bit values. Drop 1811 1811 * the upper bits to avoid VM-Fail, losing information that 1812 1812 - * does't really exist is preferable to killing the VM. 1812 1812 + * doesn't really exist is preferable to killing the VM. 1813 1813 */ 1814 1814 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, (u16)ex->error_code); 1815 1815 intr_info |= INTR_INFO_DELIVER_CODE_MASK;

+3 -3

arch/x86/kvm/x86.c

reviewed

··· 10165 10165 * 10166 10166 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip 10167 10167 * the instruction or inject an exception, then KVM can incorrecty inject a new 10168 10168 - * asynchrounous event if the event became pending after the CPU fetched the 10168 10168 + * asynchronous event if the event became pending after the CPU fetched the 10169 10169 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation) 10170 10170 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be 10171 10171 * injected on the restarted instruction instead of being deferred until the ··· 10186 10186 int r; 10187 10187 10188 10188 /* 10189 10189 - * Process nested events first, as nested VM-Exit supercedes event 10189 10189 + * Process nested events first, as nested VM-Exit supersedes event 10190 10190 * re-injection. If there's an event queued for re-injection, it will 10191 10191 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit. 10192 10192 */ ··· 10884 10884 /* 10885 10885 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10886 10886 * update must kick and wait for all vCPUs before toggling the 10887 10887 - * per-VM state, and responsing vCPUs must wait for the update 10887 10887 + * per-VM state, and responding vCPUs must wait for the update 10888 10888 * to complete before servicing KVM_REQ_APICV_UPDATE. 10889 10889 */ 10890 10890 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&

+1 -1

arch/x86/lib/delay.c

reviewed

··· 128 128 129 129 delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles); 130 130 /* 131 131 - * Use cpu_tss_rw as a cacheline-aligned, seldomly accessed per-cpu 131 131 + * Use cpu_tss_rw as a cacheline-aligned, seldom accessed per-cpu 132 132 * variable as the monitor target. 133 133 */ 134 134 __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);

+3 -3

arch/x86/mm/init_64.c

reviewed

··· 1013 1013 return; 1014 1014 } 1015 1015 1016 1016 - /* free a pte talbe */ 1016 1016 + /* free a pte table */ 1017 1017 free_pagetable(pmd_page(*pmd), 0); 1018 1018 spin_lock(&init_mm.page_table_lock); 1019 1019 pmd_clear(pmd); ··· 1031 1031 return; 1032 1032 } 1033 1033 1034 1034 - /* free a pmd talbe */ 1034 1034 + /* free a pmd table */ 1035 1035 free_pagetable(pud_page(*pud), 0); 1036 1036 spin_lock(&init_mm.page_table_lock); 1037 1037 pud_clear(pud); ··· 1049 1049 return; 1050 1050 } 1051 1051 1052 1052 - /* free a pud talbe */ 1052 1052 + /* free a pud table */ 1053 1053 free_pagetable(p4d_page(*p4d), 0); 1054 1054 spin_lock(&init_mm.page_table_lock); 1055 1055 p4d_clear(p4d);

+1 -1

arch/x86/mm/pat/memtype.c

reviewed

··· 14 14 * memory ranges: uncached, write-combining, write-through, write-protected, 15 15 * and the most commonly used and default attribute: write-back caching. 16 16 * 17 17 - * PAT support supercedes and augments MTRR support in a compatible fashion: MTRR is 17 17 + * PAT support supersedes and augments MTRR support in a compatible fashion: MTRR is 18 18 * a hardware interface to enumerate a limited number of physical memory ranges 19 19 * and set their caching attributes explicitly, programmed into the CPU via MSRs. 20 20 * Even modern CPUs have MTRRs enabled - but these are typically not touched

+2 -2

arch/x86/mm/pat/set_memory.c

reviewed

··· 1621 1621 1622 1622 /* 1623 1623 * We need to keep the pfn from the existing PTE, 1624 1624 - * after all we're only going to change it's attributes 1624 1624 + * after all we're only going to change its attributes 1625 1625 * not the memory it points to 1626 1626 */ 1627 1627 new_pte = pfn_pte(pfn, new_prot); ··· 2447 2447 /* 2448 2448 * The typical sequence for unmapping is to find a pte through 2449 2449 * lookup_address_in_pgd() (ideally, it should never return NULL because 2450 2450 - * the address is already mapped) and change it's protections. As pfn is 2450 2450 + * the address is already mapped) and change its protections. As pfn is 2451 2451 * the *target* of a mapping, it's not useful while unmapping. 2452 2452 */ 2453 2453 struct cpa_data cpa = {

+1 -1

arch/x86/mm/pti.c

reviewed

··· 6 6 * 7 7 * https://github.com/IAIK/KAISER 8 8 * 9 9 - * The original work was written by and and signed off by for the Linux 9 9 + * The original work was written by and signed off by for the Linux 10 10 * kernel by: 11 11 * 12 12 * Signed-off-by: Richard Fellner <richard.fellner@student.tugraz.at>

+1 -1

arch/x86/mm/tlb.c

reviewed

··· 355 355 356 356 /* 357 357 * Validate that it is not running on an SMT sibling as this would 358 358 - * make the excercise pointless because the siblings share L1D. If 358 358 + * make the exercise pointless because the siblings share L1D. If 359 359 * it runs on a SMT sibling, notify it with SIGBUS on return to 360 360 * user/guest 361 361 */

+1 -1

arch/x86/net/bpf_jit_comp.c

reviewed

··· 2143 2143 } else { 2144 2144 /* Only copy the arguments on-stack to current 2145 2145 * 'stack_size' and ignore the regs, used to 2146 2146 - * prepare the arguments on-stack for orign call. 2146 2146 + * prepare the arguments on-stack for origin call. 2147 2147 */ 2148 2148 if (for_call_origin) { 2149 2149 nr_regs += arg_regs;

+1 -1

arch/x86/net/bpf_jit_comp32.c

reviewed

··· 1194 1194 #define PROLOGUE_SIZE 35 1195 1195 1196 1196 /* 1197 1197 - * Emit prologue code for BPF program and check it's size. 1197 1197 + * Emit prologue code for BPF program and check its size. 1198 1198 * bpf_tail_call helper will skip it while jumping into another program. 1199 1199 */ 1200 1200 static void emit_prologue(u8 **pprog, u32 stack_depth)

+1 -1

arch/x86/platform/intel-quark/imr_selftest.c

reviewed

··· 6 6 * Copyright(c) 2015 Bryan O'Donoghue <pure.logic@nexus-software.ie> 7 7 * 8 8 * IMR self test. The purpose of this module is to run a set of tests on the 9 9 - * IMR API to validate it's sanity. We check for overlapping, reserved 9 9 + * IMR API to validate its sanity. We check for overlapping, reserved 10 10 * addresses and setup/teardown sanity. 11 11 * 12 12 */

+1 -1

arch/x86/platform/pvh/head.S

reviewed

··· 42 42 * Bit 8 (TF) must be cleared. Other bits are all unspecified. 43 43 * 44 44 * All other processor registers and flag bits are unspecified. The OS is in 45 45 - * charge of setting up it's own stack, GDT and IDT. 45 45 + * charge of setting up its own stack, GDT and IDT. 46 46 */ 47 47 48 48 #define PVH_GDT_ENTRY_CS 1

+1 -1

arch/x86/platform/uv/uv_nmi.c

reviewed

··· 741 741 this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE); 742 742 } 743 743 744 744 - /* Trigger a slave CPU to dump it's state */ 744 744 + /* Trigger a slave CPU to dump its state */ 745 745 static void uv_nmi_trigger_dump(int cpu) 746 746 { 747 747 int retry = uv_nmi_trigger_delay;

+1 -1

arch/x86/platform/uv/uv_time.c

reviewed

··· 270 270 * Read the RTC. 271 271 * 272 272 * Starting with HUB rev 2.0, the UV RTC register is replicated across all 273 273 - * cachelines of it's own page. This allows faster simultaneous reads 273 273 + * cachelines of its own page. This allows faster simultaneous reads 274 274 * from a given socket. 275 275 */ 276 276 static u64 uv_read_rtc(struct clocksource *cs)

+1 -1

arch/x86/realmode/init.c

reviewed

··· 61 61 set_real_mode_mem(mem); 62 62 63 63 /* 64 64 - * Unconditionally reserve the entire fisrt 1M, see comment in 64 64 + * Unconditionally reserve the entire first 1M, see comment in 65 65 * setup_arch(). 66 66 */ 67 67 memblock_reserve(0, SZ_1M);

+1 -1

arch/x86/xen/mmu_pv.c

reviewed

··· 34 34 * would need to validate the whole pagetable before going on. 35 35 * Naturally, this is quite slow. The solution is to "pin" a 36 36 * pagetable, which enforces all the constraints on the pagetable even 37 37 - * when it is not actively in use. This menas that Xen can be assured 37 37 + * when it is not actively in use. This means that Xen can be assured 38 38 * that it is still valid when you do load it into %cr3, and doesn't 39 39 * need to revalidate it. 40 40 *