Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf_urgent_for_v5.18_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Borislav Petkov:
- A couple of fixes to cgroup-related handling of perf events
- A couple of fixes to event encoding on Sapphire Rapids
- Pass event caps of inherited events so that perf doesn't fail wrongly
at fork()
- Add support for a new Raptor Lake CPU
* tag 'perf_urgent_for_v5.18_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/core: Always set cpuctx cgrp when enable cgroup event
perf/core: Fix perf_cgroup_switch()
perf/core: Use perf_cgroup_info->active to check if cgroup is active
perf/core: Don't pass task around when ctx sched in
perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
perf/x86/intel: Don't extend the pseudo-encoding to GP counters
perf/core: Inherit event_caps
perf/x86/uncore: Add Raptor Lake uncore support
perf/x86/msr: Add Raptor Lake CPU support
perf/x86/cstate: Add Raptor Lake support
perf/x86: Add Intel Raptor Lake support
+101
-169
+7
-2
arch/x86/events/intel/core.c
+7
-2
arch/x86/events/intel/core.c
···
302
302
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
303
303
INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
304
304
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
305
-
INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
305
+
INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
306
306
INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
307
307
INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
308
308
EVENT_EXTRA_END
···
5536
5536
/* Disabled fixed counters which are not in CPUID */
5537
5537
c->idxmsk64 &= intel_ctrl;
5538
5538
5539
-
if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
5539
+
/*
5540
+
* Don't extend the pseudo-encoding to the
5541
+
* generic counters
5542
+
*/
5543
+
if (!use_fixed_pseudo_encoding(c->code))
5540
5544
c->idxmsk64 |= (1ULL << num_counters) - 1;
5541
5545
}
5542
5546
c->idxmsk64 &=
···
6216
6212
6217
6213
case INTEL_FAM6_ALDERLAKE:
6218
6214
case INTEL_FAM6_ALDERLAKE_L:
6215
+
case INTEL_FAM6_RAPTORLAKE:
6219
6216
/*
6220
6217
* Alder Lake has 2 types of CPU, core and atom.
6221
6218
*
+12
-10
arch/x86/events/intel/cstate.c
+12
-10
arch/x86/events/intel/cstate.c
···
40
40
* Model specific counters:
41
41
* MSR_CORE_C1_RES: CORE C1 Residency Counter
42
42
* perf code: 0x00
43
-
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL
43
+
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
44
44
* Scope: Core (each processor core has a MSR)
45
45
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
46
46
* perf code: 0x01
···
51
51
* perf code: 0x02
52
52
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
53
53
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
54
-
* TGL,TNT,RKL,ADL
54
+
* TGL,TNT,RKL,ADL,RPL
55
55
* Scope: Core
56
56
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
57
57
* perf code: 0x03
58
58
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
59
-
* ICL,TGL,RKL,ADL
59
+
* ICL,TGL,RKL,ADL,RPL
60
60
* Scope: Core
61
61
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
62
62
* perf code: 0x00
63
63
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
64
-
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL
64
+
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
65
+
* RPL
65
66
* Scope: Package (physical package)
66
67
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
67
68
* perf code: 0x01
68
69
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
69
70
* GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
70
-
* ADL
71
+
* ADL,RPL
71
72
* Scope: Package (physical package)
72
73
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
73
74
* perf code: 0x02
74
75
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
75
76
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
76
-
* TGL,TNT,RKL,ADL
77
+
* TGL,TNT,RKL,ADL,RPL
77
78
* Scope: Package (physical package)
78
79
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
79
80
* perf code: 0x03
80
81
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
81
-
* KBL,CML,ICL,TGL,RKL,ADL
82
+
* KBL,CML,ICL,TGL,RKL,ADL,RPL
82
83
* Scope: Package (physical package)
83
84
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
84
85
* perf code: 0x04
85
86
* Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
86
-
* ADL
87
+
* ADL,RPL
87
88
* Scope: Package (physical package)
88
89
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
89
90
* perf code: 0x05
90
91
* Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
91
-
* ADL
92
+
* ADL,RPL
92
93
* Scope: Package (physical package)
93
94
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
94
95
* perf code: 0x06
95
96
* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
96
-
* TNT,RKL,ADL
97
+
* TNT,RKL,ADL,RPL
97
98
* Scope: Package (physical package)
98
99
*
99
100
*/
···
681
680
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &icl_cstates),
682
681
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_cstates),
683
682
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_cstates),
683
+
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates),
684
684
{ },
685
685
};
686
686
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
+1
arch/x86/events/intel/uncore.c
+1
arch/x86/events/intel/uncore.c
···
1828
1828
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rkl_uncore_init),
1829
1829
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_uncore_init),
1830
1830
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_uncore_init),
1831
+
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_uncore_init),
1831
1832
X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init),
1832
1833
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init),
1833
1834
{},
+20
arch/x86/events/intel/uncore_snb.c
+20
arch/x86/events/intel/uncore_snb.c
···
79
79
#define PCI_DEVICE_ID_INTEL_ADL_14_IMC 0x4650
80
80
#define PCI_DEVICE_ID_INTEL_ADL_15_IMC 0x4668
81
81
#define PCI_DEVICE_ID_INTEL_ADL_16_IMC 0x4670
82
+
#define PCI_DEVICE_ID_INTEL_RPL_1_IMC 0xA700
83
+
#define PCI_DEVICE_ID_INTEL_RPL_2_IMC 0xA702
84
+
#define PCI_DEVICE_ID_INTEL_RPL_3_IMC 0xA706
85
+
#define PCI_DEVICE_ID_INTEL_RPL_4_IMC 0xA709
82
86
83
87
/* SNB event control */
84
88
#define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
···
1408
1404
},
1409
1405
{ /* IMC */
1410
1406
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_16_IMC),
1407
+
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1408
+
},
1409
+
{ /* IMC */
1410
+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_1_IMC),
1411
+
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1412
+
},
1413
+
{ /* IMC */
1414
+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_2_IMC),
1415
+
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1416
+
},
1417
+
{ /* IMC */
1418
+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_3_IMC),
1419
+
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1420
+
},
1421
+
{ /* IMC */
1422
+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_4_IMC),
1411
1423
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1412
1424
},
1413
1425
{ /* end: all zeroes */ }
+1
arch/x86/events/msr.c
+1
arch/x86/events/msr.c
+5
arch/x86/include/asm/perf_event.h
+5
arch/x86/include/asm/perf_event.h
···
241
241
#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
242
242
#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
243
243
244
+
static inline bool use_fixed_pseudo_encoding(u64 code)
245
+
{
246
+
return !(code & 0xff);
247
+
}
248
+
244
249
/*
245
250
* We model BTS tracing as another fixed-mode PMC.
246
251
*
+55
-157
kernel/events/core.c
+55
-157
kernel/events/core.c
···
574
574
enum event_type_t event_type);
575
575
576
576
static void cpu_ctx_sched_in(struct perf_cpu_context *cpuctx,
577
-
enum event_type_t event_type,
578
-
struct task_struct *task);
577
+
enum event_type_t event_type);
579
578
580
579
static void update_context_time(struct perf_event_context *ctx);
581
580
static u64 perf_event_time(struct perf_event *event);
···
780
781
static inline void update_cgrp_time_from_event(struct perf_event *event)
781
782
{
782
783
struct perf_cgroup_info *info;
783
-
struct perf_cgroup *cgrp;
784
784
785
785
/*
786
786
* ensure we access cgroup data only when needed and
···
788
790
if (!is_cgroup_event(event))
789
791
return;
790
792
791
-
cgrp = perf_cgroup_from_task(current, event->ctx);
793
+
info = this_cpu_ptr(event->cgrp->info);
792
794
/*
793
795
* Do not update time when cgroup is not active
794
796
*/
795
-
if (cgroup_is_descendant(cgrp->css.cgroup, event->cgrp->css.cgroup)) {
796
-
info = this_cpu_ptr(event->cgrp->info);
797
+
if (info->active)
797
798
__update_cgrp_time(info, perf_clock(), true);
798
-
}
799
799
}
800
800
801
801
static inline void
802
-
perf_cgroup_set_timestamp(struct task_struct *task,
803
-
struct perf_event_context *ctx)
802
+
perf_cgroup_set_timestamp(struct perf_cpu_context *cpuctx)
804
803
{
805
-
struct perf_cgroup *cgrp;
804
+
struct perf_event_context *ctx = &cpuctx->ctx;
805
+
struct perf_cgroup *cgrp = cpuctx->cgrp;
806
806
struct perf_cgroup_info *info;
807
807
struct cgroup_subsys_state *css;
808
808
···
809
813
* ensure we do not access cgroup data
810
814
* unless we have the cgroup pinned (css_get)
811
815
*/
812
-
if (!task || !ctx->nr_cgroups)
816
+
if (!cgrp)
813
817
return;
814
818
815
-
cgrp = perf_cgroup_from_task(task, ctx);
819
+
WARN_ON_ONCE(!ctx->nr_cgroups);
816
820
817
821
for (css = &cgrp->css; css; css = css->parent) {
818
822
cgrp = container_of(css, struct perf_cgroup, css);
···
824
828
825
829
static DEFINE_PER_CPU(struct list_head, cgrp_cpuctx_list);
826
830
827
-
#define PERF_CGROUP_SWOUT 0x1 /* cgroup switch out every event */
828
-
#define PERF_CGROUP_SWIN 0x2 /* cgroup switch in events based on task */
829
-
830
831
/*
831
832
* reschedule events based on the cgroup constraint of task.
832
-
*
833
-
* mode SWOUT : schedule out everything
834
-
* mode SWIN : schedule in based on cgroup for next
835
833
*/
836
-
static void perf_cgroup_switch(struct task_struct *task, int mode)
834
+
static void perf_cgroup_switch(struct task_struct *task)
837
835
{
836
+
struct perf_cgroup *cgrp;
838
837
struct perf_cpu_context *cpuctx, *tmp;
839
838
struct list_head *list;
840
839
unsigned long flags;
···
840
849
*/
841
850
local_irq_save(flags);
842
851
852
+
cgrp = perf_cgroup_from_task(task, NULL);
853
+
843
854
list = this_cpu_ptr(&cgrp_cpuctx_list);
844
855
list_for_each_entry_safe(cpuctx, tmp, list, cgrp_cpuctx_entry) {
845
856
WARN_ON_ONCE(cpuctx->ctx.nr_cgroups == 0);
857
+
if (READ_ONCE(cpuctx->cgrp) == cgrp)
858
+
continue;
846
859
847
860
perf_ctx_lock(cpuctx, cpuctx->task_ctx);
848
861
perf_pmu_disable(cpuctx->ctx.pmu);
849
862
850
-
if (mode & PERF_CGROUP_SWOUT) {
851
-
cpu_ctx_sched_out(cpuctx, EVENT_ALL);
852
-
/*
853
-
* must not be done before ctxswout due
854
-
* to event_filter_match() in event_sched_out()
855
-
*/
856
-
cpuctx->cgrp = NULL;
857
-
}
863
+
cpu_ctx_sched_out(cpuctx, EVENT_ALL);
864
+
/*
865
+
* must not be done before ctxswout due
866
+
* to update_cgrp_time_from_cpuctx() in
867
+
* ctx_sched_out()
868
+
*/
869
+
cpuctx->cgrp = cgrp;
870
+
/*
871
+
* set cgrp before ctxsw in to allow
872
+
* perf_cgroup_set_timestamp() in ctx_sched_in()
873
+
* to not have to pass task around
874
+
*/
875
+
cpu_ctx_sched_in(cpuctx, EVENT_ALL);
858
876
859
-
if (mode & PERF_CGROUP_SWIN) {
860
-
WARN_ON_ONCE(cpuctx->cgrp);
861
-
/*
862
-
* set cgrp before ctxsw in to allow
863
-
* event_filter_match() to not have to pass
864
-
* task around
865
-
* we pass the cpuctx->ctx to perf_cgroup_from_task()
866
-
* because cgorup events are only per-cpu
867
-
*/
868
-
cpuctx->cgrp = perf_cgroup_from_task(task,
869
-
&cpuctx->ctx);
870
-
cpu_ctx_sched_in(cpuctx, EVENT_ALL, task);
871
-
}
872
877
perf_pmu_enable(cpuctx->ctx.pmu);
873
878
perf_ctx_unlock(cpuctx, cpuctx->task_ctx);
874
879
}
875
880
876
881
local_irq_restore(flags);
877
-
}
878
-
879
-
static inline void perf_cgroup_sched_out(struct task_struct *task,
880
-
struct task_struct *next)
881
-
{
882
-
struct perf_cgroup *cgrp1;
883
-
struct perf_cgroup *cgrp2 = NULL;
884
-
885
-
rcu_read_lock();
886
-
/*
887
-
* we come here when we know perf_cgroup_events > 0
888
-
* we do not need to pass the ctx here because we know
889
-
* we are holding the rcu lock
890
-
*/
891
-
cgrp1 = perf_cgroup_from_task(task, NULL);
892
-
cgrp2 = perf_cgroup_from_task(next, NULL);
893
-
894
-
/*
895
-
* only schedule out current cgroup events if we know
896
-
* that we are switching to a different cgroup. Otherwise,
897
-
* do no touch the cgroup events.
898
-
*/
899
-
if (cgrp1 != cgrp2)
900
-
perf_cgroup_switch(task, PERF_CGROUP_SWOUT);
901
-
902
-
rcu_read_unlock();
903
-
}
904
-
905
-
static inline void perf_cgroup_sched_in(struct task_struct *prev,
906
-
struct task_struct *task)
907
-
{
908
-
struct perf_cgroup *cgrp1;
909
-
struct perf_cgroup *cgrp2 = NULL;
910
-
911
-
rcu_read_lock();
912
-
/*
913
-
* we come here when we know perf_cgroup_events > 0
914
-
* we do not need to pass the ctx here because we know
915
-
* we are holding the rcu lock
916
-
*/
917
-
cgrp1 = perf_cgroup_from_task(task, NULL);
918
-
cgrp2 = perf_cgroup_from_task(prev, NULL);
919
-
920
-
/*
921
-
* only need to schedule in cgroup events if we are changing
922
-
* cgroup during ctxsw. Cgroup events were not scheduled
923
-
* out of ctxsw out if that was not the case.
924
-
*/
925
-
if (cgrp1 != cgrp2)
926
-
perf_cgroup_switch(task, PERF_CGROUP_SWIN);
927
-
928
-
rcu_read_unlock();
929
882
}
930
883
931
884
static int perf_cgroup_ensure_storage(struct perf_event *event,
···
967
1032
*/
968
1033
cpuctx = container_of(ctx, struct perf_cpu_context, ctx);
969
1034
970
-
/*
971
-
* Since setting cpuctx->cgrp is conditional on the current @cgrp
972
-
* matching the event's cgroup, we must do this for every new event,
973
-
* because if the first would mismatch, the second would not try again
974
-
* and we would leave cpuctx->cgrp unset.
975
-
*/
976
-
if (ctx->is_active && !cpuctx->cgrp) {
977
-
struct perf_cgroup *cgrp = perf_cgroup_from_task(current, ctx);
978
-
979
-
if (cgroup_is_descendant(cgrp->css.cgroup, event->cgrp->css.cgroup))
980
-
cpuctx->cgrp = cgrp;
981
-
}
982
-
983
1035
if (ctx->nr_cgroups++)
984
1036
return;
985
1037
1038
+
cpuctx->cgrp = perf_cgroup_from_task(current, ctx);
986
1039
list_add(&cpuctx->cgrp_cpuctx_entry,
987
1040
per_cpu_ptr(&cgrp_cpuctx_list, event->cpu));
988
1041
}
···
992
1069
if (--ctx->nr_cgroups)
993
1070
return;
994
1071
995
-
if (ctx->is_active && cpuctx->cgrp)
996
-
cpuctx->cgrp = NULL;
997
-
1072
+
cpuctx->cgrp = NULL;
998
1073
list_del(&cpuctx->cgrp_cpuctx_entry);
999
1074
}
1000
1075
···
1021
1100
{
1022
1101
}
1023
1102
1024
-
static inline void perf_cgroup_sched_out(struct task_struct *task,
1025
-
struct task_struct *next)
1026
-
{
1027
-
}
1028
-
1029
-
static inline void perf_cgroup_sched_in(struct task_struct *prev,
1030
-
struct task_struct *task)
1031
-
{
1032
-
}
1033
-
1034
1103
static inline int perf_cgroup_connect(pid_t pid, struct perf_event *event,
1035
1104
struct perf_event_attr *attr,
1036
1105
struct perf_event *group_leader)
···
1029
1118
}
1030
1119
1031
1120
static inline void
1032
-
perf_cgroup_set_timestamp(struct task_struct *task,
1033
-
struct perf_event_context *ctx)
1034
-
{
1035
-
}
1036
-
1037
-
static inline void
1038
-
perf_cgroup_switch(struct task_struct *task, struct task_struct *next)
1121
+
perf_cgroup_set_timestamp(struct perf_cpu_context *cpuctx)
1039
1122
{
1040
1123
}
1041
1124
···
1050
1145
1051
1146
static inline void
1052
1147
perf_cgroup_event_disable(struct perf_event *event, struct perf_event_context *ctx)
1148
+
{
1149
+
}
1150
+
1151
+
static void perf_cgroup_switch(struct task_struct *task)
1053
1152
{
1054
1153
}
1055
1154
#endif
···
2622
2713
static void
2623
2714
ctx_sched_in(struct perf_event_context *ctx,
2624
2715
struct perf_cpu_context *cpuctx,
2625
-
enum event_type_t event_type,
2626
-
struct task_struct *task);
2716
+
enum event_type_t event_type);
2627
2717
2628
2718
static void task_ctx_sched_out(struct perf_cpu_context *cpuctx,
2629
2719
struct perf_event_context *ctx,
···
2638
2730
}
2639
2731
2640
2732
static void perf_event_sched_in(struct perf_cpu_context *cpuctx,
2641
-
struct perf_event_context *ctx,
2642
-
struct task_struct *task)
2733
+
struct perf_event_context *ctx)
2643
2734
{
2644
-
cpu_ctx_sched_in(cpuctx, EVENT_PINNED, task);
2735
+
cpu_ctx_sched_in(cpuctx, EVENT_PINNED);
2645
2736
if (ctx)
2646
-
ctx_sched_in(ctx, cpuctx, EVENT_PINNED, task);
2647
-
cpu_ctx_sched_in(cpuctx, EVENT_FLEXIBLE, task);
2737
+
ctx_sched_in(ctx, cpuctx, EVENT_PINNED);
2738
+
cpu_ctx_sched_in(cpuctx, EVENT_FLEXIBLE);
2648
2739
if (ctx)
2649
-
ctx_sched_in(ctx, cpuctx, EVENT_FLEXIBLE, task);
2740
+
ctx_sched_in(ctx, cpuctx, EVENT_FLEXIBLE);
2650
2741
}
2651
2742
2652
2743
/*
···
2695
2788
else if (ctx_event_type & EVENT_PINNED)
2696
2789
cpu_ctx_sched_out(cpuctx, EVENT_FLEXIBLE);
2697
2790
2698
-
perf_event_sched_in(cpuctx, task_ctx, current);
2791
+
perf_event_sched_in(cpuctx, task_ctx);
2699
2792
perf_pmu_enable(cpuctx->ctx.pmu);
2700
2793
}
2701
2794
···
2918
3011
return;
2919
3012
2920
3013
if (!event_filter_match(event)) {
2921
-
ctx_sched_in(ctx, cpuctx, EVENT_TIME, current);
3014
+
ctx_sched_in(ctx, cpuctx, EVENT_TIME);
2922
3015
return;
2923
3016
}
2924
3017
···
2927
3020
* then don't put it on unless the group is on.
2928
3021
*/
2929
3022
if (leader != event && leader->state != PERF_EVENT_STATE_ACTIVE) {
2930
-
ctx_sched_in(ctx, cpuctx, EVENT_TIME, current);
3023
+
ctx_sched_in(ctx, cpuctx, EVENT_TIME);
2931
3024
return;
2932
3025
}
2933
3026
···
3575
3668
* cgroup event are system-wide mode only
3576
3669
*/
3577
3670
if (atomic_read(this_cpu_ptr(&perf_cgroup_events)))
3578
-
perf_cgroup_sched_out(task, next);
3671
+
perf_cgroup_switch(next);
3579
3672
}
3580
3673
3581
3674
/*
···
3772
3865
static void
3773
3866
ctx_sched_in(struct perf_event_context *ctx,
3774
3867
struct perf_cpu_context *cpuctx,
3775
-
enum event_type_t event_type,
3776
-
struct task_struct *task)
3868
+
enum event_type_t event_type)
3777
3869
{
3778
3870
int is_active = ctx->is_active;
3779
3871
···
3784
3878
if (is_active ^ EVENT_TIME) {
3785
3879
/* start ctx time */
3786
3880
__update_context_time(ctx, false);
3787
-
perf_cgroup_set_timestamp(task, ctx);
3881
+
perf_cgroup_set_timestamp(cpuctx);
3788
3882
/*
3789
3883
* CPU-release for the below ->is_active store,
3790
3884
* see __load_acquire() in perf_event_time_now()
···
3815
3909
}
3816
3910
3817
3911
static void cpu_ctx_sched_in(struct perf_cpu_context *cpuctx,
3818
-
enum event_type_t event_type,
3819
-
struct task_struct *task)
3912
+
enum event_type_t event_type)
3820
3913
{
3821
3914
struct perf_event_context *ctx = &cpuctx->ctx;
3822
3915
3823
-
ctx_sched_in(ctx, cpuctx, event_type, task);
3916
+
ctx_sched_in(ctx, cpuctx, event_type);
3824
3917
}
3825
3918
3826
3919
static void perf_event_context_sched_in(struct perf_event_context *ctx,
···
3861
3956
*/
3862
3957
if (!RB_EMPTY_ROOT(&ctx->pinned_groups.tree))
3863
3958
cpu_ctx_sched_out(cpuctx, EVENT_FLEXIBLE);
3864
-
perf_event_sched_in(cpuctx, ctx, task);
3959
+
perf_event_sched_in(cpuctx, ctx);
3865
3960
3866
3961
if (cpuctx->sched_cb_usage && pmu->sched_task)
3867
3962
pmu->sched_task(cpuctx->task_ctx, true);
···
3888
3983
{
3889
3984
struct perf_event_context *ctx;
3890
3985
int ctxn;
3891
-
3892
-
/*
3893
-
* If cgroup events exist on this CPU, then we need to check if we have
3894
-
* to switch in PMU state; cgroup event are system-wide mode only.
3895
-
*
3896
-
* Since cgroup events are CPU events, we must schedule these in before
3897
-
* we schedule in the task events.
3898
-
*/
3899
-
if (atomic_read(this_cpu_ptr(&perf_cgroup_events)))
3900
-
perf_cgroup_sched_in(prev, task);
3901
3986
3902
3987
for_each_task_context_nr(ctxn) {
3903
3988
ctx = task->perf_event_ctxp[ctxn];
···
4162
4267
if (cpu_event)
4163
4268
rotate_ctx(&cpuctx->ctx, cpu_event);
4164
4269
4165
-
perf_event_sched_in(cpuctx, task_ctx, current);
4270
+
perf_event_sched_in(cpuctx, task_ctx);
4166
4271
4167
4272
perf_pmu_enable(cpuctx->ctx.pmu);
4168
4273
perf_ctx_unlock(cpuctx, cpuctx->task_ctx);
···
4234
4339
clone_ctx = unclone_ctx(ctx);
4235
4340
ctx_resched(cpuctx, ctx, event_type);
4236
4341
} else {
4237
-
ctx_sched_in(ctx, cpuctx, EVENT_TIME, current);
4342
+
ctx_sched_in(ctx, cpuctx, EVENT_TIME);
4238
4343
}
4239
4344
perf_ctx_unlock(cpuctx, ctx);
4240
4345
···
11530
11635
11531
11636
event->state = PERF_EVENT_STATE_INACTIVE;
11532
11637
11638
+
if (parent_event)
11639
+
event->event_caps = parent_event->event_caps;
11640
+
11533
11641
if (event->attr.sigtrap)
11534
11642
atomic_set(&event->event_limit, 1);
11535
11643
···
13460
13562
{
13461
13563
struct task_struct *task = info;
13462
13564
rcu_read_lock();
13463
-
perf_cgroup_switch(task, PERF_CGROUP_SWOUT | PERF_CGROUP_SWIN);
13565
+
perf_cgroup_switch(task);
13464
13566
rcu_read_unlock();
13465
13567
return 0;
13466
13568
}