tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd: Add per-ring reset for vcn v5.0.0 use

If there is a problem requiring a reset of the VCN engine, it is better to
reset the VCN engine rather than the entire GPU.

Add a reset callback for the ring which will stop and start VCN if an
issue happens.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250506204948.12048-4-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Mario Limonciello and committed by
Alex Deucher b54695da b8b6e6f1

+16 -1
+16 -1
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
··· 196 196 adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; 197 197 } 198 198 199 - /* TODO: Add queue reset mask when FW fully supports it */ 200 199 adev->vcn.supported_reset = 201 200 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 201 + adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 202 202 203 203 vcn_v5_0_0_alloc_ip_dump(adev); 204 204 ··· 1172 1172 } 1173 1173 } 1174 1174 1175 + static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1176 + { 1177 + struct amdgpu_device *adev = ring->adev; 1178 + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1179 + 1180 + if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1181 + return -EOPNOTSUPP; 1182 + 1183 + vcn_v5_0_0_stop(vinst); 1184 + vcn_v5_0_0_start(vinst); 1185 + 1186 + return amdgpu_ring_test_helper(ring); 1187 + } 1188 + 1175 1189 static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { 1176 1190 .type = AMDGPU_RING_TYPE_VCN_ENC, 1177 1191 .align_mask = 0x3f, ··· 1213 1199 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1214 1200 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1215 1201 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1202 + .reset = vcn_v5_0_0_ring_reset, 1216 1203 }; 1217 1204 1218 1205 /**