tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: gpio: Add Tegra264 support

Extend the existing Tegra186 GPIO controller device tree bindings with
support for the GPIO controller found on Tegra264. The number of pins
is slightly different, but the programming model remains the same.

Add a new header, include/dt-bindings/gpio/nvidia,tegra264-gpio.h,
that defines port IDs as well as the TEGRA264_MAIN_GPIO() helper,
both of which are used in conjunction to create a unique specifier
for each pin.

On Tegra, GPIO wake events are latched and routed via the PMC.
Document the standard DT property, wakeup-parent, which is a phandle to
the PMC interrupt controller that provides the parent wake interrupt
domain for the GPIO controller. If the property is absent the driver
falls back to a compatible-based lookup.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260128085114.1137725-1-pshete@nvidia.com
[Bartosz: fixed whitespace errors]
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

authored by

Prathamesh Shete and committed by
Bartosz Golaszewski b565717e aa7e37fd

+83
+22
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
··· 86 86 - nvidia,tegra234-gpio 87 87 - nvidia,tegra234-gpio-aon 88 88 - nvidia,tegra256-gpio 89 + - nvidia,tegra264-gpio 90 + - nvidia,tegra264-gpio-uphy 91 + - nvidia,tegra264-gpio-aon 89 92 90 93 reg-names: 91 94 items: ··· 112 109 description: The interrupt outputs from the HW block, one per set of 113 110 ports, in the order the HW manual describes them. The number of entries 114 111 required varies depending on compatible value. 112 + 113 + wakeup-parent: 114 + description: Phandle to the parent interrupt controller used for wake-up. On 115 + Tegra, this typically references the PMC interrupt controller. 115 116 116 117 gpio-controller: true 117 118 ··· 164 157 - nvidia,tegra194-gpio 165 158 - nvidia,tegra234-gpio 166 159 - nvidia,tegra256-gpio 160 + - nvidia,tegra264-gpio 161 + - nvidia,tegra264-gpio-uphy 167 162 then: 168 163 properties: 169 164 interrupts: ··· 180 171 - nvidia,tegra186-gpio-aon 181 172 - nvidia,tegra194-gpio-aon 182 173 - nvidia,tegra234-gpio-aon 174 + - nvidia,tegra264-gpio-aon 183 175 then: 184 176 properties: 185 177 interrupts: 186 178 minItems: 1 187 179 maxItems: 4 180 + 181 + - if: 182 + properties: 183 + compatible: 184 + contains: 185 + enum: 186 + - nvidia,tegra264-gpio 187 + - nvidia,tegra264-gpio-uphy 188 + - nvidia,tegra264-gpio-aon 189 + then: 190 + required: 191 + - wakeup-parent 188 192 189 193 required: 190 194 - compatible
+61
include/dt-bindings/gpio/nvidia,tegra264-gpio.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 + /* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ 3 + 4 + /* 5 + * This header provides constants for binding nvidia,tegra264-gpio*. 6 + * 7 + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8 + * provide names for this. 9 + * 10 + * The second cell contains standard flag values specified in gpio.h. 11 + */ 12 + 13 + #ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H 14 + #define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H 15 + 16 + #include <dt-bindings/gpio/gpio.h> 17 + 18 + /* GPIOs implemented by main GPIO controller */ 19 + #define TEGRA264_MAIN_GPIO_PORT_T 0 20 + #define TEGRA264_MAIN_GPIO_PORT_U 1 21 + #define TEGRA264_MAIN_GPIO_PORT_V 2 22 + #define TEGRA264_MAIN_GPIO_PORT_W 3 23 + #define TEGRA264_MAIN_GPIO_PORT_AL 4 24 + #define TEGRA264_MAIN_GPIO_PORT_Y 5 25 + #define TEGRA264_MAIN_GPIO_PORT_Z 6 26 + #define TEGRA264_MAIN_GPIO_PORT_X 7 27 + #define TEGRA264_MAIN_GPIO_PORT_H 8 28 + #define TEGRA264_MAIN_GPIO_PORT_J 9 29 + #define TEGRA264_MAIN_GPIO_PORT_K 10 30 + #define TEGRA264_MAIN_GPIO_PORT_L 11 31 + #define TEGRA264_MAIN_GPIO_PORT_M 12 32 + #define TEGRA264_MAIN_GPIO_PORT_P 13 33 + #define TEGRA264_MAIN_GPIO_PORT_Q 14 34 + #define TEGRA264_MAIN_GPIO_PORT_R 15 35 + #define TEGRA264_MAIN_GPIO_PORT_S 16 36 + #define TEGRA264_MAIN_GPIO_PORT_F 17 37 + #define TEGRA264_MAIN_GPIO_PORT_G 18 38 + 39 + #define TEGRA264_MAIN_GPIO(port, offset) \ 40 + ((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset)) 41 + 42 + /* GPIOs implemented by AON GPIO controller */ 43 + #define TEGRA264_AON_GPIO_PORT_AA 0 44 + #define TEGRA264_AON_GPIO_PORT_BB 1 45 + #define TEGRA264_AON_GPIO_PORT_CC 2 46 + #define TEGRA264_AON_GPIO_PORT_DD 3 47 + #define TEGRA264_AON_GPIO_PORT_EE 4 48 + 49 + #define TEGRA264_AON_GPIO(port, offset) \ 50 + ((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset)) 51 + 52 + #define TEGRA264_UPHY_GPIO_PORT_A 0 53 + #define TEGRA264_UPHY_GPIO_PORT_B 1 54 + #define TEGRA264_UPHY_GPIO_PORT_C 2 55 + #define TEGRA264_UPHY_GPIO_PORT_D 3 56 + #define TEGRA264_UPHY_GPIO_PORT_E 4 57 + 58 + #define TEGRA264_UPHY_GPIO(port, offset) \ 59 + ((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset)) 60 + 61 + #endif