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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: microchip: mpfs: add reset controller
Add a reset controller to PolarFire SoC's clock driver. This reset
controller is registered as an aux device and read/write functions
exported to the drivers namespace so that the reset controller can
access the peripheral device reset register.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
authored by
Conor Dooley
and committed by
Claudiu Beznea
b56bae2d
89b16523
+107
-12
+1
drivers/clk/microchip/Kconfig
+1
drivers/clk/microchip/Kconfig
+98
-12
drivers/clk/microchip/clk-mpfs.c
+98
-12
drivers/clk/microchip/clk-mpfs.c
···
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* Daire McNamara,<daire.mcnamara@microchip.com>
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* Copyright (C) 2020 Microchip Technology Inc. All rights reserved.
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*/
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#include <linux/auxiliary_bus.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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#include <soc/microchip/mpfs.h>
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/* address offset of control registers */
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#define REG_MSSPLL_REF_CR 0x08u
···
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#define MSSPLL_FIXED_DIV 4u
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struct mpfs_clock_data {
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struct device *dev;
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void __iomem *base;
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void __iomem *msspll_base;
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struct clk_hw_onecell_data hw_data;
···
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spin_lock_irqsave(&mpfs_clk_lock, flags);
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reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR);
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val = reg & ~(1u << periph->shift);
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writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR);
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reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
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val = reg | (1u << periph->shift);
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writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
···
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void __iomem *base_addr = periph_hw->sys_base;
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u32 reg;
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reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR);
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if ((reg & (1u << periph->shift)) == 0u) {
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reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
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if (reg & (1u << periph->shift))
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return 1;
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}
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reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
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if (reg & (1u << periph->shift))
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return 1;
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return 0;
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}
···
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return 0;
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}
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/*
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* Peripheral clock resets
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*/
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#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
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u32 mpfs_reset_read(struct device *dev)
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{
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struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
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return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
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}
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EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
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void mpfs_reset_write(struct device *dev, u32 val)
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{
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struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
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writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
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}
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EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
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static void mpfs_reset_unregister_adev(void *_adev)
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{
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struct auxiliary_device *adev = _adev;
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auxiliary_device_delete(adev);
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}
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static void mpfs_reset_adev_release(struct device *dev)
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{
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struct auxiliary_device *adev = to_auxiliary_dev(dev);
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auxiliary_device_uninit(adev);
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kfree(adev);
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}
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static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
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{
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struct auxiliary_device *adev;
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int ret;
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adev = kzalloc(sizeof(*adev), GFP_KERNEL);
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if (!adev)
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return ERR_PTR(-ENOMEM);
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adev->name = "reset-mpfs";
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adev->dev.parent = clk_data->dev;
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adev->dev.release = mpfs_reset_adev_release;
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adev->id = 666u;
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ret = auxiliary_device_init(adev);
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if (ret) {
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kfree(adev);
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return ERR_PTR(ret);
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}
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return adev;
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}
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static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
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{
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struct auxiliary_device *adev;
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int ret;
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adev = mpfs_reset_adev_alloc(clk_data);
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if (IS_ERR(adev))
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return PTR_ERR(adev);
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ret = auxiliary_device_add(adev);
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if (ret) {
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auxiliary_device_uninit(adev);
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return ret;
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}
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return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
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}
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#else /* !CONFIG_RESET_CONTROLLER */
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static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
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{
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return 0;
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}
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#endif /* !CONFIG_RESET_CONTROLLER */
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static int mpfs_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
···
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return PTR_ERR(clk_data->msspll_base);
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clk_data->hw_data.num = num_clks;
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clk_data->dev = dev;
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dev_set_drvdata(dev, clk_data);
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ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
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clk_data);
···
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if (ret)
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return ret;
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return ret;
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return mpfs_reset_controller_register(clk_data);
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}
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static const struct of_device_id mpfs_clk_of_match_table[] = {
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{ .compatible = "microchip,mpfs-clkcfg", },
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{}
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};
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MODULE_DEVICE_TABLE(of, mpfs_clk_match_table);
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MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table);
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static struct platform_driver mpfs_clk_driver = {
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.probe = mpfs_clk_probe,
+8
include/soc/microchip/mpfs.h
+8
include/soc/microchip/mpfs.h
···
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#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
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#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
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u32 mpfs_reset_read(struct device *dev);
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void mpfs_reset_write(struct device *dev, u32 val);
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#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
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#endif /* __SOC_MPFS_H__ */