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arm64/sysreg: Drop ICH_HFGRTR_EL2.ICC_HAPR_EL1 and make RES1

The GICv5 architecture is dropping the ICC_HAPR_EL1 and ICV_HAPR_EL1
system registers. These registers were never added to the sysregs, but
the traps for them were.

Drop the trap bit from the ICH_HFGRTR_EL2 and make it Res1 as per the
upcoming GICv5 spec change. Additionally, update the EL2 setup code to
not attempt to set that bit.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260128175919.3828384-4-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Sascha Bischoff and committed by
Marc Zyngier b583177a 4a03431b

+1 -2
-1
arch/arm64/include/asm/el2_setup.h
··· 225 225 ICH_HFGRTR_EL2_ICC_ICSR_EL1 | \ 226 226 ICH_HFGRTR_EL2_ICC_PCR_EL1 | \ 227 227 ICH_HFGRTR_EL2_ICC_HPPIR_EL1 | \ 228 - ICH_HFGRTR_EL2_ICC_HAPR_EL1 | \ 229 228 ICH_HFGRTR_EL2_ICC_CR0_EL1 | \ 230 229 ICH_HFGRTR_EL2_ICC_IDRn_EL1 | \ 231 230 ICH_HFGRTR_EL2_ICC_APR_EL1)
+1 -1
arch/arm64/tools/sysreg
··· 4579 4579 Field 6 ICC_ICSR_EL1 4580 4580 Field 5 ICC_PCR_EL1 4581 4581 Field 4 ICC_HPPIR_EL1 4582 - Field 3 ICC_HAPR_EL1 4582 + Res1 3 4583 4583 Field 2 ICC_CR0_EL1 4584 4584 Field 1 ICC_IDRn_EL1 4585 4585 Field 0 ICC_APR_EL1