tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2024-05-03' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly fixes, mostly made up from amdgpu and some panel changes.

Otherwise xe, nouveau, vmwgfx and a couple of others, all seems pretty
on track.

amdgpu:
- Fix VRAM memory accounting
- DCN 3.1 fixes
- DCN 2.0 fix
- DCN 3.1.5 fix
- DCN 3.5 fix
- DCN 3.2.1 fix
- DP fixes
- Seamless boot fix
- Fix call order in amdgpu_ttm_move()
- Fix doorbell regression
- Disable panel replay temporarily

amdkfd:
- Flush wq before creating kfd process

xe:
- Fix UAF on rebind worker
- Fix ADL-N display integration

imagination:
- fix page-count macro

nouveau:
- avoid page-table allocation failures
- fix firmware memory allocation

panel:
- ili9341: avoid OF for device properties; respect deferred probe;
fix usage of errno codes

ttm:
- fix status output

vmwgfx:
- fix legacy display unit
- fix read length in fence signalling"

* tag 'drm-fixes-2024-05-03' of https://gitlab.freedesktop.org/drm/kernel: (25 commits)
drm/xe/display: Fix ADL-N detection
drm/panel: ili9341: Use predefined error codes
drm/panel: ili9341: Respect deferred probe
drm/panel: ili9341: Correct use of device property APIs
drm/xe/vm: prevent UAF in rebind_work_func()
drm/amd/display: Disable panel replay by default for now
drm/amdgpu: fix doorbell regression
drm/amdkfd: Flush the process wq before creating a kfd_process
drm/amd/display: Disable seamless boot on 128b/132b encoding
drm/amd/display: Fix DC mode screen flickering on DCN321
drm/amd/display: Add VCO speed parameter for DCN31 FPU
drm/amdgpu: once more fix the call oder in amdgpu_ttm_move() v2
drm/amd/display: Allocate zero bw after bw alloc enable
drm/amd/display: Fix incorrect DSC instance for MST
drm/amd/display: Atom Integrated System Info v2_2 for DCN35
drm/amd/display: Add dtbclk access to dcn315
drm/amd/display: Ensure that dmcub support flag is set for DCN20
drm/amd/display: Handle Y carry-over in VCP X.Y calculation
drm/amdgpu: Fix VRAM memory accounting
drm/vmwgfx: Fix invalid reads in fence signaled events
...

Linus Torvalds b5a66609 9fbc8bdf

+226 -104
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 220 220 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 221 221 kfd_mem_limit.max_ttm_mem_limit) || 222 222 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed > 223 - vram_size - reserved_for_pt)) { 223 + vram_size - reserved_for_pt - atomic64_read(&adev->vram_pin_size))) { 224 224 ret = -ENOMEM; 225 225 goto release; 226 226 }
+9 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 1243 1243 * amdgpu_bo_move_notify - notification about a memory move 1244 1244 * @bo: pointer to a buffer object 1245 1245 * @evict: if this move is evicting the buffer from the graphics address space 1246 + * @new_mem: new resource for backing the BO 1246 1247 * 1247 1248 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1248 1249 * bookkeeping. 1249 1250 * TTM driver callback which is called when ttm moves a buffer. 1250 1251 */ 1251 - void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict) 1252 + void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1253 + bool evict, 1254 + struct ttm_resource *new_mem) 1252 1255 { 1253 1256 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1257 + struct ttm_resource *old_mem = bo->resource; 1254 1258 struct amdgpu_bo *abo; 1255 1259 1256 1260 if (!amdgpu_bo_is_amdgpu_bo(bo)) ··· 1266 1262 amdgpu_bo_kunmap(abo); 1267 1263 1268 1264 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1269 - bo->resource->mem_type != TTM_PL_SYSTEM) 1265 + old_mem && old_mem->mem_type != TTM_PL_SYSTEM) 1270 1266 dma_buf_move_notify(abo->tbo.base.dma_buf); 1271 1267 1272 - /* remember the eviction */ 1273 - if (evict) 1274 - atomic64_inc(&adev->num_evictions); 1268 + /* move_notify is called before move happens */ 1269 + trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, 1270 + old_mem ? old_mem->mem_type : -1); 1275 1271 } 1276 1272 1277 1273 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
··· 328 328 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 329 329 size_t buffer_size, uint32_t *metadata_size, 330 330 uint64_t *flags); 331 - void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict); 331 + void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 332 + bool evict, 333 + struct ttm_resource *new_mem); 332 334 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo); 333 335 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 334 336 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
+29 -25
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 419 419 return false; 420 420 421 421 if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT || 422 - res->mem_type == AMDGPU_PL_PREEMPT) 422 + res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL) 423 423 return true; 424 424 425 425 if (res->mem_type != TTM_PL_VRAM) ··· 481 481 482 482 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 483 483 bo->ttm == NULL)) { 484 + amdgpu_bo_move_notify(bo, evict, new_mem); 484 485 ttm_bo_move_null(bo, new_mem); 485 - goto out; 486 + return 0; 486 487 } 487 488 if (old_mem->mem_type == TTM_PL_SYSTEM && 488 489 (new_mem->mem_type == TTM_PL_TT || 489 490 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 491 + amdgpu_bo_move_notify(bo, evict, new_mem); 490 492 ttm_bo_move_null(bo, new_mem); 491 - goto out; 493 + return 0; 492 494 } 493 495 if ((old_mem->mem_type == TTM_PL_TT || 494 496 old_mem->mem_type == AMDGPU_PL_PREEMPT) && ··· 500 498 return r; 501 499 502 500 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 501 + amdgpu_bo_move_notify(bo, evict, new_mem); 503 502 ttm_resource_free(bo, &bo->resource); 504 503 ttm_bo_assign_mem(bo, new_mem); 505 - goto out; 504 + return 0; 506 505 } 507 506 508 507 if (old_mem->mem_type == AMDGPU_PL_GDS || ··· 515 512 new_mem->mem_type == AMDGPU_PL_OA || 516 513 new_mem->mem_type == AMDGPU_PL_DOORBELL) { 517 514 /* Nothing to save here */ 515 + amdgpu_bo_move_notify(bo, evict, new_mem); 518 516 ttm_bo_move_null(bo, new_mem); 519 - goto out; 517 + return 0; 520 518 } 521 519 522 520 if (bo->type == ttm_bo_type_device && ··· 529 525 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 530 526 } 531 527 532 - if (adev->mman.buffer_funcs_enabled) { 533 - if (((old_mem->mem_type == TTM_PL_SYSTEM && 534 - new_mem->mem_type == TTM_PL_VRAM) || 535 - (old_mem->mem_type == TTM_PL_VRAM && 536 - new_mem->mem_type == TTM_PL_SYSTEM))) { 537 - hop->fpfn = 0; 538 - hop->lpfn = 0; 539 - hop->mem_type = TTM_PL_TT; 540 - hop->flags = TTM_PL_FLAG_TEMPORARY; 541 - return -EMULTIHOP; 542 - } 543 - 544 - r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 545 - } else { 546 - r = -ENODEV; 528 + if (adev->mman.buffer_funcs_enabled && 529 + ((old_mem->mem_type == TTM_PL_SYSTEM && 530 + new_mem->mem_type == TTM_PL_VRAM) || 531 + (old_mem->mem_type == TTM_PL_VRAM && 532 + new_mem->mem_type == TTM_PL_SYSTEM))) { 533 + hop->fpfn = 0; 534 + hop->lpfn = 0; 535 + hop->mem_type = TTM_PL_TT; 536 + hop->flags = TTM_PL_FLAG_TEMPORARY; 537 + return -EMULTIHOP; 547 538 } 539 + 540 + amdgpu_bo_move_notify(bo, evict, new_mem); 541 + if (adev->mman.buffer_funcs_enabled) 542 + r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 543 + else 544 + r = -ENODEV; 548 545 549 546 if (r) { 550 547 /* Check that all memory is CPU accessible */ ··· 560 555 return r; 561 556 } 562 557 563 - trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 564 - out: 565 - /* update statistics */ 558 + /* update statistics after the move */ 559 + if (evict) 560 + atomic64_inc(&adev->num_evictions); 566 561 atomic64_add(bo->base.size, &adev->num_bytes_moved); 567 - amdgpu_bo_move_notify(bo, evict); 568 562 return 0; 569 563 } 570 564 ··· 1563 1559 static void 1564 1560 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1565 1561 { 1566 - amdgpu_bo_move_notify(bo, false); 1562 + amdgpu_bo_move_notify(bo, false, NULL); 1567 1563 } 1568 1564 1569 1565 static struct ttm_device_funcs amdgpu_bo_driver = {
+8
drivers/gpu/drm/amd/amdkfd/kfd_process.c
··· 829 829 if (process) { 830 830 pr_debug("Process already found\n"); 831 831 } else { 832 + /* If the process just called exec(3), it is possible that the 833 + * cleanup of the kfd_process (following the release of the mm 834 + * of the old process image) is still in the cleanup work queue. 835 + * Make sure to drain any job before trying to recreate any 836 + * resource for this process. 837 + */ 838 + flush_workqueue(kfd_process_wq); 839 + 832 840 process = create_process(thread); 833 841 if (IS_ERR(process)) 834 842 goto out;
+12 -9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 4537 4537 /* Determine whether to enable Replay support by default. */ 4538 4538 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 4539 4539 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4540 - case IP_VERSION(3, 1, 4): 4541 - case IP_VERSION(3, 1, 5): 4542 - case IP_VERSION(3, 1, 6): 4543 - case IP_VERSION(3, 2, 0): 4544 - case IP_VERSION(3, 2, 1): 4545 - case IP_VERSION(3, 5, 0): 4546 - case IP_VERSION(3, 5, 1): 4547 - replay_feature_enabled = true; 4548 - break; 4540 + /* 4541 + * Disabled by default due to https://gitlab.freedesktop.org/drm/amd/-/issues/3344 4542 + * case IP_VERSION(3, 1, 4): 4543 + * case IP_VERSION(3, 1, 5): 4544 + * case IP_VERSION(3, 1, 6): 4545 + * case IP_VERSION(3, 2, 0): 4546 + * case IP_VERSION(3, 2, 1): 4547 + * case IP_VERSION(3, 5, 0): 4548 + * case IP_VERSION(3, 5, 1): 4549 + * replay_feature_enabled = true; 4550 + * break; 4551 + */ 4549 4552 default: 4550 4553 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 4551 4554 break;
+36 -12
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
··· 1495 1495 for (i = 0; i < MAX_PIPES; i++) { 1496 1496 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1497 1497 if (pipe_ctx->stream && 1498 - pipe_ctx->stream->link == aconnector->dc_link) 1498 + pipe_ctx->stream->link == aconnector->dc_link && 1499 + pipe_ctx->stream->sink && 1500 + pipe_ctx->stream->sink == aconnector->dc_sink) 1499 1501 break; 1500 1502 } 1501 1503 ··· 1598 1596 for (i = 0; i < MAX_PIPES; i++) { 1599 1597 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1600 1598 if (pipe_ctx->stream && 1601 - pipe_ctx->stream->link == aconnector->dc_link) 1599 + pipe_ctx->stream->link == aconnector->dc_link && 1600 + pipe_ctx->stream->sink && 1601 + pipe_ctx->stream->sink == aconnector->dc_sink) 1602 1602 break; 1603 1603 } 1604 1604 ··· 1685 1681 for (i = 0; i < MAX_PIPES; i++) { 1686 1682 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1687 1683 if (pipe_ctx->stream && 1688 - pipe_ctx->stream->link == aconnector->dc_link) 1684 + pipe_ctx->stream->link == aconnector->dc_link && 1685 + pipe_ctx->stream->sink && 1686 + pipe_ctx->stream->sink == aconnector->dc_sink) 1689 1687 break; 1690 1688 } 1691 1689 ··· 1786 1780 for (i = 0; i < MAX_PIPES; i++) { 1787 1781 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1788 1782 if (pipe_ctx->stream && 1789 - pipe_ctx->stream->link == aconnector->dc_link) 1783 + pipe_ctx->stream->link == aconnector->dc_link && 1784 + pipe_ctx->stream->sink && 1785 + pipe_ctx->stream->sink == aconnector->dc_sink) 1790 1786 break; 1791 1787 } 1792 1788 ··· 1873 1865 for (i = 0; i < MAX_PIPES; i++) { 1874 1866 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1875 1867 if (pipe_ctx->stream && 1876 - pipe_ctx->stream->link == aconnector->dc_link) 1868 + pipe_ctx->stream->link == aconnector->dc_link && 1869 + pipe_ctx->stream->sink && 1870 + pipe_ctx->stream->sink == aconnector->dc_sink) 1877 1871 break; 1878 1872 } 1879 1873 ··· 1974 1964 for (i = 0; i < MAX_PIPES; i++) { 1975 1965 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1976 1966 if (pipe_ctx->stream && 1977 - pipe_ctx->stream->link == aconnector->dc_link) 1967 + pipe_ctx->stream->link == aconnector->dc_link && 1968 + pipe_ctx->stream->sink && 1969 + pipe_ctx->stream->sink == aconnector->dc_sink) 1978 1970 break; 1979 1971 } 1980 1972 ··· 2057 2045 for (i = 0; i < MAX_PIPES; i++) { 2058 2046 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2059 2047 if (pipe_ctx->stream && 2060 - pipe_ctx->stream->link == aconnector->dc_link) 2048 + pipe_ctx->stream->link == aconnector->dc_link && 2049 + pipe_ctx->stream->sink && 2050 + pipe_ctx->stream->sink == aconnector->dc_sink) 2061 2051 break; 2062 2052 } 2063 2053 ··· 2155 2141 for (i = 0; i < MAX_PIPES; i++) { 2156 2142 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2157 2143 if (pipe_ctx->stream && 2158 - pipe_ctx->stream->link == aconnector->dc_link) 2144 + pipe_ctx->stream->link == aconnector->dc_link && 2145 + pipe_ctx->stream->sink && 2146 + pipe_ctx->stream->sink == aconnector->dc_sink) 2159 2147 break; 2160 2148 } 2161 2149 ··· 2236 2220 for (i = 0; i < MAX_PIPES; i++) { 2237 2221 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2238 2222 if (pipe_ctx->stream && 2239 - pipe_ctx->stream->link == aconnector->dc_link) 2223 + pipe_ctx->stream->link == aconnector->dc_link && 2224 + pipe_ctx->stream->sink && 2225 + pipe_ctx->stream->sink == aconnector->dc_sink) 2240 2226 break; 2241 2227 } 2242 2228 ··· 2294 2276 for (i = 0; i < MAX_PIPES; i++) { 2295 2277 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2296 2278 if (pipe_ctx->stream && 2297 - pipe_ctx->stream->link == aconnector->dc_link) 2279 + pipe_ctx->stream->link == aconnector->dc_link && 2280 + pipe_ctx->stream->sink && 2281 + pipe_ctx->stream->sink == aconnector->dc_sink) 2298 2282 break; 2299 2283 } 2300 2284 ··· 2367 2347 for (i = 0; i < MAX_PIPES; i++) { 2368 2348 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2369 2349 if (pipe_ctx->stream && 2370 - pipe_ctx->stream->link == aconnector->dc_link) 2350 + pipe_ctx->stream->link == aconnector->dc_link && 2351 + pipe_ctx->stream->sink && 2352 + pipe_ctx->stream->sink == aconnector->dc_sink) 2371 2353 break; 2372 2354 } 2373 2355 ··· 2440 2418 for (i = 0; i < MAX_PIPES; i++) { 2441 2419 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2442 2420 if (pipe_ctx->stream && 2443 - pipe_ctx->stream->link == aconnector->dc_link) 2421 + pipe_ctx->stream->link == aconnector->dc_link && 2422 + pipe_ctx->stream->sink && 2423 + pipe_ctx->stream->sink == aconnector->dc_sink) 2444 2424 break; 2445 2425 } 2446 2426
+1
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
··· 2948 2948 result = get_integrated_info_v2_1(bp, info); 2949 2949 break; 2950 2950 case 2: 2951 + case 3: 2951 2952 result = get_integrated_info_v2_2(bp, info); 2952 2953 break; 2953 2954 default:
+8
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
··· 145 145 */ 146 146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 147 147 if (safe_to_lower) { 148 + if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 149 + dcn315_smu_set_dtbclk(clk_mgr, false); 150 + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 151 + } 148 152 /* check that we're not already in lower */ 149 153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 150 154 display_count = dcn315_get_active_display_cnt_wa(dc, context); ··· 164 160 } 165 161 } 166 162 } else { 163 + if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { 164 + dcn315_smu_set_dtbclk(clk_mgr, true); 165 + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 166 + } 167 167 /* check that we're not already in D0 */ 168 168 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 169 169 union display_idle_optimization_u idle_info = { 0 };
+12 -3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
··· 712 712 * since we calculate mode support based on softmax being the max UCLK 713 713 * frequency. 714 714 */ 715 - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 716 - dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 715 + if (dc->debug.disable_dc_mode_overwrite) { 716 + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); 717 + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); 718 + } else 719 + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 720 + dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 717 721 } else { 718 722 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); 719 723 } ··· 750 746 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ 751 747 if (clk_mgr_base->clks.p_state_change_support && 752 748 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) && 753 - !dc->work_arounds.clock_update_disable_mask.uclk) 749 + !dc->work_arounds.clock_update_disable_mask.uclk) { 750 + if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite) 751 + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, 752 + max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz))); 753 + 754 754 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); 755 + } 755 756 756 757 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && 757 758 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
+3
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 1801 1801 return false; 1802 1802 } 1803 1803 1804 + if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) 1805 + return false; 1806 + 1804 1807 if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) { 1805 1808 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n"); 1806 1809 return false;
+2
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
··· 291 291 .do_urgent_latency_adjustment = false, 292 292 .urgent_latency_adjustment_fabric_clock_component_us = 0, 293 293 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 294 + .dispclk_dppclk_vco_speed_mhz = 2400.0, 294 295 .num_chans = 4, 295 296 .dummy_pstate_latency_us = 10.0 296 297 }; ··· 439 438 .do_urgent_latency_adjustment = false, 440 439 .urgent_latency_adjustment_fabric_clock_component_us = 0, 441 440 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 441 + .dispclk_dppclk_vco_speed_mhz = 2500.0, 442 442 }; 443 443 444 444 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
+1
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
··· 2449 2449 dc->caps.post_blend_color_processing = true; 2450 2450 dc->caps.force_dp_tps4_for_cp2520 = true; 2451 2451 dc->caps.extended_aux_timeout_support = true; 2452 + dc->caps.dmcub_support = true; 2452 2453 2453 2454 /* Color pipeline capabilities */ 2454 2455 dc->caps.color.dpp.dcn_arch = 1;
+3 -2
drivers/gpu/drm/imagination/pvr_fw_mips.h
··· 7 7 #include "pvr_rogue_mips.h" 8 8 9 9 #include <asm/page.h> 10 + #include <linux/math.h> 10 11 #include <linux/types.h> 11 12 12 13 /* Forward declaration from pvr_gem.h. */ 13 14 struct pvr_gem_object; 14 15 15 - #define PVR_MIPS_PT_PAGE_COUNT ((ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * ROGUE_MIPSFW_PAGE_SIZE_4K) \ 16 - >> PAGE_SHIFT) 16 + #define PVR_MIPS_PT_PAGE_COUNT DIV_ROUND_UP(ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * ROGUE_MIPSFW_PAGE_SIZE_4K, PAGE_SIZE) 17 + 17 18 /** 18 19 * struct pvr_fw_mips_data - MIPS-specific data 19 20 */
+3 -1
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
··· 15 15 }; 16 16 17 17 struct nvkm_gsp_radix3 { 18 - struct nvkm_gsp_mem mem[3]; 18 + struct nvkm_gsp_mem lvl0; 19 + struct nvkm_gsp_mem lvl1; 20 + struct sg_table lvl2; 19 21 }; 20 22 21 23 int nvkm_gsp_sg(struct nvkm_device *, u64 size, struct sg_table *);
+12 -7
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
··· 205 205 break; 206 206 case NVKM_FIRMWARE_IMG_DMA: 207 207 nvkm_memory_unref(&memory); 208 - dma_free_coherent(fw->device->dev, sg_dma_len(&fw->mem.sgl), fw->img, fw->phys); 208 + dma_unmap_single(fw->device->dev, fw->phys, sg_dma_len(&fw->mem.sgl), 209 + DMA_TO_DEVICE); 210 + kfree(fw->img); 209 211 break; 210 212 case NVKM_FIRMWARE_IMG_SGT: 211 213 nvkm_memory_unref(&memory); ··· 237 235 fw->img = kmemdup(src, fw->len, GFP_KERNEL); 238 236 break; 239 237 case NVKM_FIRMWARE_IMG_DMA: { 240 - dma_addr_t addr; 241 - 242 238 len = ALIGN(fw->len, PAGE_SIZE); 243 239 244 - fw->img = dma_alloc_coherent(fw->device->dev, len, &addr, GFP_KERNEL); 245 - if (fw->img) { 246 - memcpy(fw->img, src, fw->len); 247 - fw->phys = addr; 240 + fw->img = kmalloc(len, GFP_KERNEL); 241 + if (!fw->img) 242 + return -ENOMEM; 243 + 244 + memcpy(fw->img, src, fw->len); 245 + fw->phys = dma_map_single(fw->device->dev, fw->img, len, DMA_TO_DEVICE); 246 + if (dma_mapping_error(fw->device->dev, fw->phys)) { 247 + kfree(fw->img); 248 + return -EFAULT; 248 249 } 249 250 250 251 sg_init_one(&fw->mem.sgl, fw->img, len);
+52 -27
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
··· 1624 1624 meta->magic = GSP_FW_WPR_META_MAGIC; 1625 1625 meta->revision = GSP_FW_WPR_META_REVISION; 1626 1626 1627 - meta->sysmemAddrOfRadix3Elf = gsp->radix3.mem[0].addr; 1627 + meta->sysmemAddrOfRadix3Elf = gsp->radix3.lvl0.addr; 1628 1628 meta->sizeOfRadix3Elf = gsp->fb.wpr2.elf.size; 1629 1629 1630 1630 meta->sysmemAddrOfBootloader = gsp->boot.fw.addr; ··· 1919 1919 static void 1920 1920 nvkm_gsp_radix3_dtor(struct nvkm_gsp *gsp, struct nvkm_gsp_radix3 *rx3) 1921 1921 { 1922 - for (int i = ARRAY_SIZE(rx3->mem) - 1; i >= 0; i--) 1923 - nvkm_gsp_mem_dtor(gsp, &rx3->mem[i]); 1922 + nvkm_gsp_sg_free(gsp->subdev.device, &rx3->lvl2); 1923 + nvkm_gsp_mem_dtor(gsp, &rx3->lvl1); 1924 + nvkm_gsp_mem_dtor(gsp, &rx3->lvl0); 1924 1925 } 1925 1926 1926 1927 /** ··· 1961 1960 nvkm_gsp_radix3_sg(struct nvkm_gsp *gsp, struct sg_table *sgt, u64 size, 1962 1961 struct nvkm_gsp_radix3 *rx3) 1963 1962 { 1964 - u64 addr; 1963 + struct sg_dma_page_iter sg_dma_iter; 1964 + struct scatterlist *sg; 1965 + size_t bufsize; 1966 + u64 *pte; 1967 + int ret, i, page_idx = 0; 1965 1968 1966 - for (int i = ARRAY_SIZE(rx3->mem) - 1; i >= 0; i--) { 1967 - u64 *ptes; 1968 - size_t bufsize; 1969 - int ret, idx; 1969 + ret = nvkm_gsp_mem_ctor(gsp, GSP_PAGE_SIZE, &rx3->lvl0); 1970 + if (ret) 1971 + return ret; 1970 1972 1971 - bufsize = ALIGN((size / GSP_PAGE_SIZE) * sizeof(u64), GSP_PAGE_SIZE); 1972 - ret = nvkm_gsp_mem_ctor(gsp, bufsize, &rx3->mem[i]); 1973 - if (ret) 1974 - return ret; 1973 + ret = nvkm_gsp_mem_ctor(gsp, GSP_PAGE_SIZE, &rx3->lvl1); 1974 + if (ret) 1975 + goto lvl1_fail; 1975 1976 1976 - ptes = rx3->mem[i].data; 1977 - if (i == 2) { 1978 - struct scatterlist *sgl; 1977 + // Allocate level 2 1978 + bufsize = ALIGN((size / GSP_PAGE_SIZE) * sizeof(u64), GSP_PAGE_SIZE); 1979 + ret = nvkm_gsp_sg(gsp->subdev.device, bufsize, &rx3->lvl2); 1980 + if (ret) 1981 + goto lvl2_fail; 1979 1982 1980 - for_each_sgtable_dma_sg(sgt, sgl, idx) { 1981 - for (int j = 0; j < sg_dma_len(sgl) / GSP_PAGE_SIZE; j++) 1982 - *ptes++ = sg_dma_address(sgl) + (GSP_PAGE_SIZE * j); 1983 - } 1984 - } else { 1985 - for (int j = 0; j < size / GSP_PAGE_SIZE; j++) 1986 - *ptes++ = addr + GSP_PAGE_SIZE * j; 1983 + // Write the bus address of level 1 to level 0 1984 + pte = rx3->lvl0.data; 1985 + *pte = rx3->lvl1.addr; 1986 + 1987 + // Write the bus address of each page in level 2 to level 1 1988 + pte = rx3->lvl1.data; 1989 + for_each_sgtable_dma_page(&rx3->lvl2, &sg_dma_iter, 0) 1990 + *pte++ = sg_page_iter_dma_address(&sg_dma_iter); 1991 + 1992 + // Finally, write the bus address of each page in sgt to level 2 1993 + for_each_sgtable_sg(&rx3->lvl2, sg, i) { 1994 + void *sgl_end; 1995 + 1996 + pte = sg_virt(sg); 1997 + sgl_end = (void *)pte + sg->length; 1998 + 1999 + for_each_sgtable_dma_page(sgt, &sg_dma_iter, page_idx) { 2000 + *pte++ = sg_page_iter_dma_address(&sg_dma_iter); 2001 + page_idx++; 2002 + 2003 + // Go to the next scatterlist for level 2 if we've reached the end 2004 + if ((void *)pte >= sgl_end) 2005 + break; 1987 2006 } 1988 - 1989 - size = rx3->mem[i].size; 1990 - addr = rx3->mem[i].addr; 1991 2007 } 1992 2008 1993 - return 0; 2009 + if (ret) { 2010 + lvl2_fail: 2011 + nvkm_gsp_mem_dtor(gsp, &rx3->lvl1); 2012 + lvl1_fail: 2013 + nvkm_gsp_mem_dtor(gsp, &rx3->lvl0); 2014 + } 2015 + 2016 + return ret; 1994 2017 } 1995 2018 1996 2019 int ··· 2046 2021 sr = gsp->sr.meta.data; 2047 2022 sr->magic = GSP_FW_SR_META_MAGIC; 2048 2023 sr->revision = GSP_FW_SR_META_REVISION; 2049 - sr->sysmemAddrOfSuspendResumeData = gsp->sr.radix3.mem[0].addr; 2024 + sr->sysmemAddrOfSuspendResumeData = gsp->sr.radix3.lvl0.addr; 2050 2025 sr->sizeOfSuspendResumeData = len; 2051 2026 2052 2027 mbox0 = lower_32_bits(gsp->sr.meta.addr);
+1 -1
drivers/gpu/drm/panel/Kconfig
··· 177 177 178 178 config DRM_PANEL_ILITEK_ILI9341 179 179 tristate "Ilitek ILI9341 240x320 QVGA panels" 180 - depends on OF && SPI 180 + depends on SPI 181 181 select DRM_KMS_HELPER 182 182 select DRM_GEM_DMA_HELPER 183 183 depends on BACKLIGHT_CLASS_DEVICE
+7 -6
drivers/gpu/drm/panel/panel-ilitek-ili9341.c
··· 22 22 #include <linux/bitops.h> 23 23 #include <linux/delay.h> 24 24 #include <linux/gpio/consumer.h> 25 + #include <linux/mod_devicetable.h> 25 26 #include <linux/module.h> 26 - #include <linux/of.h> 27 + #include <linux/property.h> 27 28 #include <linux/regulator/consumer.h> 28 29 #include <linux/spi/spi.h> 29 30 ··· 422 421 423 422 ili9341_dpi_init(ili); 424 423 425 - return ret; 424 + return 0; 426 425 } 427 426 428 427 static int ili9341_dpi_enable(struct drm_panel *panel) ··· 692 691 * Every new incarnation of this display must have a unique 693 692 * data entry for the system in this driver. 694 693 */ 695 - ili->conf = of_device_get_match_data(dev); 694 + ili->conf = device_get_match_data(dev); 696 695 if (!ili->conf) { 697 696 dev_err(dev, "missing device configuration\n"); 698 697 return -ENODEV; ··· 715 714 716 715 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 717 716 if (IS_ERR(reset)) 718 - dev_err(dev, "Failed to get gpio 'reset'\n"); 717 + return dev_err_probe(dev, PTR_ERR(reset), "Failed to get gpio 'reset'\n"); 719 718 720 719 dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW); 721 720 if (IS_ERR(dc)) 722 - dev_err(dev, "Failed to get gpio 'dc'\n"); 721 + return dev_err_probe(dev, PTR_ERR(dc), "Failed to get gpio 'dc'\n"); 723 722 724 723 if (!strcmp(id->name, "sf-tc240t-9370-t")) 725 724 return ili9341_dpi_probe(spi, dc, reset); 726 725 else if (!strcmp(id->name, "yx240qv29")) 727 726 return ili9341_dbi_probe(spi, dc, reset); 728 727 729 - return -1; 728 + return -ENODEV; 730 729 } 731 730 732 731 static void ili9341_remove(struct spi_device *spi)
+1 -1
drivers/gpu/drm/ttm/ttm_tt.c
··· 92 92 */ 93 93 if (bdev->pool.use_dma_alloc && cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) { 94 94 page_flags |= TTM_TT_FLAG_DECRYPTED; 95 - drm_info(ddev, "TT memory decryption enabled."); 95 + drm_info_once(ddev, "TT memory decryption enabled."); 96 96 } 97 97 98 98 bo->ttm = bdev->funcs->ttm_tt_create(bo, page_flags);
+1
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
··· 204 204 VMW_BO_DOMAIN_VRAM, 205 205 VMW_BO_DOMAIN_VRAM); 206 206 buf->places[0].lpfn = PFN_UP(bo->resource->size); 207 + buf->busy_places[0].lpfn = PFN_UP(bo->resource->size); 207 208 ret = ttm_bo_validate(bo, &buf->placement, &ctx); 208 209 209 210 /* For some reason we didn't end up at the start of vram */
+1 -1
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
··· 991 991 } 992 992 993 993 event->event.base.type = DRM_VMW_EVENT_FENCE_SIGNALED; 994 - event->event.base.length = sizeof(*event); 994 + event->event.base.length = sizeof(event->event); 995 995 event->event.user_data = user_data; 996 996 997 997 ret = drm_event_reserve_init(dev, file_priv, &event->base, &event->event.base);
+2 -1
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
··· 84 84 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE) 85 85 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1) 86 86 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S) 87 - #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) 87 + #define IS_ALDERLAKE_P(dev_priv) (IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) || \ 88 + IS_PLATFORM(dev_priv, XE_ALDERLAKE_N)) 88 89 #define IS_XEHPSDV(dev_priv) (dev_priv && 0) 89 90 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) 90 91 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
+3
drivers/gpu/drm/xe/xe_vm.c
··· 1606 1606 /* xe_vm_close_and_put was not called? */ 1607 1607 xe_assert(xe, !vm->size); 1608 1608 1609 + if (xe_vm_in_preempt_fence_mode(vm)) 1610 + flush_work(&vm->preempt.rebind_work); 1611 + 1609 1612 mutex_destroy(&vm->snap_mutex); 1610 1613 1611 1614 if (!(vm->flags & XE_VM_FLAG_MIGRATION))