Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-microchip-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Claudiu Beznea:
- PolarFire SoC clock driver updates to use regmaps instead of iomem
addresses; with it, the reset control driver support for non-auxiliary
bus probing was included as it now depends on the regmap registered
by the clock controller driver
- A cleanup patch for the LAN966X clk driver
* tag 'clk-microchip-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
reset: mpfs: add non-auxiliary bus probing
clk: lan966x: remove unused dt-bindings include
clk: microchip: mpfs: use regmap for clocks
dt-bindings: clk: microchip: mpfs: remove first reg region
+266
-96
+22
-14
Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
+22
-14
Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
···
22
22
const: microchip,mpfs-clkcfg
23
23
24
24
reg:
25
-
items:
26
-
- description: |
27
-
clock config registers:
28
-
These registers contain enable, reset & divider tables for the, cpu,
29
-
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
30
-
for the peripheral clocks.
31
-
- description: |
32
-
mss pll dri registers:
33
-
Block of registers responsible for dynamic reconfiguration of the mss
34
-
pll
25
+
oneOf:
26
+
- items:
27
+
- description: |
28
+
clock config registers:
29
+
These registers contain enable, reset & divider tables for the, cpu,
30
+
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
31
+
for the peripheral clocks.
32
+
- description: |
33
+
mss pll dri registers:
34
+
Block of registers responsible for dynamic reconfiguration of the mss
35
+
pll
36
+
deprecated: true
37
+
- items:
38
+
- description: |
39
+
mss pll dri registers:
40
+
Block of registers responsible for dynamic reconfiguration of the mss
41
+
pll
35
42
36
43
clocks:
37
44
maxItems: 1
···
76
69
- |
77
70
#include <dt-bindings/clock/microchip,mpfs-clock.h>
78
71
soc {
79
-
#address-cells = <2>;
80
-
#size-cells = <2>;
81
-
clkcfg: clock-controller@20002000 {
72
+
#address-cells = <1>;
73
+
#size-cells = <1>;
74
+
75
+
clkcfg: clock-controller@3E001000 {
82
76
compatible = "microchip,mpfs-clkcfg";
83
-
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
77
+
reg = <0x3E001000 0x1000>;
84
78
clocks = <&ref>;
85
79
#clock-cells = <1>;
86
80
};
-2
drivers/clk/clk-lan966x.c
-2
drivers/clk/clk-lan966x.c
+2
drivers/clk/microchip/Kconfig
+2
drivers/clk/microchip/Kconfig
+184
-43
drivers/clk/microchip/clk-mpfs.c
+184
-43
drivers/clk/microchip/clk-mpfs.c
···
4
4
*
5
5
* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
6
6
*/
7
+
#include <linux/cleanup.h>
7
8
#include <linux/clk-provider.h>
8
9
#include <linux/io.h>
10
+
#include <linux/mfd/syscon.h>
9
11
#include <linux/module.h>
10
12
#include <linux/platform_device.h>
13
+
#include <linux/regmap.h>
11
14
#include <dt-bindings/clock/microchip,mpfs-clock.h>
12
15
#include <soc/microchip/mpfs.h>
13
16
···
33
30
#define MSSPLL_POSTDIV_WIDTH 0x07u
34
31
#define MSSPLL_FIXED_DIV 4u
35
32
33
+
static const struct regmap_config mpfs_clk_regmap_config = {
34
+
.reg_bits = 32,
35
+
.reg_stride = 4,
36
+
.val_bits = 32,
37
+
.val_format_endian = REGMAP_ENDIAN_LITTLE,
38
+
.max_register = REG_SUBBLK_RESET_CR,
39
+
};
40
+
36
41
/*
37
42
* This clock ID is defined here, rather than the binding headers, as it is an
38
43
* internal clock only, and therefore has no consumers in other peripheral
···
50
39
51
40
struct mpfs_clock_data {
52
41
struct device *dev;
42
+
struct regmap *regmap;
53
43
void __iomem *base;
54
44
void __iomem *msspll_base;
55
45
struct clk_hw_onecell_data hw_data;
···
79
67
80
68
#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
81
69
70
+
struct mpfs_cfg_clock {
71
+
struct regmap *map;
72
+
const struct clk_div_table *table;
73
+
u8 map_offset;
74
+
u8 shift;
75
+
u8 width;
76
+
u8 flags;
77
+
};
78
+
82
79
struct mpfs_cfg_hw_clock {
83
-
struct clk_divider cfg;
84
-
struct clk_init_data init;
80
+
struct clk_hw hw;
81
+
struct mpfs_cfg_clock cfg;
85
82
unsigned int id;
86
-
u32 reg_offset;
83
+
};
84
+
85
+
#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
86
+
87
+
struct mpfs_periph_clock {
88
+
struct regmap *map;
89
+
u8 map_offset;
90
+
u8 shift;
87
91
};
88
92
89
93
struct mpfs_periph_hw_clock {
90
-
struct clk_gate periph;
94
+
struct clk_hw hw;
95
+
struct mpfs_periph_clock periph;
91
96
unsigned int id;
92
97
};
93
98
99
+
#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
100
+
94
101
/*
95
-
* mpfs_clk_lock prevents anything else from writing to the
96
-
* mpfs clk block while a software locked register is being written.
102
+
* Protects MSSPLL outputs, since there's two to a register
97
103
*/
98
104
static DEFINE_SPINLOCK(mpfs_clk_lock);
99
105
···
249
219
/*
250
220
* "CFG" clocks
251
221
*/
222
+
static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
223
+
{
224
+
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
225
+
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
226
+
u32 val;
252
227
253
-
#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
254
-
.id = _id, \
255
-
.cfg.shift = _shift, \
256
-
.cfg.width = _width, \
257
-
.cfg.table = _table, \
258
-
.reg_offset = _offset, \
259
-
.cfg.flags = _flags, \
260
-
.cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
261
-
.cfg.lock = &mpfs_clk_lock, \
228
+
regmap_read(cfg->map, cfg->map_offset, &val);
229
+
val >>= cfg->shift;
230
+
val &= clk_div_mask(cfg->width);
231
+
232
+
return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
233
+
}
234
+
235
+
static int mpfs_cfg_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
236
+
{
237
+
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
238
+
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
239
+
240
+
return divider_determine_rate(hw, req, cfg->table, cfg->width, 0);
241
+
}
242
+
243
+
static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
244
+
{
245
+
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
246
+
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
247
+
int divider_setting;
248
+
u32 val;
249
+
u32 mask;
250
+
251
+
divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
252
+
253
+
if (divider_setting < 0)
254
+
return divider_setting;
255
+
256
+
mask = clk_div_mask(cfg->width) << cfg->shift;
257
+
val = divider_setting << cfg->shift;
258
+
regmap_update_bits(cfg->map, cfg->map_offset, val, mask);
259
+
260
+
return 0;
261
+
}
262
+
263
+
static const struct clk_ops mpfs_clk_cfg_ops = {
264
+
.recalc_rate = mpfs_cfg_clk_recalc_rate,
265
+
.determine_rate = mpfs_cfg_clk_determine_rate,
266
+
.set_rate = mpfs_cfg_clk_set_rate,
267
+
};
268
+
269
+
#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
270
+
.id = _id, \
271
+
.cfg.shift = _shift, \
272
+
.cfg.width = _width, \
273
+
.cfg.table = _table, \
274
+
.cfg.map_offset = _offset, \
275
+
.cfg.flags = _flags, \
276
+
.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \
262
277
}
263
278
264
279
#define CLK_CPU_OFFSET 0u
···
323
248
.cfg.shift = 0,
324
249
.cfg.width = 12,
325
250
.cfg.table = mpfs_div_rtcref_table,
326
-
.reg_offset = REG_RTC_CLOCK_CR,
251
+
.cfg.map_offset = REG_RTC_CLOCK_CR,
327
252
.cfg.flags = CLK_DIVIDER_ONE_BASED,
328
-
.cfg.hw.init =
329
-
CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
253
+
.hw.init =
254
+
CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
330
255
}
331
256
};
332
257
···
339
264
for (i = 0; i < num_clks; i++) {
340
265
struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
341
266
342
-
cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
343
-
ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
267
+
cfg_hw->cfg.map = data->regmap;
268
+
ret = devm_clk_hw_register(dev, &cfg_hw->hw);
344
269
if (ret)
345
270
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
346
271
cfg_hw->id);
347
272
348
273
id = cfg_hw->id;
349
-
data->hw_data.hws[id] = &cfg_hw->cfg.hw;
274
+
data->hw_data.hws[id] = &cfg_hw->hw;
350
275
}
351
276
352
277
return 0;
···
356
281
* peripheral clocks - devices connected to axi or ahb buses.
357
282
*/
358
283
359
-
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
360
-
.id = _id, \
361
-
.periph.bit_idx = _shift, \
362
-
.periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
363
-
_flags), \
364
-
.periph.lock = &mpfs_clk_lock, \
284
+
static int mpfs_periph_clk_enable(struct clk_hw *hw)
285
+
{
286
+
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
287
+
struct mpfs_periph_clock *periph = &periph_hw->periph;
288
+
289
+
regmap_update_bits(periph->map, periph->map_offset,
290
+
BIT(periph->shift), BIT(periph->shift));
291
+
292
+
return 0;
365
293
}
366
294
367
-
#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
295
+
static void mpfs_periph_clk_disable(struct clk_hw *hw)
296
+
{
297
+
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
298
+
struct mpfs_periph_clock *periph = &periph_hw->periph;
299
+
300
+
regmap_update_bits(periph->map, periph->map_offset, BIT(periph->shift), 0);
301
+
}
302
+
303
+
static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
304
+
{
305
+
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
306
+
struct mpfs_periph_clock *periph = &periph_hw->periph;
307
+
u32 val;
308
+
309
+
regmap_read(periph->map, periph->map_offset, &val);
310
+
311
+
return !!(val & BIT(periph->shift));
312
+
}
313
+
314
+
static const struct clk_ops mpfs_periph_clk_ops = {
315
+
.enable = mpfs_periph_clk_enable,
316
+
.disable = mpfs_periph_clk_disable,
317
+
.is_enabled = mpfs_periph_clk_is_enabled,
318
+
};
319
+
320
+
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
321
+
.id = _id, \
322
+
.periph.map_offset = REG_SUBBLK_CLOCK_CR, \
323
+
.periph.shift = _shift, \
324
+
.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags), \
325
+
}
326
+
327
+
#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw)
368
328
369
329
/*
370
330
* Critical clocks:
···
456
346
for (i = 0; i < num_clks; i++) {
457
347
struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
458
348
459
-
periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
460
-
ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
349
+
periph_hw->periph.map = data->regmap;
350
+
ret = devm_clk_hw_register(dev, &periph_hw->hw);
461
351
if (ret)
462
352
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
463
353
periph_hw->id);
464
354
465
355
id = periph_hws[i].id;
466
-
data->hw_data.hws[id] = &periph_hw->periph.hw;
356
+
data->hw_data.hws[id] = &periph_hw->hw;
467
357
}
468
358
469
359
return 0;
360
+
}
361
+
362
+
static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data,
363
+
struct platform_device *pdev)
364
+
{
365
+
clk_data->regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-mss-top-sysreg");
366
+
if (IS_ERR(clk_data->regmap))
367
+
return PTR_ERR(clk_data->regmap);
368
+
369
+
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 0);
370
+
if (IS_ERR(clk_data->msspll_base))
371
+
return PTR_ERR(clk_data->msspll_base);
372
+
373
+
return 0;
374
+
}
375
+
376
+
static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_data,
377
+
struct platform_device *pdev)
378
+
{
379
+
struct device *dev = &pdev->dev;
380
+
381
+
dev_warn(&pdev->dev, "falling back to old devicetree format");
382
+
383
+
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
384
+
if (IS_ERR(clk_data->base))
385
+
return PTR_ERR(clk_data->base);
386
+
387
+
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
388
+
if (IS_ERR(clk_data->msspll_base))
389
+
return PTR_ERR(clk_data->msspll_base);
390
+
391
+
clk_data->regmap = devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk_regmap_config);
392
+
if (IS_ERR(clk_data->regmap))
393
+
return PTR_ERR(clk_data->regmap);
394
+
395
+
return mpfs_reset_controller_register(dev, clk_data->regmap);
470
396
}
471
397
472
398
static int mpfs_clk_probe(struct platform_device *pdev)
···
520
374
if (!clk_data)
521
375
return -ENOMEM;
522
376
523
-
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
524
-
if (IS_ERR(clk_data->base))
525
-
return PTR_ERR(clk_data->base);
526
-
527
-
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
528
-
if (IS_ERR(clk_data->msspll_base))
529
-
return PTR_ERR(clk_data->msspll_base);
377
+
ret = mpfs_clk_syscon_probe(clk_data, pdev);
378
+
if (ret) {
379
+
ret = mpfs_clk_old_format_probe(clk_data, pdev);
380
+
if (ret)
381
+
return ret;
382
+
}
530
383
531
384
clk_data->hw_data.num = num_clks;
532
385
clk_data->dev = dev;
···
551
406
if (ret)
552
407
return ret;
553
408
554
-
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
555
-
if (ret)
556
-
return ret;
557
-
558
-
return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
409
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
559
410
}
560
411
561
412
static const struct of_device_id mpfs_clk_of_match_table[] = {
+1
drivers/reset/Kconfig
+1
drivers/reset/Kconfig
+55
-36
drivers/reset/reset-mpfs.c
+55
-36
drivers/reset/reset-mpfs.c
···
9
9
#include <linux/auxiliary_bus.h>
10
10
#include <linux/delay.h>
11
11
#include <linux/io.h>
12
+
#include <linux/mfd/syscon.h>
12
13
#include <linux/module.h>
13
14
#include <linux/of.h>
14
15
#include <linux/platform_device.h>
15
-
#include <linux/slab.h>
16
+
#include <linux/regmap.h>
16
17
#include <linux/reset-controller.h>
18
+
#include <linux/slab.h>
17
19
#include <dt-bindings/clock/microchip,mpfs-clock.h>
18
20
#include <soc/microchip/mpfs.h>
19
21
···
29
27
#define MPFS_SLEEP_MIN_US 100
30
28
#define MPFS_SLEEP_MAX_US 200
31
29
32
-
/* block concurrent access to the soft reset register */
33
-
static DEFINE_SPINLOCK(mpfs_reset_lock);
30
+
#define REG_SUBBLK_RESET_CR 0x88u
34
31
35
32
struct mpfs_reset {
36
-
void __iomem *base;
33
+
struct regmap *regmap;
37
34
struct reset_controller_dev rcdev;
38
35
};
39
36
···
47
46
static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
48
47
{
49
48
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
50
-
unsigned long flags;
51
-
u32 reg;
52
49
53
-
spin_lock_irqsave(&mpfs_reset_lock, flags);
50
+
return regmap_set_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
54
51
55
-
reg = readl(rst->base);
56
-
reg |= BIT(id);
57
-
writel(reg, rst->base);
58
-
59
-
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
60
-
61
-
return 0;
62
52
}
63
53
64
54
static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
65
55
{
66
56
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
67
-
unsigned long flags;
68
-
u32 reg;
69
57
70
-
spin_lock_irqsave(&mpfs_reset_lock, flags);
58
+
return regmap_clear_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
71
59
72
-
reg = readl(rst->base);
73
-
reg &= ~BIT(id);
74
-
writel(reg, rst->base);
75
-
76
-
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
77
-
78
-
return 0;
79
60
}
80
61
81
62
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
82
63
{
83
64
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
84
-
u32 reg = readl(rst->base);
65
+
u32 reg;
66
+
67
+
regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®);
85
68
86
69
/*
87
70
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
···
115
130
return index - MPFS_PERIPH_OFFSET;
116
131
}
117
132
118
-
static int mpfs_reset_probe(struct auxiliary_device *adev,
119
-
const struct auxiliary_device_id *id)
133
+
static int mpfs_reset_mfd_probe(struct platform_device *pdev)
120
134
{
121
-
struct device *dev = &adev->dev;
122
135
struct reset_controller_dev *rcdev;
136
+
struct device *dev = &pdev->dev;
123
137
struct mpfs_reset *rst;
124
138
125
139
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
126
140
if (!rst)
127
141
return -ENOMEM;
128
142
129
-
rst->base = (void __iomem *)adev->dev.platform_data;
143
+
rcdev = &rst->rcdev;
144
+
rcdev->dev = dev;
145
+
rcdev->ops = &mpfs_reset_ops;
146
+
147
+
rcdev->of_node = pdev->dev.parent->of_node;
148
+
rcdev->of_reset_n_cells = 1;
149
+
rcdev->of_xlate = mpfs_reset_xlate;
150
+
rcdev->nr_resets = MPFS_NUM_RESETS;
151
+
152
+
rst->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
153
+
if (IS_ERR(rst->regmap))
154
+
return dev_err_probe(dev, PTR_ERR(rst->regmap),
155
+
"Failed to find syscon regmap\n");
156
+
157
+
return devm_reset_controller_register(dev, rcdev);
158
+
}
159
+
160
+
static struct platform_driver mpfs_reset_mfd_driver = {
161
+
.probe = mpfs_reset_mfd_probe,
162
+
.driver = {
163
+
.name = "mpfs-reset",
164
+
},
165
+
};
166
+
module_platform_driver(mpfs_reset_mfd_driver);
167
+
168
+
static int mpfs_reset_adev_probe(struct auxiliary_device *adev,
169
+
const struct auxiliary_device_id *id)
170
+
{
171
+
struct reset_controller_dev *rcdev;
172
+
struct device *dev = &adev->dev;
173
+
struct mpfs_reset *rst;
174
+
175
+
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
176
+
if (!rst)
177
+
return -ENOMEM;
178
+
179
+
rst->regmap = (struct regmap *)adev->dev.platform_data;
130
180
131
181
rcdev = &rst->rcdev;
132
182
rcdev->dev = dev;
133
-
rcdev->dev->parent = dev->parent;
134
183
rcdev->ops = &mpfs_reset_ops;
184
+
135
185
rcdev->of_node = dev->parent->of_node;
136
186
rcdev->of_reset_n_cells = 1;
137
187
rcdev->of_xlate = mpfs_reset_xlate;
···
175
155
return devm_reset_controller_register(dev, rcdev);
176
156
}
177
157
178
-
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)
158
+
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map)
179
159
{
180
160
struct auxiliary_device *adev;
181
161
182
-
adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs",
183
-
(__force void *)base);
162
+
adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs", (void *)map);
184
163
if (!adev)
185
164
return -ENODEV;
186
165
···
195
176
};
196
177
MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
197
178
198
-
static struct auxiliary_driver mpfs_reset_driver = {
199
-
.probe = mpfs_reset_probe,
179
+
static struct auxiliary_driver mpfs_reset_aux_driver = {
180
+
.probe = mpfs_reset_adev_probe,
200
181
.id_table = mpfs_reset_ids,
201
182
};
202
183
203
-
module_auxiliary_driver(mpfs_reset_driver);
184
+
module_auxiliary_driver(mpfs_reset_aux_driver);
204
185
205
186
MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
206
187
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+2
-1
include/soc/microchip/mpfs.h
+2
-1
include/soc/microchip/mpfs.h
···
14
14
15
15
#include <linux/types.h>
16
16
#include <linux/of_device.h>
17
+
#include <linux/regmap.h>
17
18
18
19
struct mpfs_sys_controller;
19
20
···
45
44
46
45
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
47
46
#if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC)
48
-
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base);
47
+
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map);
49
48
#else
50
49
static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; }
51
50
#endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */