Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux into soc/drivers
This pull request contains Broadcom SoC drivers updates for 6.18:
- Andrea adds the missing MIPI DSI clock defines for the RP1 and then
continues to implement the remaining clocks for the RP1 chip (ADC,
I2S, Audio in/out, DMA, MIPI, PWM, SDIO, UART, encoder)
- Akhilesh fixes a spelling typo in the bcm47xx_sprom driver
- Brian converts the RP1 clock driver to use the new determine_rate()
API
* tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux:
clk: rp1: convert from round_rate() to determine_rate()
drivers: firmware: bcm47xx_sprom: fix spelling
clk: rp1: Implement remaining clock tree
dt-bindings: clock: rp1: Add missing MIPI DSI defines
Link: https://lore.kernel.org/r/20250910171910.666401-4-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+1000
-28
+995
-27
drivers/clk/clk-rp1.c
+995
-27
drivers/clk/clk-rp1.c
···
368
368
struct clk_divider div;
369
369
};
370
370
371
+
static struct rp1_clk_desc *clk_audio_core;
372
+
static struct rp1_clk_desc *clk_audio;
373
+
static struct rp1_clk_desc *clk_i2s;
374
+
static struct clk_hw *clk_xosc;
375
+
371
376
static inline
372
377
void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val)
373
378
{
···
480
475
struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
481
476
struct rp1_clockman *clockman = pll_core->clockman;
482
477
const struct rp1_pll_core_data *data = pll_core->data;
483
-
unsigned long calc_rate;
484
478
u32 fbdiv_int, fbdiv_frac;
485
479
486
480
/* Disable dividers to start with. */
···
488
484
clockman_write(clockman, data->fbdiv_frac_reg, 0);
489
485
spin_unlock(&clockman->regs_lock);
490
486
491
-
calc_rate = get_pll_core_divider(hw, rate, parent_rate,
492
-
&fbdiv_int, &fbdiv_frac);
487
+
get_pll_core_divider(hw, rate, parent_rate,
488
+
&fbdiv_int, &fbdiv_frac);
493
489
494
490
spin_lock(&clockman->regs_lock);
495
491
clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD);
···
500
496
/* Check that reference frequency is no greater than VCO / 16. */
501
497
if (WARN_ON_ONCE(parent_rate > (rate / 16)))
502
498
return -ERANGE;
503
-
504
-
pll_core->cached_rate = calc_rate;
505
499
506
500
spin_lock(&clockman->regs_lock);
507
501
/* Don't need to divide ref unless parent_rate > (output freq / 16) */
···
532
530
return calc_rate;
533
531
}
534
532
535
-
static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate,
536
-
unsigned long *parent_rate)
533
+
static int rp1_pll_core_determine_rate(struct clk_hw *hw,
534
+
struct clk_rate_request *req)
537
535
{
538
536
u32 fbdiv_int, fbdiv_frac;
539
537
540
-
return get_pll_core_divider(hw, rate, *parent_rate,
541
-
&fbdiv_int, &fbdiv_frac);
538
+
req->rate = get_pll_core_divider(hw, req->rate, req->best_parent_rate,
539
+
&fbdiv_int,
540
+
&fbdiv_frac);
541
+
542
+
return 0;
542
543
}
543
544
544
545
static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate,
···
619
614
return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2);
620
615
}
621
616
622
-
static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate,
623
-
unsigned long *parent_rate)
617
+
static int rp1_pll_determine_rate(struct clk_hw *hw,
618
+
struct clk_rate_request *req)
624
619
{
620
+
struct clk_hw *clk_audio_hw = &clk_audio->hw;
625
621
u32 div1, div2;
626
622
627
-
get_pll_prim_dividers(rate, *parent_rate, &div1, &div2);
623
+
if (hw == clk_audio_hw && clk_audio->cached_rate == req->rate)
624
+
req->best_parent_rate = clk_audio_core->cached_rate;
628
625
629
-
return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2);
626
+
get_pll_prim_dividers(req->rate, req->best_parent_rate, &div1, &div2);
627
+
628
+
req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, div1 * div2);
629
+
630
+
return 0;
630
631
}
631
632
632
633
static int rp1_pll_ph_is_on(struct clk_hw *hw)
···
682
671
return parent_rate / data->fixed_divider;
683
672
}
684
673
685
-
static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate,
686
-
unsigned long *parent_rate)
674
+
static int rp1_pll_ph_determine_rate(struct clk_hw *hw,
675
+
struct clk_rate_request *req)
687
676
{
688
677
struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
689
678
const struct rp1_pll_ph_data *data = pll_ph->data;
690
679
691
-
return *parent_rate / data->fixed_divider;
680
+
req->rate = req->best_parent_rate / data->fixed_divider;
681
+
682
+
return 0;
692
683
}
693
684
694
685
static int rp1_pll_divider_is_on(struct clk_hw *hw)
···
767
754
return clk_divider_ops.recalc_rate(hw, parent_rate);
768
755
}
769
756
770
-
static long rp1_pll_divider_round_rate(struct clk_hw *hw,
771
-
unsigned long rate,
772
-
unsigned long *parent_rate)
757
+
static int rp1_pll_divider_determine_rate(struct clk_hw *hw,
758
+
struct clk_rate_request *req)
773
759
{
774
-
return clk_divider_ops.round_rate(hw, rate, parent_rate);
760
+
req->rate = clk_divider_ops.determine_rate(hw, req);
761
+
762
+
return 0;
775
763
}
776
764
777
765
static int rp1_clock_is_on(struct clk_hw *hw)
···
978
964
return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);
979
965
}
980
966
967
+
static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw,
968
+
unsigned long target_rate,
969
+
int *pdiv_prim, int *pdiv_clk)
970
+
{
971
+
static const int prim_divs[] = {
972
+
2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16,
973
+
18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49,
974
+
};
975
+
const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc);
976
+
const unsigned long core_min = xosc_rate * 16;
977
+
const unsigned long core_max = 2400000000;
978
+
int best_div_prim = 1, best_div_clk = 1;
979
+
unsigned long best_rate = core_max + 1;
980
+
unsigned long core_rate = 0;
981
+
int div_int, div_frac;
982
+
u64 div;
983
+
int i;
984
+
985
+
/* Given the target rate, choose a set of divisors/multipliers */
986
+
for (i = 0; i < ARRAY_SIZE(prim_divs); i++) {
987
+
int div_prim = prim_divs[i];
988
+
int div_clk;
989
+
990
+
for (div_clk = 1; div_clk <= 256; div_clk++) {
991
+
core_rate = target_rate * div_clk * div_prim;
992
+
if (core_rate >= core_min) {
993
+
if (core_rate < best_rate) {
994
+
best_rate = core_rate;
995
+
best_div_prim = div_prim;
996
+
best_div_clk = div_clk;
997
+
}
998
+
break;
999
+
}
1000
+
}
1001
+
}
1002
+
1003
+
if (best_rate < core_max) {
1004
+
div = ((best_rate << 24) + xosc_rate / 2) / xosc_rate;
1005
+
div_int = div >> 24;
1006
+
div_frac = div % (1 << 24);
1007
+
core_rate = (xosc_rate * ((div_int << 24) + div_frac) + (1 << 23)) >> 24;
1008
+
} else {
1009
+
core_rate = 0;
1010
+
}
1011
+
1012
+
if (pdiv_prim)
1013
+
*pdiv_prim = best_div_prim;
1014
+
if (pdiv_clk)
1015
+
*pdiv_clk = best_div_clk;
1016
+
1017
+
return core_rate;
1018
+
}
1019
+
981
1020
static void rp1_clock_choose_div_and_prate(struct clk_hw *hw,
982
1021
int parent_idx,
983
1022
unsigned long rate,
···
1039
972
{
1040
973
struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
1041
974
const struct rp1_clock_data *data = clock->data;
975
+
struct clk_hw *clk_audio_hw = &clk_audio->hw;
976
+
struct clk_hw *clk_i2s_hw = &clk_i2s->hw;
1042
977
struct clk_hw *parent;
1043
978
u32 div;
1044
979
u64 tmp;
1045
980
1046
981
parent = clk_hw_get_parent_by_index(hw, parent_idx);
982
+
983
+
if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && parent == clk_audio_hw) {
984
+
*prate = clk_audio->cached_rate;
985
+
*calc_rate = rate;
986
+
return;
987
+
}
988
+
989
+
if (hw == clk_i2s_hw && parent == clk_audio_hw) {
990
+
unsigned long core_rate, audio_rate, i2s_rate;
991
+
int div_prim, div_clk;
992
+
993
+
core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk);
994
+
audio_rate = DIV_ROUND_CLOSEST(core_rate, div_prim);
995
+
i2s_rate = DIV_ROUND_CLOSEST(audio_rate, div_clk);
996
+
clk_audio_core->cached_rate = core_rate;
997
+
clk_audio->cached_rate = audio_rate;
998
+
clk_i2s->cached_rate = i2s_rate;
999
+
*prate = audio_rate;
1000
+
*calc_rate = i2s_rate;
1001
+
return;
1002
+
}
1047
1003
1048
1004
*prate = clk_hw_get_rate(parent);
1049
1005
div = rp1_clock_choose_div(rate, *prate, data);
···
1152
1062
return 0;
1153
1063
}
1154
1064
1065
+
static int rp1_varsrc_set_rate(struct clk_hw *hw,
1066
+
unsigned long rate, unsigned long parent_rate)
1067
+
{
1068
+
struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
1069
+
1070
+
/*
1071
+
* "varsrc" exists purely to let clock dividers know the frequency
1072
+
* of an externally-managed clock source (such as MIPI DSI byte-clock)
1073
+
* which may change at run-time as a side-effect of some other driver.
1074
+
*/
1075
+
clock->cached_rate = rate;
1076
+
return 0;
1077
+
}
1078
+
1079
+
static unsigned long rp1_varsrc_recalc_rate(struct clk_hw *hw,
1080
+
unsigned long parent_rate)
1081
+
{
1082
+
struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
1083
+
1084
+
return clock->cached_rate;
1085
+
}
1086
+
1087
+
static int rp1_varsrc_determine_rate(struct clk_hw *hw,
1088
+
struct clk_rate_request *req)
1089
+
{
1090
+
return 0;
1091
+
}
1092
+
1155
1093
static const struct clk_ops rp1_pll_core_ops = {
1156
1094
.is_prepared = rp1_pll_core_is_on,
1157
1095
.prepare = rp1_pll_core_on,
1158
1096
.unprepare = rp1_pll_core_off,
1159
1097
.set_rate = rp1_pll_core_set_rate,
1160
1098
.recalc_rate = rp1_pll_core_recalc_rate,
1161
-
.round_rate = rp1_pll_core_round_rate,
1099
+
.determine_rate = rp1_pll_core_determine_rate,
1162
1100
};
1163
1101
1164
1102
static const struct clk_ops rp1_pll_ops = {
1165
1103
.set_rate = rp1_pll_set_rate,
1166
1104
.recalc_rate = rp1_pll_recalc_rate,
1167
-
.round_rate = rp1_pll_round_rate,
1105
+
.determine_rate = rp1_pll_determine_rate,
1168
1106
};
1169
1107
1170
1108
static const struct clk_ops rp1_pll_ph_ops = {
···
1200
1082
.prepare = rp1_pll_ph_on,
1201
1083
.unprepare = rp1_pll_ph_off,
1202
1084
.recalc_rate = rp1_pll_ph_recalc_rate,
1203
-
.round_rate = rp1_pll_ph_round_rate,
1085
+
.determine_rate = rp1_pll_ph_determine_rate,
1204
1086
};
1205
1087
1206
1088
static const struct clk_ops rp1_pll_divider_ops = {
···
1209
1091
.unprepare = rp1_pll_divider_off,
1210
1092
.set_rate = rp1_pll_divider_set_rate,
1211
1093
.recalc_rate = rp1_pll_divider_recalc_rate,
1212
-
.round_rate = rp1_pll_divider_round_rate,
1094
+
.determine_rate = rp1_pll_divider_determine_rate,
1213
1095
};
1214
1096
1215
1097
static const struct clk_ops rp1_clk_ops = {
···
1222
1104
.set_rate_and_parent = rp1_clock_set_rate_and_parent,
1223
1105
.set_rate = rp1_clock_set_rate,
1224
1106
.determine_rate = rp1_clock_determine_rate,
1107
+
};
1108
+
1109
+
static const struct clk_ops rp1_varsrc_ops = {
1110
+
.set_rate = rp1_varsrc_set_rate,
1111
+
.recalc_rate = rp1_varsrc_recalc_rate,
1112
+
.determine_rate = rp1_varsrc_determine_rate,
1225
1113
};
1226
1114
1227
1115
static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman,
···
1365
1241
)
1366
1242
);
1367
1243
1244
+
static struct rp1_clk_desc pll_audio_desc = REGISTER_PLL(
1245
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1246
+
"pll_audio",
1247
+
(const struct clk_parent_data[]) {
1248
+
{ .hw = &pll_audio_core_desc.hw }
1249
+
},
1250
+
&rp1_pll_ops,
1251
+
CLK_SET_RATE_PARENT
1252
+
),
1253
+
CLK_DATA(rp1_pll_data,
1254
+
.ctrl_reg = PLL_AUDIO_PRIM,
1255
+
.fc0_src = FC_NUM(4, 2),
1256
+
)
1257
+
);
1258
+
1259
+
static struct rp1_clk_desc pll_video_desc = REGISTER_PLL(
1260
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1261
+
"pll_video",
1262
+
(const struct clk_parent_data[]) {
1263
+
{ .hw = &pll_video_core_desc.hw }
1264
+
},
1265
+
&rp1_pll_ops,
1266
+
0
1267
+
),
1268
+
CLK_DATA(rp1_pll_data,
1269
+
.ctrl_reg = PLL_VIDEO_PRIM,
1270
+
.fc0_src = FC_NUM(3, 2),
1271
+
)
1272
+
);
1273
+
1368
1274
static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV(
1369
1275
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1370
1276
"pll_sys_sec",
···
1410
1256
)
1411
1257
);
1412
1258
1259
+
static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV(
1260
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1261
+
"pll_video_sec",
1262
+
(const struct clk_parent_data[]) {
1263
+
{ .hw = &pll_video_core_desc.hw }
1264
+
},
1265
+
&rp1_pll_divider_ops,
1266
+
0
1267
+
),
1268
+
CLK_DATA(rp1_pll_data,
1269
+
.ctrl_reg = PLL_VIDEO_SEC,
1270
+
.fc0_src = FC_NUM(5, 3),
1271
+
)
1272
+
);
1273
+
1274
+
static const struct clk_parent_data clk_eth_tsu_parents[] = {
1275
+
{ .index = 0 },
1276
+
{ .hw = &pll_video_sec_desc.hw },
1277
+
{ .index = -1 },
1278
+
{ .index = -1 },
1279
+
{ .index = -1 },
1280
+
{ .index = -1 },
1281
+
{ .index = -1 },
1282
+
{ .index = -1 },
1283
+
};
1284
+
1413
1285
static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK(
1414
1286
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1415
1287
"clk_eth_tsu",
1416
-
(const struct clk_parent_data[]) { { .index = 0 } },
1288
+
clk_eth_tsu_parents,
1417
1289
&rp1_clk_ops,
1418
1290
0
1419
1291
),
1420
1292
CLK_DATA(rp1_clock_data,
1421
1293
.num_std_parents = 0,
1422
-
.num_aux_parents = 1,
1294
+
.num_aux_parents = 8,
1423
1295
.ctrl_reg = CLK_ETH_TSU_CTRL,
1424
1296
.div_int_reg = CLK_ETH_TSU_DIV_INT,
1425
1297
.sel_reg = CLK_ETH_TSU_SEL,
···
1458
1278
static const struct clk_parent_data clk_eth_parents[] = {
1459
1279
{ .hw = &pll_sys_sec_desc.div.hw },
1460
1280
{ .hw = &pll_sys_desc.hw },
1281
+
{ .hw = &pll_video_sec_desc.hw },
1461
1282
};
1462
1283
1463
1284
static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK(
···
1470
1289
),
1471
1290
CLK_DATA(rp1_clock_data,
1472
1291
.num_std_parents = 0,
1473
-
.num_aux_parents = 2,
1292
+
.num_aux_parents = 3,
1474
1293
.ctrl_reg = CLK_ETH_CTRL,
1475
1294
.div_int_reg = CLK_ETH_DIV_INT,
1476
1295
.sel_reg = CLK_ETH_SEL,
···
1523
1342
)
1524
1343
);
1525
1344
1345
+
static struct rp1_clk_desc pll_audio_pri_ph_desc = REGISTER_PLL(
1346
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1347
+
"pll_audio_pri_ph",
1348
+
(const struct clk_parent_data[]) {
1349
+
{ .hw = &pll_audio_desc.hw }
1350
+
},
1351
+
&rp1_pll_ph_ops,
1352
+
0
1353
+
),
1354
+
CLK_DATA(rp1_pll_ph_data,
1355
+
.ph_reg = PLL_AUDIO_PRIM,
1356
+
.fixed_divider = 2,
1357
+
.phase = RP1_PLL_PHASE_0,
1358
+
.fc0_src = FC_NUM(5, 1),
1359
+
)
1360
+
);
1361
+
1362
+
static struct rp1_clk_desc pll_video_pri_ph_desc = REGISTER_PLL(
1363
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1364
+
"pll_video_pri_ph",
1365
+
(const struct clk_parent_data[]) {
1366
+
{ .hw = &pll_video_desc.hw }
1367
+
},
1368
+
&rp1_pll_ph_ops,
1369
+
0
1370
+
),
1371
+
CLK_DATA(rp1_pll_ph_data,
1372
+
.ph_reg = PLL_VIDEO_PRIM,
1373
+
.fixed_divider = 2,
1374
+
.phase = RP1_PLL_PHASE_0,
1375
+
.fc0_src = FC_NUM(4, 3),
1376
+
)
1377
+
);
1378
+
1379
+
static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV(
1380
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1381
+
"pll_audio_sec",
1382
+
(const struct clk_parent_data[]) {
1383
+
{ .hw = &pll_audio_core_desc.hw }
1384
+
},
1385
+
&rp1_pll_divider_ops,
1386
+
0
1387
+
),
1388
+
CLK_DATA(rp1_pll_data,
1389
+
.ctrl_reg = PLL_AUDIO_SEC,
1390
+
.fc0_src = FC_NUM(6, 2),
1391
+
)
1392
+
);
1393
+
1394
+
static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV(
1395
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1396
+
"pll_audio_tern",
1397
+
(const struct clk_parent_data[]) {
1398
+
{ .hw = &pll_audio_core_desc.hw }
1399
+
},
1400
+
&rp1_pll_divider_ops,
1401
+
0
1402
+
),
1403
+
CLK_DATA(rp1_pll_data,
1404
+
.ctrl_reg = PLL_AUDIO_TERN,
1405
+
.fc0_src = FC_NUM(6, 2),
1406
+
)
1407
+
);
1408
+
1409
+
static struct rp1_clk_desc clk_slow_sys_desc = REGISTER_CLK(
1410
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1411
+
"clk_slow_sys",
1412
+
(const struct clk_parent_data[]) { { .index = 0 } },
1413
+
&rp1_clk_ops,
1414
+
CLK_IS_CRITICAL
1415
+
),
1416
+
CLK_DATA(rp1_clock_data,
1417
+
.num_std_parents = 1,
1418
+
.num_aux_parents = 0,
1419
+
.ctrl_reg = CLK_SLOW_SYS_CTRL,
1420
+
.div_int_reg = CLK_SLOW_SYS_DIV_INT,
1421
+
.sel_reg = CLK_SLOW_SYS_SEL,
1422
+
.div_int_max = DIV_INT_8BIT_MAX,
1423
+
.max_freq = 50 * HZ_PER_MHZ,
1424
+
.fc0_src = FC_NUM(1, 4),
1425
+
.clk_src_mask = 0x1,
1426
+
)
1427
+
);
1428
+
1429
+
static const struct clk_parent_data clk_dma_parents[] = {
1430
+
{ .hw = &pll_sys_pri_ph_desc.hw },
1431
+
{ .hw = &pll_video_desc.hw },
1432
+
{ .index = 0 },
1433
+
};
1434
+
1435
+
static struct rp1_clk_desc clk_dma_desc = REGISTER_CLK(
1436
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1437
+
"clk_dma",
1438
+
clk_dma_parents,
1439
+
&rp1_clk_ops,
1440
+
0
1441
+
),
1442
+
CLK_DATA(rp1_clock_data,
1443
+
.num_std_parents = 0,
1444
+
.num_aux_parents = 3,
1445
+
.ctrl_reg = CLK_DMA_CTRL,
1446
+
.div_int_reg = CLK_DMA_DIV_INT,
1447
+
.sel_reg = CLK_DMA_SEL,
1448
+
.div_int_max = DIV_INT_8BIT_MAX,
1449
+
.max_freq = 100 * HZ_PER_MHZ,
1450
+
.fc0_src = FC_NUM(2, 2),
1451
+
)
1452
+
);
1453
+
1454
+
static const struct clk_parent_data clk_uart_parents[] = {
1455
+
{ .hw = &pll_sys_pri_ph_desc.hw },
1456
+
{ .hw = &pll_video_desc.hw },
1457
+
{ .index = 0 },
1458
+
};
1459
+
1460
+
static struct rp1_clk_desc clk_uart_desc = REGISTER_CLK(
1461
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1462
+
"clk_uart",
1463
+
clk_uart_parents,
1464
+
&rp1_clk_ops,
1465
+
0
1466
+
),
1467
+
CLK_DATA(rp1_clock_data,
1468
+
.num_std_parents = 0,
1469
+
.num_aux_parents = 3,
1470
+
.ctrl_reg = CLK_UART_CTRL,
1471
+
.div_int_reg = CLK_UART_DIV_INT,
1472
+
.sel_reg = CLK_UART_SEL,
1473
+
.div_int_max = DIV_INT_8BIT_MAX,
1474
+
.max_freq = 100 * HZ_PER_MHZ,
1475
+
.fc0_src = FC_NUM(6, 7),
1476
+
)
1477
+
);
1478
+
1479
+
static const struct clk_parent_data clk_pwm0_parents[] = {
1480
+
{ .index = -1 },
1481
+
{ .hw = &pll_video_sec_desc.hw },
1482
+
{ .index = 0 },
1483
+
};
1484
+
1485
+
static struct rp1_clk_desc clk_pwm0_desc = REGISTER_CLK(
1486
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1487
+
"clk_pwm0",
1488
+
clk_pwm0_parents,
1489
+
&rp1_clk_ops,
1490
+
0
1491
+
),
1492
+
CLK_DATA(rp1_clock_data,
1493
+
.num_std_parents = 0,
1494
+
.num_aux_parents = 3,
1495
+
.ctrl_reg = CLK_PWM0_CTRL,
1496
+
.div_int_reg = CLK_PWM0_DIV_INT,
1497
+
.div_frac_reg = CLK_PWM0_DIV_FRAC,
1498
+
.sel_reg = CLK_PWM0_SEL,
1499
+
.div_int_max = DIV_INT_16BIT_MAX,
1500
+
.max_freq = 76800 * HZ_PER_KHZ,
1501
+
.fc0_src = FC_NUM(0, 5),
1502
+
)
1503
+
);
1504
+
1505
+
static const struct clk_parent_data clk_pwm1_parents[] = {
1506
+
{ .index = -1 },
1507
+
{ .hw = &pll_video_sec_desc.hw },
1508
+
{ .index = 0 },
1509
+
};
1510
+
1511
+
static struct rp1_clk_desc clk_pwm1_desc = REGISTER_CLK(
1512
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1513
+
"clk_pwm1",
1514
+
clk_pwm1_parents,
1515
+
&rp1_clk_ops,
1516
+
0
1517
+
),
1518
+
CLK_DATA(rp1_clock_data,
1519
+
.num_std_parents = 0,
1520
+
.num_aux_parents = 3,
1521
+
.ctrl_reg = CLK_PWM1_CTRL,
1522
+
.div_int_reg = CLK_PWM1_DIV_INT,
1523
+
.div_frac_reg = CLK_PWM1_DIV_FRAC,
1524
+
.sel_reg = CLK_PWM1_SEL,
1525
+
.div_int_max = DIV_INT_16BIT_MAX,
1526
+
.max_freq = 76800 * HZ_PER_KHZ,
1527
+
.fc0_src = FC_NUM(1, 5),
1528
+
)
1529
+
);
1530
+
1531
+
static const struct clk_parent_data clk_audio_in_parents[] = {
1532
+
{ .index = -1 },
1533
+
{ .index = -1 },
1534
+
{ .index = -1 },
1535
+
{ .hw = &pll_video_sec_desc.hw },
1536
+
{ .index = 0 },
1537
+
};
1538
+
1539
+
static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK(
1540
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1541
+
"clk_audio_in",
1542
+
clk_audio_in_parents,
1543
+
&rp1_clk_ops,
1544
+
0
1545
+
),
1546
+
CLK_DATA(rp1_clock_data,
1547
+
.num_std_parents = 0,
1548
+
.num_aux_parents = 5,
1549
+
.ctrl_reg = CLK_AUDIO_IN_CTRL,
1550
+
.div_int_reg = CLK_AUDIO_IN_DIV_INT,
1551
+
.sel_reg = CLK_AUDIO_IN_SEL,
1552
+
.div_int_max = DIV_INT_8BIT_MAX,
1553
+
.max_freq = 76800 * HZ_PER_KHZ,
1554
+
.fc0_src = FC_NUM(2, 5),
1555
+
)
1556
+
);
1557
+
1558
+
static const struct clk_parent_data clk_audio_out_parents[] = {
1559
+
{ .index = -1 },
1560
+
{ .index = -1 },
1561
+
{ .hw = &pll_video_sec_desc.hw },
1562
+
{ .index = 0 },
1563
+
};
1564
+
1565
+
static struct rp1_clk_desc clk_audio_out_desc = REGISTER_CLK(
1566
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1567
+
"clk_audio_out",
1568
+
clk_audio_out_parents,
1569
+
&rp1_clk_ops,
1570
+
0
1571
+
),
1572
+
CLK_DATA(rp1_clock_data,
1573
+
.num_std_parents = 0,
1574
+
.num_aux_parents = 4,
1575
+
.ctrl_reg = CLK_AUDIO_OUT_CTRL,
1576
+
.div_int_reg = CLK_AUDIO_OUT_DIV_INT,
1577
+
.sel_reg = CLK_AUDIO_OUT_SEL,
1578
+
.div_int_max = DIV_INT_8BIT_MAX,
1579
+
.max_freq = 153600 * HZ_PER_KHZ,
1580
+
.fc0_src = FC_NUM(3, 5),
1581
+
)
1582
+
);
1583
+
1584
+
static const struct clk_parent_data clk_i2s_parents[] = {
1585
+
{ .index = 0 },
1586
+
{ .hw = &pll_audio_desc.hw },
1587
+
{ .hw = &pll_audio_sec_desc.hw },
1588
+
};
1589
+
1590
+
static struct rp1_clk_desc clk_i2s_desc = REGISTER_CLK(
1591
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1592
+
"clk_i2s",
1593
+
clk_i2s_parents,
1594
+
&rp1_clk_ops,
1595
+
CLK_SET_RATE_PARENT
1596
+
),
1597
+
CLK_DATA(rp1_clock_data,
1598
+
.num_std_parents = 0,
1599
+
.num_aux_parents = 3,
1600
+
.ctrl_reg = CLK_I2S_CTRL,
1601
+
.div_int_reg = CLK_I2S_DIV_INT,
1602
+
.sel_reg = CLK_I2S_SEL,
1603
+
.div_int_max = DIV_INT_8BIT_MAX,
1604
+
.max_freq = 50 * HZ_PER_MHZ,
1605
+
.fc0_src = FC_NUM(4, 4),
1606
+
)
1607
+
);
1608
+
1609
+
static struct rp1_clk_desc clk_mipi0_cfg_desc = REGISTER_CLK(
1610
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1611
+
"clk_mipi0_cfg",
1612
+
(const struct clk_parent_data[]) { { .index = 0 } },
1613
+
&rp1_clk_ops,
1614
+
0
1615
+
),
1616
+
CLK_DATA(rp1_clock_data,
1617
+
.num_std_parents = 0,
1618
+
.num_aux_parents = 1,
1619
+
.ctrl_reg = CLK_MIPI0_CFG_CTRL,
1620
+
.div_int_reg = CLK_MIPI0_CFG_DIV_INT,
1621
+
.sel_reg = CLK_MIPI0_CFG_SEL,
1622
+
.div_int_max = DIV_INT_8BIT_MAX,
1623
+
.max_freq = 50 * HZ_PER_MHZ,
1624
+
.fc0_src = FC_NUM(4, 5),
1625
+
)
1626
+
);
1627
+
1628
+
static struct rp1_clk_desc clk_mipi1_cfg_desc = REGISTER_CLK(
1629
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1630
+
"clk_mipi1_cfg",
1631
+
(const struct clk_parent_data[]) { { .index = 0 } },
1632
+
&rp1_clk_ops,
1633
+
0
1634
+
),
1635
+
CLK_DATA(rp1_clock_data,
1636
+
.num_std_parents = 0,
1637
+
.num_aux_parents = 1,
1638
+
.ctrl_reg = CLK_MIPI1_CFG_CTRL,
1639
+
.div_int_reg = CLK_MIPI1_CFG_DIV_INT,
1640
+
.sel_reg = CLK_MIPI1_CFG_SEL,
1641
+
.div_int_max = DIV_INT_8BIT_MAX,
1642
+
.max_freq = 50 * HZ_PER_MHZ,
1643
+
.fc0_src = FC_NUM(5, 6),
1644
+
.clk_src_mask = 0x1,
1645
+
)
1646
+
);
1647
+
1648
+
static struct rp1_clk_desc clk_adc_desc = REGISTER_CLK(
1649
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1650
+
"clk_adc",
1651
+
(const struct clk_parent_data[]) { { .index = 0 } },
1652
+
&rp1_clk_ops,
1653
+
0
1654
+
),
1655
+
CLK_DATA(rp1_clock_data,
1656
+
.num_std_parents = 0,
1657
+
.num_aux_parents = 1,
1658
+
.ctrl_reg = CLK_ADC_CTRL,
1659
+
.div_int_reg = CLK_ADC_DIV_INT,
1660
+
.sel_reg = CLK_ADC_SEL,
1661
+
.div_int_max = DIV_INT_8BIT_MAX,
1662
+
.max_freq = 50 * HZ_PER_MHZ,
1663
+
.fc0_src = FC_NUM(5, 5),
1664
+
)
1665
+
);
1666
+
1667
+
static struct rp1_clk_desc clk_sdio_timer_desc = REGISTER_CLK(
1668
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1669
+
"clk_sdio_timer",
1670
+
(const struct clk_parent_data[]) { { .index = 0 } },
1671
+
&rp1_clk_ops,
1672
+
0
1673
+
),
1674
+
CLK_DATA(rp1_clock_data,
1675
+
.num_std_parents = 0,
1676
+
.num_aux_parents = 1,
1677
+
.ctrl_reg = CLK_SDIO_TIMER_CTRL,
1678
+
.div_int_reg = CLK_SDIO_TIMER_DIV_INT,
1679
+
.sel_reg = CLK_SDIO_TIMER_SEL,
1680
+
.div_int_max = DIV_INT_8BIT_MAX,
1681
+
.max_freq = 50 * HZ_PER_MHZ,
1682
+
.fc0_src = FC_NUM(3, 4),
1683
+
)
1684
+
);
1685
+
1686
+
static struct rp1_clk_desc clk_sdio_alt_src_desc = REGISTER_CLK(
1687
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1688
+
"clk_sdio_alt_src",
1689
+
(const struct clk_parent_data[]) {
1690
+
{ .hw = &pll_sys_desc.hw }
1691
+
},
1692
+
&rp1_clk_ops,
1693
+
0
1694
+
),
1695
+
CLK_DATA(rp1_clock_data,
1696
+
.num_std_parents = 0,
1697
+
.num_aux_parents = 1,
1698
+
.ctrl_reg = CLK_SDIO_ALT_SRC_CTRL,
1699
+
.div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT,
1700
+
.sel_reg = CLK_SDIO_ALT_SRC_SEL,
1701
+
.div_int_max = DIV_INT_8BIT_MAX,
1702
+
.max_freq = 200 * HZ_PER_MHZ,
1703
+
.fc0_src = FC_NUM(5, 4),
1704
+
)
1705
+
);
1706
+
1707
+
static const struct clk_parent_data clk_dpi_parents[] = {
1708
+
{ .hw = &pll_sys_desc.hw },
1709
+
{ .hw = &pll_video_sec_desc.hw },
1710
+
{ .hw = &pll_video_desc.hw },
1711
+
{ .index = -1 },
1712
+
{ .index = -1 },
1713
+
{ .index = -1 },
1714
+
{ .index = -1 },
1715
+
{ .index = -1 },
1716
+
};
1717
+
1718
+
static struct rp1_clk_desc clk_dpi_desc = REGISTER_CLK(
1719
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1720
+
"clk_dpi",
1721
+
clk_dpi_parents,
1722
+
&rp1_clk_ops,
1723
+
CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */
1724
+
),
1725
+
CLK_DATA(rp1_clock_data,
1726
+
.num_std_parents = 0,
1727
+
.num_aux_parents = 8,
1728
+
.ctrl_reg = VIDEO_CLK_DPI_CTRL,
1729
+
.div_int_reg = VIDEO_CLK_DPI_DIV_INT,
1730
+
.sel_reg = VIDEO_CLK_DPI_SEL,
1731
+
.div_int_max = DIV_INT_8BIT_MAX,
1732
+
.max_freq = 200 * HZ_PER_MHZ,
1733
+
.fc0_src = FC_NUM(1, 6),
1734
+
)
1735
+
);
1736
+
1737
+
static const struct clk_parent_data clk_gp0_parents[] = {
1738
+
{ .index = 0 },
1739
+
{ .index = -1 },
1740
+
{ .index = -1 },
1741
+
{ .index = -1 },
1742
+
{ .index = -1 },
1743
+
{ .index = -1 },
1744
+
{ .hw = &pll_sys_desc.hw },
1745
+
{ .index = -1 },
1746
+
{ .index = -1 },
1747
+
{ .index = -1 },
1748
+
{ .hw = &clk_i2s_desc.hw },
1749
+
{ .hw = &clk_adc_desc.hw },
1750
+
{ .index = -1 },
1751
+
{ .index = -1 },
1752
+
{ .index = -1 },
1753
+
{ .hw = &clk_sys_desc.hw },
1754
+
};
1755
+
1756
+
static struct rp1_clk_desc clk_gp0_desc = REGISTER_CLK(
1757
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1758
+
"clk_gp0",
1759
+
clk_gp0_parents,
1760
+
&rp1_clk_ops,
1761
+
0
1762
+
),
1763
+
CLK_DATA(rp1_clock_data,
1764
+
.num_std_parents = 0,
1765
+
.num_aux_parents = 16,
1766
+
.oe_mask = BIT(0),
1767
+
.ctrl_reg = CLK_GP0_CTRL,
1768
+
.div_int_reg = CLK_GP0_DIV_INT,
1769
+
.div_frac_reg = CLK_GP0_DIV_FRAC,
1770
+
.sel_reg = CLK_GP0_SEL,
1771
+
.div_int_max = DIV_INT_16BIT_MAX,
1772
+
.max_freq = 100 * HZ_PER_MHZ,
1773
+
.fc0_src = FC_NUM(0, 1),
1774
+
)
1775
+
);
1776
+
1777
+
static const struct clk_parent_data clk_gp1_parents[] = {
1778
+
{ .hw = &clk_sdio_timer_desc.hw },
1779
+
{ .index = -1 },
1780
+
{ .index = -1 },
1781
+
{ .index = -1 },
1782
+
{ .index = -1 },
1783
+
{ .index = -1 },
1784
+
{ .hw = &pll_sys_pri_ph_desc.hw },
1785
+
{ .index = -1 },
1786
+
{ .index = -1 },
1787
+
{ .index = -1 },
1788
+
{ .hw = &clk_adc_desc.hw },
1789
+
{ .hw = &clk_dpi_desc.hw },
1790
+
{ .hw = &clk_pwm0_desc.hw },
1791
+
{ .index = -1 },
1792
+
{ .index = -1 },
1793
+
{ .index = -1 },
1794
+
};
1795
+
1796
+
static struct rp1_clk_desc clk_gp1_desc = REGISTER_CLK(
1797
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1798
+
"clk_gp1",
1799
+
clk_gp1_parents,
1800
+
&rp1_clk_ops,
1801
+
0
1802
+
),
1803
+
CLK_DATA(rp1_clock_data,
1804
+
.num_std_parents = 0,
1805
+
.num_aux_parents = 16,
1806
+
.oe_mask = BIT(1),
1807
+
.ctrl_reg = CLK_GP1_CTRL,
1808
+
.div_int_reg = CLK_GP1_DIV_INT,
1809
+
.div_frac_reg = CLK_GP1_DIV_FRAC,
1810
+
.sel_reg = CLK_GP1_SEL,
1811
+
.div_int_max = DIV_INT_16BIT_MAX,
1812
+
.max_freq = 100 * HZ_PER_MHZ,
1813
+
.fc0_src = FC_NUM(1, 1),
1814
+
)
1815
+
);
1816
+
1817
+
static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = REGISTER_CLK(
1818
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1819
+
"clksrc_mipi0_dsi_byteclk",
1820
+
(const struct clk_parent_data[]) { { .index = 0 } },
1821
+
&rp1_varsrc_ops,
1822
+
0
1823
+
),
1824
+
CLK_DATA(rp1_clock_data,
1825
+
.num_std_parents = 1,
1826
+
.num_aux_parents = 0,
1827
+
)
1828
+
);
1829
+
1830
+
static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = REGISTER_CLK(
1831
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1832
+
"clksrc_mipi1_dsi_byteclk",
1833
+
(const struct clk_parent_data[]) { { .index = 0 } },
1834
+
&rp1_varsrc_ops,
1835
+
0
1836
+
),
1837
+
CLK_DATA(rp1_clock_data,
1838
+
.num_std_parents = 1,
1839
+
.num_aux_parents = 0,
1840
+
)
1841
+
);
1842
+
1843
+
static const struct clk_parent_data clk_mipi0_dpi_parents[] = {
1844
+
{ .hw = &pll_sys_desc.hw },
1845
+
{ .hw = &pll_video_sec_desc.hw },
1846
+
{ .hw = &pll_video_desc.hw },
1847
+
{ .hw = &clksrc_mipi0_dsi_byteclk_desc.hw },
1848
+
{ .index = -1 },
1849
+
{ .index = -1 },
1850
+
{ .index = -1 },
1851
+
{ .index = -1 },
1852
+
};
1853
+
1854
+
static struct rp1_clk_desc clk_mipi0_dpi_desc = REGISTER_CLK(
1855
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1856
+
"clk_mipi0_dpi",
1857
+
clk_mipi0_dpi_parents,
1858
+
&rp1_clk_ops,
1859
+
CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */
1860
+
),
1861
+
CLK_DATA(rp1_clock_data,
1862
+
.num_std_parents = 0,
1863
+
.num_aux_parents = 8,
1864
+
.ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL,
1865
+
.div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT,
1866
+
.div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC,
1867
+
.sel_reg = VIDEO_CLK_MIPI0_DPI_SEL,
1868
+
.div_int_max = DIV_INT_8BIT_MAX,
1869
+
.max_freq = 200 * HZ_PER_MHZ,
1870
+
.fc0_src = FC_NUM(2, 6),
1871
+
)
1872
+
);
1873
+
1874
+
static const struct clk_parent_data clk_mipi1_dpi_parents[] = {
1875
+
{ .hw = &pll_sys_desc.hw },
1876
+
{ .hw = &pll_video_sec_desc.hw },
1877
+
{ .hw = &pll_video_desc.hw },
1878
+
{ .hw = &clksrc_mipi1_dsi_byteclk_desc.hw },
1879
+
{ .index = -1 },
1880
+
{ .index = -1 },
1881
+
{ .index = -1 },
1882
+
{ .index = -1 },
1883
+
};
1884
+
1885
+
static struct rp1_clk_desc clk_mipi1_dpi_desc = REGISTER_CLK(
1886
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1887
+
"clk_mipi1_dpi",
1888
+
clk_mipi1_dpi_parents,
1889
+
&rp1_clk_ops,
1890
+
CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */
1891
+
),
1892
+
CLK_DATA(rp1_clock_data,
1893
+
.num_std_parents = 0,
1894
+
.num_aux_parents = 8,
1895
+
.ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL,
1896
+
.div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT,
1897
+
.div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC,
1898
+
.sel_reg = VIDEO_CLK_MIPI1_DPI_SEL,
1899
+
.div_int_max = DIV_INT_8BIT_MAX,
1900
+
.max_freq = 200 * HZ_PER_MHZ,
1901
+
.fc0_src = FC_NUM(3, 6),
1902
+
)
1903
+
);
1904
+
1905
+
static const struct clk_parent_data clk_gp2_parents[] = {
1906
+
{ .hw = &clk_sdio_alt_src_desc.hw },
1907
+
{ .index = -1 },
1908
+
{ .index = -1 },
1909
+
{ .index = -1 },
1910
+
{ .index = -1 },
1911
+
{ .index = -1 },
1912
+
{ .hw = &pll_sys_sec_desc.hw },
1913
+
{ .index = -1 },
1914
+
{ .hw = &pll_video_desc.hw },
1915
+
{ .hw = &clk_audio_in_desc.hw },
1916
+
{ .hw = &clk_dpi_desc.hw },
1917
+
{ .hw = &clk_pwm0_desc.hw },
1918
+
{ .hw = &clk_pwm1_desc.hw },
1919
+
{ .hw = &clk_mipi0_dpi_desc.hw },
1920
+
{ .hw = &clk_mipi1_cfg_desc.hw },
1921
+
{ .hw = &clk_sys_desc.hw },
1922
+
};
1923
+
1924
+
static struct rp1_clk_desc clk_gp2_desc = REGISTER_CLK(
1925
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1926
+
"clk_gp2",
1927
+
clk_gp2_parents,
1928
+
&rp1_clk_ops,
1929
+
0
1930
+
),
1931
+
CLK_DATA(rp1_clock_data,
1932
+
.num_std_parents = 0,
1933
+
.num_aux_parents = 16,
1934
+
.oe_mask = BIT(2),
1935
+
.ctrl_reg = CLK_GP2_CTRL,
1936
+
.div_int_reg = CLK_GP2_DIV_INT,
1937
+
.div_frac_reg = CLK_GP2_DIV_FRAC,
1938
+
.sel_reg = CLK_GP2_SEL,
1939
+
.div_int_max = DIV_INT_16BIT_MAX,
1940
+
.max_freq = 100 * HZ_PER_MHZ,
1941
+
.fc0_src = FC_NUM(2, 1),
1942
+
)
1943
+
);
1944
+
1945
+
static const struct clk_parent_data clk_gp3_parents[] = {
1946
+
{ .index = 0 },
1947
+
{ .index = -1 },
1948
+
{ .index = -1 },
1949
+
{ .index = -1 },
1950
+
{ .index = -1 },
1951
+
{ .index = -1 },
1952
+
{ .index = -1 },
1953
+
{ .index = -1 },
1954
+
{ .hw = &pll_video_pri_ph_desc.hw },
1955
+
{ .hw = &clk_audio_out_desc.hw },
1956
+
{ .index = -1 },
1957
+
{ .index = -1 },
1958
+
{ .hw = &clk_mipi1_dpi_desc.hw },
1959
+
{ .index = -1 },
1960
+
{ .index = -1 },
1961
+
{ .index = -1 },
1962
+
};
1963
+
1964
+
static struct rp1_clk_desc clk_gp3_desc = REGISTER_CLK(
1965
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
1966
+
"clk_gp3",
1967
+
clk_gp3_parents,
1968
+
&rp1_clk_ops,
1969
+
0
1970
+
),
1971
+
CLK_DATA(rp1_clock_data,
1972
+
.num_std_parents = 0,
1973
+
.num_aux_parents = 16,
1974
+
.oe_mask = BIT(3),
1975
+
.ctrl_reg = CLK_GP3_CTRL,
1976
+
.div_int_reg = CLK_GP3_DIV_INT,
1977
+
.div_frac_reg = CLK_GP3_DIV_FRAC,
1978
+
.sel_reg = CLK_GP3_SEL,
1979
+
.div_int_max = DIV_INT_16BIT_MAX,
1980
+
.max_freq = 100 * HZ_PER_MHZ,
1981
+
.fc0_src = FC_NUM(3, 1),
1982
+
)
1983
+
);
1984
+
1985
+
static const struct clk_parent_data clk_gp4_parents[] = {
1986
+
{ .index = 0 },
1987
+
{ .index = -1 },
1988
+
{ .index = -1 },
1989
+
{ .index = -1 },
1990
+
{ .index = -1 },
1991
+
{ .index = -1 },
1992
+
{ .index = -1 },
1993
+
{ .hw = &pll_video_sec_desc.hw },
1994
+
{ .index = -1 },
1995
+
{ .index = -1 },
1996
+
{ .index = -1 },
1997
+
{ .hw = &clk_mipi0_cfg_desc.hw },
1998
+
{ .hw = &clk_uart_desc.hw },
1999
+
{ .index = -1 },
2000
+
{ .index = -1 },
2001
+
{ .hw = &clk_sys_desc.hw },
2002
+
};
2003
+
2004
+
static struct rp1_clk_desc clk_gp4_desc = REGISTER_CLK(
2005
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
2006
+
"clk_gp4",
2007
+
clk_gp4_parents,
2008
+
&rp1_clk_ops,
2009
+
0
2010
+
),
2011
+
CLK_DATA(rp1_clock_data,
2012
+
.num_std_parents = 0,
2013
+
.num_aux_parents = 16,
2014
+
.oe_mask = BIT(4),
2015
+
.ctrl_reg = CLK_GP4_CTRL,
2016
+
.div_int_reg = CLK_GP4_DIV_INT,
2017
+
.div_frac_reg = CLK_GP4_DIV_FRAC,
2018
+
.sel_reg = CLK_GP4_SEL,
2019
+
.div_int_max = DIV_INT_16BIT_MAX,
2020
+
.max_freq = 100 * HZ_PER_MHZ,
2021
+
.fc0_src = FC_NUM(4, 1),
2022
+
)
2023
+
);
2024
+
2025
+
static const struct clk_parent_data clk_vec_parents[] = {
2026
+
{ .hw = &pll_sys_pri_ph_desc.hw },
2027
+
{ .hw = &pll_video_sec_desc.hw },
2028
+
{ .hw = &pll_video_desc.hw },
2029
+
{ .index = -1 },
2030
+
{ .index = -1 },
2031
+
{ .index = -1 },
2032
+
{ .index = -1 },
2033
+
{ .index = -1 },
2034
+
};
2035
+
2036
+
static struct rp1_clk_desc clk_vec_desc = REGISTER_CLK(
2037
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
2038
+
"clk_vec",
2039
+
clk_vec_parents,
2040
+
&rp1_clk_ops,
2041
+
CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */
2042
+
),
2043
+
CLK_DATA(rp1_clock_data,
2044
+
.num_std_parents = 0,
2045
+
.num_aux_parents = 8,
2046
+
.ctrl_reg = VIDEO_CLK_VEC_CTRL,
2047
+
.div_int_reg = VIDEO_CLK_VEC_DIV_INT,
2048
+
.sel_reg = VIDEO_CLK_VEC_SEL,
2049
+
.div_int_max = DIV_INT_8BIT_MAX,
2050
+
.max_freq = 108 * HZ_PER_MHZ,
2051
+
.fc0_src = FC_NUM(0, 6),
2052
+
)
2053
+
);
2054
+
2055
+
static const struct clk_parent_data clk_gp5_parents[] = {
2056
+
{ .index = 0 },
2057
+
{ .index = -1 },
2058
+
{ .index = -1 },
2059
+
{ .index = -1 },
2060
+
{ .index = -1 },
2061
+
{ .index = -1 },
2062
+
{ .index = -1 },
2063
+
{ .hw = &pll_video_sec_desc.hw },
2064
+
{ .hw = &clk_eth_tsu_desc.hw },
2065
+
{ .index = -1 },
2066
+
{ .hw = &clk_vec_desc.hw },
2067
+
{ .index = -1 },
2068
+
{ .index = -1 },
2069
+
{ .index = -1 },
2070
+
{ .index = -1 },
2071
+
{ .index = -1 },
2072
+
};
2073
+
2074
+
static struct rp1_clk_desc clk_gp5_desc = REGISTER_CLK(
2075
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(
2076
+
"clk_gp5",
2077
+
clk_gp5_parents,
2078
+
&rp1_clk_ops,
2079
+
0
2080
+
),
2081
+
CLK_DATA(rp1_clock_data,
2082
+
.num_std_parents = 0,
2083
+
.num_aux_parents = 16,
2084
+
.oe_mask = BIT(5),
2085
+
.ctrl_reg = CLK_GP5_CTRL,
2086
+
.div_int_reg = CLK_GP5_DIV_INT,
2087
+
.div_frac_reg = CLK_GP5_DIV_FRAC,
2088
+
.sel_reg = CLK_GP5_SEL,
2089
+
.div_int_max = DIV_INT_16BIT_MAX,
2090
+
.max_freq = 100 * HZ_PER_MHZ,
2091
+
.fc0_src = FC_NUM(5, 1),
2092
+
)
2093
+
);
2094
+
1526
2095
static struct rp1_clk_desc *const clk_desc_array[] = {
1527
2096
[RP1_PLL_SYS_CORE] = &pll_sys_core_desc,
1528
2097
[RP1_PLL_AUDIO_CORE] = &pll_audio_core_desc,
···
2283
1352
[RP1_CLK_SYS] = &clk_sys_desc,
2284
1353
[RP1_PLL_SYS_PRI_PH] = &pll_sys_pri_ph_desc,
2285
1354
[RP1_PLL_SYS_SEC] = &pll_sys_sec_desc,
1355
+
[RP1_PLL_AUDIO] = &pll_audio_desc,
1356
+
[RP1_PLL_VIDEO] = &pll_video_desc,
1357
+
[RP1_PLL_AUDIO_PRI_PH] = &pll_audio_pri_ph_desc,
1358
+
[RP1_PLL_VIDEO_PRI_PH] = &pll_video_pri_ph_desc,
1359
+
[RP1_PLL_AUDIO_SEC] = &pll_audio_sec_desc,
1360
+
[RP1_PLL_VIDEO_SEC] = &pll_video_sec_desc,
1361
+
[RP1_PLL_AUDIO_TERN] = &pll_audio_tern_desc,
1362
+
[RP1_CLK_SLOW_SYS] = &clk_slow_sys_desc,
1363
+
[RP1_CLK_DMA] = &clk_dma_desc,
1364
+
[RP1_CLK_UART] = &clk_uart_desc,
1365
+
[RP1_CLK_PWM0] = &clk_pwm0_desc,
1366
+
[RP1_CLK_PWM1] = &clk_pwm1_desc,
1367
+
[RP1_CLK_AUDIO_IN] = &clk_audio_in_desc,
1368
+
[RP1_CLK_AUDIO_OUT] = &clk_audio_out_desc,
1369
+
[RP1_CLK_I2S] = &clk_i2s_desc,
1370
+
[RP1_CLK_MIPI0_CFG] = &clk_mipi0_cfg_desc,
1371
+
[RP1_CLK_MIPI1_CFG] = &clk_mipi1_cfg_desc,
1372
+
[RP1_CLK_ADC] = &clk_adc_desc,
1373
+
[RP1_CLK_SDIO_TIMER] = &clk_sdio_timer_desc,
1374
+
[RP1_CLK_SDIO_ALT_SRC] = &clk_sdio_alt_src_desc,
1375
+
[RP1_CLK_GP0] = &clk_gp0_desc,
1376
+
[RP1_CLK_GP1] = &clk_gp1_desc,
1377
+
[RP1_CLK_GP2] = &clk_gp2_desc,
1378
+
[RP1_CLK_GP3] = &clk_gp3_desc,
1379
+
[RP1_CLK_GP4] = &clk_gp4_desc,
1380
+
[RP1_CLK_GP5] = &clk_gp5_desc,
1381
+
[RP1_CLK_VEC] = &clk_vec_desc,
1382
+
[RP1_CLK_DPI] = &clk_dpi_desc,
1383
+
[RP1_CLK_MIPI0_DPI] = &clk_mipi0_dpi_desc,
1384
+
[RP1_CLK_MIPI1_DPI] = &clk_mipi1_dpi_desc,
1385
+
[RP1_CLK_MIPI0_DSI_BYTECLOCK] = &clksrc_mipi0_dsi_byteclk_desc,
1386
+
[RP1_CLK_MIPI1_DSI_BYTECLOCK] = &clksrc_mipi1_dsi_byteclk_desc,
2286
1387
};
2287
1388
2288
1389
static const struct regmap_range rp1_reg_ranges[] = {
···
2428
1465
if (desc && desc->clk_register && desc->data)
2429
1466
hws[i] = desc->clk_register(clockman, desc);
2430
1467
}
1468
+
1469
+
clk_audio_core = &pll_audio_core_desc;
1470
+
clk_audio = &pll_audio_desc;
1471
+
clk_i2s = &clk_i2s_desc;
1472
+
clk_xosc = clk_hw_get_parent_by_index(&clk_i2s->hw, 0);
2431
1473
2432
1474
platform_set_drvdata(pdev, clockman);
2433
1475
+1
-1
drivers/firmware/broadcom/bcm47xx_sprom.c
+1
-1
drivers/firmware/broadcom/bcm47xx_sprom.c
···
404
404
ENTRY(0x00000700, u8, pre, "noiselvl5gua1", noiselvl5gua[1], 0, fb);
405
405
ENTRY(0x00000700, u8, pre, "noiselvl5gua2", noiselvl5gua[2], 0, fb);
406
406
}
407
-
#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */
407
+
#undef ENTRY /* It's specific, uses local variable, don't use it (again). */
408
408
409
409
static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom,
410
410
const char *prefix, bool fallback)