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drm/amd/pm: correct the address of Arcturus fan related registers

These registers have different address from other SMU V11 ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by
Alex Deucher b64625a3 bc08cab6

+133 -5
+133 -5
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
··· 81 81 82 82 #define smnPCIE_ESM_CTRL 0x111003D0 83 83 84 + #define mmCG_FDO_CTRL0_ARCT 0x8B 85 + #define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0 86 + 87 + #define mmCG_FDO_CTRL1_ARCT 0x8C 88 + #define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0 89 + 90 + #define mmCG_FDO_CTRL2_ARCT 0x8D 91 + #define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0 92 + 93 + #define mmCG_TACH_CTRL_ARCT 0x8E 94 + #define mmCG_TACH_CTRL_ARCT_BASE_IDX 0 95 + 96 + #define mmCG_TACH_STATUS_ARCT 0x8F 97 + #define mmCG_TACH_STATUS_ARCT_BASE_IDX 0 98 + 99 + #define mmCG_THERMAL_STATUS_ARCT 0x90 100 + #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0 101 + 84 102 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = { 85 103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 86 104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), ··· 1180 1162 return ret; 1181 1163 } 1182 1164 1165 + static int arcturus_set_fan_static_mode(struct smu_context *smu, 1166 + uint32_t mode) 1167 + { 1168 + struct amdgpu_device *adev = smu->adev; 1169 + 1170 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, 1171 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), 1172 + CG_FDO_CTRL2, TMIN, 0)); 1173 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, 1174 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), 1175 + CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1176 + 1177 + return 0; 1178 + } 1179 + 1183 1180 static int arcturus_get_fan_speed_rpm(struct smu_context *smu, 1184 1181 uint32_t *speed) 1185 1182 { 1183 + struct amdgpu_device *adev = smu->adev; 1184 + uint32_t crystal_clock_freq = 2500; 1185 + uint32_t tach_status; 1186 + uint64_t tmp64; 1186 1187 int ret = 0; 1187 1188 1188 1189 if (!speed) ··· 1214 1177 speed); 1215 1178 break; 1216 1179 default: 1217 - ret = smu_v11_0_get_fan_speed_rpm(smu, 1218 - speed); 1180 + /* 1181 + * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1182 + * detected via register retrieving. To workaround this, we will 1183 + * report the fan speed as 0 RPM if user just requested such. 1184 + */ 1185 + if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM) 1186 + && !smu->user_dpm_profile.fan_speed_rpm) { 1187 + *speed = 0; 1188 + return 0; 1189 + } 1190 + 1191 + tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; 1192 + tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT); 1193 + do_div(tmp64, tach_status); 1194 + *speed = (uint32_t)tmp64; 1195 + 1219 1196 break; 1220 1197 } 1221 1198 1222 1199 return ret; 1200 + } 1201 + 1202 + static int arcturus_set_fan_speed_pwm(struct smu_context *smu, 1203 + uint32_t speed) 1204 + { 1205 + struct amdgpu_device *adev = smu->adev; 1206 + uint32_t duty100, duty; 1207 + uint64_t tmp64; 1208 + 1209 + speed = MIN(speed, 255); 1210 + 1211 + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), 1212 + CG_FDO_CTRL1, FMAX_DUTY100); 1213 + if (!duty100) 1214 + return -EINVAL; 1215 + 1216 + tmp64 = (uint64_t)speed * duty100; 1217 + do_div(tmp64, 255); 1218 + duty = (uint32_t)tmp64; 1219 + 1220 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT, 1221 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT), 1222 + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1223 + 1224 + return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1225 + } 1226 + 1227 + static int arcturus_set_fan_speed_rpm(struct smu_context *smu, 1228 + uint32_t speed) 1229 + { 1230 + struct amdgpu_device *adev = smu->adev; 1231 + /* 1232 + * crystal_clock_freq used for fan speed rpm calculation is 1233 + * always 25Mhz. So, hardcode it as 2500(in 10K unit). 1234 + */ 1235 + uint32_t crystal_clock_freq = 2500; 1236 + uint32_t tach_period; 1237 + 1238 + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1239 + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT, 1240 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT), 1241 + CG_TACH_CTRL, TARGET_PERIOD, 1242 + tach_period)); 1243 + 1244 + return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1245 + } 1246 + 1247 + static int arcturus_get_fan_speed_pwm(struct smu_context *smu, 1248 + uint32_t *speed) 1249 + { 1250 + struct amdgpu_device *adev = smu->adev; 1251 + uint32_t duty100, duty; 1252 + uint64_t tmp64; 1253 + 1254 + /* 1255 + * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1256 + * detected via register retrieving. To workaround this, we will 1257 + * report the fan speed as 0 PWM if user just requested such. 1258 + */ 1259 + if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM) 1260 + && !smu->user_dpm_profile.fan_speed_pwm) { 1261 + *speed = 0; 1262 + return 0; 1263 + } 1264 + 1265 + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), 1266 + CG_FDO_CTRL1, FMAX_DUTY100); 1267 + duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT), 1268 + CG_THERMAL_STATUS, FDO_PWM_DUTY); 1269 + if (!duty100) 1270 + return -EINVAL; 1271 + 1272 + tmp64 = (uint64_t)duty * 255; 1273 + do_div(tmp64, duty100); 1274 + *speed = MIN((uint32_t)tmp64, 255); 1275 + 1276 + return 0; 1223 1277 } 1224 1278 1225 1279 static int arcturus_get_fan_parameters(struct smu_context *smu) ··· 2398 2270 .print_clk_levels = arcturus_print_clk_levels, 2399 2271 .force_clk_levels = arcturus_force_clk_levels, 2400 2272 .read_sensor = arcturus_read_sensor, 2401 - .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 2273 + .get_fan_speed_pwm = arcturus_get_fan_speed_pwm, 2402 2274 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm, 2403 2275 .get_power_profile_mode = arcturus_get_power_profile_mode, 2404 2276 .set_power_profile_mode = arcturus_set_power_profile_mode, ··· 2444 2316 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 2445 2317 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 2446 2318 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 2447 - .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 2448 - .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 2319 + .set_fan_speed_pwm = arcturus_set_fan_speed_pwm, 2320 + .set_fan_speed_rpm = arcturus_set_fan_speed_rpm, 2449 2321 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 2450 2322 .gfx_off_control = smu_v11_0_gfx_off_control, 2451 2323 .register_irq_handler = smu_v11_0_register_irq_handler,