phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver

Changes the wiz_p_mac_div_sel() and wiz_mode_select() to
configure serdes for USXGMII.

Adds the support to configure mac_src_sel, refclk_sel and
rxfclk_sel in the LANECTL register and configures the serdes for
usxgmii.

[rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code.

Signed-off-by: Tanmay Patil <t-patil@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20220628122255.24265-4-rogerq@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Tanmay Patil and committed by

Vinod Koul 3 years ago b64a85fb 288440de

+50 -1

1 changed file

expand all

drivers

phy

phy-j721e-wiz.c

+50 -1

drivers/phy/ti/phy-j721e-wiz.c

··· 129 129 REG_FIELD(WIZ_LANECTL(3), 22, 23), 130 130 }; 131 131 132 + static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 133 + REG_FIELD(WIZ_LANECTL(0), 20, 21), 134 + REG_FIELD(WIZ_LANECTL(1), 20, 21), 135 + REG_FIELD(WIZ_LANECTL(2), 20, 21), 136 + REG_FIELD(WIZ_LANECTL(3), 20, 21), 137 + }; 138 + 139 + static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 140 + REG_FIELD(WIZ_LANECTL(0), 6, 7), 141 + REG_FIELD(WIZ_LANECTL(1), 6, 7), 142 + REG_FIELD(WIZ_LANECTL(2), 6, 7), 143 + REG_FIELD(WIZ_LANECTL(3), 6, 7), 144 + }; 145 + 146 + static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 147 + REG_FIELD(WIZ_LANECTL(0), 18, 19), 148 + REG_FIELD(WIZ_LANECTL(1), 18, 19), 149 + REG_FIELD(WIZ_LANECTL(2), 18, 19), 150 + REG_FIELD(WIZ_LANECTL(3), 18, 19), 151 + }; 132 152 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 133 153 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 134 154 REG_FIELD(WIZ_LANEDIV(1), 16, 22), ··· 300 280 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 301 281 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 302 282 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 283 + struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 284 + struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 285 + struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 303 286 struct regmap_field *pma_cmn_refclk_int_mode; 304 287 struct regmap_field *pma_cmn_refclk_mode; 305 288 struct regmap_field *pma_cmn_refclk_dig_div; ··· 349 326 350 327 for (i = 0; i < num_lanes; i++) { 351 328 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 352 - wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { 329 + wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 330 + wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 353 331 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 354 332 if (ret) 355 333 return ret; ··· 378 354 mode = LANE_MODE_GEN2; 379 355 else 380 356 continue; 357 + 358 + if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 359 + ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 360 + ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 361 + ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); 362 + mode = LANE_MODE_GEN1; 363 + } 381 364 382 365 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 383 366 if (ret) ··· 553 522 if (IS_ERR(wiz->p0_fullrt_div[i])) { 554 523 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 555 524 return PTR_ERR(wiz->p0_fullrt_div[i]); 525 + } 526 + 527 + wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 528 + if (IS_ERR(wiz->p0_mac_src_sel[i])) { 529 + dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 530 + return PTR_ERR(wiz->p0_mac_src_sel[i]); 531 + } 532 + 533 + wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 534 + if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 535 + dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 536 + return PTR_ERR(wiz->p0_rxfclk_sel[i]); 537 + } 538 + 539 + wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 540 + if (IS_ERR(wiz->p0_refclk_sel[i])) { 541 + dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 542 + return PTR_ERR(wiz->p0_refclk_sel[i]); 556 543 } 557 544 558 545 wiz->p_mac_div_sel0[i] =

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