Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: visconti: Add VIIF clocks
Add the control sequence of register bits to handle the clocks and the
resets of Video Input Interface.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Yuji Ishikawa
and committed by
Stephen Boyd
b65e179b
beeff790
+73
-2
+73
-2
drivers/clk/visconti/clkc-tmpv770x.c
+73
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drivers/clk/visconti/clkc-tmpv770x.c
···
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#include "reset.h"
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/* Must be equal to the last clock/reset ID increased by one */
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#define CLKS_NR (TMPV770X_CLK_BUSLCK + 1)
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#define RESETS_NR (TMPV770X_RESET_SBUSCLK + 1)
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#define CLKS_NR (TMPV770X_CLK_VIIFBS1_PROC + 1)
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#define RESETS_NR (TMPV770X_RESET_VIIFBS1_L1ISP + 1)
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static DEFINE_SPINLOCK(tmpv770x_clk_lock);
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static DEFINE_SPINLOCK(tmpv770x_rst_lock);
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static const struct clk_parent_data pietherplls_parent_data[] = {
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{ .fw_name = "pietherpll", .name = "pietherpll", },
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};
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static const struct clk_parent_data pidnnplls_parent_data[] = {
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{ .fw_name = "pidnnpll", .name = "pidnnpll", },
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};
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static const struct visconti_fixed_clk fixed_clk_tables[] = {
···
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pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
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CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
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TMPV770X_RESET_PIETHER_125M, },
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};
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static const struct visconti_clk_gate_table pidnnpll_clk_gate_tables[] = {
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{ TMPV770X_CLK_VIIFBS0, "viifbs0",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 1, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS0_PROC, "viifbs0_proc",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 18, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS0_L1ISP, "viifbs0_l1isp",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 17, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS0_L2ISP, "viifbs0_l2isp",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 16, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS1, "viifbs1",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 5, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS1_PROC, "viifbs1_proc",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 22, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS1_L1ISP, "viifbs1_l1isp",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 21, 1,
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NO_RESET, },
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{ TMPV770X_CLK_VIIFBS1_L2ISP, "viifbs1_l2isp",
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pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
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0, 0x58, 0x158, 20, 1,
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NO_RESET, },
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};
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static const struct visconti_clk_gate_table clk_gate_tables[] = {
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x14, 0x114, 0, 4,
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TMPV770X_RESET_SBUSCLK, },
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{ TMPV770X_CLK_VIIF0_CFGCLK, "csi2rx0cfg",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x58, 0x158, 0, 24,
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NO_RESET, },
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{ TMPV770X_CLK_VIIF0_APBCLK, "csi2rx0apb",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x58, 0x158, 2, 4,
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NO_RESET, },
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{ TMPV770X_CLK_VIIF1_CFGCLK, "csi2rx1cfg",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x58, 0x158, 4, 24,
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NO_RESET, },
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{ TMPV770X_CLK_VIIF1_APBCLK, "csi2rx1apb",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x58, 0x158, 6, 4,
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NO_RESET, },
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};
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static const struct visconti_reset_data clk_reset_data[] = {
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[TMPV770X_RESET_PIPCMIF] = { 0x464, 0x564, 0, },
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[TMPV770X_RESET_PICKMON] = { 0x410, 0x510, 8, },
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[TMPV770X_RESET_SBUSCLK] = { 0x414, 0x514, 0, },
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[TMPV770X_RESET_VIIFBS0] = { 0x458, 0x558, 0, },
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[TMPV770X_RESET_VIIFBS0_APB] = { 0x458, 0x558, 1, },
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[TMPV770X_RESET_VIIFBS0_L2ISP] = { 0x458, 0x558, 16, },
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[TMPV770X_RESET_VIIFBS0_L1ISP] = { 0x458, 0x558, 17, },
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[TMPV770X_RESET_VIIFBS1] = { 0x458, 0x558, 4, },
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[TMPV770X_RESET_VIIFBS1_APB] = { 0x458, 0x558, 5, },
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[TMPV770X_RESET_VIIFBS1_L2ISP] = { 0x458, 0x558, 20, },
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[TMPV770X_RESET_VIIFBS1_L1ISP] = { 0x458, 0x558, 21, },
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};
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static int visconti_clk_probe(struct platform_device *pdev)
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clk_reset_data, &tmpv770x_clk_lock);
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if (ret) {
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dev_err(dev, "Failed to register pietherpll clock gate: %d\n", ret);
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return ret;
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}
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ret = visconti_clk_register_gates(ctx, pidnnpll_clk_gate_tables,
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ARRAY_SIZE(pidnnpll_clk_gate_tables),
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clk_reset_data, &tmpv770x_clk_lock);
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if (ret) {
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dev_err(dev, "Failed to register pidnnpll clock gate: %d\n", ret);
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return ret;
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}
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