tjh.dev / kernel
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Merge tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:
"Some things that I missed due to travel, or that came in late.

Two fixes also going to stable:

- A revert of a buggy change to the 8xx TLB miss handlers.

- Our flushing of SPE (Signal Processing Engine) registers on fork
was broken.

Other changes:

- A change to the KVM decrementer emulation to use proper APIs.

- Some cleanups to the way we do code patching in the 8xx code.

- Expose the maximum possible memory for the system in
/proc/powerpc/lparcfg.

- Merge some updates from Scott: "a couple device tree updates, and a
fix for a missing prototype warning"

A few other minor fixes and a handful of fixes for our selftests.

Thanks to: Aravinda Prasad, Breno Leitao, Camelia Groza, Christophe
Leroy, Felipe Rechia, Joel Stanley, Naveen N. Rao, Paul Mackerras,
Scott Wood, Tyrel Datwyler"

* tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (21 commits)
selftests/powerpc: Fix compilation issue due to asm label
selftests/powerpc/cache_shape: Fix out-of-tree build
selftests/powerpc/switch_endian: Fix out-of-tree build
selftests/powerpc/pmu: Link ebb tests with -no-pie
selftests/powerpc/signal: Fix out-of-tree build
selftests/powerpc/ptrace: Fix out-of-tree build
powerpc/xmon: Relax frame size for clang
selftests: powerpc: Fix warning for security subdir
selftests/powerpc: Relax L1d miss targets for rfi_flush test
powerpc/process: Fix flush_all_to_thread for SPE
powerpc/pseries: add missing cpumask.h include file
selftests/powerpc: Fix ptrace tm failure
KVM: PPC: Use exported tb_to_ns() function in decrementer emulation
powerpc/pseries: Export maximum memory value
powerpc/8xx: Use patch_site for perf counters setup
powerpc/8xx: Use patch_site for memory setup patching
powerpc/code-patching: Add a helper to get the address of a patch_site
Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP"
powerpc/8xx: add missing header in 8xx_mmu.c
powerpc/8xx: Add DT node for using the SEC engine of the MPC885
...

Linus Torvalds b69f9e17 63c6e188

+169 -145
+2 -2
arch/powerpc/boot/dts/fsl/t2080rdb.dts
··· 77 77 }; 78 78 79 79 ethernet@f0000 { 80 - phy-handle = <&xg_cs4315_phy1>; 80 + phy-handle = <&xg_cs4315_phy2>; 81 81 phy-connection-type = "xgmii"; 82 82 }; 83 83 84 84 ethernet@f2000 { 85 - phy-handle = <&xg_cs4315_phy2>; 85 + phy-handle = <&xg_cs4315_phy1>; 86 86 phy-connection-type = "xgmii"; 87 87 }; 88 88
+12 -1
arch/powerpc/boot/dts/mpc885ads.dts
··· 72 72 #address-cells = <1>; 73 73 #size-cells = <1>; 74 74 device_type = "soc"; 75 - ranges = <0x0 0xff000000 0x4000>; 75 + ranges = <0x0 0xff000000 0x28000>; 76 76 bus-frequency = <0>; 77 77 78 78 // Temporary -- will go away once kernel uses ranges for get_immrbase(). ··· 223 223 #address-cells = <1>; 224 224 #size-cells = <0>; 225 225 }; 226 + }; 227 + 228 + crypto@20000 { 229 + compatible = "fsl,sec1.2", "fsl,sec1.0"; 230 + reg = <0x20000 0x8000>; 231 + interrupts = <1 1>; 232 + interrupt-parent = <&PIC>; 233 + fsl,num-channels = <1>; 234 + fsl,channel-fifo-len = <24>; 235 + fsl,exec-units-mask = <0x4c>; 236 + fsl,descriptor-types-mask = <0x05000154>; 226 237 }; 227 238 }; 228 239
+5
arch/powerpc/include/asm/code-patching.h
··· 36 36 int patch_instruction_site(s32 *addr, unsigned int instr); 37 37 int patch_branch_site(s32 *site, unsigned long target, int flags); 38 38 39 + static inline unsigned long patch_site_addr(s32 *site) 40 + { 41 + return (unsigned long)site + *site; 42 + } 43 + 39 44 int instr_is_relative_branch(unsigned int instr); 40 45 int instr_is_relative_link_branch(unsigned int instr); 41 46 int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
+15 -28
arch/powerpc/include/asm/mmu-8xx.h
··· 34 34 * respectively NA for All or X for Supervisor and no access for User. 35 35 * Then we use the APG to say whether accesses are according to Page rules or 36 36 * "all Supervisor" rules (Access to all) 37 - * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP: 38 - * When that bit is not set access is done iaw "all user" 39 - * which means no access iaw page rules. 40 - * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED 41 - * 0x => No access => 11 (all accesses performed as user iaw page definition) 42 - * 10 => No user => 01 (all accesses performed according to page definition) 43 - * 11 => User => 00 (all accesses performed as supervisor iaw page definition) 37 + * Therefore, we define 2 APG groups. lsb is _PMD_USER 38 + * 0 => No user => 01 (all accesses performed according to page definition) 39 + * 1 => User => 00 (all accesses performed as supervisor iaw page definition) 44 40 * We define all 16 groups so that all other bits of APG can take any value 45 41 */ 46 - #ifdef CONFIG_SWAP 47 - #define MI_APG_INIT 0xf4f4f4f4 48 - #else 49 42 #define MI_APG_INIT 0x44444444 50 - #endif 51 43 52 44 /* The effective page number register. When read, contains the information 53 45 * about the last instruction TLB miss. When MI_RPN is written, bits in ··· 107 115 * Supervisor and no access for user and NA for ALL. 108 116 * Then we use the APG to say whether accesses are according to Page rules or 109 117 * "all Supervisor" rules (Access to all) 110 - * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP: 111 - * When that bit is not set access is done iaw "all user" 112 - * which means no access iaw page rules. 113 - * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED 114 - * 0x => No access => 11 (all accesses performed as user iaw page definition) 115 - * 10 => No user => 01 (all accesses performed according to page definition) 116 - * 11 => User => 00 (all accesses performed as supervisor iaw page definition) 118 + * Therefore, we define 2 APG groups. lsb is _PMD_USER 119 + * 0 => No user => 01 (all accesses performed according to page definition) 120 + * 1 => User => 00 (all accesses performed as supervisor iaw page definition) 117 121 * We define all 16 groups so that all other bits of APG can take any value 118 122 */ 119 - #ifdef CONFIG_SWAP 120 - #define MD_APG_INIT 0xf4f4f4f4 121 - #else 122 123 #define MD_APG_INIT 0x44444444 123 - #endif 124 124 125 125 /* The effective page number register. When read, contains the information 126 126 * about the last instruction TLB miss. When MD_RPN is written, bits in ··· 163 179 * a processor working register during a tablewalk. 164 180 */ 165 181 #define SPRN_M_TW 799 166 - 167 - /* APGs */ 168 - #define M_APG0 0x00000000 169 - #define M_APG1 0x00000020 170 - #define M_APG2 0x00000040 171 - #define M_APG3 0x00000060 172 182 173 183 #ifdef CONFIG_PPC_MM_SLICES 174 184 #include <asm/nohash/32/slice.h> ··· 228 250 return mmu_psize_defs[mmu_psize].shift; 229 251 BUG(); 230 252 } 253 + 254 + /* patch sites */ 255 + extern s32 patch__itlbmiss_linmem_top; 256 + extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp; 257 + extern s32 patch__fixupdar_linmem_top; 258 + 259 + extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2; 260 + extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3; 261 + extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf; 231 262 232 263 #endif /* !__ASSEMBLY__ */ 233 264
+1
arch/powerpc/include/asm/rtas.h
··· 5 5 #include <linux/spinlock.h> 6 6 #include <asm/page.h> 7 7 #include <linux/time.h> 8 + #include <linux/cpumask.h> 8 9 9 10 /* 10 11 * Definitions for talking to the RTAS on CHRP machines.
+57 -40
arch/powerpc/kernel/head_8xx.S
··· 31 31 #include <asm/asm-offsets.h> 32 32 #include <asm/ptrace.h> 33 33 #include <asm/export.h> 34 + #include <asm/code-patching-asm.h> 34 35 35 36 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 36 37 /* By simply checking Address >= 0x80000000, we know if its a kernel address */ ··· 319 318 cmpli cr0, r11, PAGE_OFFSET@h 320 319 #ifndef CONFIG_PIN_TLB_TEXT 321 320 /* It is assumed that kernel code fits into the first 8M page */ 322 - _ENTRY(ITLBMiss_cmp) 323 - cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h 321 + 0: cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h 322 + patch_site 0b, patch__itlbmiss_linmem_top 324 323 #endif 325 324 #endif 326 325 #endif ··· 354 353 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 355 354 mtcr r12 356 355 #endif 357 - 358 - #ifdef CONFIG_SWAP 359 - rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1 360 - #endif 361 356 /* Load the MI_TWC with the attributes for this "segment." */ 362 357 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 363 358 359 + #ifdef CONFIG_SWAP 360 + rlwinm r11, r10, 32-5, _PAGE_PRESENT 361 + and r11, r11, r10 362 + rlwimi r10, r11, 0, _PAGE_PRESENT 363 + #endif 364 364 li r11, RPN_PATTERN | 0x200 365 365 /* The Linux PTE won't go exactly into the MMU TLB. 366 366 * Software indicator bits 20 and 23 must be clear. ··· 374 372 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 375 373 376 374 /* Restore registers */ 377 - _ENTRY(itlb_miss_exit_1) 378 - mfspr r10, SPRN_SPRG_SCRATCH0 375 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 379 376 mfspr r11, SPRN_SPRG_SCRATCH1 380 377 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 381 378 mfspr r12, SPRN_SPRG_SCRATCH2 382 379 #endif 383 380 rfi 381 + patch_site 0b, patch__itlbmiss_exit_1 382 + 384 383 #ifdef CONFIG_PERF_EVENTS 385 - _ENTRY(itlb_miss_perf) 386 - lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 384 + patch_site 0f, patch__itlbmiss_perf 385 + 0: lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 387 386 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 388 387 addi r11, r11, 1 389 388 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) ··· 438 435 #ifndef CONFIG_PIN_TLB_IMMR 439 436 cmpli cr0, r11, VIRT_IMMR_BASE@h 440 437 #endif 441 - _ENTRY(DTLBMiss_cmp) 442 - cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 438 + 0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 439 + patch_site 0b, patch__dtlbmiss_linmem_top 443 440 #ifndef CONFIG_PIN_TLB_IMMR 444 - _ENTRY(DTLBMiss_jmp) 445 - beq- DTLBMissIMMR 441 + 0: beq- DTLBMissIMMR 442 + patch_site 0b, patch__dtlbmiss_immr_jmp 446 443 #endif 447 444 blt cr7, DTLBMissLinear 448 445 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha ··· 473 470 * above. 474 471 */ 475 472 rlwimi r11, r10, 0, _PAGE_GUARDED 476 - #ifdef CONFIG_SWAP 477 - /* _PAGE_ACCESSED has to be set. We use second APG bit for that, 0 478 - * on that bit will represent a Non Access group 479 - */ 480 - rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1 481 - #endif 482 473 mtspr SPRN_MD_TWC, r11 483 474 475 + /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 476 + * We also need to know if the insn is a load/store, so: 477 + * Clear _PAGE_PRESENT and load that which will 478 + * trap into DTLB Error with store bit set accordinly. 479 + */ 480 + /* PRESENT=0x1, ACCESSED=0x20 481 + * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 482 + * r10 = (r10 & ~PRESENT) | r11; 483 + */ 484 + #ifdef CONFIG_SWAP 485 + rlwinm r11, r10, 32-5, _PAGE_PRESENT 486 + and r11, r11, r10 487 + rlwimi r10, r11, 0, _PAGE_PRESENT 488 + #endif 484 489 /* The Linux PTE won't go exactly into the MMU TLB. 485 490 * Software indicator bits 24, 25, 26, and 27 must be 486 491 * set. All other Linux PTE bits control the behavior ··· 500 489 501 490 /* Restore registers */ 502 491 mtspr SPRN_DAR, r11 /* Tag DAR */ 503 - _ENTRY(dtlb_miss_exit_1) 504 - mfspr r10, SPRN_SPRG_SCRATCH0 492 + 493 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 505 494 mfspr r11, SPRN_SPRG_SCRATCH1 506 495 mfspr r12, SPRN_SPRG_SCRATCH2 507 496 rfi 497 + patch_site 0b, patch__dtlbmiss_exit_1 498 + 508 499 #ifdef CONFIG_PERF_EVENTS 509 - _ENTRY(dtlb_miss_perf) 510 - lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 500 + patch_site 0f, patch__dtlbmiss_perf 501 + 0: lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 511 502 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 512 503 addi r11, r11, 1 513 504 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) ··· 650 637 */ 651 638 DTLBMissIMMR: 652 639 mtcr r12 653 - /* Set 512k byte guarded page and mark it valid and accessed */ 654 - li r10, MD_PS512K | MD_GUARDED | MD_SVALID | M_APG2 640 + /* Set 512k byte guarded page and mark it valid */ 641 + li r10, MD_PS512K | MD_GUARDED | MD_SVALID 655 642 mtspr SPRN_MD_TWC, r10 656 643 mfspr r10, SPRN_IMMR /* Get current IMMR */ 657 644 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ ··· 661 648 662 649 li r11, RPN_PATTERN 663 650 mtspr SPRN_DAR, r11 /* Tag DAR */ 664 - _ENTRY(dtlb_miss_exit_2) 665 - mfspr r10, SPRN_SPRG_SCRATCH0 651 + 652 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 666 653 mfspr r11, SPRN_SPRG_SCRATCH1 667 654 mfspr r12, SPRN_SPRG_SCRATCH2 668 655 rfi 656 + patch_site 0b, patch__dtlbmiss_exit_2 669 657 670 658 DTLBMissLinear: 671 659 mtcr r12 672 - /* Set 8M byte page and mark it valid and accessed */ 673 - li r11, MD_PS8MEG | MD_SVALID | M_APG2 660 + /* Set 8M byte page and mark it valid */ 661 + li r11, MD_PS8MEG | MD_SVALID 674 662 mtspr SPRN_MD_TWC, r11 675 663 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 676 664 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ ··· 680 666 681 667 li r11, RPN_PATTERN 682 668 mtspr SPRN_DAR, r11 /* Tag DAR */ 683 - _ENTRY(dtlb_miss_exit_3) 684 - mfspr r10, SPRN_SPRG_SCRATCH0 669 + 670 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 685 671 mfspr r11, SPRN_SPRG_SCRATCH1 686 672 mfspr r12, SPRN_SPRG_SCRATCH2 687 673 rfi 674 + patch_site 0b, patch__dtlbmiss_exit_3 688 675 689 676 #ifndef CONFIG_PIN_TLB_TEXT 690 677 ITLBMissLinear: 691 678 mtcr r12 692 - /* Set 8M byte page and mark it valid,accessed */ 693 - li r11, MI_PS8MEG | MI_SVALID | M_APG2 679 + /* Set 8M byte page and mark it valid */ 680 + li r11, MI_PS8MEG | MI_SVALID 694 681 mtspr SPRN_MI_TWC, r11 695 682 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 696 683 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ 697 684 _PAGE_PRESENT 698 685 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 699 686 700 - _ENTRY(itlb_miss_exit_2) 701 - mfspr r10, SPRN_SPRG_SCRATCH0 687 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 702 688 mfspr r11, SPRN_SPRG_SCRATCH1 703 689 mfspr r12, SPRN_SPRG_SCRATCH2 704 690 rfi 691 + patch_site 0b, patch__itlbmiss_exit_2 705 692 #endif 706 693 707 694 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions ··· 720 705 mfspr r11, SPRN_M_TW /* Get level 1 table */ 721 706 blt+ 3f 722 707 rlwinm r11, r10, 16, 0xfff8 723 - _ENTRY(FixupDAR_cmp) 724 - cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 708 + 709 + 0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h 710 + patch_site 0b, patch__fixupdar_linmem_top 711 + 725 712 /* create physical page address from effective address */ 726 713 tophys(r11, r10) 727 714 blt- cr7, 201f ··· 977 960 ori r8, r8, MI_EVALID /* Mark it valid */ 978 961 mtspr SPRN_MI_EPN, r8 979 962 li r8, MI_PS8MEG /* Set 8M byte page */ 980 - ori r8, r8, MI_SVALID | M_APG2 /* Make it valid, APG 2 */ 963 + ori r8, r8, MI_SVALID /* Make it valid */ 981 964 mtspr SPRN_MI_TWC, r8 982 965 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 983 966 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ ··· 1004 987 ori r8, r8, MD_EVALID /* Mark it valid */ 1005 988 mtspr SPRN_MD_EPN, r8 1006 989 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */ 1007 - ori r8, r8, MD_SVALID | M_APG2 /* Make it valid and accessed */ 990 + ori r8, r8, MD_SVALID /* Make it valid */ 1008 991 mtspr SPRN_MD_TWC, r8 1009 992 mr r8, r9 /* Create paddr for TLB */ 1010 993 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
+1 -2
arch/powerpc/kernel/process.c
··· 590 590 if (tsk->thread.regs) { 591 591 preempt_disable(); 592 592 BUG_ON(tsk != current); 593 - save_all(tsk); 594 - 595 593 #ifdef CONFIG_SPE 596 594 if (tsk->thread.regs->msr & MSR_SPE) 597 595 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); 598 596 #endif 597 + save_all(tsk); 599 598 600 599 preempt_enable(); 601 600 }
+1 -2
arch/powerpc/kvm/book3s_hv.c
··· 2337 2337 kvmppc_core_prepare_to_enter(vcpu); 2338 2338 return; 2339 2339 } 2340 - dec_nsec = (vcpu->arch.dec_expires - now) * NSEC_PER_SEC 2341 - / tb_ticks_per_sec; 2340 + dec_nsec = tb_to_ns(vcpu->arch.dec_expires - now); 2342 2341 hrtimer_start(&vcpu->arch.dec_timer, dec_nsec, HRTIMER_MODE_REL); 2343 2342 vcpu->arch.timer_running = 1; 2344 2343 }
+3 -4
arch/powerpc/kvm/emulate.c
··· 61 61 62 62 dec_time = vcpu->arch.dec; 63 63 /* 64 - * Guest timebase ticks at the same frequency as host decrementer. 65 - * So use the host decrementer calculations for decrementer emulation. 64 + * Guest timebase ticks at the same frequency as host timebase. 65 + * So use the host timebase calculations for decrementer emulation. 66 66 */ 67 - dec_time = dec_time << decrementer_clockevent.shift; 68 - do_div(dec_time, decrementer_clockevent.mult); 67 + dec_time = tb_to_ns(dec_time); 69 68 dec_nsec = do_div(dec_time, NSEC_PER_SEC); 70 69 hrtimer_start(&vcpu->arch.dec_timer, 71 70 ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL);
+9 -17
arch/powerpc/mm/8xx_mmu.c
··· 13 13 */ 14 14 15 15 #include <linux/memblock.h> 16 + #include <linux/mmu_context.h> 16 17 #include <asm/fixmap.h> 17 18 #include <asm/code-patching.h> 18 19 ··· 80 79 for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) { 81 80 mtspr(SPRN_MD_CTR, ctr | (i << 8)); 82 81 mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) | MD_EVALID); 83 - mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID | M_APG2); 82 + mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID); 84 83 mtspr(SPRN_MD_RPN, addr | flags | _PAGE_PRESENT); 85 84 addr += LARGE_PAGE_SIZE_8M; 86 85 mem -= LARGE_PAGE_SIZE_8M; ··· 98 97 map_kernel_page(v + offset, p + offset, PAGE_KERNEL_NCG); 99 98 } 100 99 101 - /* Address of instructions to patch */ 102 - #ifndef CONFIG_PIN_TLB_IMMR 103 - extern unsigned int DTLBMiss_jmp; 104 - #endif 105 - extern unsigned int DTLBMiss_cmp, FixupDAR_cmp; 106 - #ifndef CONFIG_PIN_TLB_TEXT 107 - extern unsigned int ITLBMiss_cmp; 108 - #endif 109 - 110 - static void __init mmu_patch_cmp_limit(unsigned int *addr, unsigned long mapped) 100 + static void __init mmu_patch_cmp_limit(s32 *site, unsigned long mapped) 111 101 { 112 - unsigned int instr = *addr; 102 + unsigned int instr = *(unsigned int *)patch_site_addr(site); 113 103 114 104 instr &= 0xffff0000; 115 105 instr |= (unsigned long)__va(mapped) >> 16; 116 - patch_instruction(addr, instr); 106 + patch_instruction_site(site, instr); 117 107 } 118 108 119 109 unsigned long __init mmu_mapin_ram(unsigned long top) ··· 115 123 mapped = 0; 116 124 mmu_mapin_immr(); 117 125 #ifndef CONFIG_PIN_TLB_IMMR 118 - patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP); 126 + patch_instruction_site(&patch__dtlbmiss_immr_jmp, PPC_INST_NOP); 119 127 #endif 120 128 #ifndef CONFIG_PIN_TLB_TEXT 121 - mmu_patch_cmp_limit(&ITLBMiss_cmp, 0); 129 + mmu_patch_cmp_limit(&patch__itlbmiss_linmem_top, 0); 122 130 #endif 123 131 } else { 124 132 mapped = top & ~(LARGE_PAGE_SIZE_8M - 1); 125 133 } 126 134 127 - mmu_patch_cmp_limit(&DTLBMiss_cmp, mapped); 128 - mmu_patch_cmp_limit(&FixupDAR_cmp, mapped); 135 + mmu_patch_cmp_limit(&patch__dtlbmiss_linmem_top, mapped); 136 + mmu_patch_cmp_limit(&patch__fixupdar_linmem_top, mapped); 129 137 130 138 /* If the size of RAM is not an exact power of two, we may not 131 139 * have covered RAM in its entirety with 8 MiB
+12 -15
arch/powerpc/perf/8xx-pmu.c
··· 31 31 32 32 extern unsigned long itlb_miss_counter, dtlb_miss_counter; 33 33 extern atomic_t instruction_counter; 34 - extern unsigned int itlb_miss_perf, dtlb_miss_perf; 35 - extern unsigned int itlb_miss_exit_1, itlb_miss_exit_2; 36 - extern unsigned int dtlb_miss_exit_1, dtlb_miss_exit_2, dtlb_miss_exit_3; 37 34 38 35 static atomic_t insn_ctr_ref; 39 36 static atomic_t itlb_miss_ref; ··· 100 103 break; 101 104 case PERF_8xx_ID_ITLB_LOAD_MISS: 102 105 if (atomic_inc_return(&itlb_miss_ref) == 1) { 103 - unsigned long target = (unsigned long)&itlb_miss_perf; 106 + unsigned long target = patch_site_addr(&patch__itlbmiss_perf); 104 107 105 - patch_branch(&itlb_miss_exit_1, target, 0); 108 + patch_branch_site(&patch__itlbmiss_exit_1, target, 0); 106 109 #ifndef CONFIG_PIN_TLB_TEXT 107 - patch_branch(&itlb_miss_exit_2, target, 0); 110 + patch_branch_site(&patch__itlbmiss_exit_2, target, 0); 108 111 #endif 109 112 } 110 113 val = itlb_miss_counter; 111 114 break; 112 115 case PERF_8xx_ID_DTLB_LOAD_MISS: 113 116 if (atomic_inc_return(&dtlb_miss_ref) == 1) { 114 - unsigned long target = (unsigned long)&dtlb_miss_perf; 117 + unsigned long target = patch_site_addr(&patch__dtlbmiss_perf); 115 118 116 - patch_branch(&dtlb_miss_exit_1, target, 0); 117 - patch_branch(&dtlb_miss_exit_2, target, 0); 118 - patch_branch(&dtlb_miss_exit_3, target, 0); 119 + patch_branch_site(&patch__dtlbmiss_exit_1, target, 0); 120 + patch_branch_site(&patch__dtlbmiss_exit_2, target, 0); 121 + patch_branch_site(&patch__dtlbmiss_exit_3, target, 0); 119 122 } 120 123 val = dtlb_miss_counter; 121 124 break; ··· 177 180 break; 178 181 case PERF_8xx_ID_ITLB_LOAD_MISS: 179 182 if (atomic_dec_return(&itlb_miss_ref) == 0) { 180 - patch_instruction(&itlb_miss_exit_1, insn); 183 + patch_instruction_site(&patch__itlbmiss_exit_1, insn); 181 184 #ifndef CONFIG_PIN_TLB_TEXT 182 - patch_instruction(&itlb_miss_exit_2, insn); 185 + patch_instruction_site(&patch__itlbmiss_exit_2, insn); 183 186 #endif 184 187 } 185 188 break; 186 189 case PERF_8xx_ID_DTLB_LOAD_MISS: 187 190 if (atomic_dec_return(&dtlb_miss_ref) == 0) { 188 - patch_instruction(&dtlb_miss_exit_1, insn); 189 - patch_instruction(&dtlb_miss_exit_2, insn); 190 - patch_instruction(&dtlb_miss_exit_3, insn); 191 + patch_instruction_site(&patch__dtlbmiss_exit_1, insn); 192 + patch_instruction_site(&patch__dtlbmiss_exit_2, insn); 193 + patch_instruction_site(&patch__dtlbmiss_exit_3, insn); 191 194 } 192 195 break; 193 196 }
+13
arch/powerpc/platforms/pseries/lparcfg.c
··· 26 26 #include <linux/seq_file.h> 27 27 #include <linux/slab.h> 28 28 #include <linux/uaccess.h> 29 + #include <linux/hugetlb.h> 29 30 #include <asm/lppaca.h> 30 31 #include <asm/hvcall.h> 31 32 #include <asm/firmware.h> ··· 37 36 #include <asm/vio.h> 38 37 #include <asm/mmu.h> 39 38 #include <asm/machdep.h> 39 + #include <asm/drmem.h> 40 40 41 41 #include "pseries.h" 42 42 ··· 435 433 seq_printf(m, "power_mode_data=%016lx\n", retbuf[0]); 436 434 } 437 435 436 + static void maxmem_data(struct seq_file *m) 437 + { 438 + unsigned long maxmem = 0; 439 + 440 + maxmem += drmem_info->n_lmbs * drmem_info->lmb_size; 441 + maxmem += hugetlb_total_pages() * PAGE_SIZE; 442 + 443 + seq_printf(m, "MaxMem=%ld\n", maxmem); 444 + } 445 + 438 446 static int pseries_lparcfg_data(struct seq_file *m, void *v) 439 447 { 440 448 int partition_potential_processors; ··· 503 491 seq_printf(m, "slb_size=%d\n", mmu_slb_size); 504 492 #endif 505 493 parse_em_data(m); 494 + maxmem_data(m); 506 495 507 496 return 0; 508 497 }
+6
arch/powerpc/xmon/Makefile
··· 11 11 ORIG_CFLAGS := $(KBUILD_CFLAGS) 12 12 KBUILD_CFLAGS = $(subst $(CC_FLAGS_FTRACE),,$(ORIG_CFLAGS)) 13 13 14 + ifdef CONFIG_CC_IS_CLANG 15 + # clang stores addresses on the stack causing the frame size to blow 16 + # out. See https://github.com/ClangBuiltLinux/linux/issues/252 17 + KBUILD_CFLAGS += -Wframe-larger-than=4096 18 + endif 19 + 14 20 ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC) 15 21 16 22 obj-y += xmon.o nonstdio.o spr_access.o
+2 -7
tools/testing/selftests/powerpc/cache_shape/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 - TEST_PROGS := cache_shape 3 - 4 - all: $(TEST_PROGS) 5 - 6 - $(TEST_PROGS): ../harness.c ../utils.c 2 + TEST_GEN_PROGS := cache_shape 7 3 8 4 top_srcdir = ../../../../.. 9 5 include ../../lib.mk 10 6 11 - clean: 12 - rm -f $(TEST_PROGS) *.o 7 + $(TEST_GEN_PROGS): ../harness.c ../utils.c
+3
tools/testing/selftests/powerpc/pmu/ebb/Makefile
··· 5 5 # The EBB handler is 64-bit code and everything links against it 6 6 CFLAGS += -m64 7 7 8 + # Toolchains may build PIE by default which breaks the assembly 9 + LDFLAGS += -no-pie 10 + 8 11 TEST_GEN_PROGS := reg_access_test event_attributes_test cycles_test \ 9 12 cycles_with_freeze_test pmc56_overflow_test \ 10 13 ebb_vs_cpu_event_test cpu_event_vs_ebb_test \
+4 -9
tools/testing/selftests/powerpc/ptrace/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 - TEST_PROGS := ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \ 2 + TEST_GEN_PROGS := ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \ 3 3 ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx ptrace-tm-vsx \ 4 4 ptrace-tm-spd-vsx ptrace-tm-spr ptrace-hwbreak ptrace-pkey core-pkey \ 5 5 perf-hwbreak ptrace-syscall ··· 7 7 top_srcdir = ../../../../.. 8 8 include ../../lib.mk 9 9 10 - all: $(TEST_PROGS) 11 - 12 10 CFLAGS += -m64 -I../../../../../usr/include -I../tm -mhtm -fno-pie 13 11 14 - ptrace-pkey core-pkey: child.h 15 - ptrace-pkey core-pkey: LDLIBS += -pthread 12 + $(OUTPUT)/ptrace-pkey $(OUTPUT)/core-pkey: child.h 13 + $(OUTPUT)/ptrace-pkey $(OUTPUT)/core-pkey: LDLIBS += -pthread 16 14 17 - $(TEST_PROGS): ../harness.c ../utils.c ../lib/reg.S ptrace.h 18 - 19 - clean: 20 - rm -f $(TEST_PROGS) *.o 15 + $(TEST_GEN_PROGS): ../harness.c ../utils.c ../lib/reg.S ptrace.h
+2 -2
tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c
··· 67 67 "3: ;" 68 68 : [res] "=r" (result), [texasr] "=r" (texasr) 69 69 : [gpr_1]"i"(GPR_1), [gpr_2]"i"(GPR_2), [gpr_4]"i"(GPR_4), 70 - [sprn_texasr] "i" (SPRN_TEXASR), [flt_1] "r" (&a), 71 - [flt_2] "r" (&b), [flt_4] "r" (&d) 70 + [sprn_texasr] "i" (SPRN_TEXASR), [flt_1] "b" (&a), 71 + [flt_4] "b" (&d) 72 72 : "memory", "r5", "r6", "r7", 73 73 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 74 74 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+1
tools/testing/selftests/powerpc/security/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0+ 2 2 3 3 TEST_GEN_PROGS := rfi_flush 4 + top_srcdir = ../../../../.. 4 5 5 6 CFLAGS += -I../../../../../usr/include 6 7
+13 -5
tools/testing/selftests/powerpc/security/rfi_flush.c
··· 49 49 struct perf_event_read v; 50 50 __u64 l1d_misses_total = 0; 51 51 unsigned long iterations = 100000, zero_size = 24 * 1024; 52 + unsigned long l1d_misses_expected; 52 53 int rfi_flush_org, rfi_flush; 53 54 54 55 SKIP_IF(geteuid() != 0); ··· 72 71 73 72 iter = repetitions; 74 73 74 + /* 75 + * We expect to see l1d miss for each cacheline access when rfi_flush 76 + * is set. Allow a small variation on this. 77 + */ 78 + l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); 79 + 75 80 again: 76 81 FAIL_IF(perf_event_reset(fd)); 77 82 ··· 85 78 86 79 FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v)); 87 80 88 - /* Expect at least zero_size/CACHELINE_SIZE misses per iteration */ 89 - if (v.l1d_misses >= (iterations * zero_size / CACHELINE_SIZE) && rfi_flush) 81 + if (rfi_flush && v.l1d_misses >= l1d_misses_expected) 90 82 passes++; 91 - else if (v.l1d_misses < iterations && !rfi_flush) 83 + else if (!rfi_flush && v.l1d_misses < (l1d_misses_expected / 2)) 92 84 passes++; 93 85 94 86 l1d_misses_total += v.l1d_misses; ··· 98 92 if (passes < repetitions) { 99 93 printf("FAIL (L1D misses with rfi_flush=%d: %llu %c %lu) [%d/%d failures]\n", 100 94 rfi_flush, l1d_misses_total, rfi_flush ? '<' : '>', 101 - rfi_flush ? (repetitions * iterations * zero_size / CACHELINE_SIZE) : iterations, 95 + rfi_flush ? repetitions * l1d_misses_expected : 96 + repetitions * l1d_misses_expected / 2, 102 97 repetitions - passes, repetitions); 103 98 rc = 1; 104 99 } else 105 100 printf("PASS (L1D misses with rfi_flush=%d: %llu %c %lu) [%d/%d pass]\n", 106 101 rfi_flush, l1d_misses_total, rfi_flush ? '>' : '<', 107 - rfi_flush ? (repetitions * iterations * zero_size / CACHELINE_SIZE) : iterations, 102 + rfi_flush ? repetitions * l1d_misses_expected : 103 + repetitions * l1d_misses_expected / 2, 108 104 passes, repetitions); 109 105 110 106 if (rfi_flush == rfi_flush_org) {
+3 -8
tools/testing/selftests/powerpc/signal/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 - TEST_PROGS := signal signal_tm 3 - 4 - all: $(TEST_PROGS) 5 - 6 - $(TEST_PROGS): ../harness.c ../utils.c signal.S 2 + TEST_GEN_PROGS := signal signal_tm 7 3 8 4 CFLAGS += -maltivec 9 - signal_tm: CFLAGS += -mhtm 5 + $(OUTPUT)/signal_tm: CFLAGS += -mhtm 10 6 11 7 top_srcdir = ../../../../.. 12 8 include ../../lib.mk 13 9 14 - clean: 15 - rm -f $(TEST_PROGS) *.o 10 + $(TEST_GEN_PROGS): ../harness.c ../utils.c signal.S
+1
tools/testing/selftests/powerpc/switch_endian/Makefile
··· 8 8 top_srcdir = ../../../../.. 9 9 include ../../lib.mk 10 10 11 + $(OUTPUT)/switch_endian_test: ASFLAGS += -I $(OUTPUT) 11 12 $(OUTPUT)/switch_endian_test: $(OUTPUT)/check-reversed.S 12 13 13 14 $(OUTPUT)/check-reversed.o: $(OUTPUT)/check.o
+3 -3
tools/testing/selftests/powerpc/utils.c
··· 25 25 #include "utils.h" 26 26 27 27 static char auxv[4096]; 28 - extern unsigned int dscr_insn[]; 29 28 30 29 int read_auxv(char *buf, ssize_t buf_size) 31 30 { ··· 246 247 ucontext_t *ctx = (ucontext_t *)unused; 247 248 unsigned long *pc = &UCONTEXT_NIA(ctx); 248 249 249 - if (*pc == (unsigned long)&dscr_insn) { 250 + /* mtspr 3,RS to check for move to DSCR below */ 251 + if ((*((unsigned int *)*pc) & 0xfc1fffff) == 0x7c0303a6) { 250 252 if (!warned++) 251 253 printf("WARNING: Skipping over dscr setup. Consider running 'ppc64_cpu --dscr=1' manually.\n"); 252 254 *pc += 4; ··· 271 271 init = 1; 272 272 } 273 273 274 - asm volatile("dscr_insn: mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); 274 + asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); 275 275 }