drm/amdgpu: Move ip block related functions

+1 -120

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 116 116 #include "amdgpu_reg_state.h" 117 117 #include "amdgpu_userq.h" 118 118 #include "amdgpu_eviction_fence.h" 119 + #include "amdgpu_ip.h" 119 120 #if defined(CONFIG_DRM_AMD_ISP) 120 121 #include "amdgpu_isp.h" 121 122 #endif ··· 362 361 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 363 362 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 364 363 #define MAX_KIQ_REG_TRY 1000 365 - 366 - int amdgpu_device_ip_set_clockgating_state(void *dev, 367 - enum amd_ip_block_type block_type, 368 - enum amd_clockgating_state state); 369 - int amdgpu_device_ip_set_powergating_state(void *dev, 370 - enum amd_ip_block_type block_type, 371 - enum amd_powergating_state state); 372 - void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 373 - u64 *flags); 374 - int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 375 - enum amd_ip_block_type block_type); 376 - bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, 377 - enum amd_ip_block_type block_type); 378 - bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 379 - enum amd_ip_block_type block_type); 380 - int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 381 - 382 - int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 383 - 384 - #define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM 385 - 386 - struct amdgpu_ip_block_status { 387 - bool valid; 388 - bool sw; 389 - bool hw; 390 - bool late_initialized; 391 - bool hang; 392 - }; 393 - 394 - struct amdgpu_ip_block_version { 395 - const enum amd_ip_block_type type; 396 - const u32 major; 397 - const u32 minor; 398 - const u32 rev; 399 - const struct amd_ip_funcs *funcs; 400 - }; 401 - 402 - struct amdgpu_ip_block { 403 - struct amdgpu_ip_block_status status; 404 - const struct amdgpu_ip_block_version *version; 405 - struct amdgpu_device *adev; 406 - }; 407 - 408 - int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 409 - enum amd_ip_block_type type, 410 - u32 major, u32 minor); 411 - 412 - struct amdgpu_ip_block * 413 - amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 414 - enum amd_ip_block_type type); 415 - 416 - int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 417 - const struct amdgpu_ip_block_version *ip_block_version); 418 364 419 365 /* 420 366 * BIOS. ··· 703 755 u32 reg_offset; 704 756 resource_size_t bus_addr; 705 757 struct amdgpu_bo *bo; 706 - }; 707 - 708 - /* Define the HW IP blocks will be used in driver , add more if necessary */ 709 - enum amd_hw_ip_block_type { 710 - GC_HWIP = 1, 711 - HDP_HWIP, 712 - SDMA0_HWIP, 713 - SDMA1_HWIP, 714 - SDMA2_HWIP, 715 - SDMA3_HWIP, 716 - SDMA4_HWIP, 717 - SDMA5_HWIP, 718 - SDMA6_HWIP, 719 - SDMA7_HWIP, 720 - LSDMA_HWIP, 721 - MMHUB_HWIP, 722 - ATHUB_HWIP, 723 - NBIO_HWIP, 724 - MP0_HWIP, 725 - MP1_HWIP, 726 - UVD_HWIP, 727 - VCN_HWIP = UVD_HWIP, 728 - JPEG_HWIP = VCN_HWIP, 729 - VCN1_HWIP, 730 - VCE_HWIP, 731 - VPE_HWIP, 732 - DF_HWIP, 733 - DCE_HWIP, 734 - OSSSYS_HWIP, 735 - SMUIO_HWIP, 736 - PWR_HWIP, 737 - NBIF_HWIP, 738 - THM_HWIP, 739 - CLK_HWIP, 740 - UMC_HWIP, 741 - RSMU_HWIP, 742 - XGMI_HWIP, 743 - DCI_HWIP, 744 - PCIE_HWIP, 745 - ISP_HWIP, 746 - ATU_HWIP, 747 - AIGC_HWIP, 748 - MAX_HWIP 749 - }; 750 - 751 - #define HWIP_MAX_INSTANCE 48 752 - 753 - #define HW_ID_MAX 300 754 - #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 755 - (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 756 - #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 757 - #define IP_VERSION_MAJ(ver) ((ver) >> 24) 758 - #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 759 - #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 760 - #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 761 - #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 762 - #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 763 - 764 - struct amdgpu_ip_map_info { 765 - /* Map of logical to actual dev instances/mask */ 766 - uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 767 - int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 768 - enum amd_hw_ip_block_type block, 769 - int8_t inst); 770 - uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 771 - enum amd_hw_ip_block_type block, 772 - uint32_t mask); 773 758 }; 774 759 775 760 enum amdgpu_uid_type {

-323

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 313 313 sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state); 314 314 } 315 315 316 - int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block) 317 - { 318 - int r; 319 - 320 - if (ip_block->version->funcs->suspend) { 321 - r = ip_block->version->funcs->suspend(ip_block); 322 - if (r) { 323 - dev_err(ip_block->adev->dev, 324 - "suspend of IP block <%s> failed %d\n", 325 - ip_block->version->funcs->name, r); 326 - return r; 327 - } 328 - } 329 - 330 - ip_block->status.hw = false; 331 - return 0; 332 - } 333 - 334 - int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) 335 - { 336 - int r; 337 - 338 - if (ip_block->version->funcs->resume) { 339 - r = ip_block->version->funcs->resume(ip_block); 340 - if (r) { 341 - dev_err(ip_block->adev->dev, 342 - "resume of IP block <%s> failed %d\n", 343 - ip_block->version->funcs->name, r); 344 - return r; 345 - } 346 - } 347 - 348 - ip_block->status.hw = true; 349 - return 0; 350 - } 351 - 352 316 /** 353 317 * DOC: board_info 354 318 * ··· 2228 2264 .reprobe = NULL, 2229 2265 .can_switch = amdgpu_switcheroo_can_switch, 2230 2266 }; 2231 - 2232 - /** 2233 - * amdgpu_device_ip_set_clockgating_state - set the CG state 2234 - * 2235 - * @dev: amdgpu_device pointer 2236 - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 2237 - * @state: clockgating state (gate or ungate) 2238 - * 2239 - * Sets the requested clockgating state for all instances of 2240 - * the hardware IP specified. 2241 - * Returns the error code from the last instance. 2242 - */ 2243 - int amdgpu_device_ip_set_clockgating_state(void *dev, 2244 - enum amd_ip_block_type block_type, 2245 - enum amd_clockgating_state state) 2246 - { 2247 - struct amdgpu_device *adev = dev; 2248 - int i, r = 0; 2249 - 2250 - for (i = 0; i < adev->num_ip_blocks; i++) { 2251 - if (!adev->ip_blocks[i].status.valid) 2252 - continue; 2253 - if (adev->ip_blocks[i].version->type != block_type) 2254 - continue; 2255 - if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) 2256 - continue; 2257 - r = adev->ip_blocks[i].version->funcs->set_clockgating_state( 2258 - &adev->ip_blocks[i], state); 2259 - if (r) 2260 - dev_err(adev->dev, 2261 - "set_clockgating_state of IP block <%s> failed %d\n", 2262 - adev->ip_blocks[i].version->funcs->name, r); 2263 - } 2264 - return r; 2265 - } 2266 - 2267 - /** 2268 - * amdgpu_device_ip_set_powergating_state - set the PG state 2269 - * 2270 - * @dev: amdgpu_device pointer 2271 - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 2272 - * @state: powergating state (gate or ungate) 2273 - * 2274 - * Sets the requested powergating state for all instances of 2275 - * the hardware IP specified. 2276 - * Returns the error code from the last instance. 2277 - */ 2278 - int amdgpu_device_ip_set_powergating_state(void *dev, 2279 - enum amd_ip_block_type block_type, 2280 - enum amd_powergating_state state) 2281 - { 2282 - struct amdgpu_device *adev = dev; 2283 - int i, r = 0; 2284 - 2285 - for (i = 0; i < adev->num_ip_blocks; i++) { 2286 - if (!adev->ip_blocks[i].status.valid) 2287 - continue; 2288 - if (adev->ip_blocks[i].version->type != block_type) 2289 - continue; 2290 - if (!adev->ip_blocks[i].version->funcs->set_powergating_state) 2291 - continue; 2292 - r = adev->ip_blocks[i].version->funcs->set_powergating_state( 2293 - &adev->ip_blocks[i], state); 2294 - if (r) 2295 - dev_err(adev->dev, 2296 - "set_powergating_state of IP block <%s> failed %d\n", 2297 - adev->ip_blocks[i].version->funcs->name, r); 2298 - } 2299 - return r; 2300 - } 2301 - 2302 - /** 2303 - * amdgpu_device_ip_get_clockgating_state - get the CG state 2304 - * 2305 - * @adev: amdgpu_device pointer 2306 - * @flags: clockgating feature flags 2307 - * 2308 - * Walks the list of IPs on the device and updates the clockgating 2309 - * flags for each IP. 2310 - * Updates @flags with the feature flags for each hardware IP where 2311 - * clockgating is enabled. 2312 - */ 2313 - void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 2314 - u64 *flags) 2315 - { 2316 - int i; 2317 - 2318 - for (i = 0; i < adev->num_ip_blocks; i++) { 2319 - if (!adev->ip_blocks[i].status.valid) 2320 - continue; 2321 - if (adev->ip_blocks[i].version->funcs->get_clockgating_state) 2322 - adev->ip_blocks[i].version->funcs->get_clockgating_state( 2323 - &adev->ip_blocks[i], flags); 2324 - } 2325 - } 2326 - 2327 - /** 2328 - * amdgpu_device_ip_wait_for_idle - wait for idle 2329 - * 2330 - * @adev: amdgpu_device pointer 2331 - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 2332 - * 2333 - * Waits for the request hardware IP to be idle. 2334 - * Returns 0 for success or a negative error code on failure. 2335 - */ 2336 - int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 2337 - enum amd_ip_block_type block_type) 2338 - { 2339 - int i, r; 2340 - 2341 - for (i = 0; i < adev->num_ip_blocks; i++) { 2342 - if (!adev->ip_blocks[i].status.valid) 2343 - continue; 2344 - if (adev->ip_blocks[i].version->type == block_type) { 2345 - if (adev->ip_blocks[i].version->funcs->wait_for_idle) { 2346 - r = adev->ip_blocks[i].version->funcs->wait_for_idle( 2347 - &adev->ip_blocks[i]); 2348 - if (r) 2349 - return r; 2350 - } 2351 - break; 2352 - } 2353 - } 2354 - return 0; 2355 - 2356 - } 2357 - 2358 - /** 2359 - * amdgpu_device_ip_is_hw - is the hardware IP enabled 2360 - * 2361 - * @adev: amdgpu_device pointer 2362 - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 2363 - * 2364 - * Check if the hardware IP is enable or not. 2365 - * Returns true if it the IP is enable, false if not. 2366 - */ 2367 - bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, 2368 - enum amd_ip_block_type block_type) 2369 - { 2370 - int i; 2371 - 2372 - for (i = 0; i < adev->num_ip_blocks; i++) { 2373 - if (adev->ip_blocks[i].version->type == block_type) 2374 - return adev->ip_blocks[i].status.hw; 2375 - } 2376 - return false; 2377 - } 2378 - 2379 - /** 2380 - * amdgpu_device_ip_is_valid - is the hardware IP valid 2381 - * 2382 - * @adev: amdgpu_device pointer 2383 - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 2384 - * 2385 - * Check if the hardware IP is valid or not. 2386 - * Returns true if it the IP is valid, false if not. 2387 - */ 2388 - bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 2389 - enum amd_ip_block_type block_type) 2390 - { 2391 - int i; 2392 - 2393 - for (i = 0; i < adev->num_ip_blocks; i++) { 2394 - if (adev->ip_blocks[i].version->type == block_type) 2395 - return adev->ip_blocks[i].status.valid; 2396 - } 2397 - return false; 2398 - 2399 - } 2400 - 2401 - /** 2402 - * amdgpu_device_ip_get_ip_block - get a hw IP pointer 2403 - * 2404 - * @adev: amdgpu_device pointer 2405 - * @type: Type of hardware IP (SMU, GFX, UVD, etc.) 2406 - * 2407 - * Returns a pointer to the hardware IP block structure 2408 - * if it exists for the asic, otherwise NULL. 2409 - */ 2410 - struct amdgpu_ip_block * 2411 - amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 2412 - enum amd_ip_block_type type) 2413 - { 2414 - int i; 2415 - 2416 - for (i = 0; i < adev->num_ip_blocks; i++) 2417 - if (adev->ip_blocks[i].version->type == type) 2418 - return &adev->ip_blocks[i]; 2419 - 2420 - return NULL; 2421 - } 2422 - 2423 - /** 2424 - * amdgpu_device_ip_block_version_cmp 2425 - * 2426 - * @adev: amdgpu_device pointer 2427 - * @type: enum amd_ip_block_type 2428 - * @major: major version 2429 - * @minor: minor version 2430 - * 2431 - * return 0 if equal or greater 2432 - * return 1 if smaller or the ip_block doesn't exist 2433 - */ 2434 - int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 2435 - enum amd_ip_block_type type, 2436 - u32 major, u32 minor) 2437 - { 2438 - struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); 2439 - 2440 - if (ip_block && ((ip_block->version->major > major) || 2441 - ((ip_block->version->major == major) && 2442 - (ip_block->version->minor >= minor)))) 2443 - return 0; 2444 - 2445 - return 1; 2446 - } 2447 - 2448 - static const char *ip_block_names[] = { 2449 - [AMD_IP_BLOCK_TYPE_COMMON] = "common", 2450 - [AMD_IP_BLOCK_TYPE_GMC] = "gmc", 2451 - [AMD_IP_BLOCK_TYPE_IH] = "ih", 2452 - [AMD_IP_BLOCK_TYPE_SMC] = "smu", 2453 - [AMD_IP_BLOCK_TYPE_PSP] = "psp", 2454 - [AMD_IP_BLOCK_TYPE_DCE] = "dce", 2455 - [AMD_IP_BLOCK_TYPE_GFX] = "gfx", 2456 - [AMD_IP_BLOCK_TYPE_SDMA] = "sdma", 2457 - [AMD_IP_BLOCK_TYPE_UVD] = "uvd", 2458 - [AMD_IP_BLOCK_TYPE_VCE] = "vce", 2459 - [AMD_IP_BLOCK_TYPE_ACP] = "acp", 2460 - [AMD_IP_BLOCK_TYPE_VCN] = "vcn", 2461 - [AMD_IP_BLOCK_TYPE_MES] = "mes", 2462 - [AMD_IP_BLOCK_TYPE_JPEG] = "jpeg", 2463 - [AMD_IP_BLOCK_TYPE_VPE] = "vpe", 2464 - [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", 2465 - [AMD_IP_BLOCK_TYPE_ISP] = "isp", 2466 - [AMD_IP_BLOCK_TYPE_RAS] = "ras", 2467 - }; 2468 - 2469 - static const char *ip_block_name(struct amdgpu_device *adev, enum amd_ip_block_type type) 2470 - { 2471 - int idx = (int)type; 2472 - 2473 - return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : "unknown"; 2474 - } 2475 - 2476 - /** 2477 - * amdgpu_device_ip_block_add 2478 - * 2479 - * @adev: amdgpu_device pointer 2480 - * @ip_block_version: pointer to the IP to add 2481 - * 2482 - * Adds the IP block driver information to the collection of IPs 2483 - * on the asic. 2484 - */ 2485 - int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 2486 - const struct amdgpu_ip_block_version *ip_block_version) 2487 - { 2488 - if (!ip_block_version) 2489 - return -EINVAL; 2490 - 2491 - switch (ip_block_version->type) { 2492 - case AMD_IP_BLOCK_TYPE_VCN: 2493 - if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 2494 - return 0; 2495 - break; 2496 - case AMD_IP_BLOCK_TYPE_JPEG: 2497 - if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) 2498 - return 0; 2499 - break; 2500 - default: 2501 - break; 2502 - } 2503 - 2504 - dev_info(adev->dev, "detected ip block number %d <%s_v%d_%d_%d> (%s)\n", 2505 - adev->num_ip_blocks, 2506 - ip_block_name(adev, ip_block_version->type), 2507 - ip_block_version->major, 2508 - ip_block_version->minor, 2509 - ip_block_version->rev, 2510 - ip_block_version->funcs->name); 2511 - 2512 - adev->ip_blocks[adev->num_ip_blocks].adev = adev; 2513 - 2514 - adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; 2515 - 2516 - return 0; 2517 - } 2518 2267 2519 2268 /** 2520 2269 * amdgpu_device_enable_virtual_display - enable virtual display feature

+324

drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c

··· 94 94 adev->ip_map.logical_to_dev_inst = amdgpu_logical_to_dev_inst; 95 95 adev->ip_map.logical_to_dev_mask = amdgpu_logical_to_dev_mask; 96 96 } 97 + 98 + int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block) 99 + { 100 + int r; 101 + 102 + if (ip_block->version->funcs->suspend) { 103 + r = ip_block->version->funcs->suspend(ip_block); 104 + if (r) { 105 + dev_err(ip_block->adev->dev, 106 + "suspend of IP block <%s> failed %d\n", 107 + ip_block->version->funcs->name, r); 108 + return r; 109 + } 110 + } 111 + 112 + ip_block->status.hw = false; 113 + return 0; 114 + } 115 + 116 + int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) 117 + { 118 + int r; 119 + 120 + if (ip_block->version->funcs->resume) { 121 + r = ip_block->version->funcs->resume(ip_block); 122 + if (r) { 123 + dev_err(ip_block->adev->dev, 124 + "resume of IP block <%s> failed %d\n", 125 + ip_block->version->funcs->name, r); 126 + return r; 127 + } 128 + } 129 + 130 + ip_block->status.hw = true; 131 + return 0; 132 + } 133 + 134 + /** 135 + * amdgpu_device_ip_get_ip_block - get a hw IP pointer 136 + * 137 + * @adev: amdgpu_device pointer 138 + * @type: Type of hardware IP (SMU, GFX, UVD, etc.) 139 + * 140 + * Returns a pointer to the hardware IP block structure 141 + * if it exists for the asic, otherwise NULL. 142 + */ 143 + struct amdgpu_ip_block * 144 + amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 145 + enum amd_ip_block_type type) 146 + { 147 + int i; 148 + 149 + for (i = 0; i < adev->num_ip_blocks; i++) 150 + if (adev->ip_blocks[i].version->type == type) 151 + return &adev->ip_blocks[i]; 152 + 153 + return NULL; 154 + } 155 + 156 + /** 157 + * amdgpu_device_ip_block_version_cmp 158 + * 159 + * @adev: amdgpu_device pointer 160 + * @type: enum amd_ip_block_type 161 + * @major: major version 162 + * @minor: minor version 163 + * 164 + * return 0 if equal or greater 165 + * return 1 if smaller or the ip_block doesn't exist 166 + */ 167 + int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 168 + enum amd_ip_block_type type, u32 major, 169 + u32 minor) 170 + { 171 + struct amdgpu_ip_block *ip_block = 172 + amdgpu_device_ip_get_ip_block(adev, type); 173 + 174 + if (ip_block && ((ip_block->version->major > major) || 175 + ((ip_block->version->major == major) && 176 + (ip_block->version->minor >= minor)))) 177 + return 0; 178 + 179 + return 1; 180 + } 181 + 182 + static const char *const ip_block_names[] = { 183 + [AMD_IP_BLOCK_TYPE_COMMON] = "common", 184 + [AMD_IP_BLOCK_TYPE_GMC] = "gmc", 185 + [AMD_IP_BLOCK_TYPE_IH] = "ih", 186 + [AMD_IP_BLOCK_TYPE_SMC] = "smu", 187 + [AMD_IP_BLOCK_TYPE_PSP] = "psp", 188 + [AMD_IP_BLOCK_TYPE_DCE] = "dce", 189 + [AMD_IP_BLOCK_TYPE_GFX] = "gfx", 190 + [AMD_IP_BLOCK_TYPE_SDMA] = "sdma", 191 + [AMD_IP_BLOCK_TYPE_UVD] = "uvd", 192 + [AMD_IP_BLOCK_TYPE_VCE] = "vce", 193 + [AMD_IP_BLOCK_TYPE_ACP] = "acp", 194 + [AMD_IP_BLOCK_TYPE_VCN] = "vcn", 195 + [AMD_IP_BLOCK_TYPE_MES] = "mes", 196 + [AMD_IP_BLOCK_TYPE_JPEG] = "jpeg", 197 + [AMD_IP_BLOCK_TYPE_VPE] = "vpe", 198 + [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", 199 + [AMD_IP_BLOCK_TYPE_ISP] = "isp", 200 + [AMD_IP_BLOCK_TYPE_RAS] = "ras", 201 + }; 202 + 203 + static const char *ip_block_name(struct amdgpu_device *adev, 204 + enum amd_ip_block_type type) 205 + { 206 + int idx = (int)type; 207 + 208 + return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : 209 + "unknown"; 210 + } 211 + 212 + /** 213 + * amdgpu_device_ip_block_add 214 + * 215 + * @adev: amdgpu_device pointer 216 + * @ip_block_version: pointer to the IP to add 217 + * 218 + * Adds the IP block driver information to the collection of IPs 219 + * on the asic. 220 + */ 221 + int amdgpu_device_ip_block_add( 222 + struct amdgpu_device *adev, 223 + const struct amdgpu_ip_block_version *ip_block_version) 224 + { 225 + if (!ip_block_version) 226 + return -EINVAL; 227 + 228 + switch (ip_block_version->type) { 229 + case AMD_IP_BLOCK_TYPE_VCN: 230 + if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 231 + return 0; 232 + break; 233 + case AMD_IP_BLOCK_TYPE_JPEG: 234 + if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) 235 + return 0; 236 + break; 237 + default: 238 + break; 239 + } 240 + 241 + dev_info(adev->dev, "detected ip block number %d <%s_v%d_%d_%d> (%s)\n", 242 + adev->num_ip_blocks, 243 + ip_block_name(adev, ip_block_version->type), 244 + ip_block_version->major, ip_block_version->minor, 245 + ip_block_version->rev, ip_block_version->funcs->name); 246 + 247 + adev->ip_blocks[adev->num_ip_blocks].adev = adev; 248 + 249 + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; 250 + 251 + return 0; 252 + } 253 + 254 + /** 255 + * amdgpu_device_ip_set_clockgating_state - set the CG state 256 + * 257 + * @dev: amdgpu_device pointer 258 + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 259 + * @state: clockgating state (gate or ungate) 260 + * 261 + * Sets the requested clockgating state for all instances of 262 + * the hardware IP specified. 263 + * Returns the error code from the last instance. 264 + */ 265 + int amdgpu_device_ip_set_clockgating_state(void *dev, 266 + enum amd_ip_block_type block_type, 267 + enum amd_clockgating_state state) 268 + { 269 + struct amdgpu_device *adev = dev; 270 + int i, r = 0; 271 + 272 + for (i = 0; i < adev->num_ip_blocks; i++) { 273 + if (!adev->ip_blocks[i].status.valid) 274 + continue; 275 + if (adev->ip_blocks[i].version->type != block_type) 276 + continue; 277 + if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) 278 + continue; 279 + r = adev->ip_blocks[i].version->funcs->set_clockgating_state( 280 + &adev->ip_blocks[i], state); 281 + if (r) 282 + dev_err(adev->dev, 283 + "set_clockgating_state of IP block <%s> failed %d\n", 284 + adev->ip_blocks[i].version->funcs->name, r); 285 + } 286 + return r; 287 + } 288 + 289 + /** 290 + * amdgpu_device_ip_set_powergating_state - set the PG state 291 + * 292 + * @dev: amdgpu_device pointer 293 + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 294 + * @state: powergating state (gate or ungate) 295 + * 296 + * Sets the requested powergating state for all instances of 297 + * the hardware IP specified. 298 + * Returns the error code from the last instance. 299 + */ 300 + int amdgpu_device_ip_set_powergating_state(void *dev, 301 + enum amd_ip_block_type block_type, 302 + enum amd_powergating_state state) 303 + { 304 + struct amdgpu_device *adev = dev; 305 + int i, r = 0; 306 + 307 + for (i = 0; i < adev->num_ip_blocks; i++) { 308 + if (!adev->ip_blocks[i].status.valid) 309 + continue; 310 + if (adev->ip_blocks[i].version->type != block_type) 311 + continue; 312 + if (!adev->ip_blocks[i].version->funcs->set_powergating_state) 313 + continue; 314 + r = adev->ip_blocks[i].version->funcs->set_powergating_state( 315 + &adev->ip_blocks[i], state); 316 + if (r) 317 + dev_err(adev->dev, 318 + "set_powergating_state of IP block <%s> failed %d\n", 319 + adev->ip_blocks[i].version->funcs->name, r); 320 + } 321 + return r; 322 + } 323 + 324 + /** 325 + * amdgpu_device_ip_get_clockgating_state - get the CG state 326 + * 327 + * @adev: amdgpu_device pointer 328 + * @flags: clockgating feature flags 329 + * 330 + * Walks the list of IPs on the device and updates the clockgating 331 + * flags for each IP. 332 + * Updates @flags with the feature flags for each hardware IP where 333 + * clockgating is enabled. 334 + */ 335 + void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 336 + u64 *flags) 337 + { 338 + int i; 339 + 340 + for (i = 0; i < adev->num_ip_blocks; i++) { 341 + if (!adev->ip_blocks[i].status.valid) 342 + continue; 343 + if (adev->ip_blocks[i].version->funcs->get_clockgating_state) 344 + adev->ip_blocks[i].version->funcs->get_clockgating_state( 345 + &adev->ip_blocks[i], flags); 346 + } 347 + } 348 + 349 + /** 350 + * amdgpu_device_ip_wait_for_idle - wait for idle 351 + * 352 + * @adev: amdgpu_device pointer 353 + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 354 + * 355 + * Waits for the request hardware IP to be idle. 356 + * Returns 0 for success or a negative error code on failure. 357 + */ 358 + int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 359 + enum amd_ip_block_type block_type) 360 + { 361 + int i, r; 362 + 363 + for (i = 0; i < adev->num_ip_blocks; i++) { 364 + if (!adev->ip_blocks[i].status.valid) 365 + continue; 366 + if (adev->ip_blocks[i].version->type == block_type) { 367 + if (adev->ip_blocks[i].version->funcs->wait_for_idle) { 368 + r = adev->ip_blocks[i] 369 + .version->funcs->wait_for_idle( 370 + &adev->ip_blocks[i]); 371 + if (r) 372 + return r; 373 + } 374 + break; 375 + } 376 + } 377 + return 0; 378 + } 379 + 380 + /** 381 + * amdgpu_device_ip_is_hw - is the hardware IP enabled 382 + * 383 + * @adev: amdgpu_device pointer 384 + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 385 + * 386 + * Check if the hardware IP is enable or not. 387 + * Returns true if it the IP is enable, false if not. 388 + */ 389 + bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, 390 + enum amd_ip_block_type block_type) 391 + { 392 + int i; 393 + 394 + for (i = 0; i < adev->num_ip_blocks; i++) { 395 + if (adev->ip_blocks[i].version->type == block_type) 396 + return adev->ip_blocks[i].status.hw; 397 + } 398 + return false; 399 + } 400 + 401 + /** 402 + * amdgpu_device_ip_is_valid - is the hardware IP valid 403 + * 404 + * @adev: amdgpu_device pointer 405 + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) 406 + * 407 + * Check if the hardware IP is valid or not. 408 + * Returns true if it the IP is valid, false if not. 409 + */ 410 + bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 411 + enum amd_ip_block_type block_type) 412 + { 413 + int i; 414 + 415 + for (i = 0; i < adev->num_ip_blocks; i++) { 416 + if (adev->ip_blocks[i].version->type == block_type) 417 + return adev->ip_blocks[i].status.valid; 418 + } 419 + return false; 420 + }

+125

drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h

··· 24 24 #ifndef __AMDGPU_IP_H__ 25 25 #define __AMDGPU_IP_H__ 26 26 27 + #include "amd_shared.h" 28 + 29 + struct amdgpu_device; 30 + 31 + /* Define the HW IP blocks will be used in driver , add more if necessary */ 32 + enum amd_hw_ip_block_type { 33 + GC_HWIP = 1, 34 + HDP_HWIP, 35 + SDMA0_HWIP, 36 + SDMA1_HWIP, 37 + SDMA2_HWIP, 38 + SDMA3_HWIP, 39 + SDMA4_HWIP, 40 + SDMA5_HWIP, 41 + SDMA6_HWIP, 42 + SDMA7_HWIP, 43 + LSDMA_HWIP, 44 + MMHUB_HWIP, 45 + ATHUB_HWIP, 46 + NBIO_HWIP, 47 + MP0_HWIP, 48 + MP1_HWIP, 49 + UVD_HWIP, 50 + VCN_HWIP = UVD_HWIP, 51 + JPEG_HWIP = VCN_HWIP, 52 + VCN1_HWIP, 53 + VCE_HWIP, 54 + VPE_HWIP, 55 + DF_HWIP, 56 + DCE_HWIP, 57 + OSSSYS_HWIP, 58 + SMUIO_HWIP, 59 + PWR_HWIP, 60 + NBIF_HWIP, 61 + THM_HWIP, 62 + CLK_HWIP, 63 + UMC_HWIP, 64 + RSMU_HWIP, 65 + XGMI_HWIP, 66 + DCI_HWIP, 67 + PCIE_HWIP, 68 + ISP_HWIP, 69 + ATU_HWIP, 70 + AIGC_HWIP, 71 + MAX_HWIP 72 + }; 73 + 74 + #define HWIP_MAX_INSTANCE 48 75 + 76 + #define HW_ID_MAX 300 77 + #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 78 + (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 79 + #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 80 + #define IP_VERSION_MAJ(ver) ((ver) >> 24) 81 + #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 82 + #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 83 + #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 84 + #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 85 + #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 86 + 87 + struct amdgpu_ip_map_info { 88 + /* Map of logical to actual dev instances/mask */ 89 + uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 90 + int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 91 + enum amd_hw_ip_block_type block, 92 + int8_t inst); 93 + uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 94 + enum amd_hw_ip_block_type block, 95 + uint32_t mask); 96 + }; 97 + 98 + #define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM 99 + 100 + struct amdgpu_ip_block_status { 101 + bool valid; 102 + bool sw; 103 + bool hw; 104 + bool late_initialized; 105 + bool hang; 106 + }; 107 + 108 + struct amdgpu_ip_block_version { 109 + const enum amd_ip_block_type type; 110 + const u32 major; 111 + const u32 minor; 112 + const u32 rev; 113 + const struct amd_ip_funcs *funcs; 114 + }; 115 + 116 + struct amdgpu_ip_block { 117 + struct amdgpu_ip_block_status status; 118 + const struct amdgpu_ip_block_version *version; 119 + struct amdgpu_device *adev; 120 + }; 121 + 27 122 void amdgpu_ip_map_init(struct amdgpu_device *adev); 123 + 124 + int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 125 + int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 126 + 127 + struct amdgpu_ip_block * 128 + amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 129 + enum amd_ip_block_type type); 130 + 131 + int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 132 + enum amd_ip_block_type type, u32 major, 133 + u32 minor); 134 + 135 + int amdgpu_device_ip_block_add( 136 + struct amdgpu_device *adev, 137 + const struct amdgpu_ip_block_version *ip_block_version); 138 + 139 + int amdgpu_device_ip_set_clockgating_state(void *dev, 140 + enum amd_ip_block_type block_type, 141 + enum amd_clockgating_state state); 142 + int amdgpu_device_ip_set_powergating_state(void *dev, 143 + enum amd_ip_block_type block_type, 144 + enum amd_powergating_state state); 145 + void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 146 + u64 *flags); 147 + int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 148 + enum amd_ip_block_type block_type); 149 + bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, 150 + enum amd_ip_block_type block_type); 151 + bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 152 + enum amd_ip_block_type block_type); 28 153 29 154 #endif /* __AMDGPU_IP_H__ */

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