Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Change pci_raw_ops to pci_raw_read/write
We want to allow different implementations of pci_raw_ops for standard
and extended config space on x86. Rather than clutter generic code with
knowledge of this, we make pci_raw_ops private to x86 and use it to
implement the new raw interface -- raw_pci_read() and raw_pci_write().
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
authored by
Matthew Wilcox
and committed by
Linus Torvalds
b6ce068a
a0ca9909
+78
-85
+8
-17
arch/ia64/pci/pci.c
+8
-17
arch/ia64/pci/pci.c
···
43
43
#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
44
44
(((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
45
45
46
-
static int
47
-
pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
46
+
int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
48
47
int reg, int len, u32 *value)
49
48
{
50
49
u64 addr, data = 0;
···
67
68
return 0;
68
69
}
69
70
70
-
static int
71
-
pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
71
+
int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
72
72
int reg, int len, u32 value)
73
73
{
74
74
u64 addr;
···
89
91
return 0;
90
92
}
91
93
92
-
static struct pci_raw_ops pci_sal_ops = {
93
-
.read = pci_sal_read,
94
-
.write = pci_sal_write
95
-
};
96
-
97
-
struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
98
-
99
-
static int
100
-
pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
94
+
static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
95
+
int size, u32 *value)
101
96
{
102
-
return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
97
+
return raw_pci_read(pci_domain_nr(bus), bus->number,
103
98
devfn, where, size, value);
104
99
}
105
100
106
-
static int
107
-
pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
101
+
static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
102
+
int size, u32 value)
108
103
{
109
-
return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
104
+
return raw_pci_write(pci_domain_nr(bus), bus->number,
110
105
devfn, where, size, value);
111
106
}
112
107
+8
-8
arch/ia64/sn/pci/tioce_provider.c
+8
-8
arch/ia64/sn/pci/tioce_provider.c
···
752
752
* Determine the secondary bus number of the port2 logical PPB.
753
753
* This is used to decide whether a given pci device resides on
754
754
* port1 or port2. Note: We don't have enough plumbing set up
755
-
* here to use pci_read_config_xxx() so use the raw_pci_ops vector.
755
+
* here to use pci_read_config_xxx() so use raw_pci_read().
756
756
*/
757
757
758
758
seg = tioce_common->ce_pcibus.bs_persist_segment;
759
759
bus = tioce_common->ce_pcibus.bs_persist_busnum;
760
760
761
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
761
+
raw_pci_read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
762
762
tioce_kern->ce_port1_secondary = (u8) tmp;
763
763
764
764
/*
···
799
799
800
800
/* mem base/limit */
801
801
802
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
802
+
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
803
803
PCI_MEMORY_BASE, 2, &tmp);
804
804
base = (u64)tmp << 16;
805
805
806
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
806
+
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
807
807
PCI_MEMORY_LIMIT, 2, &tmp);
808
808
limit = (u64)tmp << 16;
809
809
limit |= 0xfffffUL;
···
817
817
* attributes.
818
818
*/
819
819
820
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
820
+
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
821
821
PCI_PREF_MEMORY_BASE, 2, &tmp);
822
822
base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
823
823
824
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
824
+
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
825
825
PCI_PREF_BASE_UPPER32, 4, &tmp);
826
826
base |= (u64)tmp << 32;
827
827
828
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
828
+
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
829
829
PCI_PREF_MEMORY_LIMIT, 2, &tmp);
830
830
831
831
limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
832
832
limit |= 0xfffffUL;
833
833
834
-
raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
834
+
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
835
835
PCI_PREF_LIMIT_UPPER32, 4, &tmp);
836
836
limit |= (u64)tmp << 32;
837
837
+1
-1
arch/x86/kernel/quirks.c
+1
-1
arch/x86/kernel/quirks.c
+23
-2
arch/x86/pci/common.c
+23
-2
arch/x86/pci/common.c
···
26
26
unsigned long pirq_table_addr;
27
27
struct pci_bus *pci_root_bus;
28
28
struct pci_raw_ops *raw_pci_ops;
29
+
struct pci_raw_ops *raw_pci_ext_ops;
30
+
31
+
int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
32
+
int reg, int len, u32 *val)
33
+
{
34
+
if (reg < 256 && raw_pci_ops)
35
+
return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
36
+
if (raw_pci_ext_ops)
37
+
return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
38
+
return -EINVAL;
39
+
}
40
+
41
+
int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
42
+
int reg, int len, u32 val)
43
+
{
44
+
if (reg < 256 && raw_pci_ops)
45
+
return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
46
+
if (raw_pci_ext_ops)
47
+
return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
48
+
return -EINVAL;
49
+
}
29
50
30
51
static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
31
52
{
32
-
return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
53
+
return raw_pci_read(pci_domain_nr(bus), bus->number,
33
54
devfn, where, size, value);
34
55
}
35
56
36
57
static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
37
58
{
38
-
return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
59
+
return raw_pci_write(pci_domain_nr(bus), bus->number,
39
60
devfn, where, size, value);
40
61
}
41
62
+2
-2
arch/x86/pci/direct.c
+2
-2
arch/x86/pci/direct.c
···
14
14
#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
15
15
(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
16
16
17
-
int pci_conf1_read(unsigned int seg, unsigned int bus,
17
+
static int pci_conf1_read(unsigned int seg, unsigned int bus,
18
18
unsigned int devfn, int reg, int len, u32 *value)
19
19
{
20
20
unsigned long flags;
···
45
45
return 0;
46
46
}
47
47
48
-
int pci_conf1_write(unsigned int seg, unsigned int bus,
48
+
static int pci_conf1_write(unsigned int seg, unsigned int bus,
49
49
unsigned int devfn, int reg, int len, u32 value)
50
50
{
51
51
unsigned long flags;
+4
-2
arch/x86/pci/fixup.c
+4
-2
arch/x86/pci/fixup.c
···
215
215
216
216
static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
217
217
{
218
-
return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
218
+
return raw_pci_read(pci_domain_nr(bus), bus->number,
219
+
devfn, where, size, value);
219
220
}
220
221
221
222
/*
···
232
231
if ((offset) && (where == offset))
233
232
value = value & 0xfffffffc;
234
233
235
-
return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
234
+
return raw_pci_write(pci_domain_nr(bus), bus->number,
235
+
devfn, where, size, value);
236
236
}
237
237
238
238
static struct pci_ops quirk_pcie_aspm_ops = {
+1
-1
arch/x86/pci/legacy.c
+1
-1
arch/x86/pci/legacy.c
···
22
22
if (pci_find_bus(0, n))
23
23
continue;
24
24
for (devfn = 0; devfn < 256; devfn += 8) {
25
-
if (!raw_pci_ops->read(0, n, devfn, PCI_VENDOR_ID, 2, &l) &&
25
+
if (!raw_pci_read(0, n, devfn, PCI_VENDOR_ID, 2, &l) &&
26
26
l != 0x0000 && l != 0xffff) {
27
27
DBG("Found device at %02x:%02x [%04x]\n", n, devfn, l);
28
28
printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
+2
-8
arch/x86/pci/mmconfig_32.c
+2
-8
arch/x86/pci/mmconfig_32.c
···
68
68
return -EINVAL;
69
69
}
70
70
71
-
if (reg < 256)
72
-
return pci_conf1_read(seg,bus,devfn,reg,len,value);
73
-
74
71
base = get_base_addr(seg, bus, devfn);
75
72
if (!base)
76
73
goto err;
···
101
104
if ((bus > 255) || (devfn > 255) || (reg > 4095))
102
105
return -EINVAL;
103
106
104
-
if (reg < 256)
105
-
return pci_conf1_write(seg,bus,devfn,reg,len,value);
106
-
107
107
base = get_base_addr(seg, bus, devfn);
108
108
if (!base)
109
109
return -EINVAL;
···
132
138
133
139
int __init pci_mmcfg_arch_init(void)
134
140
{
135
-
printk(KERN_INFO "PCI: Using MMCONFIG\n");
136
-
raw_pci_ops = &pci_mmcfg;
141
+
printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
142
+
raw_pci_ext_ops = &pci_mmcfg;
137
143
return 1;
138
144
}
+1
-7
arch/x86/pci/mmconfig_64.c
+1
-7
arch/x86/pci/mmconfig_64.c
···
58
58
return -EINVAL;
59
59
}
60
60
61
-
if (reg < 256)
62
-
return pci_conf1_read(seg,bus,devfn,reg,len,value);
63
-
64
61
addr = pci_dev_base(seg, bus, devfn);
65
62
if (!addr)
66
63
goto err;
···
85
88
/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
86
89
if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
87
90
return -EINVAL;
88
-
89
-
if (reg < 256)
90
-
return pci_conf1_write(seg,bus,devfn,reg,len,value);
91
91
92
92
addr = pci_dev_base(seg, bus, devfn);
93
93
if (!addr)
···
144
150
return 0;
145
151
}
146
152
}
147
-
raw_pci_ops = &pci_mmcfg;
153
+
raw_pci_ext_ops = &pci_mmcfg;
148
154
return 1;
149
155
}
+11
-4
arch/x86/pci/pci.h
+11
-4
arch/x86/pci/pci.h
···
85
85
extern int (*pcibios_enable_irq)(struct pci_dev *dev);
86
86
extern void (*pcibios_disable_irq)(struct pci_dev *dev);
87
87
88
-
extern int pci_conf1_write(unsigned int seg, unsigned int bus,
89
-
unsigned int devfn, int reg, int len, u32 value);
90
-
extern int pci_conf1_read(unsigned int seg, unsigned int bus,
91
-
unsigned int devfn, int reg, int len, u32 *value);
88
+
struct pci_raw_ops {
89
+
int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
90
+
int reg, int len, u32 *val);
91
+
int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
92
+
int reg, int len, u32 val);
93
+
};
94
+
95
+
extern struct pci_raw_ops *raw_pci_ops;
96
+
extern struct pci_raw_ops *raw_pci_ext_ops;
97
+
98
+
extern struct pci_raw_ops pci_direct_conf1;
92
99
93
100
extern int pci_direct_probe(void);
94
101
extern void pci_direct_init(int type);
-3
arch/x86/pci/visws.c
-3
arch/x86/pci/visws.c
+6
-19
drivers/acpi/osl.c
+6
-19
drivers/acpi/osl.c
···
200
200
201
201
acpi_status acpi_os_initialize1(void)
202
202
{
203
-
/*
204
-
* Initialize PCI configuration space access, as we'll need to access
205
-
* it while walking the namespace (bus 0 and root bridges w/ _BBNs).
206
-
*/
207
-
if (!raw_pci_ops) {
208
-
printk(KERN_ERR PREFIX
209
-
"Access to PCI configuration space unavailable\n");
210
-
return AE_NULL_ENTRY;
211
-
}
212
203
kacpid_wq = create_singlethread_workqueue("kacpid");
213
204
kacpi_notify_wq = create_singlethread_workqueue("kacpi_notify");
214
205
BUG_ON(!kacpid_wq);
···
644
653
return AE_ERROR;
645
654
}
646
655
647
-
BUG_ON(!raw_pci_ops);
648
-
649
-
result = raw_pci_ops->read(pci_id->segment, pci_id->bus,
650
-
PCI_DEVFN(pci_id->device, pci_id->function),
651
-
reg, size, value);
656
+
result = raw_pci_read(pci_id->segment, pci_id->bus,
657
+
PCI_DEVFN(pci_id->device, pci_id->function),
658
+
reg, size, value);
652
659
653
660
return (result ? AE_ERROR : AE_OK);
654
661
}
···
671
682
return AE_ERROR;
672
683
}
673
684
674
-
BUG_ON(!raw_pci_ops);
675
-
676
-
result = raw_pci_ops->write(pci_id->segment, pci_id->bus,
677
-
PCI_DEVFN(pci_id->device, pci_id->function),
678
-
reg, size, value);
685
+
result = raw_pci_write(pci_id->segment, pci_id->bus,
686
+
PCI_DEVFN(pci_id->device, pci_id->function),
687
+
reg, size, value);
679
688
680
689
return (result ? AE_ERROR : AE_OK);
681
690
}
+8
-8
include/linux/pci.h
+8
-8
include/linux/pci.h
···
301
301
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
302
302
};
303
303
304
-
struct pci_raw_ops {
305
-
int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
306
-
int reg, int len, u32 *val);
307
-
int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
308
-
int reg, int len, u32 val);
309
-
};
310
-
311
-
extern struct pci_raw_ops *raw_pci_ops;
304
+
/*
305
+
* ACPI needs to be able to access PCI config space before we've done a
306
+
* PCI bus scan and created pci_bus structures.
307
+
*/
308
+
extern int raw_pci_read(unsigned int domain, unsigned int bus,
309
+
unsigned int devfn, int reg, int len, u32 *val);
310
+
extern int raw_pci_write(unsigned int domain, unsigned int bus,
311
+
unsigned int devfn, int reg, int len, u32 val);
312
312
313
313
struct pci_bus_region {
314
314
resource_size_t start;