+1

arch/arm/include/asm/kvm_host.h

reviewed

··· 33 33 #define KVM_PRIVATE_MEM_SLOTS 4 34 34 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 35 35 #define KVM_HAVE_ONE_REG 36 36 + #define KVM_HALT_POLL_NS_DEFAULT 500000 36 37 37 38 #define KVM_VCPU_MAX_FEATURES 2 38 39

+1

arch/arm64/include/asm/kvm_host.h

reviewed

··· 33 33 #define KVM_USER_MEM_SLOTS 32 34 34 #define KVM_PRIVATE_MEM_SLOTS 4 35 35 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 36 36 + #define KVM_HALT_POLL_NS_DEFAULT 500000 36 37 37 38 #include <kvm/arm_vgic.h> 38 39 #include <kvm/arm_arch_timer.h>

+1

arch/mips/include/asm/kvm_host.h

reviewed

··· 61 61 #define KVM_PRIVATE_MEM_SLOTS 0 62 62 63 63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 64 64 + #define KVM_HALT_POLL_NS_DEFAULT 500000 64 65 65 66 66 67

+1

arch/powerpc/include/asm/kvm_host.h

reviewed

··· 44 44 #ifdef CONFIG_KVM_MMIO 45 45 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 46 46 #endif 47 47 + #define KVM_HALT_POLL_NS_DEFAULT 500000 47 48 48 49 /* These values are internal and can be increased later */ 49 50 #define KVM_NR_IRQCHIPS 1

+6

arch/powerpc/kvm/book3s.c

reviewed

··· 829 829 unsigned long size = kvmppc_get_gpr(vcpu, 4); 830 830 unsigned long addr = kvmppc_get_gpr(vcpu, 5); 831 831 u64 buf; 832 832 + int srcu_idx; 832 833 int ret; 833 834 834 835 if (!is_power_of_2(size) || (size > sizeof(buf))) 835 836 return H_TOO_HARD; 836 837 838 838 + srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 837 839 ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, size, &buf); 840 840 + srcu_read_unlock(&vcpu->kvm->srcu, srcu_idx); 838 841 if (ret != 0) 839 842 return H_TOO_HARD; 840 843 ··· 872 869 unsigned long addr = kvmppc_get_gpr(vcpu, 5); 873 870 unsigned long val = kvmppc_get_gpr(vcpu, 6); 874 871 u64 buf; 872 872 + int srcu_idx; 875 873 int ret; 876 874 877 875 switch (size) { ··· 896 892 return H_TOO_HARD; 897 893 } 898 894 895 895 + srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 899 896 ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, size, &buf); 897 897 + srcu_read_unlock(&vcpu->kvm->srcu, srcu_idx); 900 898 if (ret != 0) 901 899 return H_TOO_HARD; 902 900

+5 -1

arch/powerpc/kvm/book3s_hv.c

reviewed

··· 2692 2692 2693 2693 while (vcpu->arch.state == KVMPPC_VCPU_RUNNABLE && 2694 2694 (vc->vcore_state == VCORE_RUNNING || 2695 2695 - vc->vcore_state == VCORE_EXITING)) 2695 2695 + vc->vcore_state == VCORE_EXITING || 2696 2696 + vc->vcore_state == VCORE_PIGGYBACK)) 2696 2697 kvmppc_wait_for_exec(vc, vcpu, TASK_UNINTERRUPTIBLE); 2698 2698 + 2699 2699 + if (vc->vcore_state == VCORE_PREEMPT && vc->runner == NULL) 2700 2700 + kvmppc_vcore_end_preempt(vc); 2697 2701 2698 2702 if (vcpu->arch.state == KVMPPC_VCPU_RUNNABLE) { 2699 2703 kvmppc_remove_runnable(vc, vcpu);

+1

arch/powerpc/kvm/book3s_hv_rmhandlers.S

reviewed

··· 1257 1257 bl kvmhv_accumulate_time 1258 1258 #endif 1259 1259 1260 1260 + mr r3, r12 1260 1261 /* Increment exit count, poke other threads to exit */ 1261 1262 bl kvmhv_commence_exit 1262 1263 nop

+1

arch/s390/include/asm/kvm_host.h

reviewed

··· 35 35 */ 36 36 #define KVM_NR_IRQCHIPS 1 37 37 #define KVM_IRQCHIP_NUM_PINS 4096 38 38 + #define KVM_HALT_POLL_NS_DEFAULT 0 38 39 39 40 #define SIGP_CTRL_C 0x80 40 41 #define SIGP_CTRL_SCN_MASK 0x3f

+1

arch/x86/include/asm/kvm_host.h

reviewed

··· 40 40 41 41 #define KVM_PIO_PAGE_OFFSET 1 42 42 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 43 43 + #define KVM_HALT_POLL_NS_DEFAULT 500000 43 44 44 45 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 45 46

+1

arch/x86/include/asm/msr-index.h

reviewed

··· 331 331 /* C1E active bits in int pending message */ 332 332 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 333 333 #define MSR_K8_TSEG_ADDR 0xc0010112 334 334 + #define MSR_K8_TSEG_MASK 0xc0010113 334 335 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 335 336 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 336 337 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */

+18 -7

arch/x86/kvm/mmu.c

reviewed

··· 3322 3322 break; 3323 3323 3324 3324 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, 3325 3325 - leaf); 3325 3325 + iterator.level); 3326 3326 } 3327 3327 3328 3328 walk_shadow_page_lockless_end(vcpu); ··· 3614 3614 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, 3615 3615 struct rsvd_bits_validate *rsvd_check, 3616 3616 int maxphyaddr, int level, bool nx, bool gbpages, 3617 3617 - bool pse) 3617 3617 + bool pse, bool amd) 3618 3618 { 3619 3619 u64 exb_bit_rsvd = 0; 3620 3620 u64 gbpages_bit_rsvd = 0; ··· 3631 3631 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for 3632 3632 * leaf entries) on AMD CPUs only. 3633 3633 */ 3634 3634 - if (guest_cpuid_is_amd(vcpu)) 3634 3634 + if (amd) 3635 3635 nonleaf_bit8_rsvd = rsvd_bits(8, 8); 3636 3636 3637 3637 switch (level) { ··· 3699 3699 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, 3700 3700 cpuid_maxphyaddr(vcpu), context->root_level, 3701 3701 context->nx, guest_cpuid_has_gbpages(vcpu), 3702 3702 - is_pse(vcpu)); 3702 3702 + is_pse(vcpu), guest_cpuid_is_amd(vcpu)); 3703 3703 } 3704 3704 3705 3705 static void ··· 3749 3749 void 3750 3750 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) 3751 3751 { 3752 3752 + /* 3753 3753 + * Passing "true" to the last argument is okay; it adds a check 3754 3754 + * on bit 8 of the SPTEs which KVM doesn't use anyway. 3755 3755 + */ 3752 3756 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, 3753 3757 boot_cpu_data.x86_phys_bits, 3754 3758 context->shadow_root_level, context->nx, 3755 3755 - guest_cpuid_has_gbpages(vcpu), is_pse(vcpu)); 3759 3759 + guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), 3760 3760 + true); 3756 3761 } 3757 3762 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); 3763 3763 + 3764 3764 + static inline bool boot_cpu_is_amd(void) 3765 3765 + { 3766 3766 + WARN_ON_ONCE(!tdp_enabled); 3767 3767 + return shadow_x_mask == 0; 3768 3768 + } 3758 3769 3759 3770 /* 3760 3771 * the direct page table on host, use as much mmu features as ··· 3775 3764 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, 3776 3765 struct kvm_mmu *context) 3777 3766 { 3778 3778 - if (guest_cpuid_is_amd(vcpu)) 3767 3767 + if (boot_cpu_is_amd()) 3779 3768 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, 3780 3769 boot_cpu_data.x86_phys_bits, 3781 3770 context->shadow_root_level, false, 3782 3782 - cpu_has_gbpages, true); 3771 3771 + cpu_has_gbpages, true, true); 3783 3772 else 3784 3773 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, 3785 3774 boot_cpu_data.x86_phys_bits,

+3 -1

arch/x86/kvm/svm.c

reviewed

··· 202 202 static int nested = true; 203 203 module_param(nested, int, S_IRUGO); 204 204 205 205 + static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 205 206 static void svm_flush_tlb(struct kvm_vcpu *vcpu); 206 207 static void svm_complete_interrupts(struct vcpu_svm *svm); 207 208 ··· 1264 1263 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. 1265 1264 * It also updates the guest-visible cr0 value. 1266 1265 */ 1267 1267 - (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); 1266 1266 + svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); 1267 1267 + kvm_mmu_reset_context(&svm->vcpu); 1268 1268 1269 1269 save->cr4 = X86_CR4_PAE; 1270 1270 /* rdx = ?? */

+2

arch/x86/kvm/x86.c

reviewed

··· 2190 2190 case MSR_IA32_LASTINTFROMIP: 2191 2191 case MSR_IA32_LASTINTTOIP: 2192 2192 case MSR_K8_SYSCFG: 2193 2193 + case MSR_K8_TSEG_ADDR: 2194 2194 + case MSR_K8_TSEG_MASK: 2193 2195 case MSR_K7_HWCR: 2194 2196 case MSR_VM_HSAVE_PA: 2195 2197 case MSR_K8_INT_PENDING_MSG:

+2 -2

virt/kvm/kvm_main.c

reviewed

··· 66 66 MODULE_AUTHOR("Qumranet"); 67 67 MODULE_LICENSE("GPL"); 68 68 69 69 - /* halt polling only reduces halt latency by 5-7 us, 500us is enough */ 70 70 - static unsigned int halt_poll_ns = 500000; 69 69 + /* Architectures should define their poll value according to the halt latency */ 70 70 + static unsigned int halt_poll_ns = KVM_HALT_POLL_NS_DEFAULT; 71 71 module_param(halt_poll_ns, uint, S_IRUGO | S_IWUSR); 72 72 73 73 /* Default doubles per-vcpu halt_poll_ns. */