Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
counter: 104-quad-8: Utilize iomap interface
This driver doesn't need to access I/O ports directly via inb()/outb()
and friends. This patch abstracts such access by calling ioport_map()
to enable the use of more typical ioread8()/iowrite8() I/O memory
accessor calls.
Link: https://lore.kernel.org/r/861c003318dce3d2bef4061711643bb04f5ec14f.1652201921.git.william.gray@linaro.org
Cc: Syed Nayyar Waris <syednwaris@gmail.com>
Suggested-by: David Laight <David.Laight@ACULAB.COM>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Link: https://lore.kernel.org/r/e971b897cacfac4cb2eca478f5533d2875f5cadd.1657813472.git.william.gray@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
William Breathitt Gray
and committed by
Greg Kroah-Hartman
b6e9cded
dd4a6bf3
+89
-80
+89
-80
drivers/counter/104-quad-8.c
+89
-80
drivers/counter/104-quad-8.c
···
63
63
unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
64
64
unsigned int index_polarity[QUAD8_NUM_COUNTERS];
65
65
unsigned int cable_fault_enable;
66
-
unsigned int base;
66
+
void __iomem *base;
67
67
};
68
68
69
69
#define QUAD8_REG_INTERRUPT_STATUS 0x10
···
118
118
if (signal->id < 16)
119
119
return -EINVAL;
120
120
121
-
state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
122
-
& BIT(signal->id - 16);
121
+
state = ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) &
122
+
BIT(signal->id - 16);
123
123
124
124
*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
125
125
···
130
130
struct counter_count *count, u64 *val)
131
131
{
132
132
struct quad8 *const priv = counter_priv(counter);
133
-
const int base_offset = priv->base + 2 * count->id;
133
+
void __iomem *const base_offset = priv->base + 2 * count->id;
134
134
unsigned int flags;
135
135
unsigned int borrow;
136
136
unsigned int carry;
137
137
unsigned long irqflags;
138
138
int i;
139
139
140
-
flags = inb(base_offset + 1);
140
+
flags = ioread8(base_offset + 1);
141
141
borrow = flags & QUAD8_FLAG_BT;
142
142
carry = !!(flags & QUAD8_FLAG_CT);
143
143
···
147
147
spin_lock_irqsave(&priv->lock, irqflags);
148
148
149
149
/* Reset Byte Pointer; transfer Counter to Output Latch */
150
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
151
-
base_offset + 1);
150
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
151
+
base_offset + 1);
152
152
153
153
for (i = 0; i < 3; i++)
154
-
*val |= (unsigned long)inb(base_offset) << (8 * i);
154
+
*val |= (unsigned long)ioread8(base_offset) << (8 * i);
155
155
156
156
spin_unlock_irqrestore(&priv->lock, irqflags);
157
157
···
162
162
struct counter_count *count, u64 val)
163
163
{
164
164
struct quad8 *const priv = counter_priv(counter);
165
-
const int base_offset = priv->base + 2 * count->id;
165
+
void __iomem *const base_offset = priv->base + 2 * count->id;
166
166
unsigned long irqflags;
167
167
int i;
168
168
···
173
173
spin_lock_irqsave(&priv->lock, irqflags);
174
174
175
175
/* Reset Byte Pointer */
176
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
176
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
177
177
178
178
/* Counter can only be set via Preset Register */
179
179
for (i = 0; i < 3; i++)
180
-
outb(val >> (8 * i), base_offset);
180
+
iowrite8(val >> (8 * i), base_offset);
181
181
182
182
/* Transfer Preset Register to Counter */
183
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
183
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
184
184
185
185
/* Reset Byte Pointer */
186
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
186
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
187
187
188
188
/* Set Preset Register back to original value */
189
189
val = priv->preset[count->id];
190
190
for (i = 0; i < 3; i++)
191
-
outb(val >> (8 * i), base_offset);
191
+
iowrite8(val >> (8 * i), base_offset);
192
192
193
193
/* Reset Borrow, Carry, Compare, and Sign flags */
194
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
194
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
195
195
/* Reset Error flag */
196
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
196
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
197
197
198
198
spin_unlock_irqrestore(&priv->lock, irqflags);
199
199
···
246
246
unsigned int *const quadrature_mode = priv->quadrature_mode + id;
247
247
unsigned int *const scale = priv->quadrature_scale + id;
248
248
unsigned int *const synchronous_mode = priv->synchronous_mode + id;
249
-
const int base_offset = priv->base + 2 * id + 1;
249
+
void __iomem *const base_offset = priv->base + 2 * id + 1;
250
250
unsigned long irqflags;
251
251
unsigned int mode_cfg;
252
252
unsigned int idr_cfg;
···
266
266
if (*synchronous_mode) {
267
267
*synchronous_mode = 0;
268
268
/* Disable synchronous function mode */
269
-
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
269
+
iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
270
270
}
271
271
} else {
272
272
*quadrature_mode = 1;
···
292
292
}
293
293
294
294
/* Load mode configuration to Counter Mode Register */
295
-
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
295
+
iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset);
296
296
297
297
spin_unlock_irqrestore(&priv->lock, irqflags);
298
298
···
305
305
{
306
306
const struct quad8 *const priv = counter_priv(counter);
307
307
unsigned int ud_flag;
308
-
const unsigned int flag_addr = priv->base + 2 * count->id + 1;
308
+
void __iomem *const flag_addr = priv->base + 2 * count->id + 1;
309
309
310
310
/* U/D flag: nonzero = up, zero = down */
311
-
ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
311
+
ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
312
312
313
313
*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
314
314
COUNTER_COUNT_DIRECTION_BACKWARD;
···
402
402
struct counter_event_node *event_node;
403
403
unsigned int next_irq_trigger;
404
404
unsigned long ior_cfg;
405
-
unsigned long base_offset;
405
+
void __iomem *base_offset;
406
406
407
407
spin_lock_irqsave(&priv->lock, irqflags);
408
408
···
438
438
priv->preset_enable[event_node->channel] << 1 |
439
439
priv->irq_trigger[event_node->channel] << 3;
440
440
base_offset = priv->base + 2 * event_node->channel + 1;
441
-
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
441
+
iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset);
442
442
443
443
/* Enable IRQ line */
444
444
irq_enabled |= BIT(event_node->channel);
445
445
}
446
446
447
-
outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
447
+
iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
448
448
449
449
spin_unlock_irqrestore(&priv->lock, irqflags);
450
450
···
508
508
{
509
509
struct quad8 *const priv = counter_priv(counter);
510
510
const size_t channel_id = signal->id - 16;
511
-
const int base_offset = priv->base + 2 * channel_id + 1;
511
+
void __iomem *const base_offset = priv->base + 2 * channel_id + 1;
512
512
unsigned long irqflags;
513
513
unsigned int idr_cfg = index_polarity << 1;
514
514
···
519
519
priv->index_polarity[channel_id] = index_polarity;
520
520
521
521
/* Load Index Control configuration to Index Control Register */
522
-
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
522
+
iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
523
523
524
524
spin_unlock_irqrestore(&priv->lock, irqflags);
525
525
···
549
549
{
550
550
struct quad8 *const priv = counter_priv(counter);
551
551
const size_t channel_id = signal->id - 16;
552
-
const int base_offset = priv->base + 2 * channel_id + 1;
552
+
void __iomem *const base_offset = priv->base + 2 * channel_id + 1;
553
553
unsigned long irqflags;
554
554
unsigned int idr_cfg = synchronous_mode;
555
555
···
566
566
priv->synchronous_mode[channel_id] = synchronous_mode;
567
567
568
568
/* Load Index Control configuration to Index Control Register */
569
-
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
569
+
iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
570
570
571
571
spin_unlock_irqrestore(&priv->lock, irqflags);
572
572
···
614
614
struct quad8 *const priv = counter_priv(counter);
615
615
unsigned int count_mode;
616
616
unsigned int mode_cfg;
617
-
const int base_offset = priv->base + 2 * count->id + 1;
617
+
void __iomem *const base_offset = priv->base + 2 * count->id + 1;
618
618
unsigned long irqflags;
619
619
620
620
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
···
648
648
mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
649
649
650
650
/* Load mode configuration to Counter Mode Register */
651
-
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
651
+
iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset);
652
652
653
653
spin_unlock_irqrestore(&priv->lock, irqflags);
654
654
···
669
669
struct counter_count *count, u8 enable)
670
670
{
671
671
struct quad8 *const priv = counter_priv(counter);
672
-
const int base_offset = priv->base + 2 * count->id;
672
+
void __iomem *const base_offset = priv->base + 2 * count->id;
673
673
unsigned long irqflags;
674
674
unsigned int ior_cfg;
675
675
···
681
681
priv->irq_trigger[count->id] << 3;
682
682
683
683
/* Load I/O control configuration */
684
-
outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
684
+
iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
685
685
686
686
spin_unlock_irqrestore(&priv->lock, irqflags);
687
687
···
697
697
struct counter_count *count, u32 *noise_error)
698
698
{
699
699
const struct quad8 *const priv = counter_priv(counter);
700
-
const int base_offset = priv->base + 2 * count->id + 1;
700
+
void __iomem *const base_offset = priv->base + 2 * count->id + 1;
701
701
702
-
*noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
702
+
*noise_error = !!(ioread8(base_offset) & QUAD8_FLAG_E);
703
703
704
704
return 0;
705
705
}
···
717
717
static void quad8_preset_register_set(struct quad8 *const priv, const int id,
718
718
const unsigned int preset)
719
719
{
720
-
const unsigned int base_offset = priv->base + 2 * id;
720
+
void __iomem *const base_offset = priv->base + 2 * id;
721
721
int i;
722
722
723
723
priv->preset[id] = preset;
724
724
725
725
/* Reset Byte Pointer */
726
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
726
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
727
727
728
728
/* Set Preset Register */
729
729
for (i = 0; i < 3; i++)
730
-
outb(preset >> (8 * i), base_offset);
730
+
iowrite8(preset >> (8 * i), base_offset);
731
731
}
732
732
733
733
static int quad8_count_preset_write(struct counter_device *counter,
···
816
816
u8 preset_enable)
817
817
{
818
818
struct quad8 *const priv = counter_priv(counter);
819
-
const int base_offset = priv->base + 2 * count->id + 1;
819
+
void __iomem *const base_offset = priv->base + 2 * count->id + 1;
820
820
unsigned long irqflags;
821
821
unsigned int ior_cfg;
822
822
···
831
831
priv->irq_trigger[count->id] << 3;
832
832
833
833
/* Load I/O control configuration to Input / Output Control Register */
834
-
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
834
+
iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset);
835
835
836
836
spin_unlock_irqrestore(&priv->lock, irqflags);
837
837
···
858
858
}
859
859
860
860
/* Logic 0 = cable fault */
861
-
status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
861
+
status = ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
862
862
863
863
spin_unlock_irqrestore(&priv->lock, irqflags);
864
864
···
899
899
/* Enable is active low in Differential Encoder Cable Status register */
900
900
cable_fault_enable = ~priv->cable_fault_enable;
901
901
902
-
outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
902
+
iowrite8(cable_fault_enable,
903
+
priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
903
904
904
905
spin_unlock_irqrestore(&priv->lock, irqflags);
905
906
···
924
923
{
925
924
struct quad8 *const priv = counter_priv(counter);
926
925
const size_t channel_id = signal->id / 2;
927
-
const int base_offset = priv->base + 2 * channel_id;
926
+
void __iomem *const base_offset = priv->base + 2 * channel_id;
928
927
unsigned long irqflags;
929
928
930
929
spin_lock_irqsave(&priv->lock, irqflags);
···
932
931
priv->fck_prescaler[channel_id] = prescaler;
933
932
934
933
/* Reset Byte Pointer */
935
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
934
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
936
935
937
936
/* Set filter clock factor */
938
-
outb(prescaler, base_offset);
939
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
940
-
base_offset + 1);
937
+
iowrite8(prescaler, base_offset);
938
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
939
+
base_offset + 1);
941
940
942
941
spin_unlock_irqrestore(&priv->lock, irqflags);
943
942
···
1085
1084
{
1086
1085
struct counter_device *counter = private;
1087
1086
struct quad8 *const priv = counter_priv(counter);
1088
-
const unsigned long base = priv->base;
1087
+
void __iomem *const base = priv->base;
1089
1088
unsigned long irq_status;
1090
1089
unsigned long channel;
1091
1090
u8 event;
1092
1091
1093
-
irq_status = inb(base + QUAD8_REG_INTERRUPT_STATUS);
1092
+
irq_status = ioread8(base + QUAD8_REG_INTERRUPT_STATUS);
1094
1093
if (!irq_status)
1095
1094
return IRQ_NONE;
1096
1095
···
1119
1118
}
1120
1119
1121
1120
/* Clear pending interrupts on device */
1122
-
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
1121
+
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
1123
1122
1124
1123
return IRQ_HANDLED;
1124
+
}
1125
+
1126
+
static void quad8_init_counter(void __iomem *const base_offset)
1127
+
{
1128
+
unsigned long i;
1129
+
1130
+
/* Reset Byte Pointer */
1131
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
1132
+
/* Reset filter clock factor */
1133
+
iowrite8(0, base_offset);
1134
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1135
+
base_offset + 1);
1136
+
/* Reset Byte Pointer */
1137
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
1138
+
/* Reset Preset Register */
1139
+
for (i = 0; i < 3; i++)
1140
+
iowrite8(0x00, base_offset);
1141
+
/* Reset Borrow, Carry, Compare, and Sign flags */
1142
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
1143
+
/* Reset Error flag */
1144
+
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
1145
+
/* Binary encoding; Normal count; non-quadrature mode */
1146
+
iowrite8(QUAD8_CTR_CMR, base_offset + 1);
1147
+
/* Disable A and B inputs; preset on index; FLG1 as Carry */
1148
+
iowrite8(QUAD8_CTR_IOR, base_offset + 1);
1149
+
/* Disable index function; negative index polarity */
1150
+
iowrite8(QUAD8_CTR_IDR, base_offset + 1);
1125
1151
}
1126
1152
1127
1153
static int quad8_probe(struct device *dev, unsigned int id)
1128
1154
{
1129
1155
struct counter_device *counter;
1130
1156
struct quad8 *priv;
1131
-
int i, j;
1132
-
unsigned int base_offset;
1157
+
unsigned long i;
1133
1158
int err;
1134
1159
1135
1160
if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
···
1169
1142
return -ENOMEM;
1170
1143
priv = counter_priv(counter);
1171
1144
1145
+
priv->base = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
1146
+
if (!priv->base)
1147
+
return -ENOMEM;
1148
+
1172
1149
/* Initialize Counter device and driver data */
1173
1150
counter->name = dev_name(dev);
1174
1151
counter->parent = dev;
···
1181
1150
counter->num_counts = ARRAY_SIZE(quad8_counts);
1182
1151
counter->signals = quad8_signals;
1183
1152
counter->num_signals = ARRAY_SIZE(quad8_signals);
1184
-
priv->base = base[id];
1185
1153
1186
1154
spin_lock_init(&priv->lock);
1187
1155
1188
1156
/* Reset Index/Interrupt Register */
1189
-
outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT);
1157
+
iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT);
1190
1158
/* Reset all counters and disable interrupt function */
1191
-
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
1159
+
iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP);
1192
1160
/* Set initial configuration for all counters */
1193
-
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
1194
-
base_offset = base[id] + 2 * i;
1195
-
/* Reset Byte Pointer */
1196
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
1197
-
/* Reset filter clock factor */
1198
-
outb(0, base_offset);
1199
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1200
-
base_offset + 1);
1201
-
/* Reset Byte Pointer */
1202
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
1203
-
/* Reset Preset Register */
1204
-
for (j = 0; j < 3; j++)
1205
-
outb(0x00, base_offset);
1206
-
/* Reset Borrow, Carry, Compare, and Sign flags */
1207
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
1208
-
/* Reset Error flag */
1209
-
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
1210
-
/* Binary encoding; Normal count; non-quadrature mode */
1211
-
outb(QUAD8_CTR_CMR, base_offset + 1);
1212
-
/* Disable A and B inputs; preset on index; FLG1 as Carry */
1213
-
outb(QUAD8_CTR_IOR, base_offset + 1);
1214
-
/* Disable index function; negative index polarity */
1215
-
outb(QUAD8_CTR_IDR, base_offset + 1);
1216
-
}
1161
+
for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
1162
+
quad8_init_counter(priv->base + 2 * i);
1217
1163
/* Disable Differential Encoder Cable Status for all channels */
1218
-
outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);
1164
+
iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
1219
1165
/* Enable all counters and enable interrupt function */
1220
-
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP);
1166
+
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC,
1167
+
priv->base + QUAD8_REG_CHAN_OP);
1221
1168
1222
1169
err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
1223
1170
IRQF_SHARED, counter->name, counter);