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mmc: mtk-sd: Aggregate R/W for top_base iospace case where possible

In case the controller uses the top_base iospace, most register
read/writes can be changed from multiple RWs to a single read
and a single write.

Where possible, and where it makes sense, aggregate the multiple
reads and writes to just one.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250325110701.52623-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

authored by

AngeloGioacchino Del Regno and committed by
Ulf Hansson b70721fd 1649904e

+28 -24
+28 -24
drivers/mmc/host/mtk-sd.c
··· 1975 1975 1976 1976 if (host->dev_comp->data_tune) { 1977 1977 if (host->top_base) { 1978 - sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1979 - PAD_DAT_RD_RXDLY_SEL); 1980 - sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1981 - DATA_K_VALUE_SEL); 1982 - sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1983 - PAD_CMD_RD_RXDLY_SEL); 1978 + u32 top_ctl_val = readl(host->top_base + EMMC_TOP_CONTROL); 1979 + u32 top_cmd_val = readl(host->top_base + EMMC_TOP_CMD); 1980 + 1981 + top_cmd_val |= PAD_CMD_RD_RXDLY_SEL; 1982 + top_ctl_val |= PAD_DAT_RD_RXDLY_SEL; 1983 + top_ctl_val &= ~DATA_K_VALUE_SEL; 1984 1984 if (host->tuning_step > PAD_DELAY_HALF) { 1985 - sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1986 - PAD_DAT_RD_RXDLY2_SEL); 1987 - sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1988 - PAD_CMD_RD_RXDLY2_SEL); 1985 + top_cmd_val |= PAD_CMD_RD_RXDLY2_SEL; 1986 + top_ctl_val |= PAD_DAT_RD_RXDLY2_SEL; 1989 1987 } 1988 + 1989 + writel(top_ctl_val, host->top_base + EMMC_TOP_CONTROL); 1990 + writel(top_cmd_val, host->top_base + EMMC_TOP_CMD); 1990 1991 } else { 1991 1992 sdr_set_bits(host->base + tune_reg, 1992 1993 MSDC_PAD_TUNE_RD_SEL | ··· 2197 2196 u32 tune_reg = host->dev_comp->pad_tune_reg; 2198 2197 2199 2198 if (host->top_base) { 2199 + u32 regval = readl(host->top_base + EMMC_TOP_CMD); 2200 + 2201 + regval &= ~(PAD_CMD_RXDLY | PAD_CMD_RXDLY2); 2202 + 2200 2203 if (value < PAD_DELAY_HALF) { 2201 - sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value); 2202 - sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0); 2204 + regval |= FIELD_PREP(PAD_CMD_RXDLY, value); 2203 2205 } else { 2204 - sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 2205 - PAD_DELAY_HALF - 1); 2206 - sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 2207 - value - PAD_DELAY_HALF); 2206 + regval |= FIELD_PREP(PAD_CMD_RXDLY, PAD_DELAY_HALF - 1); 2207 + regval |= FIELD_PREP(PAD_CMD_RXDLY2, value - PAD_DELAY_HALF); 2208 2208 } 2209 + writel(regval, host->top_base + EMMC_TOP_CMD); 2209 2210 } else { 2210 2211 if (value < PAD_DELAY_HALF) { 2211 2212 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value); ··· 2227 2224 u32 tune_reg = host->dev_comp->pad_tune_reg; 2228 2225 2229 2226 if (host->top_base) { 2227 + u32 regval = readl(host->top_base + EMMC_TOP_CONTROL); 2228 + 2229 + regval &= ~(PAD_DAT_RD_RXDLY | PAD_DAT_RD_RXDLY2); 2230 + 2230 2231 if (value < PAD_DELAY_HALF) { 2231 - sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2232 - PAD_DAT_RD_RXDLY, value); 2233 - sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2234 - PAD_DAT_RD_RXDLY2, 0); 2232 + regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, value); 2233 + regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value); 2235 2234 } else { 2236 - sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2237 - PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1); 2238 - sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2239 - PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF); 2235 + regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1); 2236 + regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF); 2240 2237 } 2238 + writel(regval, host->top_base + EMMC_TOP_CONTROL); 2241 2239 } else { 2242 2240 if (value < PAD_DELAY_HALF) { 2243 2241 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);