Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: renesas: rcar-gen3-usb2: Add support for RZ/T2H SoC
Add initial support for the Renesas RZ/T2H SoC to the R-Car Gen3 USB2 PHY
driver. The RZ/T2H SoC requires configuration of additional
hardware-specific bits for proper VBUS level control and OTG operation.
Introduce the `vblvl_ctrl` flag in the SoC-specific driver data to enable
handling of VBUS level selection logic using `VBCTRL.VBLVL` bits. This is
required for managing the VBUS status detection and drive logic based on
SoC-specific needs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250808215209.3692744-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Lad Prabhakar
and committed by
Vinod Koul
b725741f
4b7aa47e
+75
-7
+75
-7
drivers/phy/renesas/phy-rcar-gen3-usb2.c
+75
-7
drivers/phy/renesas/phy-rcar-gen3-usb2.c
···
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* Copyright (C) 2014 Cogent Embedded, Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/extcon-provider.h>
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#include <linux/interrupt.h>
···
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#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
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/* OBINTSTA and OBINTEN */
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#define USB2_OBINTSTA_CLEAR GENMASK(31, 0)
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#define USB2_OBINT_SESSVLDCHG BIT(12)
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#define USB2_OBINT_IDDIGCHG BIT(11)
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#define USB2_OBINT_VBSTAINT BIT(3)
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#define USB2_OBINT_IDCHG_EN BIT(0) /* RZ/G2L specific */
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/* VBCTRL */
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#define USB2_VBCTRL_VBSTA_MASK GENMASK(31, 28)
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#define USB2_VBCTRL_VBSTA_DEFAULT 2
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#define USB2_VBCTRL_VBLVL_MASK GENMASK(23, 20)
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#define USB2_VBCTRL_VBLVL(m) FIELD_PREP_CONST(USB2_VBCTRL_VBLVL_MASK, (m))
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#define USB2_VBCTRL_OCCLREN BIT(16)
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#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
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#define USB2_VBCTRL_SIDDQREL BIT(2)
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#define USB2_VBCTRL_VBOUT BIT(0)
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/* LINECTRL1 */
···
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/* ADPCTRL */
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#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
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#define USB2_ADPCTRL_IDDIG BIT(19)
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#define USB2_ADPCTRL_VBUSVALID BIT(18)
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#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
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#define USB2_ADPCTRL_DRVVBUS BIT(4)
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···
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bool no_adp_ctrl;
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bool init_bus;
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bool utmi_ctrl;
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bool vblvl_ctrl;
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u32 obint_enable_bits;
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};
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···
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u32 val;
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dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
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if (ch->phy_data->no_adp_ctrl) {
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if (ch->phy_data->no_adp_ctrl || ch->phy_data->vblvl_ctrl) {
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if (ch->vbus)
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regulator_hardware_enable(ch->vbus, vbus);
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···
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static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
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{
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if (ch->phy_data->vblvl_ctrl) {
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bool vbus_valid;
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bool device;
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device = !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
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vbus_valid = !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_VBUSVALID);
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return !(device && !vbus_valid);
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}
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if (!ch->uses_otg_pins)
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return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
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···
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writel(val, usb2_base + USB2_LINECTRL1);
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if (!ch->phy_data->no_adp_ctrl) {
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val = readl(usb2_base + USB2_VBCTRL);
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val &= ~USB2_VBCTRL_OCCLREN;
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writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
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val = readl(usb2_base + USB2_ADPCTRL);
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writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
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if (ch->phy_data->vblvl_ctrl) {
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val = readl(usb2_base + USB2_VBCTRL);
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val = (val & ~USB2_VBCTRL_VBLVL_MASK) | USB2_VBCTRL_VBLVL(2);
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writel(val, usb2_base + USB2_VBCTRL);
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val = readl(usb2_base + USB2_ADPCTRL);
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writel(val | USB2_ADPCTRL_IDPULLUP | USB2_ADPCTRL_DRVVBUS,
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usb2_base + USB2_ADPCTRL);
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} else {
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val = readl(usb2_base + USB2_VBCTRL);
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val &= ~USB2_VBCTRL_OCCLREN;
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writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
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val = readl(usb2_base + USB2_ADPCTRL);
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writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
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}
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}
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mdelay(20);
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···
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writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTEN);
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rcar_gen3_device_recognition(ch);
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}
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static void rcar_gen3_configure_vblvl_ctrl(struct rcar_gen3_chan *ch)
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{
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void __iomem *usb2_base = ch->base;
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u32 val;
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if (!ch->phy_data->vblvl_ctrl)
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return;
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val = readl(usb2_base + USB2_VBCTRL);
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if ((val & USB2_VBCTRL_VBSTA_MASK) ==
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FIELD_PREP_CONST(USB2_VBCTRL_VBSTA_MASK, USB2_VBCTRL_VBSTA_DEFAULT))
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val &= ~USB2_VBCTRL_VBLVL_MASK;
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else
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val |= USB2_VBCTRL_VBLVL(USB2_VBCTRL_VBSTA_DEFAULT);
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writel(val, usb2_base + USB2_VBCTRL);
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}
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static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
···
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status = readl(usb2_base + USB2_OBINTSTA);
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if (status & ch->phy_data->obint_enable_bits) {
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dev_vdbg(dev, "%s: %08x\n", __func__, status);
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writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTSTA);
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if (ch->phy_data->vblvl_ctrl)
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writel(USB2_OBINTSTA_CLEAR, usb2_base + USB2_OBINTSTA);
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else
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writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTSTA);
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rcar_gen3_device_recognition(ch);
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rcar_gen3_configure_vblvl_ctrl(ch);
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ret = IRQ_HANDLED;
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}
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}
···
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/* Initialize otg part (only if we initialize a PHY with IRQs). */
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if (rphy->int_enable_bits)
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rcar_gen3_init_otg(channel);
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if (channel->phy_data->vblvl_ctrl) {
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/* SIDDQ mode release */
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writel(readl(usb2_base + USB2_VBCTRL) | USB2_VBCTRL_SIDDQREL,
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usb2_base + USB2_VBCTRL);
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udelay(250);
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}
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if (channel->phy_data->utmi_ctrl) {
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val = readl(usb2_base + USB2_REGEN_CG_CTRL) | USB2_REGEN_CG_CTRL_UPHY_WEN;
···
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.obint_enable_bits = USB2_OBINT_IDCHG_EN,
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};
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static const struct rcar_gen3_phy_drv_data rz_t2h_phy_usb2_data = {
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.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
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.vblvl_ctrl = true,
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.obint_enable_bits = USB2_OBINT_IDCHG_EN | USB2_OBINT_VBSTAINT,
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};
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static const struct rcar_gen3_phy_drv_data rz_v2h_phy_usb2_data = {
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.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
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.no_adp_ctrl = true,
···
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{
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.compatible = "renesas,usb2-phy-r9a09g057",
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.data = &rz_v2h_phy_usb2_data,
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},
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{
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.compatible = "renesas,usb2-phy-r9a09g077",
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.data = &rz_t2h_phy_usb2_data,
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},
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{
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.compatible = "renesas,rzg2l-usb2-phy",