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drm/msm/dpu: Add interrupt registers for DPU 13.0.0

DPU version 13.0.0 introduces changes to the interrupt register
layout. Update the driver to support these modifications for
proper interrupt handling.

Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698708/
Link: https://lore.kernel.org/r/20260115092749.533-9-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Yuanjie Yang and committed by
Dmitry Baryshkov b78956dc 2482c6f9

+88 -1
+88 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
··· 40 40 #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004) 41 41 #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008) 42 42 43 + #define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf)) 44 + #define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c0) 45 + #define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c4) 46 + #define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c8) 47 + #define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf)) 48 + #define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x000) 49 + #define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x004) 50 + #define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x008) 51 + 43 52 /** 44 53 * struct dpu_intr_reg - array of DPU register sets 45 54 * @clr_off: offset to CLEAR reg ··· 205 196 MDP_INTF_REV_7xxx_INTR_CLEAR(8), 206 197 MDP_INTF_REV_7xxx_INTR_EN(8), 207 198 MDP_INTF_REV_7xxx_INTR_STATUS(8) 199 + }, 200 + }; 201 + 202 + /* 203 + * dpu_intr_set_13xx - List of DPU interrupt registers for DPU >= 13.0 204 + */ 205 + static const struct dpu_intr_reg dpu_intr_set_13xx[] = { 206 + [MDP_SSPP_TOP0_INTR] = { 207 + INTR_CLEAR, 208 + INTR_EN, 209 + INTR_STATUS 210 + }, 211 + [MDP_SSPP_TOP0_INTR2] = { 212 + INTR2_CLEAR, 213 + INTR2_EN, 214 + INTR2_STATUS 215 + }, 216 + [MDP_SSPP_TOP0_HIST_INTR] = { 217 + HIST_INTR_CLEAR, 218 + HIST_INTR_EN, 219 + HIST_INTR_STATUS 220 + }, 221 + [MDP_INTF0_INTR] = { 222 + MDP_INTF_REV_13xx_INTR_CLEAR(0), 223 + MDP_INTF_REV_13xx_INTR_EN(0), 224 + MDP_INTF_REV_13xx_INTR_STATUS(0) 225 + }, 226 + [MDP_INTF1_INTR] = { 227 + MDP_INTF_REV_13xx_INTR_CLEAR(1), 228 + MDP_INTF_REV_13xx_INTR_EN(1), 229 + MDP_INTF_REV_13xx_INTR_STATUS(1) 230 + }, 231 + [MDP_INTF1_TEAR_INTR] = { 232 + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1), 233 + MDP_INTF_REV_13xx_INTR_TEAR_EN(1), 234 + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1) 235 + }, 236 + [MDP_INTF2_INTR] = { 237 + MDP_INTF_REV_13xx_INTR_CLEAR(2), 238 + MDP_INTF_REV_13xx_INTR_EN(2), 239 + MDP_INTF_REV_13xx_INTR_STATUS(2) 240 + }, 241 + [MDP_INTF2_TEAR_INTR] = { 242 + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2), 243 + MDP_INTF_REV_13xx_INTR_TEAR_EN(2), 244 + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2) 245 + }, 246 + [MDP_INTF3_INTR] = { 247 + MDP_INTF_REV_13xx_INTR_CLEAR(3), 248 + MDP_INTF_REV_13xx_INTR_EN(3), 249 + MDP_INTF_REV_13xx_INTR_STATUS(3) 250 + }, 251 + [MDP_INTF4_INTR] = { 252 + MDP_INTF_REV_13xx_INTR_CLEAR(4), 253 + MDP_INTF_REV_13xx_INTR_EN(4), 254 + MDP_INTF_REV_13xx_INTR_STATUS(4) 255 + }, 256 + [MDP_INTF5_INTR] = { 257 + MDP_INTF_REV_13xx_INTR_CLEAR(5), 258 + MDP_INTF_REV_13xx_INTR_EN(5), 259 + MDP_INTF_REV_13xx_INTR_STATUS(5) 260 + }, 261 + [MDP_INTF6_INTR] = { 262 + MDP_INTF_REV_13xx_INTR_CLEAR(6), 263 + MDP_INTF_REV_13xx_INTR_EN(6), 264 + MDP_INTF_REV_13xx_INTR_STATUS(6) 265 + }, 266 + [MDP_INTF7_INTR] = { 267 + MDP_INTF_REV_13xx_INTR_CLEAR(7), 268 + MDP_INTF_REV_13xx_INTR_EN(7), 269 + MDP_INTF_REV_13xx_INTR_STATUS(7) 270 + }, 271 + [MDP_INTF8_INTR] = { 272 + MDP_INTF_REV_13xx_INTR_CLEAR(8), 273 + MDP_INTF_REV_13xx_INTR_EN(8), 274 + MDP_INTF_REV_13xx_INTR_STATUS(8) 208 275 }, 209 276 }; 210 277 ··· 592 507 if (!intr) 593 508 return ERR_PTR(-ENOMEM); 594 509 595 - if (m->mdss_ver->core_major_ver >= 7) 510 + if (m->mdss_ver->core_major_ver >= 13) 511 + intr->intr_set = dpu_intr_set_13xx; 512 + else if (m->mdss_ver->core_major_ver >= 7) 596 513 intr->intr_set = dpu_intr_set_7xxx; 597 514 else 598 515 intr->intr_set = dpu_intr_set_legacy;