Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2022-09-10' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"From a train in the Irish countryside, regular drm fixes for 6.0-rc5.
This is mostly amdgpu/amdkfd and i915 fixes, then one panfrost, one
ttm and one edid fix. Nothing too major going on. Hopefully a quiet
week next week for LPC.
edid:
- Fix EDID 1.4 range-descriptor parsing
ttm:
- Fix ghost-object bulk moves
i915:
- Fix MIPI sequence block copy from BIOS' table
- Fix PCODE min freq setup when GuC's SLPC is in use
- Implement Workaround for eDP
- Fix has_flat_ccs selection for DG1
amdgpu:
- Firmware header fix
- SMU 13.x fix
- Debugfs memory leak fix
- NBIO 7.7 fix
- Firmware memory leak fix
amdkfd:
- Debug output fix
panfrost:
- Fix devfreq OPP"
* tag 'drm-fixes-2022-09-10' of git://anongit.freedesktop.org/drm/drm:
drm/panfrost: devfreq: set opp to the recommended one to configure regulator
drm/ttm: cleanup the resource of ghost objects after locking them
drm/amdgpu: prevent toc firmware memory leak
drm/amdgpu: correct doorbell range/size value for CSDMA_DOORBELL_RANGE
drm/amdkfd: print address in hex format rather than decimal
drm/amd/display: fix memory leak when using debugfs_lookup()
drm/amd/pm: add missing SetMGpuFanBoostLimitRpm mapping for SMU 13.0.7
drm/amd/amdgpu: add rlc_firmware_header_v2_4 to amdgpu_firmware_header
drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
drm/i915: Implement WaEdpLinkRateDataReload
drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC
drm/i915/bios: Copy the whole MIPI sequence block
drm/ttm: update bulk move object of ghost BO
drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets
+149
-35
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
···
1728
1728
add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1729
1729
1730
1730
if (user_addr) {
1731
-
pr_debug("creating userptr BO for user_addr = %llu\n", user_addr);
1731
+
pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1732
1732
ret = init_user_pages(*mem, user_addr, criu_resume);
1733
1733
if (ret)
1734
1734
goto allocate_init_user_pages_failed;
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
486
486
release_firmware(psp->ta_fw);
487
487
psp->ta_fw = NULL;
488
488
}
489
-
if (adev->psp.cap_fw) {
489
+
if (psp->cap_fw) {
490
490
release_firmware(psp->cap_fw);
491
491
psp->cap_fw = NULL;
492
492
}
493
-
493
+
if (psp->toc_fw) {
494
+
release_firmware(psp->toc_fw);
495
+
psp->toc_fw = NULL;
496
+
}
494
497
if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
495
498
adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
496
499
psp_sysfs_fini(adev);
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
···
390
390
struct rlc_firmware_header_v2_1 rlc_v2_1;
391
391
struct rlc_firmware_header_v2_2 rlc_v2_2;
392
392
struct rlc_firmware_header_v2_3 rlc_v2_3;
393
+
struct rlc_firmware_header_v2_4 rlc_v2_4;
393
394
struct sdma_firmware_header_v1_0 sdma;
394
395
struct sdma_firmware_header_v1_1 sdma_v1_1;
395
396
struct sdma_firmware_header_v2_0 sdma_v2_0;
-6
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
-6
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
···
68
68
doorbell_range = REG_SET_FIELD(doorbell_range,
69
69
GDC0_BIF_CSDMA_DOORBELL_RANGE,
70
70
SIZE, doorbell_size);
71
-
doorbell_range = REG_SET_FIELD(doorbell_range,
72
-
GDC0_BIF_SDMA0_DOORBELL_RANGE,
73
-
OFFSET, doorbell_index);
74
-
doorbell_range = REG_SET_FIELD(doorbell_range,
75
-
GDC0_BIF_SDMA0_DOORBELL_RANGE,
76
-
SIZE, doorbell_size);
77
71
} else {
78
72
doorbell_range = REG_SET_FIELD(doorbell_range,
79
73
GDC0_BIF_SDMA0_DOORBELL_RANGE,
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
···
120
120
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
121
121
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
122
122
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
123
+
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
123
124
};
124
125
125
126
static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
+2
-2
drivers/gpu/drm/drm_debugfs.c
+2
-2
drivers/gpu/drm/drm_debugfs.c
···
377
377
if (connector->status != connector_status_connected)
378
378
return -ENODEV;
379
379
380
-
seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq);
381
-
seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq);
380
+
seq_printf(m, "Min: %u\n", connector->display_info.monitor_range.min_vfreq);
381
+
seq_printf(m, "Max: %u\n", connector->display_info.monitor_range.max_vfreq);
382
382
383
383
return 0;
384
384
}
+18
-6
drivers/gpu/drm/drm_edid.c
+18
-6
drivers/gpu/drm/drm_edid.c
···
5971
5971
}
5972
5972
5973
5973
static
5974
-
void get_monitor_range(const struct detailed_timing *timing,
5975
-
void *info_monitor_range)
5974
+
void get_monitor_range(const struct detailed_timing *timing, void *c)
5976
5975
{
5977
-
struct drm_monitor_range_info *monitor_range = info_monitor_range;
5976
+
struct detailed_mode_closure *closure = c;
5977
+
struct drm_display_info *info = &closure->connector->display_info;
5978
+
struct drm_monitor_range_info *monitor_range = &info->monitor_range;
5978
5979
const struct detailed_non_pixel *data = &timing->data.other_data;
5979
5980
const struct detailed_data_monitor_range *range = &data->data.range;
5981
+
const struct edid *edid = closure->drm_edid->edid;
5980
5982
5981
5983
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
5982
5984
return;
···
5994
5992
5995
5993
monitor_range->min_vfreq = range->min_vfreq;
5996
5994
monitor_range->max_vfreq = range->max_vfreq;
5995
+
5996
+
if (edid->revision >= 4) {
5997
+
if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
5998
+
monitor_range->min_vfreq += 255;
5999
+
if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6000
+
monitor_range->max_vfreq += 255;
6001
+
}
5997
6002
}
5998
6003
5999
6004
static void drm_get_monitor_range(struct drm_connector *connector,
6000
6005
const struct drm_edid *drm_edid)
6001
6006
{
6002
-
struct drm_display_info *info = &connector->display_info;
6007
+
const struct drm_display_info *info = &connector->display_info;
6008
+
struct detailed_mode_closure closure = {
6009
+
.connector = connector,
6010
+
.drm_edid = drm_edid,
6011
+
};
6003
6012
6004
6013
if (!version_greater(drm_edid, 1, 1))
6005
6014
return;
6006
6015
6007
-
drm_for_each_detailed_block(drm_edid, get_monitor_range,
6008
-
&info->monitor_range);
6016
+
drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6009
6017
6010
6018
DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6011
6019
info->monitor_range.min_vfreq,
+7
drivers/gpu/drm/i915/display/intel_bios.c
+7
drivers/gpu/drm/i915/display/intel_bios.c
···
479
479
480
480
block_size = get_blocksize(block);
481
481
482
+
/*
483
+
* Version number and new block size are considered
484
+
* part of the header for MIPI sequenece block v3+.
485
+
*/
486
+
if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3)
487
+
block_size += 5;
488
+
482
489
entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3),
483
490
GFP_KERNEL);
484
491
if (!entry) {
+22
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+22
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
671
671
intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
672
672
&link_bw, &rate_select);
673
673
674
+
/*
675
+
* WaEdpLinkRateDataReload
676
+
*
677
+
* Parade PS8461E MUX (used on varius TGL+ laptops) needs
678
+
* to snoop the link rates reported by the sink when we
679
+
* use LINK_RATE_SET in order to operate in jitter cleaning
680
+
* mode (as opposed to redriver mode). Unfortunately it
681
+
* loses track of the snooped link rates when powered down,
682
+
* so we need to make it re-snoop often. Without this high
683
+
* link rates are not stable.
684
+
*/
685
+
if (!link_bw) {
686
+
struct intel_connector *connector = intel_dp->attached_connector;
687
+
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
688
+
689
+
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Reloading eDP link rates\n",
690
+
connector->base.base.id, connector->base.name);
691
+
692
+
drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
693
+
sink_rates, sizeof(sink_rates));
694
+
}
695
+
674
696
if (link_bw)
675
697
drm_dbg_kms(&i915->drm,
676
698
"[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n",
+3
drivers/gpu/drm/i915/gem/i915_gem_object.c
+3
drivers/gpu/drm/i915/gem/i915_gem_object.c
···
723
723
bool lmem_placement = false;
724
724
int i;
725
725
726
+
if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))
727
+
return false;
728
+
726
729
for (i = 0; i < obj->mm.n_placements; i++) {
727
730
/* Compression is not allowed for the objects with smem placement */
728
731
if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
+1
-1
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+1
-1
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+9
-10
drivers/gpu/drm/i915/gt/intel_llc.c
+9
-10
drivers/gpu/drm/i915/gt/intel_llc.c
···
12
12
#include "intel_llc.h"
13
13
#include "intel_mchbar_regs.h"
14
14
#include "intel_pcode.h"
15
+
#include "intel_rps.h"
15
16
16
17
struct ia_constants {
17
18
unsigned int min_gpu_freq;
···
56
55
if (!HAS_LLC(i915) || IS_DGFX(i915))
57
56
return false;
58
57
59
-
if (rps->max_freq <= rps->min_freq)
60
-
return false;
61
-
62
58
consts->max_ia_freq = cpu_max_MHz();
63
59
64
60
consts->min_ring_freq =
···
63
65
/* convert DDR frequency from units of 266.6MHz to bandwidth */
64
66
consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
65
67
66
-
consts->min_gpu_freq = rps->min_freq;
67
-
consts->max_gpu_freq = rps->max_freq;
68
-
if (GRAPHICS_VER(i915) >= 9) {
69
-
/* Convert GT frequency to 50 HZ units */
70
-
consts->min_gpu_freq /= GEN9_FREQ_SCALER;
71
-
consts->max_gpu_freq /= GEN9_FREQ_SCALER;
72
-
}
68
+
consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps);
69
+
consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps);
73
70
74
71
return true;
75
72
}
···
123
130
if (!get_ia_constants(llc, &consts))
124
131
return;
125
132
133
+
/*
134
+
* Although this is unlikely on any platform during initialization,
135
+
* let's ensure we don't get accidentally into infinite loop
136
+
*/
137
+
if (consts.max_gpu_freq <= consts.min_gpu_freq)
138
+
return;
126
139
/*
127
140
* For each potential GPU frequency, load a ring frequency we'd like
128
141
* to use for memory access. We do this by specifying the IA frequency
+50
drivers/gpu/drm/i915/gt/intel_rps.c
+50
drivers/gpu/drm/i915/gt/intel_rps.c
···
2126
2126
return intel_gpu_freq(rps, rps->max_freq_softlimit);
2127
2127
}
2128
2128
2129
+
/**
2130
+
* intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
2131
+
* @rps: the intel_rps structure
2132
+
*
2133
+
* Returns the max frequency in a raw format. In newer platforms raw is in
2134
+
* units of 50 MHz.
2135
+
*/
2136
+
u32 intel_rps_get_max_raw_freq(struct intel_rps *rps)
2137
+
{
2138
+
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
2139
+
u32 freq;
2140
+
2141
+
if (rps_uses_slpc(rps)) {
2142
+
return DIV_ROUND_CLOSEST(slpc->rp0_freq,
2143
+
GT_FREQUENCY_MULTIPLIER);
2144
+
} else {
2145
+
freq = rps->max_freq;
2146
+
if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
2147
+
/* Convert GT frequency to 50 MHz units */
2148
+
freq /= GEN9_FREQ_SCALER;
2149
+
}
2150
+
return freq;
2151
+
}
2152
+
}
2153
+
2129
2154
u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
2130
2155
{
2131
2156
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
···
2237
2212
return slpc->min_freq_softlimit;
2238
2213
else
2239
2214
return intel_gpu_freq(rps, rps->min_freq_softlimit);
2215
+
}
2216
+
2217
+
/**
2218
+
* intel_rps_get_min_raw_freq - returns the min frequency in some raw format.
2219
+
* @rps: the intel_rps structure
2220
+
*
2221
+
* Returns the min frequency in a raw format. In newer platforms raw is in
2222
+
* units of 50 MHz.
2223
+
*/
2224
+
u32 intel_rps_get_min_raw_freq(struct intel_rps *rps)
2225
+
{
2226
+
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
2227
+
u32 freq;
2228
+
2229
+
if (rps_uses_slpc(rps)) {
2230
+
return DIV_ROUND_CLOSEST(slpc->min_freq,
2231
+
GT_FREQUENCY_MULTIPLIER);
2232
+
} else {
2233
+
freq = rps->min_freq;
2234
+
if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
2235
+
/* Convert GT frequency to 50 MHz units */
2236
+
freq /= GEN9_FREQ_SCALER;
2237
+
}
2238
+
return freq;
2239
+
}
2240
2240
}
2241
2241
2242
2242
static int set_min_freq(struct intel_rps *rps, u32 val)
+2
drivers/gpu/drm/i915/gt/intel_rps.h
+2
drivers/gpu/drm/i915/gt/intel_rps.h
···
37
37
u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
38
38
u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
39
39
u32 intel_rps_get_min_frequency(struct intel_rps *rps);
40
+
u32 intel_rps_get_min_raw_freq(struct intel_rps *rps);
40
41
int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);
41
42
u32 intel_rps_get_max_frequency(struct intel_rps *rps);
43
+
u32 intel_rps_get_max_raw_freq(struct intel_rps *rps);
42
44
int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);
43
45
u32 intel_rps_get_rp0_frequency(struct intel_rps *rps);
44
46
u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
+11
drivers/gpu/drm/panfrost/panfrost_devfreq.c
+11
drivers/gpu/drm/panfrost/panfrost_devfreq.c
···
131
131
return PTR_ERR(opp);
132
132
133
133
panfrost_devfreq_profile.initial_freq = cur_freq;
134
+
135
+
/*
136
+
* Set the recommend OPP this will enable and configure the regulator
137
+
* if any and will avoid a switch off by regulator_late_cleanup()
138
+
*/
139
+
ret = dev_pm_opp_set_opp(dev, opp);
140
+
if (ret) {
141
+
DRM_DEV_ERROR(dev, "Couldn't set recommended OPP\n");
142
+
return ret;
143
+
}
144
+
134
145
dev_pm_opp_put(opp);
135
146
136
147
/*
+8
-5
drivers/gpu/drm/ttm/ttm_bo_util.c
+8
-5
drivers/gpu/drm/ttm/ttm_bo_util.c
···
236
236
if (bo->type != ttm_bo_type_sg)
237
237
fbo->base.base.resv = &fbo->base.base._resv;
238
238
239
-
if (fbo->base.resource) {
240
-
ttm_resource_set_bo(fbo->base.resource, &fbo->base);
241
-
bo->resource = NULL;
242
-
}
243
-
244
239
dma_resv_init(&fbo->base.base._resv);
245
240
fbo->base.base.dev = NULL;
246
241
ret = dma_resv_trylock(&fbo->base.base._resv);
247
242
WARN_ON(!ret);
243
+
244
+
if (fbo->base.resource) {
245
+
ttm_resource_set_bo(fbo->base.resource, &fbo->base);
246
+
bo->resource = NULL;
247
+
ttm_bo_set_bulk_move(&fbo->base, NULL);
248
+
} else {
249
+
fbo->base.bulk_move = NULL;
250
+
}
248
251
249
252
ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1);
250
253
if (ret) {
+2
-2
include/drm/drm_connector.h
+2
-2
include/drm/drm_connector.h
+5
include/drm/drm_edid.h
+5
include/drm/drm_edid.h
···
92
92
u8 str[13];
93
93
} __attribute__((packed));
94
94
95
+
#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
96
+
#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
97
+
#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
98
+
#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
99
+
95
100
#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
96
101
#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
97
102
#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02