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PM / devfreq: rk3399_dmc: Drop excess timing properties
All of these properties are initialized by ARM Trusted Firmware, and
have been since the early days of this chip. It's redundant (and
possibly wrong) to do this here now. What's more, there seems to be some
confusion about the units and some of the definitions of this timing
struct: the DT docs say MHz for many of these, but downstream users were
in Hz (and therefore, the ATF interface was Hz). Also, the in-driver
usage for some of these (e.g., for comparing to target frequency) were
in Hz too. So doubly wrong.
We can avoid thinking about who got the right units by dropping the
unnecessary code and properties. They are marked deprecated in the
binding schema.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
authored by
Brian Norris
and committed by
Chanwoo Choi
b82acf82
5f50c52f
+29
-115
+29
-115
drivers/devfreq/rk3399_dmc.c
+29
-115
drivers/devfreq/rk3399_dmc.c
···
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#include <soc/rockchip/rk3399_grf.h>
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#include <soc/rockchip/rockchip_sip.h>
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-
struct dram_timing {
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-
unsigned int ddr3_speed_bin;
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-
unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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-
unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int dram_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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-
};
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-
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struct rk3399_dmcfreq {
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struct device *dev;
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struct devfreq *devfreq;
···
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struct clk *dmc_clk;
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struct devfreq_event_dev *edev;
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struct mutex lock;
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struct dram_timing timing;
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struct regulator *vdd_center;
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struct regmap *regmap_pmu;
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unsigned long rate, target_rate;
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unsigned long volt, target_volt;
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unsigned int odt_dis_freq;
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int odt_pd_arg0, odt_pd_arg1;
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+
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unsigned int pd_idle;
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unsigned int sr_idle;
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+
unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int ddr3_odt_dis_freq;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int lpddr4_odt_dis_freq;
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};
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static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
···
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static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
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rk3399_dmcfreq_resume);
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static int of_get_ddr_timings(struct dram_timing *timing,
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struct device_node *np)
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+
static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data,
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struct device_node *np)
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{
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int ret = 0;
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ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
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&timing->ddr3_speed_bin);
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ret |= of_property_read_u32(np, "rockchip,pd_idle",
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&timing->pd_idle);
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&data->pd_idle);
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ret |= of_property_read_u32(np, "rockchip,sr_idle",
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&timing->sr_idle);
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&data->sr_idle);
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ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
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&timing->sr_mc_gate_idle);
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&data->sr_mc_gate_idle);
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ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
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&timing->srpd_lite_idle);
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&data->srpd_lite_idle);
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ret |= of_property_read_u32(np, "rockchip,standby_idle",
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&timing->standby_idle);
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-
ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
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&timing->auto_pd_dis_freq);
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-
ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
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&timing->dram_dll_dis_freq);
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-
ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
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&timing->phy_dll_dis_freq);
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&data->standby_idle);
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ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
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&timing->ddr3_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
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&timing->ddr3_drv);
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ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
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&timing->ddr3_odt);
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ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
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&timing->phy_ddr3_ca_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
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&timing->phy_ddr3_dq_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
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&timing->phy_ddr3_odt);
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&data->ddr3_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
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&timing->lpddr3_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
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&timing->lpddr3_drv);
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ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
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&timing->lpddr3_odt);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
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&timing->phy_lpddr3_ca_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
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&timing->phy_lpddr3_dq_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
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-
&timing->phy_lpddr3_odt);
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&data->lpddr3_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
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&timing->lpddr4_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
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&timing->lpddr4_drv);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
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&timing->lpddr4_dq_odt);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
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&timing->lpddr4_ca_odt);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
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&timing->phy_lpddr4_ca_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
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&timing->phy_lpddr4_ck_cs_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
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&timing->phy_lpddr4_dq_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
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&timing->phy_lpddr4_odt);
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&data->lpddr4_odt_dis_freq);
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return ret;
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}
···
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node, *node;
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struct rk3399_dmcfreq *data;
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int ret, index, size;
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uint32_t *timing;
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int ret;
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struct dev_pm_opp *opp;
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u32 ddr_type;
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u32 val;
···
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return ret;
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}
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-
/*
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* Get dram timing and pass it to arm trust firmware,
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* the dram driver in arm trust firmware will get these
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* timing and to do dram initial.
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*/
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if (!of_get_ddr_timings(&data->timing, np)) {
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timing = &data->timing.ddr3_speed_bin;
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size = sizeof(struct dram_timing) / 4;
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for (index = 0; index < size; index++) {
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
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ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
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0, 0, 0, 0, &res);
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if (res.a0) {
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dev_err(dev, "Failed to set dram param: %ld\n",
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res.a0);
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ret = -EINVAL;
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goto err_edev;
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-
}
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}
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}
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+
rk3399_dmcfreq_of_props(data, np);
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node = of_parse_phandle(np, "rockchip,pmu", 0);
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if (!node)
···
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switch (ddr_type) {
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case RK3399_PMUGRF_DDRTYPE_DDR3:
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data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
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data->odt_dis_freq = data->ddr3_odt_dis_freq;
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break;
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case RK3399_PMUGRF_DDRTYPE_LPDDR3:
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data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
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data->odt_dis_freq = data->lpddr3_odt_dis_freq;
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break;
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case RK3399_PMUGRF_DDRTYPE_LPDDR4:
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data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
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+
data->odt_dis_freq = data->lpddr4_odt_dis_freq;
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break;
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default:
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ret = -EINVAL;
···
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* arg2:
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* bit[0] : odt enable
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*/
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data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
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((data->timing.sr_mc_gate_idle & 0xff) << 8) |
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((data->timing.standby_idle & 0xffff) << 16);
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data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
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((data->timing.srpd_lite_idle & 0xfff) << 16);
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+
data->odt_pd_arg0 = (data->sr_idle & 0xff) |
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((data->sr_mc_gate_idle & 0xff) << 8) |
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+
((data->standby_idle & 0xffff) << 16);
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+
data->odt_pd_arg1 = (data->pd_idle & 0xfff) |
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+
((data->srpd_lite_idle & 0xfff) << 16);
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/*
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* We add a devfreq driver to our parent since it has a device tree node