Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - relocate PFVF PF related logic
Move device specific PFVF logic related to the PF to the newly created
adf_gen2_pfvf.c.
This refactory is done to isolate the GEN2 PFVF code into its own file
in preparation for the introduction of support for PFVF for GEN4
devices.
In addition the PFVF PF logic for dh895xcc has been isolated to
adf_dh895xcc_hw_data.c.
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Marco Chiappero
and committed by
Herbert Xu
b85bd945
1d613312
+103
-69
+1
drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+1
drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+1
drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
+1
drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
+2
-1
drivers/crypto/qat/qat_common/Makefile
+2
-1
drivers/crypto/qat/qat_common/Makefile
-48
drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
-48
drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
···
4
4
#include "icp_qat_hw.h"
5
5
#include <linux/pci.h>
6
6
7
-
#define ADF_GEN2_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
8
-
9
-
u32 adf_gen2_get_pf2vf_offset(u32 i)
10
-
{
11
-
return ADF_GEN2_PF2VF_OFFSET(i);
12
-
}
13
-
EXPORT_SYMBOL_GPL(adf_gen2_get_pf2vf_offset);
14
-
15
-
u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr)
16
-
{
17
-
u32 errsou3, errmsk3, vf_int_mask;
18
-
19
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/* Get the interrupt sources triggered by VFs */
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errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3);
21
-
vf_int_mask = ADF_GEN2_ERR_REG_VF2PF(errsou3);
22
-
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-
/* To avoid adding duplicate entries to work queue, clear
24
-
* vf_int_mask_sets bits that are already masked in ERRMSK register.
25
-
*/
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-
errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3);
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-
vf_int_mask &= ~ADF_GEN2_ERR_REG_VF2PF(errmsk3);
28
-
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return vf_int_mask;
30
-
}
31
-
EXPORT_SYMBOL_GPL(adf_gen2_get_vf2pf_sources);
32
-
33
-
void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
34
-
{
35
-
/* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
36
-
if (vf_mask & 0xFFFF) {
37
-
u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
38
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& ~ADF_GEN2_ERR_MSK_VF2PF(vf_mask);
39
-
ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
40
-
}
41
-
}
42
-
EXPORT_SYMBOL_GPL(adf_gen2_enable_vf2pf_interrupts);
43
-
44
-
void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
45
-
{
46
-
/* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
47
-
if (vf_mask & 0xFFFF) {
48
-
u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
49
-
| ADF_GEN2_ERR_MSK_VF2PF(vf_mask);
50
-
ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
51
-
}
52
-
}
53
-
EXPORT_SYMBOL_GPL(adf_gen2_disable_vf2pf_interrupts);
54
-
55
7
u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self)
56
8
{
57
9
if (!self || !self->accel_mask)
-13
drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
-13
drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
···
136
136
#define ADF_GEN2_CERRSSMSH(i) ((i) * 0x4000 + 0x10)
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#define ADF_GEN2_ERRSSMSH_EN BIT(3)
138
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-
/* VF2PF interrupts */
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-
#define ADF_GEN2_ERRSOU3 (0x3A000 + 0x0C)
141
-
#define ADF_GEN2_ERRSOU5 (0x3A000 + 0xD8)
142
-
#define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C)
143
-
#define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC)
144
-
#define ADF_GEN2_ERR_REG_VF2PF(vf_src) (((vf_src) & 0x01FFFE00) >> 9)
145
-
#define ADF_GEN2_ERR_MSK_VF2PF(vf_mask) (((vf_mask) & 0xFFFF) << 9)
146
-
147
-
u32 adf_gen2_get_pf2vf_offset(u32 i);
148
-
u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_bar);
149
-
void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
150
-
void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
151
-
152
139
u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self);
153
140
u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self);
154
141
void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
+57
drivers/crypto/qat/qat_common/adf_gen2_pfvf.c
+57
drivers/crypto/qat/qat_common/adf_gen2_pfvf.c
···
1
+
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2
+
/* Copyright(c) 2021 Intel Corporation */
3
+
#include <linux/types.h>
4
+
#include "adf_accel_devices.h"
5
+
#include "adf_gen2_pfvf.h"
6
+
7
+
/* VF2PF interrupts */
8
+
#define ADF_GEN2_ERR_REG_VF2PF(vf_src) (((vf_src) & 0x01FFFE00) >> 9)
9
+
#define ADF_GEN2_ERR_MSK_VF2PF(vf_mask) (((vf_mask) & 0xFFFF) << 9)
10
+
11
+
#define ADF_GEN2_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
12
+
13
+
u32 adf_gen2_get_pf2vf_offset(u32 i)
14
+
{
15
+
return ADF_GEN2_PF2VF_OFFSET(i);
16
+
}
17
+
EXPORT_SYMBOL_GPL(adf_gen2_get_pf2vf_offset);
18
+
19
+
u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr)
20
+
{
21
+
u32 errsou3, errmsk3, vf_int_mask;
22
+
23
+
/* Get the interrupt sources triggered by VFs */
24
+
errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3);
25
+
vf_int_mask = ADF_GEN2_ERR_REG_VF2PF(errsou3);
26
+
27
+
/* To avoid adding duplicate entries to work queue, clear
28
+
* vf_int_mask_sets bits that are already masked in ERRMSK register.
29
+
*/
30
+
errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3);
31
+
vf_int_mask &= ~ADF_GEN2_ERR_REG_VF2PF(errmsk3);
32
+
33
+
return vf_int_mask;
34
+
}
35
+
EXPORT_SYMBOL_GPL(adf_gen2_get_vf2pf_sources);
36
+
37
+
void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
38
+
{
39
+
/* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
40
+
if (vf_mask & 0xFFFF) {
41
+
u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
42
+
& ~ADF_GEN2_ERR_MSK_VF2PF(vf_mask);
43
+
ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
44
+
}
45
+
}
46
+
EXPORT_SYMBOL_GPL(adf_gen2_enable_vf2pf_interrupts);
47
+
48
+
void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
49
+
{
50
+
/* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
51
+
if (vf_mask & 0xFFFF) {
52
+
u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
53
+
| ADF_GEN2_ERR_MSK_VF2PF(vf_mask);
54
+
ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
55
+
}
56
+
}
57
+
EXPORT_SYMBOL_GPL(adf_gen2_disable_vf2pf_interrupts);
+19
drivers/crypto/qat/qat_common/adf_gen2_pfvf.h
+19
drivers/crypto/qat/qat_common/adf_gen2_pfvf.h
···
1
+
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2
+
/* Copyright(c) 2021 Intel Corporation */
3
+
#ifndef ADF_GEN2_PFVF_H
4
+
#define ADF_GEN2_PFVF_H
5
+
6
+
#include <linux/types.h>
7
+
#include "adf_accel_devices.h"
8
+
9
+
#define ADF_GEN2_ERRSOU3 (0x3A000 + 0x0C)
10
+
#define ADF_GEN2_ERRSOU5 (0x3A000 + 0xD8)
11
+
#define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C)
12
+
#define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC)
13
+
14
+
u32 adf_gen2_get_pf2vf_offset(u32 i);
15
+
u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_bar);
16
+
void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
17
+
void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
18
+
19
+
#endif /* ADF_GEN2_PFVF_H */
+21
-7
drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+21
-7
drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
···
4
4
#include <adf_pf2vf_msg.h>
5
5
#include <adf_common_drv.h>
6
6
#include <adf_gen2_hw_data.h>
7
+
#include <adf_gen2_pfvf.h>
7
8
#include "adf_dh895xcc_hw_data.h"
8
9
#include "icp_qat_hw.h"
9
10
···
115
114
116
115
static u32 get_vf2pf_sources(void __iomem *pmisc_bar)
117
116
{
118
-
u32 errsou5, errmsk5, vf_int_mask;
117
+
u32 errsou3, errmsk3, errsou5, errmsk5, vf_int_mask;
119
118
120
-
vf_int_mask = adf_gen2_get_vf2pf_sources(pmisc_bar);
119
+
/* Get the interrupt sources triggered by VFs */
120
+
errsou3 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRSOU3);
121
+
vf_int_mask = ADF_DH895XCC_ERR_REG_VF2PF_L(errsou3);
121
122
122
-
/* Get the interrupt sources triggered by VFs, but to avoid duplicates
123
-
* in the work queue, clear vf_int_mask_sets bits that are already
124
-
* masked in ERRMSK register.
123
+
/* To avoid adding duplicate entries to work queue, clear
124
+
* vf_int_mask_sets bits that are already masked in ERRMSK register.
125
125
*/
126
+
errmsk3 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRMSK3);
127
+
vf_int_mask &= ~ADF_DH895XCC_ERR_REG_VF2PF_L(errmsk3);
128
+
129
+
/* Do the same for ERRSOU5 */
126
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errsou5 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRSOU5);
127
131
errmsk5 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRMSK5);
128
132
vf_int_mask |= ADF_DH895XCC_ERR_REG_VF2PF_U(errsou5);
···
139
133
static void enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
140
134
{
141
135
/* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
142
-
adf_gen2_enable_vf2pf_interrupts(pmisc_addr, vf_mask);
136
+
if (vf_mask & 0xFFFF) {
137
+
u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
138
+
& ~ADF_DH895XCC_ERR_MSK_VF2PF_L(vf_mask);
139
+
ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
140
+
}
143
141
144
142
/* Enable VF2PF Messaging Ints - VFs 16 through 31 per vf_mask[31:16] */
145
143
if (vf_mask >> 16) {
···
157
147
static void disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
158
148
{
159
149
/* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
160
-
adf_gen2_disable_vf2pf_interrupts(pmisc_addr, vf_mask);
150
+
if (vf_mask & 0xFFFF) {
151
+
u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
152
+
| ADF_DH895XCC_ERR_MSK_VF2PF_L(vf_mask);
153
+
ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
154
+
}
161
155
162
156
/* Disable VF2PF interrupts for VFs 16 through 31 per vf_mask[31:16] */
163
157
if (vf_mask >> 16) {
+2
drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
+2
drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
···
25
25
#define ADF_DH895XCC_SMIA1_MASK 0x1
26
26
27
27
/* Masks for VF2PF interrupts */
28
+
#define ADF_DH895XCC_ERR_REG_VF2PF_L(vf_src) (((vf_src) & 0x01FFFE00) >> 9)
29
+
#define ADF_DH895XCC_ERR_MSK_VF2PF_L(vf_mask) (((vf_mask) & 0xFFFF) << 9)
28
30
#define ADF_DH895XCC_ERR_REG_VF2PF_U(vf_src) (((vf_src) & 0x0000FFFF) << 16)
29
31
#define ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask) ((vf_mask) >> 16)
30
32