Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/dram: convert to struct intel_display
Convert everything except uncore access to struct
intel_display. Converting the graphics version checks to display version
checks needs a tweak for display version 13, which have graphics version
12.
While at it, convert logging to drm_dbg_kms().
v2: Handle display version 13
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251120161846.3128999-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+120
-114
+1
-1
drivers/gpu/drm/i915/display/i9xx_wm.c
+1
-1
drivers/gpu/drm/i915/display/i9xx_wm.c
···
90
90
91
91
static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)
92
92
{
93
-
const struct dram_info *dram_info = intel_dram_info(display->drm);
93
+
const struct dram_info *dram_info = intel_dram_info(display);
94
94
bool is_ddr3 = dram_info->type == INTEL_DRAM_DDR3;
95
95
int i;
96
96
+1
-1
drivers/gpu/drm/i915/display/intel_bw.c
+1
-1
drivers/gpu/drm/i915/display/intel_bw.c
+1
-3
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
-3
drivers/gpu/drm/i915/display/intel_cdclk.c
···
3737
3737
3738
3738
static int i9xx_hrawclk(struct intel_display *display)
3739
3739
{
3740
-
struct drm_i915_private *i915 = to_i915(display->drm);
3741
-
3742
3740
/* hrawclock is 1/4 the FSB frequency */
3743
-
return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4);
3741
+
return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4);
3744
3742
}
3745
3743
3746
3744
/**
+1
-1
drivers/gpu/drm/i915/display/intel_display_power.c
+1
-1
drivers/gpu/drm/i915/display/intel_display_power.c
···
1616
1616
1617
1617
static void tgl_bw_buddy_init(struct intel_display *display)
1618
1618
{
1619
-
const struct dram_info *dram_info = intel_dram_info(display->drm);
1619
+
const struct dram_info *dram_info = intel_dram_info(display);
1620
1620
const struct buddy_page_mask *table;
1621
1621
unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
1622
1622
int config, i;
+107
-98
drivers/gpu/drm/i915/display/intel_dram.c
+107
-98
drivers/gpu/drm/i915/display/intel_dram.c
···
56
56
57
57
#undef DRAM_TYPE_STR
58
58
59
-
static enum intel_dram_type pnv_dram_type(struct drm_i915_private *i915)
59
+
static enum intel_dram_type pnv_dram_type(struct intel_display *display)
60
60
{
61
+
struct drm_i915_private *i915 = to_i915(display->drm);
62
+
61
63
return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ?
62
64
INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2;
63
65
}
64
66
65
-
static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
67
+
static unsigned int pnv_mem_freq(struct intel_display *display)
66
68
{
69
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
67
70
u32 tmp;
68
71
69
72
tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
···
83
80
return 0;
84
81
}
85
82
86
-
static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
83
+
static unsigned int ilk_mem_freq(struct intel_display *display)
87
84
{
85
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
88
86
u16 ddrpll;
89
87
90
88
ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
···
99
95
case 0x18:
100
96
return 1600000;
101
97
default:
102
-
drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
103
-
ddrpll & 0xff);
98
+
drm_dbg_kms(display->drm, "unknown memory frequency 0x%02x\n",
99
+
ddrpll & 0xff);
104
100
return 0;
105
101
}
106
102
}
107
103
108
-
static unsigned int chv_mem_freq(struct drm_i915_private *i915)
104
+
static unsigned int chv_mem_freq(struct intel_display *display)
109
105
{
110
106
u32 val;
111
107
112
-
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_CCK));
113
-
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG);
114
-
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_CCK));
108
+
vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK));
109
+
val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG);
110
+
vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK));
115
111
116
112
switch ((val >> 2) & 0x7) {
117
113
case 3:
···
121
117
}
122
118
}
123
119
124
-
static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
120
+
static unsigned int vlv_mem_freq(struct intel_display *display)
125
121
{
126
122
u32 val;
127
123
128
-
vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
129
-
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
130
-
vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT));
124
+
vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_PUNIT));
125
+
val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
126
+
vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_PUNIT));
131
127
132
128
switch ((val >> 6) & 3) {
133
129
case 0:
···
142
138
return 0;
143
139
}
144
140
145
-
unsigned int intel_mem_freq(struct drm_i915_private *i915)
141
+
unsigned int intel_mem_freq(struct intel_display *display)
146
142
{
147
-
if (IS_PINEVIEW(i915))
148
-
return pnv_mem_freq(i915);
149
-
else if (GRAPHICS_VER(i915) == 5)
150
-
return ilk_mem_freq(i915);
151
-
else if (IS_CHERRYVIEW(i915))
152
-
return chv_mem_freq(i915);
153
-
else if (IS_VALLEYVIEW(i915))
154
-
return vlv_mem_freq(i915);
143
+
if (display->platform.pineview)
144
+
return pnv_mem_freq(display);
145
+
else if (DISPLAY_VER(display) == 5)
146
+
return ilk_mem_freq(display);
147
+
else if (display->platform.cherryview)
148
+
return chv_mem_freq(display);
149
+
else if (display->platform.valleyview)
150
+
return vlv_mem_freq(display);
155
151
else
156
152
return 0;
157
153
}
158
154
159
-
static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
155
+
static unsigned int i9xx_fsb_freq(struct intel_display *display)
160
156
{
157
+
struct drm_i915_private *i915 = to_i915(display->drm);
161
158
u32 fsb;
162
159
163
160
/*
···
171
166
*/
172
167
fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
173
168
174
-
if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
169
+
if (display->platform.pineview || display->platform.mobile) {
175
170
switch (fsb) {
176
171
case CLKCFG_FSB_400:
177
172
return 400000;
···
212
207
}
213
208
}
214
209
215
-
static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
210
+
static unsigned int ilk_fsb_freq(struct intel_display *display)
216
211
{
212
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
217
213
u16 fsb;
218
214
219
215
fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff;
···
235
229
case 0x018:
236
230
return 6400000;
237
231
default:
238
-
drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
232
+
drm_dbg_kms(display->drm, "unknown fsb frequency 0x%04x\n", fsb);
239
233
return 0;
240
234
}
241
235
}
242
236
243
-
unsigned int intel_fsb_freq(struct drm_i915_private *i915)
237
+
unsigned int intel_fsb_freq(struct intel_display *display)
244
238
{
245
-
if (GRAPHICS_VER(i915) == 5)
246
-
return ilk_fsb_freq(i915);
247
-
else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
248
-
return i9xx_fsb_freq(i915);
239
+
if (DISPLAY_VER(display) == 5)
240
+
return ilk_fsb_freq(display);
241
+
else if (IS_DISPLAY_VER(display, 3, 4))
242
+
return i9xx_fsb_freq(display);
249
243
else
250
244
return 0;
251
245
}
252
246
253
-
static int i915_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
247
+
static int i915_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
254
248
{
255
-
dram_info->fsb_freq = intel_fsb_freq(i915);
249
+
dram_info->fsb_freq = intel_fsb_freq(display);
256
250
if (dram_info->fsb_freq)
257
-
drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq);
251
+
drm_dbg_kms(display->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq);
258
252
259
-
dram_info->mem_freq = intel_mem_freq(i915);
253
+
dram_info->mem_freq = intel_mem_freq(display);
260
254
if (dram_info->mem_freq)
261
-
drm_dbg(&i915->drm, "DDR speed: %d kHz\n", dram_info->mem_freq);
255
+
drm_dbg_kms(display->drm, "DDR speed: %d kHz\n", dram_info->mem_freq);
262
256
263
-
if (IS_PINEVIEW(i915))
264
-
dram_info->type = pnv_dram_type(i915);
257
+
if (display->platform.pineview)
258
+
dram_info->type = pnv_dram_type(display);
265
259
266
260
return 0;
267
261
}
···
397
391
}
398
392
399
393
static void
400
-
skl_dram_print_dimm_info(struct drm_i915_private *i915,
394
+
skl_dram_print_dimm_info(struct intel_display *display,
401
395
struct dram_dimm_info *dimm,
402
396
int channel, char dimm_name)
403
397
{
404
-
drm_dbg_kms(&i915->drm,
398
+
drm_dbg_kms(display->drm,
405
399
"CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb+ DIMMs: %s\n",
406
400
channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
407
401
str_yes_no(skl_is_16gb_dimm(dimm)));
408
402
}
409
403
410
404
static void
411
-
skl_dram_get_dimm_l_info(struct drm_i915_private *i915,
405
+
skl_dram_get_dimm_l_info(struct intel_display *display,
412
406
struct dram_dimm_info *dimm,
413
407
int channel, u32 val)
414
408
{
415
-
if (GRAPHICS_VER(i915) >= 11) {
409
+
if (DISPLAY_VER(display) >= 11) {
416
410
dimm->size = icl_get_dimm_l_size(val);
417
411
dimm->width = icl_get_dimm_l_width(val);
418
412
dimm->ranks = icl_get_dimm_l_ranks(val);
···
422
416
dimm->ranks = skl_get_dimm_l_ranks(val);
423
417
}
424
418
425
-
skl_dram_print_dimm_info(i915, dimm, channel, 'L');
419
+
skl_dram_print_dimm_info(display, dimm, channel, 'L');
426
420
}
427
421
428
422
static void
429
-
skl_dram_get_dimm_s_info(struct drm_i915_private *i915,
423
+
skl_dram_get_dimm_s_info(struct intel_display *display,
430
424
struct dram_dimm_info *dimm,
431
425
int channel, u32 val)
432
426
{
433
-
if (GRAPHICS_VER(i915) >= 11) {
427
+
if (DISPLAY_VER(display) >= 11) {
434
428
dimm->size = icl_get_dimm_s_size(val);
435
429
dimm->width = icl_get_dimm_s_width(val);
436
430
dimm->ranks = icl_get_dimm_s_ranks(val);
···
440
434
dimm->ranks = skl_get_dimm_s_ranks(val);
441
435
}
442
436
443
-
skl_dram_print_dimm_info(i915, dimm, channel, 'S');
437
+
skl_dram_print_dimm_info(display, dimm, channel, 'S');
444
438
}
445
439
446
440
static int
447
-
skl_dram_get_channel_info(struct drm_i915_private *i915,
441
+
skl_dram_get_channel_info(struct intel_display *display,
448
442
struct dram_channel_info *ch,
449
443
int channel, u32 val)
450
444
{
451
-
skl_dram_get_dimm_l_info(i915, &ch->dimm_l, channel, val);
452
-
skl_dram_get_dimm_s_info(i915, &ch->dimm_s, channel, val);
445
+
skl_dram_get_dimm_l_info(display, &ch->dimm_l, channel, val);
446
+
skl_dram_get_dimm_s_info(display, &ch->dimm_s, channel, val);
453
447
454
448
if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
455
-
drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
449
+
drm_dbg_kms(display->drm, "CH%u not populated\n", channel);
456
450
return -EINVAL;
457
451
}
458
452
···
466
460
ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
467
461
skl_is_16gb_dimm(&ch->dimm_s);
468
462
469
-
drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n",
463
+
drm_dbg_kms(display->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n",
470
464
channel, ch->ranks, str_yes_no(ch->is_16gb_dimm));
471
465
472
466
return 0;
···
482
476
}
483
477
484
478
static int
485
-
skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram_info)
479
+
skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info)
486
480
{
481
+
struct drm_i915_private *i915 = to_i915(display->drm);
487
482
struct dram_channel_info ch0 = {}, ch1 = {};
488
483
u32 val;
489
484
int ret;
···
494
487
495
488
val = intel_uncore_read(&i915->uncore,
496
489
SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
497
-
ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
490
+
ret = skl_dram_get_channel_info(display, &ch0, 0, val);
498
491
if (ret == 0)
499
492
dram_info->num_channels++;
500
493
501
494
val = intel_uncore_read(&i915->uncore,
502
495
SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
503
-
ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
496
+
ret = skl_dram_get_channel_info(display, &ch1, 1, val);
504
497
if (ret == 0)
505
498
dram_info->num_channels++;
506
499
507
500
if (dram_info->num_channels == 0) {
508
-
drm_info(&i915->drm, "Number of memory channels is zero\n");
501
+
drm_info(display->drm, "Number of memory channels is zero\n");
509
502
return -EINVAL;
510
503
}
511
504
512
505
if (ch0.ranks == 0 && ch1.ranks == 0) {
513
-
drm_info(&i915->drm, "couldn't get memory rank information\n");
506
+
drm_info(display->drm, "couldn't get memory rank information\n");
514
507
return -EINVAL;
515
508
}
516
509
···
518
511
519
512
dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
520
513
521
-
drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
514
+
drm_dbg_kms(display->drm, "Memory configuration is symmetric? %s\n",
522
515
str_yes_no(dram_info->symmetric_memory));
523
516
524
-
drm_dbg_kms(&i915->drm, "16Gb+ DIMMs: %s\n",
517
+
drm_dbg_kms(display->drm, "16Gb+ DIMMs: %s\n",
525
518
str_yes_no(dram_info->has_16gb_dimms));
526
519
527
520
return 0;
528
521
}
529
522
530
523
static enum intel_dram_type
531
-
skl_get_dram_type(struct drm_i915_private *i915)
524
+
skl_get_dram_type(struct intel_display *display)
532
525
{
526
+
struct drm_i915_private *i915 = to_i915(display->drm);
533
527
u32 val;
534
528
535
529
val = intel_uncore_read(&i915->uncore,
···
552
544
}
553
545
554
546
static int
555
-
skl_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
547
+
skl_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
556
548
{
557
549
int ret;
558
550
559
-
dram_info->type = skl_get_dram_type(i915);
551
+
dram_info->type = skl_get_dram_type(display);
560
552
561
-
ret = skl_dram_get_channels_info(i915, dram_info);
553
+
ret = skl_dram_get_channels_info(display, dram_info);
562
554
if (ret)
563
555
return ret;
564
556
···
643
635
dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
644
636
}
645
637
646
-
static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
638
+
static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
647
639
{
640
+
struct drm_i915_private *i915 = to_i915(display->drm);
648
641
u32 val;
649
642
u8 valid_ranks = 0;
650
643
int i;
···
666
657
bxt_get_dimm_info(&dimm, val);
667
658
type = bxt_get_dimm_type(val);
668
659
669
-
drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
660
+
drm_WARN_ON(display->drm, type != INTEL_DRAM_UNKNOWN &&
670
661
dram_info->type != INTEL_DRAM_UNKNOWN &&
671
662
dram_info->type != type);
672
663
673
-
drm_dbg_kms(&i915->drm,
664
+
drm_dbg_kms(display->drm,
674
665
"CH%u DIMM size: %u Gb, width: X%u, ranks: %u\n",
675
666
i - BXT_D_CR_DRP0_DUNIT_START,
676
667
dimm.size, dimm.width, dimm.ranks);
···
683
674
}
684
675
685
676
if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
686
-
drm_info(&i915->drm, "couldn't get memory information\n");
677
+
drm_info(display->drm, "couldn't get memory information\n");
687
678
return -EINVAL;
688
679
}
689
680
690
681
return 0;
691
682
}
692
683
693
-
static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
684
+
static int icl_pcode_read_mem_global_info(struct intel_display *display,
694
685
struct dram_info *dram_info)
695
686
{
696
687
u32 val = 0;
697
688
int ret;
698
689
699
-
ret = intel_pcode_read(&dev_priv->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
690
+
ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
700
691
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
701
692
if (ret)
702
693
return ret;
703
694
704
-
if (GRAPHICS_VER(dev_priv) == 12) {
695
+
if (DISPLAY_VER(display) >= 12) {
705
696
switch (val & 0xf) {
706
697
case 0:
707
698
dram_info->type = INTEL_DRAM_DDR4;
···
752
743
return 0;
753
744
}
754
745
755
-
static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
746
+
static int gen11_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
756
747
{
757
748
int ret;
758
749
759
-
ret = skl_dram_get_channels_info(i915, dram_info);
750
+
ret = skl_dram_get_channels_info(display, dram_info);
760
751
if (ret)
761
752
return ret;
762
753
763
-
return icl_pcode_read_mem_global_info(i915, dram_info);
754
+
return icl_pcode_read_mem_global_info(display, dram_info);
764
755
}
765
756
766
-
static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
757
+
static int gen12_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
767
758
{
768
-
return icl_pcode_read_mem_global_info(i915, dram_info);
759
+
return icl_pcode_read_mem_global_info(display, dram_info);
769
760
}
770
761
771
-
static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
762
+
static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
772
763
{
773
-
struct intel_display *display = i915->display;
764
+
struct drm_i915_private *i915 = to_i915(display->drm);
774
765
u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
775
766
776
767
switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
···
793
784
dram_info->type = INTEL_DRAM_LPDDR3;
794
785
break;
795
786
case 8:
796
-
drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
787
+
drm_WARN_ON(display->drm, !display->platform.dgfx);
797
788
dram_info->type = INTEL_DRAM_GDDR;
798
789
break;
799
790
case 9:
800
-
drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
791
+
drm_WARN_ON(display->drm, !display->platform.dgfx);
801
792
dram_info->type = INTEL_DRAM_GDDR_ECC;
802
793
break;
803
794
default:
···
815
806
return 0;
816
807
}
817
808
818
-
int intel_dram_detect(struct drm_i915_private *i915)
809
+
int intel_dram_detect(struct intel_display *display)
819
810
{
820
-
struct intel_display *display = i915->display;
811
+
struct drm_i915_private *i915 = to_i915(display->drm);
821
812
struct dram_info *dram_info;
822
813
int ret;
823
814
824
-
if (IS_DG2(i915) || !intel_display_device_present(display))
815
+
if (display->platform.dg2 || !HAS_DISPLAY(display))
825
816
return 0;
826
817
827
-
dram_info = drmm_kzalloc(&i915->drm, sizeof(*dram_info), GFP_KERNEL);
818
+
dram_info = drmm_kzalloc(display->drm, sizeof(*dram_info), GFP_KERNEL);
828
819
if (!dram_info)
829
820
return -ENOMEM;
830
821
831
822
i915->dram_info = dram_info;
832
823
833
824
if (DISPLAY_VER(display) >= 14)
834
-
ret = xelpdp_get_dram_info(i915, dram_info);
835
-
else if (GRAPHICS_VER(i915) >= 12)
836
-
ret = gen12_get_dram_info(i915, dram_info);
837
-
else if (GRAPHICS_VER(i915) >= 11)
838
-
ret = gen11_get_dram_info(i915, dram_info);
839
-
else if (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
840
-
ret = bxt_get_dram_info(i915, dram_info);
841
-
else if (GRAPHICS_VER(i915) >= 9)
842
-
ret = skl_get_dram_info(i915, dram_info);
825
+
ret = xelpdp_get_dram_info(display, dram_info);
826
+
else if (DISPLAY_VER(display) >= 12)
827
+
ret = gen12_get_dram_info(display, dram_info);
828
+
else if (DISPLAY_VER(display) >= 11)
829
+
ret = gen11_get_dram_info(display, dram_info);
830
+
else if (display->platform.broxton || display->platform.geminilake)
831
+
ret = bxt_get_dram_info(display, dram_info);
832
+
else if (DISPLAY_VER(display) >= 9)
833
+
ret = skl_get_dram_info(display, dram_info);
843
834
else
844
-
ret = i915_get_dram_info(i915, dram_info);
835
+
ret = i915_get_dram_info(display, dram_info);
845
836
846
-
drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
837
+
drm_dbg_kms(display->drm, "DRAM type: %s\n",
847
838
intel_dram_type_str(dram_info->type));
848
839
849
-
drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
840
+
drm_dbg_kms(display->drm, "DRAM channels: %u\n", dram_info->num_channels);
850
841
851
-
drm_dbg_kms(&i915->drm, "Num QGV points %u\n", dram_info->num_qgv_points);
852
-
drm_dbg_kms(&i915->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points);
842
+
drm_dbg_kms(display->drm, "Num QGV points %u\n", dram_info->num_qgv_points);
843
+
drm_dbg_kms(display->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points);
853
844
854
845
/* TODO: Do we want to abort probe on dram detection failures? */
855
846
if (ret)
···
863
854
* checks, and prefer not dereferencing on platforms that shouldn't look at dram
864
855
* info, to catch accidental and incorrect dram info checks.
865
856
*/
866
-
const struct dram_info *intel_dram_info(struct drm_device *drm)
857
+
const struct dram_info *intel_dram_info(struct intel_display *display)
867
858
{
868
-
struct drm_i915_private *i915 = to_i915(drm);
859
+
struct drm_i915_private *i915 = to_i915(display->drm);
869
860
870
861
return i915->dram_info;
871
862
}
+5
-6
drivers/gpu/drm/i915/display/intel_dram.h
+5
-6
drivers/gpu/drm/i915/display/intel_dram.h
···
8
8
9
9
#include <linux/types.h>
10
10
11
-
struct drm_i915_private;
12
-
struct drm_device;
11
+
struct intel_display;
13
12
14
13
struct dram_info {
15
14
enum intel_dram_type {
···
34
35
bool has_16gb_dimms;
35
36
};
36
37
37
-
int intel_dram_detect(struct drm_i915_private *i915);
38
-
unsigned int intel_fsb_freq(struct drm_i915_private *i915);
39
-
unsigned int intel_mem_freq(struct drm_i915_private *i915);
40
-
const struct dram_info *intel_dram_info(struct drm_device *drm);
38
+
int intel_dram_detect(struct intel_display *display);
39
+
unsigned int intel_fsb_freq(struct intel_display *display);
40
+
unsigned int intel_mem_freq(struct intel_display *display);
41
+
const struct dram_info *intel_dram_info(struct intel_display *display);
41
42
const char *intel_dram_type_str(enum intel_dram_type type);
42
43
43
44
#endif /* __INTEL_DRAM_H__ */
+2
-2
drivers/gpu/drm/i915/display/skl_watermark.c
+2
-2
drivers/gpu/drm/i915/display/skl_watermark.c
···
3125
3125
if (display->platform.kabylake ||
3126
3126
display->platform.coffeelake ||
3127
3127
display->platform.cometlake) {
3128
-
const struct dram_info *dram_info = intel_dram_info(display->drm);
3128
+
const struct dram_info *dram_info = intel_dram_info(display);
3129
3129
3130
3130
return dram_info->symmetric_memory;
3131
3131
}
···
3169
3169
3170
3170
static bool need_16gb_dimm_wa(struct intel_display *display)
3171
3171
{
3172
-
const struct dram_info *dram_info = intel_dram_info(display->drm);
3172
+
const struct dram_info *dram_info = intel_dram_info(display);
3173
3173
3174
3174
return (display->platform.skylake || display->platform.kabylake ||
3175
3175
display->platform.coffeelake || display->platform.cometlake ||
+1
-1
drivers/gpu/drm/i915/i915_driver.c
+1
-1
drivers/gpu/drm/i915/i915_driver.c
+1
-1
drivers/gpu/drm/xe/display/xe_display.c
+1
-1
drivers/gpu/drm/xe/display/xe_display.c