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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: clock: add SM6350 QCOM video clock bindings

Add device tree bindings for video clock controller for SM6350 SoCs.

Signed-off-by: Konrad Dybcio <konradybcio@kernel.org>
Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-2-cc22386433f4@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Konrad Dybcio and committed by
Bjorn Andersson b887afb9 0af2f6be

+47
+20
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
··· 14 14 domains on Qualcomm SoCs. 15 15 16 16 See also:: 17 + include/dt-bindings/clock/qcom,sm6350-videocc.h 17 18 include/dt-bindings/clock/qcom,videocc-sc7180.h 18 19 include/dt-bindings/clock/qcom,videocc-sc7280.h 19 20 include/dt-bindings/clock/qcom,videocc-sdm845.h ··· 27 26 - qcom,sc7180-videocc 28 27 - qcom,sc7280-videocc 29 28 - qcom,sdm845-videocc 29 + - qcom,sm6350-videocc 30 30 - qcom,sm8150-videocc 31 31 - qcom,sm8250-videocc 32 32 ··· 88 86 items: 89 87 - const: bi_tcxo 90 88 - const: bi_tcxo_ao 89 + 90 + - if: 91 + properties: 92 + compatible: 93 + enum: 94 + - qcom,sm6350-videocc 95 + then: 96 + properties: 97 + clocks: 98 + items: 99 + - description: Video AHB clock from GCC 100 + - description: Board XO source 101 + - description: Sleep Clock source 102 + clock-names: 103 + items: 104 + - const: iface 105 + - const: bi_tcxo 106 + - const: sleep_clk 91 107 92 108 - if: 93 109 properties:
+27
include/dt-bindings/clock/qcom,sm6350-videocc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H 8 + #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H 9 + 10 + /* VIDEO_CC clocks */ 11 + #define VIDEO_PLL0 0 12 + #define VIDEO_PLL0_OUT_EVEN 1 13 + #define VIDEO_CC_IRIS_AHB_CLK 2 14 + #define VIDEO_CC_IRIS_CLK_SRC 3 15 + #define VIDEO_CC_MVS0_AXI_CLK 4 16 + #define VIDEO_CC_MVS0_CORE_CLK 5 17 + #define VIDEO_CC_MVSC_CORE_CLK 6 18 + #define VIDEO_CC_MVSC_CTL_AXI_CLK 7 19 + #define VIDEO_CC_SLEEP_CLK 8 20 + #define VIDEO_CC_SLEEP_CLK_SRC 9 21 + #define VIDEO_CC_VENUS_AHB_CLK 10 22 + 23 + /* GDSCs */ 24 + #define MVSC_GDSC 0 25 + #define MVS0_GDSC 1 26 + 27 + #endif