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linux
Merge branch 'net-stmmac-replace-speed_mode_2500-method'
Russell King says:
====================
net: stmmac: replace speed_mode_2500() method
This series replaces the speed_mode_2500() method with a new method
that is more flexible, allowing the platform glue driver to populate
phylink's supported_interfaces and set the PHY-side interface mode.
The only user of this method is currently dwmac-intel, which we
update to use this new method.
====================
Link: https://patch.msgid.link/aBNe0Vt81vmqVCma@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+49
-44
+16
-17
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+16
-17
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
···
284
284
}
285
285
}
286
286
287
-
static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
287
+
static void tgl_get_interfaces(struct stmmac_priv *priv, void *bsp_priv,
288
+
unsigned long *interfaces)
288
289
{
289
-
struct intel_priv_data *intel_priv = intel_data;
290
-
struct stmmac_priv *priv = netdev_priv(ndev);
291
-
int serdes_phy_addr = 0;
292
-
u32 data = 0;
293
-
294
-
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
290
+
struct intel_priv_data *intel_priv = bsp_priv;
291
+
phy_interface_t interface;
292
+
int data;
295
293
296
294
/* Determine the link speed mode: 2.5Gbps/1Gbps */
297
-
data = mdiobus_read(priv->mii, serdes_phy_addr,
298
-
SERDES_GCR);
295
+
data = mdiobus_read(priv->mii, intel_priv->mdio_adhoc_addr, SERDES_GCR);
296
+
if (data < 0)
297
+
return;
299
298
300
-
if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
301
-
SERDES_LINK_MODE_2G5) {
299
+
if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) {
302
300
dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
303
-
priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
304
301
priv->plat->mdio_bus_data->default_an_inband = false;
302
+
interface = PHY_INTERFACE_MODE_2500BASEX;
303
+
} else {
304
+
interface = PHY_INTERFACE_MODE_SGMII;
305
305
}
306
+
307
+
__set_bit(interface, interfaces);
308
+
priv->plat->phy_interface = interface;
306
309
}
307
310
308
311
/* Program PTP Clock Frequency for different variant of
···
932
929
plat->rx_queues_to_use = 6;
933
930
plat->tx_queues_to_use = 4;
934
931
plat->clk_ptp_rate = 204800000;
935
-
plat->speed_mode_2500 = intel_speed_mode_2500;
932
+
plat->get_interfaces = tgl_get_interfaces;
936
933
937
934
plat->safety_feat_cfg->tsoee = 1;
938
935
plat->safety_feat_cfg->mrxpee = 0;
···
951
948
struct plat_stmmacenet_data *plat)
952
949
{
953
950
plat->bus_id = 1;
954
-
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
955
951
plat->serdes_powerup = intel_serdes_powerup;
956
952
plat->serdes_powerdown = intel_serdes_powerdown;
957
953
return tgl_common_data(pdev, plat);
···
964
962
struct plat_stmmacenet_data *plat)
965
963
{
966
964
plat->bus_id = 2;
967
-
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
968
965
plat->serdes_powerup = intel_serdes_powerup;
969
966
plat->serdes_powerdown = intel_serdes_powerdown;
970
967
return tgl_common_data(pdev, plat);
···
977
976
struct plat_stmmacenet_data *plat)
978
977
{
979
978
plat->bus_id = 1;
980
-
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
981
979
982
980
/* SerDes power up and power down are done in BIOS for ADL */
983
981
···
991
991
struct plat_stmmacenet_data *plat)
992
992
{
993
993
plat->bus_id = 2;
994
-
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
995
994
996
995
/* SerDes power up and power down are done in BIOS for ADL */
997
996
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
···
21
21
#define SERDES_RATE_MASK GENMASK(9, 8)
22
22
#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
23
23
#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
24
-
#define SERDES_LINK_MODE_SHIFT 1
25
24
#define SERDES_PWR_ST_SHIFT 4
26
25
#define SERDES_PWR_ST_P0 0x0
27
26
#define SERDES_PWR_ST_P3 0x3
+31
-25
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+31
-25
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
1258
1258
static int stmmac_phy_setup(struct stmmac_priv *priv)
1259
1259
{
1260
1260
struct stmmac_mdio_bus_data *mdio_bus_data;
1261
-
int mode = priv->plat->phy_interface;
1261
+
struct phylink_config *config;
1262
1262
struct fwnode_handle *fwnode;
1263
1263
struct phylink_pcs *pcs;
1264
1264
struct phylink *phylink;
1265
1265
1266
-
priv->phylink_config.dev = &priv->dev->dev;
1267
-
priv->phylink_config.type = PHYLINK_NETDEV;
1268
-
priv->phylink_config.mac_managed_pm = true;
1266
+
config = &priv->phylink_config;
1267
+
1268
+
config->dev = &priv->dev->dev;
1269
+
config->type = PHYLINK_NETDEV;
1270
+
config->mac_managed_pm = true;
1269
1271
1270
1272
/* Stmmac always requires an RX clock for hardware initialization */
1271
-
priv->phylink_config.mac_requires_rxc = true;
1273
+
config->mac_requires_rxc = true;
1272
1274
1273
1275
if (!(priv->plat->flags & STMMAC_FLAG_RX_CLK_RUNS_IN_LPI))
1274
-
priv->phylink_config.eee_rx_clk_stop_enable = true;
1276
+
config->eee_rx_clk_stop_enable = true;
1275
1277
1276
1278
/* Set the default transmit clock stop bit based on the platform glue */
1277
1279
priv->tx_lpi_clk_stop = priv->plat->flags &
···
1281
1279
1282
1280
mdio_bus_data = priv->plat->mdio_bus_data;
1283
1281
if (mdio_bus_data)
1284
-
priv->phylink_config.default_an_inband =
1285
-
mdio_bus_data->default_an_inband;
1282
+
config->default_an_inband = mdio_bus_data->default_an_inband;
1286
1283
1287
-
/* Set the platform/firmware specified interface mode. Note, phylink
1288
-
* deals with the PHY interface mode, not the MAC interface mode.
1284
+
/* Get the PHY interface modes (at the PHY end of the link) that
1285
+
* are supported by the platform.
1289
1286
*/
1290
-
__set_bit(mode, priv->phylink_config.supported_interfaces);
1287
+
if (priv->plat->get_interfaces)
1288
+
priv->plat->get_interfaces(priv, priv->plat->bsp_priv,
1289
+
config->supported_interfaces);
1290
+
1291
+
/* Set the platform/firmware specified interface mode if the
1292
+
* supported interfaces have not already been provided using
1293
+
* phy_interface as a last resort.
1294
+
*/
1295
+
if (phy_interface_empty(config->supported_interfaces))
1296
+
__set_bit(priv->plat->phy_interface,
1297
+
config->supported_interfaces);
1291
1298
1292
1299
/* If we have an xpcs, it defines which PHY interfaces are supported. */
1293
1300
if (priv->hw->xpcs)
···
1305
1294
pcs = priv->hw->phylink_pcs;
1306
1295
1307
1296
if (pcs)
1308
-
phy_interface_or(priv->phylink_config.supported_interfaces,
1309
-
priv->phylink_config.supported_interfaces,
1297
+
phy_interface_or(config->supported_interfaces,
1298
+
config->supported_interfaces,
1310
1299
pcs->supported_interfaces);
1311
1300
1312
1301
if (priv->dma_cap.eee) {
1313
1302
/* Assume all supported interfaces also support LPI */
1314
-
memcpy(priv->phylink_config.lpi_interfaces,
1315
-
priv->phylink_config.supported_interfaces,
1316
-
sizeof(priv->phylink_config.lpi_interfaces));
1303
+
memcpy(config->lpi_interfaces, config->supported_interfaces,
1304
+
sizeof(config->lpi_interfaces));
1317
1305
1318
1306
/* All full duplex speeds above 100Mbps are supported */
1319
-
priv->phylink_config.lpi_capabilities = ~(MAC_1000FD - 1) |
1320
-
MAC_100FD;
1321
-
priv->phylink_config.lpi_timer_default = eee_timer * 1000;
1322
-
priv->phylink_config.eee_enabled_default = true;
1307
+
config->lpi_capabilities = ~(MAC_1000FD - 1) | MAC_100FD;
1308
+
config->lpi_timer_default = eee_timer * 1000;
1309
+
config->eee_enabled_default = true;
1323
1310
}
1324
1311
1325
1312
fwnode = priv->plat->port_node;
1326
1313
if (!fwnode)
1327
1314
fwnode = dev_fwnode(priv->device);
1328
1315
1329
-
phylink = phylink_create(&priv->phylink_config, fwnode,
1330
-
mode, &stmmac_phylink_mac_ops);
1316
+
phylink = phylink_create(config, fwnode, priv->plat->phy_interface,
1317
+
&stmmac_phylink_mac_ops);
1331
1318
if (IS_ERR(phylink))
1332
1319
return PTR_ERR(phylink);
1333
1320
···
7735
7726
priv->plat->bus_id);
7736
7727
goto error_mdio_register;
7737
7728
}
7738
-
7739
-
if (priv->plat->speed_mode_2500)
7740
-
priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7741
7729
7742
7730
ret = stmmac_pcs_setup(ndev);
7743
7731
if (ret)
+2
-1
include/linux/stmmac.h
+2
-1
include/linux/stmmac.h
···
233
233
u8 tx_sched_algorithm;
234
234
struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
235
235
struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
236
+
void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv,
237
+
unsigned long *interfaces);
236
238
int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i,
237
239
phy_interface_t interface, int speed);
238
240
void (*fix_mac_speed)(void *priv, int speed, unsigned int mode);
239
241
int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
240
242
int (*serdes_powerup)(struct net_device *ndev, void *priv);
241
243
void (*serdes_powerdown)(struct net_device *ndev, void *priv);
242
-
void (*speed_mode_2500)(struct net_device *ndev, void *priv);
243
244
int (*mac_finish)(struct net_device *ndev,
244
245
void *priv,
245
246
unsigned int mode,