Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
memory: tegra: Group error handling related registers
Group MC error related registers into a struct as they could have SoC
specific values. Tegra264 has different register offsets than the
existing devices and so in order to add support for Tegra264 we need to
first make this change.
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
authored by
Ketan Patil
and committed by
Krzysztof Kozlowski
b8a177f1
2413283f
+71
-39
+32
-15
drivers/memory/tegra/mc.c
+32
-15
drivers/memory/tegra/mc.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <linux/clk.h>
···
55
55
{ /* sentinel */ }
56
56
};
57
57
MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
58
+
59
+
const struct tegra_mc_regs tegra20_mc_regs = {
60
+
.cfg_channel_enable = 0xdf8,
61
+
.err_status = 0x08,
62
+
.err_add = 0x0c,
63
+
.err_add_hi = 0x11fc,
64
+
.err_vpr_status = 0x654,
65
+
.err_vpr_add = 0x658,
66
+
.err_sec_status = 0x67c,
67
+
.err_sec_add = 0x680,
68
+
.err_mts_status = 0x9b0,
69
+
.err_mts_add = 0x9b4,
70
+
.err_gen_co_status = 0xc00,
71
+
.err_gen_co_add = 0xc04,
72
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.err_route_status = 0x9c0,
73
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.err_route_add = 0x9c4,
74
+
};
58
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static void tegra_mc_devm_action_put_device(void *data)
60
77
{
···
608
591
609
592
switch (intmask) {
610
593
case MC_INT_DECERR_VPR:
611
-
status_reg = MC_ERR_VPR_STATUS;
612
-
addr_reg = MC_ERR_VPR_ADR;
594
+
status_reg = mc->soc->regs->err_vpr_status;
595
+
addr_reg = mc->soc->regs->err_vpr_add;
613
596
break;
614
597
615
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case MC_INT_SECERR_SEC:
616
-
status_reg = MC_ERR_SEC_STATUS;
617
-
addr_reg = MC_ERR_SEC_ADR;
599
+
status_reg = mc->soc->regs->err_sec_status;
600
+
addr_reg = mc->soc->regs->err_sec_add;
618
601
break;
619
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620
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case MC_INT_DECERR_MTS:
621
-
status_reg = MC_ERR_MTS_STATUS;
622
-
addr_reg = MC_ERR_MTS_ADR;
604
+
status_reg = mc->soc->regs->err_mts_status;
605
+
addr_reg = mc->soc->regs->err_mts_add;
623
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break;
624
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625
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case MC_INT_DECERR_GENERALIZED_CARVEOUT:
626
-
status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS;
627
-
addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR;
609
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status_reg = mc->soc->regs->err_gen_co_status;
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+
addr_reg = mc->soc->regs->err_gen_co_add;
628
611
break;
629
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case MC_INT_DECERR_ROUTE_SANITY:
631
-
status_reg = MC_ERR_ROUTE_SANITY_STATUS;
632
-
addr_reg = MC_ERR_ROUTE_SANITY_ADR;
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+
status_reg = mc->soc->regs->err_route_status;
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+
addr_reg = mc->soc->regs->err_route_add;
633
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break;
634
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635
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default:
636
-
status_reg = MC_ERR_STATUS;
637
-
addr_reg = MC_ERR_ADR;
619
+
status_reg = mc->soc->regs->err_status;
620
+
addr_reg = mc->soc->regs->err_add;
638
621
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
640
623
if (mc->soc->has_addr_hi_reg)
641
-
addr_hi_reg = MC_ERR_ADR_HI;
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addr_hi_reg = mc->soc->regs->err_add_hi;
642
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#endif
643
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break;
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}
···
891
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unsigned int i;
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u32 value;
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894
-
value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE);
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value = mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable);
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if (value <= 0) {
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mc->num_channels = mc->soc->num_channels;
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return;
+1
-15
drivers/memory/tegra/mc.h
+1
-15
drivers/memory/tegra/mc.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
2
/*
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-
* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
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#ifndef MEMORY_TEGRA_MC_H
···
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#define MC_INTSTATUS 0x00
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#define MC_INTMASK 0x04
17
-
#define MC_ERR_STATUS 0x08
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-
#define MC_ERR_ADR 0x0c
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#define MC_GART_ERROR_REQ 0x30
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
···
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#define MC_EMEM_ARB_OVERRIDE 0xe8
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#define MC_TIMING_CONTROL_DBG 0xf8
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#define MC_TIMING_CONTROL 0xfc
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-
#define MC_ERR_VPR_STATUS 0x654
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#define MC_ERR_VPR_ADR 0x658
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-
#define MC_ERR_SEC_STATUS 0x67c
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-
#define MC_ERR_SEC_ADR 0x680
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-
#define MC_ERR_MTS_STATUS 0x9b0
49
-
#define MC_ERR_MTS_ADR 0x9b4
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-
#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0
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-
#define MC_ERR_ROUTE_SANITY_ADR 0x9c4
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-
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
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-
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
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-
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
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#define MC_GLOBAL_INTSTATUS 0xf24
56
-
#define MC_ERR_ADR_HI 0x11fc
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47
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#define MC_INT_DECERR_ROUTE_SANITY BIT(20)
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#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)
+2
-1
drivers/memory/tegra/tegra114.c
+2
-1
drivers/memory/tegra/tegra114.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
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-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
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#include <linux/of.h>
···
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1114
.resets = tegra114_mc_resets,
1115
1115
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
1116
1116
.ops = &tegra30_mc_ops,
1117
+
.regs = &tegra20_mc_regs,
1117
1118
};
+3
-1
drivers/memory/tegra/tegra124.c
+3
-1
drivers/memory/tegra/tegra124.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
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2
/*
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-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
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#include <linux/of.h>
···
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.num_resets = ARRAY_SIZE(tegra124_mc_resets),
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.icc_ops = &tegra124_mc_icc_ops,
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.ops = &tegra30_mc_ops,
1278
+
.regs = &tegra20_mc_regs,
1278
1279
};
1279
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#endif /* CONFIG_ARCH_TEGRA_124_SOC */
1280
1281
···
1308
1307
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
1309
1308
.icc_ops = &tegra124_mc_icc_ops,
1310
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.ops = &tegra30_mc_ops,
1310
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.regs = &tegra20_mc_regs,
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1311
};
1312
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#endif /* CONFIG_ARCH_TEGRA_132_SOC */
+2
-1
drivers/memory/tegra/tegra186.c
+2
-1
drivers/memory/tegra/tegra186.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
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-
* Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved.
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4
*/
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#include <linux/io.h>
···
914
914
.ops = &tegra186_mc_ops,
915
915
.ch_intmask = 0x0000000f,
916
916
.global_intstatus_channel_shift = 0,
917
+
.regs = &tegra20_mc_regs,
917
918
};
918
919
#endif
+2
-1
drivers/memory/tegra/tegra194.c
+2
-1
drivers/memory/tegra/tegra194.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
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5
6
6
#include <soc/tegra/mc.h>
···
1358
1358
.icc_ops = &tegra_mc_icc_ops,
1359
1359
.ch_intmask = 0x00000f00,
1360
1360
.global_intstatus_channel_shift = 8,
1361
+
.regs = &tegra20_mc_regs,
1361
1362
};
+2
-1
drivers/memory/tegra/tegra20.c
+2
-1
drivers/memory/tegra/tegra20.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2012-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <linux/bitfield.h>
···
778
778
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
779
779
.icc_ops = &tegra20_mc_icc_ops,
780
780
.ops = &tegra20_mc_ops,
781
+
.regs = &tegra20_mc_regs,
781
782
};
+2
-1
drivers/memory/tegra/tegra210.c
+2
-1
drivers/memory/tegra/tegra210.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2015-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <dt-bindings/memory/tegra210-mc.h>
···
1287
1287
.resets = tegra210_mc_resets,
1288
1288
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
1289
1289
.ops = &tegra30_mc_ops,
1290
+
.regs = &tegra20_mc_regs,
1290
1291
};
+2
-1
drivers/memory/tegra/tegra234.c
+2
-1
drivers/memory/tegra/tegra234.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2022-2026, NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <soc/tegra/mc.h>
···
1152
1152
* supported.
1153
1153
*/
1154
1154
.num_carveouts = 32,
1155
+
.regs = &tegra20_mc_regs,
1155
1156
};
+2
-1
drivers/memory/tegra/tegra30.c
+2
-1
drivers/memory/tegra/tegra30.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <linux/device.h>
···
1400
1400
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
1401
1401
.icc_ops = &tegra30_mc_icc_ops,
1402
1402
.ops = &tegra30_mc_ops,
1403
+
.regs = &tegra20_mc_regs,
1403
1404
};
+21
-1
include/soc/tegra/mc.h
+21
-1
include/soc/tegra/mc.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
2
/*
3
-
* Copyright (C) 2014 NVIDIA Corporation
3
+
* Copyright (C) 2014-2026 NVIDIA Corporation
4
4
*/
5
5
6
6
#ifndef __SOC_TEGRA_MC_H__
···
168
168
int (*probe_device)(struct tegra_mc *mc, struct device *dev);
169
169
};
170
170
171
+
struct tegra_mc_regs {
172
+
unsigned int cfg_channel_enable;
173
+
unsigned int err_status;
174
+
unsigned int err_add;
175
+
unsigned int err_add_hi;
176
+
unsigned int err_vpr_status;
177
+
unsigned int err_vpr_add;
178
+
unsigned int err_sec_status;
179
+
unsigned int err_sec_add;
180
+
unsigned int err_mts_status;
181
+
unsigned int err_mts_add;
182
+
unsigned int err_gen_co_status;
183
+
unsigned int err_gen_co_add;
184
+
unsigned int err_route_status;
185
+
unsigned int err_route_add;
186
+
};
187
+
171
188
struct tegra_mc_soc {
172
189
const struct tegra_mc_client *clients;
173
190
unsigned int num_clients;
···
213
196
214
197
const struct tegra_mc_icc_ops *icc_ops;
215
198
const struct tegra_mc_ops *ops;
199
+
const struct tegra_mc_regs *regs;
216
200
};
217
201
218
202
struct tegra_mc {
···
273
255
return -ENODEV;
274
256
}
275
257
#endif
258
+
259
+
extern const struct tegra_mc_regs tegra20_mc_regs;
276
260
277
261
#endif /* __SOC_TEGRA_MC_H__ */