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clk: sp7021: switch to FIELD_PREP_WM16 macro

The sp7021 clock driver has its own shifted high word mask macro,
similar to the ones many Rockchip drivers have.

Remove it, and replace instances of it with hw_bitfield.h's
FIELD_PREP_WM16 macro, which does the same thing except in a common
macro that also does compile-time error checking.

This was compile-tested with 32-bit ARM with Clang, no runtime tests
were performed as I lack the hardware. However, I verified that fix
commit 5c667d5a5a3e ("clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()")
is not regressed. No warning is produced.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>

authored by

Nicolas Frattaroli and committed by
Yury Norov (NVIDIA) b8b56771 30e91957

+8 -14
+8 -14
drivers/clk/clk-sp7021.c
··· 7 7 #include <linux/clk-provider.h> 8 8 #include <linux/of.h> 9 9 #include <linux/bitfield.h> 10 + #include <linux/hw_bitfield.h> 10 11 #include <linux/slab.h> 11 12 #include <linux/io.h> 12 13 #include <linux/err.h> ··· 38 37 #define MASK_DIVR GENMASK(8, 7) 39 38 #define MASK_DIVN GENMASK(7, 0) 40 39 #define MASK_DIVM GENMASK(14, 8) 41 - 42 - /* HIWORD_MASK FIELD_PREP */ 43 - #define HWM_FIELD_PREP(mask, value) \ 44 - ({ \ 45 - u64 _m = mask; \ 46 - (_m << 16) | FIELD_PREP(_m, value); \ 47 - }) 48 40 49 41 struct sp_pll { 50 42 struct clk_hw hw; ··· 307 313 u32 r0, r1, r2; 308 314 309 315 r0 = BIT(clk->bp_bit + 16); 310 - r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); 311 - r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]); 312 - r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]); 313 - r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]); 316 + r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]); 317 + r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]); 318 + r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]); 319 + r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]); 314 320 315 - r1 = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]); 321 + r1 = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]); 316 322 317 - r2 = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1); 318 - r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1); 323 + r2 = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1); 324 + r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1); 319 325 320 326 spin_lock_irqsave(&clk->lock, flags); 321 327 writel(r0, clk->reg);