Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

+3 -3

Documentation/DocBook/drm.tmpl

··· 73 73 services. 74 74 </para> 75 75 <para> 76 - The core of every DRM driver is struct drm_device. Drivers 77 - will typically statically initialize a drm_device structure, 76 + The core of every DRM driver is struct drm_driver. Drivers 77 + will typically statically initialize a drm_driver structure, 78 78 then pass it to drm_init() at load time. 79 79 </para> 80 80 ··· 84 84 <title>Driver initialization</title> 85 85 <para> 86 86 Before calling the DRM initialization routines, the driver must 87 - first create and fill out a struct drm_device structure. 87 + first create and fill out a struct drm_driver structure. 88 88 </para> 89 89 <programlisting> 90 90 static struct drm_driver driver = {

+5 -4

drivers/gpu/drm/drm_info.c

··· 283 283 #endif 284 284 285 285 mutex_lock(&dev->struct_mutex); 286 - seq_printf(m, "vma use count: %d, high_memory = %p, 0x%08llx\n", 286 + seq_printf(m, "vma use count: %d, high_memory = %pK, 0x%pK\n", 287 287 atomic_read(&dev->vma_count), 288 - high_memory, (u64)virt_to_phys(high_memory)); 288 + high_memory, (void *)virt_to_phys(high_memory)); 289 289 290 290 list_for_each_entry(pt, &dev->vmalist, head) { 291 291 vma = pt->vma; 292 292 if (!vma) 293 293 continue; 294 294 seq_printf(m, 295 - "\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx000", 296 - pt->pid, vma->vm_start, vma->vm_end, 295 + "\n%5d 0x%pK-0x%pK %c%c%c%c%c%c 0x%08lx000", 296 + pt->pid, 297 + (void *)vma->vm_start, (void *)vma->vm_end, 297 298 vma->vm_flags & VM_READ ? 'r' : '-', 298 299 vma->vm_flags & VM_WRITE ? 'w' : '-', 299 300 vma->vm_flags & VM_EXEC ? 'x' : '-',

+4 -1

drivers/gpu/drm/i915/i915_drv.c

··· 46 46 unsigned int i915_powersave = 1; 47 47 module_param_named(powersave, i915_powersave, int, 0600); 48 48 49 + unsigned int i915_enable_rc6 = 0; 50 + module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); 51 + 49 52 unsigned int i915_lvds_downclock = 0; 50 53 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); 51 54 ··· 363 360 /* Resume the modeset for every activated CRTC */ 364 361 drm_helper_resume_force_mode(dev); 365 362 366 - if (dev_priv->renderctx && dev_priv->pwrctx) 363 + if (IS_IRONLAKE_M(dev)) 367 364 ironlake_enable_rc6(dev); 368 365 } 369 366

+1

drivers/gpu/drm/i915/i915_drv.h

··· 958 958 extern unsigned int i915_powersave; 959 959 extern unsigned int i915_lvds_downclock; 960 960 extern unsigned int i915_panel_use_ssc; 961 + extern unsigned int i915_enable_rc6; 961 962 962 963 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 963 964 extern int i915_resume(struct drm_device *dev);

+3 -1

drivers/gpu/drm/i915/i915_reg.h

··· 174 174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 175 175 */ 176 176 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 177 - #define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */ 177 + #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 178 + #define MI_INVALIDATE_TLB (1<<18) 179 + #define MI_INVALIDATE_BSD (1<<7) 178 180 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 179 181 #define MI_BATCH_NON_SECURE (1) 180 182 #define MI_BATCH_NON_SECURE_I965 (1<<8)

+53 -46

drivers/gpu/drm/i915/intel_display.c

··· 5558 5558 /* Reset flags back to the 'unknown' status so that they 5559 5559 * will be correctly set on the initial modeset. 5560 5560 */ 5561 - intel_crtc->cursor_addr = 0; 5562 5561 intel_crtc->dpms_mode = -1; 5563 - intel_crtc->active = true; /* force the pipe off on setup_init_config */ 5564 5562 } 5565 5563 5566 5564 static struct drm_crtc_helper_funcs intel_helper_funcs = { ··· 5664 5666 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5665 5667 5666 5668 intel_crtc_reset(&intel_crtc->base); 5669 + intel_crtc->active = true; /* force the pipe off on setup_init_config */ 5667 5670 5668 5671 if (HAS_PCH_SPLIT(dev)) { 5669 5672 intel_helper_funcs.prepare = ironlake_crtc_prepare; ··· 6462 6463 } 6463 6464 } 6464 6465 6465 - void intel_disable_clock_gating(struct drm_device *dev) 6466 + static void ironlake_teardown_rc6(struct drm_device *dev) 6466 6467 { 6467 6468 struct drm_i915_private *dev_priv = dev->dev_private; 6468 6469 6469 6470 if (dev_priv->renderctx) { 6470 - struct drm_i915_gem_object *obj = dev_priv->renderctx; 6471 - 6472 - I915_WRITE(CCID, 0); 6473 - POSTING_READ(CCID); 6474 - 6475 - i915_gem_object_unpin(obj); 6476 - drm_gem_object_unreference(&obj->base); 6471 + i915_gem_object_unpin(dev_priv->renderctx); 6472 + drm_gem_object_unreference(&dev_priv->renderctx->base); 6477 6473 dev_priv->renderctx = NULL; 6478 6474 } 6479 6475 6480 6476 if (dev_priv->pwrctx) { 6481 - struct drm_i915_gem_object *obj = dev_priv->pwrctx; 6482 - 6483 - I915_WRITE(PWRCTXA, 0); 6484 - POSTING_READ(PWRCTXA); 6485 - 6486 - i915_gem_object_unpin(obj); 6487 - drm_gem_object_unreference(&obj->base); 6477 + i915_gem_object_unpin(dev_priv->pwrctx); 6478 + drm_gem_object_unreference(&dev_priv->pwrctx->base); 6488 6479 dev_priv->pwrctx = NULL; 6489 6480 } 6490 6481 } ··· 6483 6494 { 6484 6495 struct drm_i915_private *dev_priv = dev->dev_private; 6485 6496 6486 - /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 6487 - I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 6488 - wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 6489 - 10); 6490 - POSTING_READ(CCID); 6491 - I915_WRITE(PWRCTXA, 0); 6492 - POSTING_READ(PWRCTXA); 6493 - I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 6494 - POSTING_READ(RSTDBYCTL); 6495 - i915_gem_object_unpin(dev_priv->renderctx); 6496 - drm_gem_object_unreference(&dev_priv->renderctx->base); 6497 - dev_priv->renderctx = NULL; 6498 - i915_gem_object_unpin(dev_priv->pwrctx); 6499 - drm_gem_object_unreference(&dev_priv->pwrctx->base); 6500 - dev_priv->pwrctx = NULL; 6497 + if (I915_READ(PWRCTXA)) { 6498 + /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 6499 + I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 6500 + wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 6501 + 50); 6502 + 6503 + I915_WRITE(PWRCTXA, 0); 6504 + POSTING_READ(PWRCTXA); 6505 + 6506 + I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 6507 + POSTING_READ(RSTDBYCTL); 6508 + } 6509 + 6510 + ironlake_disable_rc6(dev); 6511 + } 6512 + 6513 + static int ironlake_setup_rc6(struct drm_device *dev) 6514 + { 6515 + struct drm_i915_private *dev_priv = dev->dev_private; 6516 + 6517 + if (dev_priv->renderctx == NULL) 6518 + dev_priv->renderctx = intel_alloc_context_page(dev); 6519 + if (!dev_priv->renderctx) 6520 + return -ENOMEM; 6521 + 6522 + if (dev_priv->pwrctx == NULL) 6523 + dev_priv->pwrctx = intel_alloc_context_page(dev); 6524 + if (!dev_priv->pwrctx) { 6525 + ironlake_teardown_rc6(dev); 6526 + return -ENOMEM; 6527 + } 6528 + 6529 + return 0; 6501 6530 } 6502 6531 6503 6532 void ironlake_enable_rc6(struct drm_device *dev) ··· 6523 6516 struct drm_i915_private *dev_priv = dev->dev_private; 6524 6517 int ret; 6525 6518 6519 + /* rc6 disabled by default due to repeated reports of hanging during 6520 + * boot and resume. 6521 + */ 6522 + if (!i915_enable_rc6) 6523 + return; 6524 + 6525 + ret = ironlake_setup_rc6(dev); 6526 + if (ret) 6527 + return; 6528 + 6526 6529 /* 6527 6530 * GPU can automatically power down the render unit if given a page 6528 6531 * to save state. 6529 6532 */ 6530 6533 ret = BEGIN_LP_RING(6); 6531 6534 if (ret) { 6532 - ironlake_disable_rc6(dev); 6535 + ironlake_teardown_rc6(dev); 6533 6536 return; 6534 6537 } 6538 + 6535 6539 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 6536 6540 OUT_RING(MI_SET_CONTEXT); 6537 6541 OUT_RING(dev_priv->renderctx->gtt_offset | ··· 6558 6540 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); 6559 6541 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 6560 6542 } 6543 + 6561 6544 6562 6545 /* Set up chip specific display functions */ 6563 6546 static void intel_init_display(struct drm_device *dev) ··· 6802 6783 if (IS_GEN6(dev)) 6803 6784 gen6_enable_rps(dev_priv); 6804 6785 6805 - if (IS_IRONLAKE_M(dev)) { 6806 - dev_priv->renderctx = intel_alloc_context_page(dev); 6807 - if (!dev_priv->renderctx) 6808 - goto skip_rc6; 6809 - dev_priv->pwrctx = intel_alloc_context_page(dev); 6810 - if (!dev_priv->pwrctx) { 6811 - i915_gem_object_unpin(dev_priv->renderctx); 6812 - drm_gem_object_unreference(&dev_priv->renderctx->base); 6813 - dev_priv->renderctx = NULL; 6814 - goto skip_rc6; 6815 - } 6786 + if (IS_IRONLAKE_M(dev)) 6816 6787 ironlake_enable_rc6(dev); 6817 - } 6818 6788 6819 - skip_rc6: 6820 6789 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 6821 6790 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 6822 6791 (unsigned long)dev);

+30 -6

drivers/gpu/drm/i915/intel_dp.c

··· 1639 1639 return 0; 1640 1640 } 1641 1641 1642 + static bool 1643 + intel_dp_detect_audio(struct drm_connector *connector) 1644 + { 1645 + struct intel_dp *intel_dp = intel_attached_dp(connector); 1646 + struct edid *edid; 1647 + bool has_audio = false; 1648 + 1649 + edid = drm_get_edid(connector, &intel_dp->adapter); 1650 + if (edid) { 1651 + has_audio = drm_detect_monitor_audio(edid); 1652 + 1653 + connector->display_info.raw_edid = NULL; 1654 + kfree(edid); 1655 + } 1656 + 1657 + return has_audio; 1658 + } 1659 + 1642 1660 static int 1643 1661 intel_dp_set_property(struct drm_connector *connector, 1644 1662 struct drm_property *property, ··· 1670 1652 return ret; 1671 1653 1672 1654 if (property == intel_dp->force_audio_property) { 1673 - if (val == intel_dp->force_audio) 1655 + int i = val; 1656 + bool has_audio; 1657 + 1658 + if (i == intel_dp->force_audio) 1674 1659 return 0; 1675 1660 1676 - intel_dp->force_audio = val; 1661 + intel_dp->force_audio = i; 1677 1662 1678 - if (val > 0 && intel_dp->has_audio) 1679 - return 0; 1680 - if (val < 0 && !intel_dp->has_audio) 1663 + if (i == 0) 1664 + has_audio = intel_dp_detect_audio(connector); 1665 + else 1666 + has_audio = i > 0; 1667 + 1668 + if (has_audio == intel_dp->has_audio) 1681 1669 return 0; 1682 1670 1683 - intel_dp->has_audio = val > 0; 1671 + intel_dp->has_audio = has_audio; 1684 1672 goto done; 1685 1673 } 1686 1674

-1

drivers/gpu/drm/i915/intel_drv.h

··· 298 298 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 299 299 u16 *blue, int regno); 300 300 extern void intel_enable_clock_gating(struct drm_device *dev); 301 - extern void intel_disable_clock_gating(struct drm_device *dev); 302 301 extern void ironlake_enable_drps(struct drm_device *dev); 303 302 extern void ironlake_disable_drps(struct drm_device *dev); 304 303 extern void gen6_enable_rps(struct drm_i915_private *dev_priv);

+33 -6

drivers/gpu/drm/i915/intel_hdmi.c

··· 251 251 &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); 252 252 } 253 253 254 + static bool 255 + intel_hdmi_detect_audio(struct drm_connector *connector) 256 + { 257 + struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 258 + struct drm_i915_private *dev_priv = connector->dev->dev_private; 259 + struct edid *edid; 260 + bool has_audio = false; 261 + 262 + edid = drm_get_edid(connector, 263 + &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); 264 + if (edid) { 265 + if (edid->input & DRM_EDID_INPUT_DIGITAL) 266 + has_audio = drm_detect_monitor_audio(edid); 267 + 268 + connector->display_info.raw_edid = NULL; 269 + kfree(edid); 270 + } 271 + 272 + return has_audio; 273 + } 274 + 254 275 static int 255 276 intel_hdmi_set_property(struct drm_connector *connector, 256 277 struct drm_property *property, ··· 285 264 return ret; 286 265 287 266 if (property == intel_hdmi->force_audio_property) { 288 - if (val == intel_hdmi->force_audio) 267 + int i = val; 268 + bool has_audio; 269 + 270 + if (i == intel_hdmi->force_audio) 289 271 return 0; 290 272 291 - intel_hdmi->force_audio = val; 273 + intel_hdmi->force_audio = i; 292 274 293 - if (val > 0 && intel_hdmi->has_audio) 294 - return 0; 295 - if (val < 0 && !intel_hdmi->has_audio) 275 + if (i == 0) 276 + has_audio = intel_hdmi_detect_audio(connector); 277 + else 278 + has_audio = i > 0; 279 + 280 + if (has_audio == intel_hdmi->has_audio) 296 281 return 0; 297 282 298 - intel_hdmi->has_audio = val > 0; 283 + intel_hdmi->has_audio = has_audio; 299 284 goto done; 300 285 } 301 286

+6 -6

drivers/gpu/drm/i915/intel_lvds.c

··· 261 261 return true; 262 262 } 263 263 264 - /* Make sure pre-965s set dither correctly */ 265 - if (INTEL_INFO(dev)->gen < 4) { 266 - if (dev_priv->lvds_dither) 267 - pfit_control |= PANEL_8TO6_DITHER_ENABLE; 268 - } 269 - 270 264 /* Native modes don't need fitting */ 271 265 if (adjusted_mode->hdisplay == mode->hdisplay && 272 266 adjusted_mode->vdisplay == mode->vdisplay) ··· 368 374 } 369 375 370 376 out: 377 + /* If not enabling scaling, be consistent and always use 0. */ 371 378 if ((pfit_control & PFIT_ENABLE) == 0) { 372 379 pfit_control = 0; 373 380 pfit_pgm_ratios = 0; 374 381 } 382 + 383 + /* Make sure pre-965 set dither correctly */ 384 + if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) 385 + pfit_control |= PANEL_8TO6_DITHER_ENABLE; 386 + 375 387 if (pfit_control != intel_lvds->pfit_control || 376 388 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { 377 389 intel_lvds->pfit_control = pfit_control;

+16 -10

drivers/gpu/drm/i915/intel_ringbuffer.c

··· 1059 1059 } 1060 1060 1061 1061 static int gen6_ring_flush(struct intel_ring_buffer *ring, 1062 - u32 invalidate_domains, 1063 - u32 flush_domains) 1062 + u32 invalidate, u32 flush) 1064 1063 { 1064 + uint32_t cmd; 1065 1065 int ret; 1066 1066 1067 - if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) 1067 + if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0) 1068 1068 return 0; 1069 1069 1070 1070 ret = intel_ring_begin(ring, 4); 1071 1071 if (ret) 1072 1072 return ret; 1073 1073 1074 - intel_ring_emit(ring, MI_FLUSH_DW); 1074 + cmd = MI_FLUSH_DW; 1075 + if (invalidate & I915_GEM_GPU_DOMAINS) 1076 + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; 1077 + intel_ring_emit(ring, cmd); 1075 1078 intel_ring_emit(ring, 0); 1076 1079 intel_ring_emit(ring, 0); 1077 - intel_ring_emit(ring, 0); 1080 + intel_ring_emit(ring, MI_NOOP); 1078 1081 intel_ring_advance(ring); 1079 1082 return 0; 1080 1083 } ··· 1233 1230 } 1234 1231 1235 1232 static int blt_ring_flush(struct intel_ring_buffer *ring, 1236 - u32 invalidate_domains, 1237 - u32 flush_domains) 1233 + u32 invalidate, u32 flush) 1238 1234 { 1235 + uint32_t cmd; 1239 1236 int ret; 1240 1237 1241 - if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) 1238 + if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0) 1242 1239 return 0; 1243 1240 1244 1241 ret = blt_ring_begin(ring, 4); 1245 1242 if (ret) 1246 1243 return ret; 1247 1244 1248 - intel_ring_emit(ring, MI_FLUSH_DW); 1245 + cmd = MI_FLUSH_DW; 1246 + if (invalidate & I915_GEM_DOMAIN_RENDER) 1247 + cmd |= MI_INVALIDATE_TLB; 1248 + intel_ring_emit(ring, cmd); 1249 1249 intel_ring_emit(ring, 0); 1250 1250 intel_ring_emit(ring, 0); 1251 - intel_ring_emit(ring, 0); 1251 + intel_ring_emit(ring, MI_NOOP); 1252 1252 intel_ring_advance(ring); 1253 1253 return 0; 1254 1254 }

+55 -11

drivers/gpu/drm/i915/intel_sdvo.c

··· 46 46 SDVO_TV_MASK) 47 47 48 48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 49 + #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 49 50 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 50 51 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 51 52 ··· 1360 1359 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1361 1360 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1362 1361 } 1363 - } 1362 + } else 1363 + status = connector_status_disconnected; 1364 1364 connector->display_info.raw_edid = NULL; 1365 1365 kfree(edid); 1366 1366 } ··· 1409 1407 1410 1408 if ((intel_sdvo_connector->output_flag & response) == 0) 1411 1409 ret = connector_status_disconnected; 1412 - else if (response & SDVO_TMDS_MASK) 1410 + else if (IS_TMDS(intel_sdvo_connector)) 1413 1411 ret = intel_sdvo_hdmi_sink_detect(connector); 1414 - else 1415 - ret = connector_status_connected; 1412 + else { 1413 + struct edid *edid; 1414 + 1415 + /* if we have an edid check it matches the connection */ 1416 + edid = intel_sdvo_get_edid(connector); 1417 + if (edid == NULL) 1418 + edid = intel_sdvo_get_analog_edid(connector); 1419 + if (edid != NULL) { 1420 + if (edid->input & DRM_EDID_INPUT_DIGITAL) 1421 + ret = connector_status_disconnected; 1422 + else 1423 + ret = connector_status_connected; 1424 + connector->display_info.raw_edid = NULL; 1425 + kfree(edid); 1426 + } else 1427 + ret = connector_status_connected; 1428 + } 1416 1429 1417 1430 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1418 1431 if (ret == connector_status_connected) { ··· 1463 1446 edid = intel_sdvo_get_analog_edid(connector); 1464 1447 1465 1448 if (edid != NULL) { 1466 - if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1449 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1450 + bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1451 + bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector); 1452 + 1453 + if (connector_is_digital == monitor_is_digital) { 1467 1454 drm_mode_connector_update_edid_property(connector, edid); 1468 1455 drm_add_edid_modes(connector, edid); 1469 1456 } 1457 + 1470 1458 connector->display_info.raw_edid = NULL; 1471 1459 kfree(edid); 1472 1460 } ··· 1690 1668 kfree(connector); 1691 1669 } 1692 1670 1671 + static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1672 + { 1673 + struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1674 + struct edid *edid; 1675 + bool has_audio = false; 1676 + 1677 + if (!intel_sdvo->is_hdmi) 1678 + return false; 1679 + 1680 + edid = intel_sdvo_get_edid(connector); 1681 + if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1682 + has_audio = drm_detect_monitor_audio(edid); 1683 + 1684 + return has_audio; 1685 + } 1686 + 1693 1687 static int 1694 1688 intel_sdvo_set_property(struct drm_connector *connector, 1695 1689 struct drm_property *property, ··· 1722 1684 return ret; 1723 1685 1724 1686 if (property == intel_sdvo_connector->force_audio_property) { 1725 - if (val == intel_sdvo_connector->force_audio) 1687 + int i = val; 1688 + bool has_audio; 1689 + 1690 + if (i == intel_sdvo_connector->force_audio) 1726 1691 return 0; 1727 1692 1728 - intel_sdvo_connector->force_audio = val; 1693 + intel_sdvo_connector->force_audio = i; 1729 1694 1730 - if (val > 0 && intel_sdvo->has_hdmi_audio) 1731 - return 0; 1732 - if (val < 0 && !intel_sdvo->has_hdmi_audio) 1695 + if (i == 0) 1696 + has_audio = intel_sdvo_detect_hdmi_audio(connector); 1697 + else 1698 + has_audio = i > 0; 1699 + 1700 + if (has_audio == intel_sdvo->has_hdmi_audio) 1733 1701 return 0; 1734 1702 1735 - intel_sdvo->has_hdmi_audio = val > 0; 1703 + intel_sdvo->has_hdmi_audio = has_audio; 1736 1704 goto done; 1737 1705 } 1738 1706

+30 -13

drivers/gpu/drm/i915/intel_tv.c

··· 1234 1234 * \return false if TV is disconnected. 1235 1235 */ 1236 1236 static int 1237 - intel_tv_detect_type (struct intel_tv *intel_tv) 1237 + intel_tv_detect_type (struct intel_tv *intel_tv, 1238 + struct drm_connector *connector) 1238 1239 { 1239 1240 struct drm_encoder *encoder = &intel_tv->base.base; 1240 1241 struct drm_device *dev = encoder->dev; ··· 1246 1245 int type; 1247 1246 1248 1247 /* Disable TV interrupts around load detect or we'll recurse */ 1249 - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1250 - i915_disable_pipestat(dev_priv, 0, 1251 - PIPE_HOTPLUG_INTERRUPT_ENABLE | 1252 - PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); 1253 - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1248 + if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1249 + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1250 + i915_disable_pipestat(dev_priv, 0, 1251 + PIPE_HOTPLUG_INTERRUPT_ENABLE | 1252 + PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); 1253 + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1254 + } 1254 1255 1255 1256 save_tv_dac = tv_dac = I915_READ(TV_DAC); 1256 1257 save_tv_ctl = tv_ctl = I915_READ(TV_CTL); ··· 1305 1302 I915_WRITE(TV_CTL, save_tv_ctl); 1306 1303 1307 1304 /* Restore interrupt config */ 1308 - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1309 - i915_enable_pipestat(dev_priv, 0, 1310 - PIPE_HOTPLUG_INTERRUPT_ENABLE | 1311 - PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); 1312 - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1305 + if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1306 + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1307 + i915_enable_pipestat(dev_priv, 0, 1308 + PIPE_HOTPLUG_INTERRUPT_ENABLE | 1309 + PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); 1310 + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1311 + } 1313 1312 1314 1313 return type; 1315 1314 } ··· 1361 1356 drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V); 1362 1357 1363 1358 if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) { 1364 - type = intel_tv_detect_type(intel_tv); 1359 + type = intel_tv_detect_type(intel_tv, connector); 1365 1360 } else if (force) { 1366 1361 struct drm_crtc *crtc; 1367 1362 int dpms_mode; ··· 1369 1364 crtc = intel_get_load_detect_pipe(&intel_tv->base, connector, 1370 1365 &mode, &dpms_mode); 1371 1366 if (crtc) { 1372 - type = intel_tv_detect_type(intel_tv); 1367 + type = intel_tv_detect_type(intel_tv, connector); 1373 1368 intel_release_load_detect_pipe(&intel_tv->base, connector, 1374 1369 dpms_mode); 1375 1370 } else ··· 1662 1657 1663 1658 intel_encoder = &intel_tv->base; 1664 1659 connector = &intel_connector->base; 1660 + 1661 + /* The documentation, for the older chipsets at least, recommend 1662 + * using a polling method rather than hotplug detection for TVs. 1663 + * This is because in order to perform the hotplug detection, the PLLs 1664 + * for the TV must be kept alive increasing power drain and starving 1665 + * bandwidth from other encoders. Notably for instance, it causes 1666 + * pipe underruns on Crestline when this encoder is supposedly idle. 1667 + * 1668 + * More recent chipsets favour HDMI rather than integrated S-Video. 1669 + */ 1670 + connector->polled = 1671 + DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1665 1672 1666 1673 drm_connector_init(dev, connector, &intel_tv_connector_funcs, 1667 1674 DRM_MODE_CONNECTOR_SVIDEO);

+40 -58

drivers/gpu/drm/radeon/atombios_crtc.c

··· 48 48 49 49 switch (radeon_crtc->rmx_type) { 50 50 case RMX_CENTER: 51 - args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 52 - args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 53 - args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 54 - args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 51 + args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 52 + args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 + args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 54 + args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 55 break; 56 56 case RMX_ASPECT: 57 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58 58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59 59 60 60 if (a1 > a2) { 61 - args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 62 - args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 61 + args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 62 + args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 63 } else if (a2 > a1) { 64 - args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 65 - args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 64 + args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 65 + args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 66 } 67 67 break; 68 68 case RMX_FULL: 69 69 default: 70 - args.usOverscanRight = radeon_crtc->h_border; 71 - args.usOverscanLeft = radeon_crtc->h_border; 72 - args.usOverscanBottom = radeon_crtc->v_border; 73 - args.usOverscanTop = radeon_crtc->v_border; 70 + args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 71 + args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 72 + args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 73 + args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 74 74 break; 75 75 } 76 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); ··· 419 419 memset(&args, 0, sizeof(args)); 420 420 421 421 if (ASIC_IS_DCE5(rdev)) { 422 - args.v3.usSpreadSpectrumAmountFrac = 0; 422 + args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 423 423 args.v3.ucSpreadSpectrumType = ss->type; 424 424 switch (pll_id) { 425 425 case ATOM_PPLL1: 426 426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 427 - args.v3.usSpreadSpectrumAmount = ss->amount; 428 - args.v3.usSpreadSpectrumStep = ss->step; 427 + args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 428 + args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 429 429 break; 430 430 case ATOM_PPLL2: 431 431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 432 - args.v3.usSpreadSpectrumAmount = ss->amount; 433 - args.v3.usSpreadSpectrumStep = ss->step; 432 + args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 433 + args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 434 434 break; 435 435 case ATOM_DCPLL: 436 436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 437 - args.v3.usSpreadSpectrumAmount = 0; 438 - args.v3.usSpreadSpectrumStep = 0; 437 + args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); 438 + args.v3.usSpreadSpectrumStep = cpu_to_le16(0); 439 439 break; 440 440 case ATOM_PPLL_INVALID: 441 441 return; ··· 447 447 switch (pll_id) { 448 448 case ATOM_PPLL1: 449 449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 450 - args.v2.usSpreadSpectrumAmount = ss->amount; 451 - args.v2.usSpreadSpectrumStep = ss->step; 450 + args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 451 + args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 452 452 break; 453 453 case ATOM_PPLL2: 454 454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 455 - args.v2.usSpreadSpectrumAmount = ss->amount; 456 - args.v2.usSpreadSpectrumStep = ss->step; 455 + args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 456 + args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 457 457 break; 458 458 case ATOM_DCPLL: 459 459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 460 - args.v2.usSpreadSpectrumAmount = 0; 461 - args.v2.usSpreadSpectrumStep = 0; 460 + args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); 461 + args.v2.usSpreadSpectrumStep = cpu_to_le16(0); 462 462 break; 463 463 case ATOM_PPLL_INVALID: 464 464 return; ··· 538 538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 539 539 else 540 540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 541 - 542 541 } 543 542 544 543 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ··· 554 555 dp_clock = dig_connector->dp_clock; 555 556 } 556 557 } 557 - /* this might work properly with the new pll algo */ 558 - #if 0 /* doesn't work properly on some laptops */ 558 + 559 559 /* use recommended ref_div for ss */ 560 560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 561 + pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 561 562 if (ss_enabled) { 562 563 if (ss->refdiv) { 563 564 pll->flags |= RADEON_PLL_USE_REF_DIV; 564 565 pll->reference_div = ss->refdiv; 566 + if (ASIC_IS_AVIVO(rdev)) 567 + pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 565 568 } 566 569 } 567 570 } 568 - #endif 571 + 569 572 if (ASIC_IS_AVIVO(rdev)) { 570 573 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 571 574 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 572 575 adjusted_clock = mode->clock * 2; 573 576 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 574 577 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 575 - /* rv515 needs more testing with this option */ 576 - if (rdev->family != CHIP_RV515) { 577 - if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 578 - pll->flags |= RADEON_PLL_IS_LCD; 579 - } 578 + if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 579 + pll->flags |= RADEON_PLL_IS_LCD; 580 580 } else { 581 581 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 582 582 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; ··· 719 721 * SetPixelClock provides the dividers 720 722 */ 721 723 args.v5.ucCRTC = ATOM_CRTC_INVALID; 722 - args.v5.usPixelClock = dispclk; 724 + args.v5.usPixelClock = cpu_to_le16(dispclk); 723 725 args.v5.ucPpll = ATOM_DCPLL; 724 726 break; 725 727 case 6: 726 728 /* if the default dcpll clock is specified, 727 729 * SetPixelClock provides the dividers 728 730 */ 729 - args.v6.ulDispEngClkFreq = dispclk; 731 + args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 730 732 args.v6.ucPpll = ATOM_DCPLL; 731 733 break; 732 734 default: ··· 955 957 /* adjust pixel clock as needed */ 956 958 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); 957 959 958 - /* rv515 seems happier with the old algo */ 959 - if (rdev->family == CHIP_RV515) 960 - radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 961 - &ref_div, &post_div); 962 - else if (ASIC_IS_AVIVO(rdev)) 960 + if (ASIC_IS_AVIVO(rdev)) 963 961 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 964 962 &ref_div, &post_div); 965 963 else ··· 989 995 } 990 996 } 991 997 992 - static int evergreen_crtc_do_set_base(struct drm_crtc *crtc, 993 - struct drm_framebuffer *fb, 994 - int x, int y, int atomic) 998 + static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 999 + struct drm_framebuffer *fb, 1000 + int x, int y, int atomic) 995 1001 { 996 1002 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 997 1003 struct drm_device *dev = crtc->dev; ··· 1130 1136 (x << 16) | y); 1131 1137 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1132 1138 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1133 - 1134 - if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 1135 - WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1136 - EVERGREEN_INTERLEAVE_EN); 1137 - else 1138 - WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1139 1139 1140 1140 if (!atomic && fb && fb != crtc->fb) { 1141 1141 radeon_fb = to_radeon_framebuffer(fb); ··· 1288 1300 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1289 1301 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1290 1302 1291 - if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 1292 - WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1293 - AVIVO_D1MODE_INTERLEAVE_EN); 1294 - else 1295 - WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1296 - 1297 1303 if (!atomic && fb && fb != crtc->fb) { 1298 1304 radeon_fb = to_radeon_framebuffer(fb); 1299 1305 rbo = radeon_fb->obj->driver_private; ··· 1311 1329 struct radeon_device *rdev = dev->dev_private; 1312 1330 1313 1331 if (ASIC_IS_DCE4(rdev)) 1314 - return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0); 1332 + return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1315 1333 else if (ASIC_IS_AVIVO(rdev)) 1316 1334 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1317 1335 else ··· 1326 1344 struct radeon_device *rdev = dev->dev_private; 1327 1345 1328 1346 if (ASIC_IS_DCE4(rdev)) 1329 - return evergreen_crtc_do_set_base(crtc, fb, x, y, 1); 1347 + return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1330 1348 else if (ASIC_IS_AVIVO(rdev)) 1331 1349 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1332 1350 else

+17 -5

drivers/gpu/drm/radeon/evergreen.c

··· 1192 1192 radeon_ring_write(rdev, 1); 1193 1193 /* FIXME: implement */ 1194 1194 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1195 - radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); 1195 + radeon_ring_write(rdev, 1196 + #ifdef __BIG_ENDIAN 1197 + (2 << 0) | 1198 + #endif 1199 + (ib->gpu_addr & 0xFFFFFFFC)); 1196 1200 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 1197 1201 radeon_ring_write(rdev, ib->length_dw); 1198 1202 } ··· 1211 1207 return -EINVAL; 1212 1208 1213 1209 r700_cp_stop(rdev); 1214 - WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 1210 + WREG32(CP_RB_CNTL, 1211 + #ifdef __BIG_ENDIAN 1212 + BUF_SWAP_32BIT | 1213 + #endif 1214 + RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1215 1215 1216 1216 fw_data = (const __be32 *)rdev->pfp_fw->data; 1217 1217 WREG32(CP_PFP_UCODE_ADDR, 0); ··· 1334 1326 WREG32(CP_RB_WPTR, 0); 1335 1327 1336 1328 /* set the wb address wether it's enabled or not */ 1337 - WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 1329 + WREG32(CP_RB_RPTR_ADDR, 1330 + #ifdef __BIG_ENDIAN 1331 + RB_RPTR_SWAP(2) | 1332 + #endif 1333 + ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 1338 1334 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1339 1335 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1340 1336 ··· 2639 2627 while (rptr != wptr) { 2640 2628 /* wptr/rptr are in bytes! */ 2641 2629 ring_index = rptr / 4; 2642 - src_id = rdev->ih.ring[ring_index] & 0xff; 2643 - src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; 2630 + src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 2631 + src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 2644 2632 2645 2633 switch (src_id) { 2646 2634 case 1: /* D1 vblank/vline */

+16 -7

drivers/gpu/drm/radeon/evergreen_blit_kms.c

··· 55 55 if (h < 8) 56 56 h = 8; 57 57 58 - cb_color_info = ((format << 2) | (1 << 24)); 58 + cb_color_info = ((format << 2) | (1 << 24) | (1 << 8)); 59 59 pitch = (w / 8) - 1; 60 60 slice = ((w * h) / 64) - 1; 61 61 ··· 133 133 134 134 /* high addr, stride */ 135 135 sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); 136 + #ifdef __BIG_ENDIAN 137 + sq_vtx_constant_word2 |= (2 << 30); 138 + #endif 136 139 /* xyzw swizzles */ 137 140 sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12); 138 141 ··· 176 173 sq_tex_resource_word0 = (1 << 0); /* 2D */ 177 174 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | 178 175 ((w - 1) << 18)); 179 - sq_tex_resource_word1 = ((h - 1) << 0); 176 + sq_tex_resource_word1 = ((h - 1) << 0) | (1 << 28); 180 177 /* xyzw swizzles */ 181 178 sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25); 182 179 ··· 224 221 radeon_ring_write(rdev, DI_PT_RECTLIST); 225 222 226 223 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); 227 - radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); 224 + radeon_ring_write(rdev, 225 + #ifdef __BIG_ENDIAN 226 + (2 << 2) | 227 + #endif 228 + DI_INDEX_SIZE_16_BIT); 228 229 229 230 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); 230 231 radeon_ring_write(rdev, 1); ··· 548 541 int evergreen_blit_init(struct radeon_device *rdev) 549 542 { 550 543 u32 obj_size; 551 - int r, dwords; 544 + int i, r, dwords; 552 545 void *ptr; 553 546 u32 packet2s[16]; 554 547 int num_packet2s = 0; ··· 564 557 565 558 dwords = rdev->r600_blit.state_len; 566 559 while (dwords & 0xf) { 567 - packet2s[num_packet2s++] = PACKET2(0); 560 + packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); 568 561 dwords++; 569 562 } 570 563 ··· 605 598 if (num_packet2s) 606 599 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), 607 600 packet2s, num_packet2s * 4); 608 - memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4); 609 - memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4); 601 + for (i = 0; i < evergreen_vs_size; i++) 602 + *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); 603 + for (i = 0; i < evergreen_ps_size; i++) 604 + *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); 610 605 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 611 606 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 612 607

+8

drivers/gpu/drm/radeon/evergreen_blit_shaders.c

··· 311 311 0x00000000, 312 312 0x3c000000, 313 313 0x67961001, 314 + #ifdef __BIG_ENDIAN 315 + 0x000a0000, 316 + #else 314 317 0x00080000, 318 + #endif 315 319 0x00000000, 316 320 0x1c000000, 317 321 0x67961000, 322 + #ifdef __BIG_ENDIAN 323 + 0x00020008, 324 + #else 318 325 0x00000008, 326 + #endif 319 327 0x00000000, 320 328 }; 321 329

+1

drivers/gpu/drm/radeon/evergreend.h

··· 98 98 #define BUF_SWAP_32BIT (2 << 16) 99 99 #define CP_RB_RPTR 0x8700 100 100 #define CP_RB_RPTR_ADDR 0xC10C 101 + #define RB_RPTR_SWAP(x) ((x) << 0) 101 102 #define CP_RB_RPTR_ADDR_HI 0xC110 102 103 #define CP_RB_RPTR_WR 0xC108 103 104 #define CP_RB_WPTR 0xC114

+4 -1

drivers/gpu/drm/radeon/mkregtable.c

··· 673 673 last_reg = strtol(last_reg_s, NULL, 16); 674 674 675 675 do { 676 - if (fgets(buf, 1024, file) == NULL) 676 + if (fgets(buf, 1024, file) == NULL) { 677 + fclose(file); 677 678 return -1; 679 + } 678 680 len = strlen(buf); 679 681 if (ftell(file) == end) 680 682 done = 1; ··· 687 685 fprintf(stderr, 688 686 "Error matching regular expression %d in %s\n", 689 687 r, filename); 688 + fclose(file); 690 689 return -1; 691 690 } else { 692 691 buf[match[0].rm_eo] = 0;

+59 -4

drivers/gpu/drm/radeon/r100.c

··· 1427 1427 } 1428 1428 track->zb.robj = reloc->robj; 1429 1429 track->zb.offset = idx_value; 1430 + track->zb_dirty = true; 1430 1431 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1431 1432 break; 1432 1433 case RADEON_RB3D_COLOROFFSET: ··· 1440 1439 } 1441 1440 track->cb[0].robj = reloc->robj; 1442 1441 track->cb[0].offset = idx_value; 1442 + track->cb_dirty = true; 1443 1443 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1444 1444 break; 1445 1445 case RADEON_PP_TXOFFSET_0: ··· 1456 1454 } 1457 1455 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1458 1456 track->textures[i].robj = reloc->robj; 1457 + track->tex_dirty = true; 1459 1458 break; 1460 1459 case RADEON_PP_CUBIC_OFFSET_T0_0: 1461 1460 case RADEON_PP_CUBIC_OFFSET_T0_1: ··· 1474 1471 track->textures[0].cube_info[i].offset = idx_value; 1475 1472 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1476 1473 track->textures[0].cube_info[i].robj = reloc->robj; 1474 + track->tex_dirty = true; 1477 1475 break; 1478 1476 case RADEON_PP_CUBIC_OFFSET_T1_0: 1479 1477 case RADEON_PP_CUBIC_OFFSET_T1_1: ··· 1492 1488 track->textures[1].cube_info[i].offset = idx_value; 1493 1489 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1494 1490 track->textures[1].cube_info[i].robj = reloc->robj; 1491 + track->tex_dirty = true; 1495 1492 break; 1496 1493 case RADEON_PP_CUBIC_OFFSET_T2_0: 1497 1494 case RADEON_PP_CUBIC_OFFSET_T2_1: ··· 1510 1505 track->textures[2].cube_info[i].offset = idx_value; 1511 1506 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1512 1507 track->textures[2].cube_info[i].robj = reloc->robj; 1508 + track->tex_dirty = true; 1513 1509 break; 1514 1510 case RADEON_RE_WIDTH_HEIGHT: 1515 1511 track->maxy = ((idx_value >> 16) & 0x7FF); 1512 + track->cb_dirty = true; 1513 + track->zb_dirty = true; 1516 1514 break; 1517 1515 case RADEON_RB3D_COLORPITCH: 1518 1516 r = r100_cs_packet_next_reloc(p, &reloc); ··· 1536 1528 ib[idx] = tmp; 1537 1529 1538 1530 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1531 + track->cb_dirty = true; 1539 1532 break; 1540 1533 case RADEON_RB3D_DEPTHPITCH: 1541 1534 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1535 + track->zb_dirty = true; 1542 1536 break; 1543 1537 case RADEON_RB3D_CNTL: 1544 1538 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { ··· 1565 1555 return -EINVAL; 1566 1556 } 1567 1557 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1558 + track->cb_dirty = true; 1559 + track->zb_dirty = true; 1568 1560 break; 1569 1561 case RADEON_RB3D_ZSTENCILCNTL: 1570 1562 switch (idx_value & 0xf) { ··· 1584 1572 default: 1585 1573 break; 1586 1574 } 1575 + track->zb_dirty = true; 1587 1576 break; 1588 1577 case RADEON_RB3D_ZPASS_ADDR: 1589 1578 r = r100_cs_packet_next_reloc(p, &reloc); ··· 1601 1588 uint32_t temp = idx_value >> 4; 1602 1589 for (i = 0; i < track->num_texture; i++) 1603 1590 track->textures[i].enabled = !!(temp & (1 << i)); 1591 + track->tex_dirty = true; 1604 1592 } 1605 1593 break; 1606 1594 case RADEON_SE_VF_CNTL: ··· 1616 1602 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1617 1603 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1618 1604 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1605 + track->tex_dirty = true; 1619 1606 break; 1620 1607 case RADEON_PP_TEX_PITCH_0: 1621 1608 case RADEON_PP_TEX_PITCH_1: 1622 1609 case RADEON_PP_TEX_PITCH_2: 1623 1610 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1624 1611 track->textures[i].pitch = idx_value + 32; 1612 + track->tex_dirty = true; 1625 1613 break; 1626 1614 case RADEON_PP_TXFILTER_0: 1627 1615 case RADEON_PP_TXFILTER_1: ··· 1637 1621 tmp = (idx_value >> 27) & 0x7; 1638 1622 if (tmp == 2 || tmp == 6) 1639 1623 track->textures[i].roundup_h = false; 1624 + track->tex_dirty = true; 1640 1625 break; 1641 1626 case RADEON_PP_TXFORMAT_0: 1642 1627 case RADEON_PP_TXFORMAT_1: ··· 1690 1673 } 1691 1674 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1692 1675 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1676 + track->tex_dirty = true; 1693 1677 break; 1694 1678 case RADEON_PP_CUBIC_FACES_0: 1695 1679 case RADEON_PP_CUBIC_FACES_1: ··· 1701 1683 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1702 1684 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1703 1685 } 1686 + track->tex_dirty = true; 1704 1687 break; 1705 1688 default: 1706 1689 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", ··· 3337 3318 unsigned long size; 3338 3319 unsigned prim_walk; 3339 3320 unsigned nverts; 3340 - unsigned num_cb = track->num_cb; 3321 + unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 3341 3322 3342 - if (!track->zb_cb_clear && !track->color_channel_mask && 3323 + if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 3343 3324 !track->blend_read_enable) 3344 3325 num_cb = 0; 3345 3326 ··· 3360 3341 return -EINVAL; 3361 3342 } 3362 3343 } 3363 - if (track->z_enabled) { 3344 + track->cb_dirty = false; 3345 + 3346 + if (track->zb_dirty && track->z_enabled) { 3364 3347 if (track->zb.robj == NULL) { 3365 3348 DRM_ERROR("[drm] No buffer for z buffer !\n"); 3366 3349 return -EINVAL; ··· 3379 3358 return -EINVAL; 3380 3359 } 3381 3360 } 3361 + track->zb_dirty = false; 3362 + 3363 + if (track->aa_dirty && track->aaresolve) { 3364 + if (track->aa.robj == NULL) { 3365 + DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 3366 + return -EINVAL; 3367 + } 3368 + /* I believe the format comes from colorbuffer0. */ 3369 + size = track->aa.pitch * track->cb[0].cpp * track->maxy; 3370 + size += track->aa.offset; 3371 + if (size > radeon_bo_size(track->aa.robj)) { 3372 + DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 3373 + "(need %lu have %lu) !\n", i, size, 3374 + radeon_bo_size(track->aa.robj)); 3375 + DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 3376 + i, track->aa.pitch, track->cb[0].cpp, 3377 + track->aa.offset, track->maxy); 3378 + return -EINVAL; 3379 + } 3380 + } 3381 + track->aa_dirty = false; 3382 + 3382 3383 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3383 3384 if (track->vap_vf_cntl & (1 << 14)) { 3384 3385 nverts = track->vap_alt_nverts; ··· 3460 3417 prim_walk); 3461 3418 return -EINVAL; 3462 3419 } 3463 - return r100_cs_track_texture_check(rdev, track); 3420 + 3421 + if (track->tex_dirty) { 3422 + track->tex_dirty = false; 3423 + return r100_cs_track_texture_check(rdev, track); 3424 + } 3425 + return 0; 3464 3426 } 3465 3427 3466 3428 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3467 3429 { 3468 3430 unsigned i, face; 3431 + 3432 + track->cb_dirty = true; 3433 + track->zb_dirty = true; 3434 + track->tex_dirty = true; 3435 + track->aa_dirty = true; 3469 3436 3470 3437 if (rdev->family < CHIP_R300) { 3471 3438 track->num_cb = 1; ··· 3490 3437 track->num_texture = 16; 3491 3438 track->maxy = 4096; 3492 3439 track->separate_cube = 0; 3440 + track->aaresolve = true; 3441 + track->aa.robj = NULL; 3493 3442 } 3494 3443 3495 3444 for (i = 0; i < track->num_cb; i++) {

+6 -7

drivers/gpu/drm/radeon/r100_track.h

··· 52 52 unsigned compress_format; 53 53 }; 54 54 55 - struct r100_cs_track_limits { 56 - unsigned num_cb; 57 - unsigned num_texture; 58 - unsigned max_levels; 59 - }; 60 - 61 55 struct r100_cs_track { 62 - struct radeon_device *rdev; 63 56 unsigned num_cb; 64 57 unsigned num_texture; 65 58 unsigned maxy; ··· 66 73 struct r100_cs_track_array arrays[11]; 67 74 struct r100_cs_track_cb cb[R300_MAX_CB]; 68 75 struct r100_cs_track_cb zb; 76 + struct r100_cs_track_cb aa; 69 77 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 70 78 bool z_enabled; 71 79 bool separate_cube; 72 80 bool zb_cb_clear; 73 81 bool blend_read_enable; 82 + bool cb_dirty; 83 + bool zb_dirty; 84 + bool tex_dirty; 85 + bool aa_dirty; 86 + bool aaresolve; 74 87 }; 75 88 76 89 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);

+18

drivers/gpu/drm/radeon/r200.c

··· 184 184 } 185 185 track->zb.robj = reloc->robj; 186 186 track->zb.offset = idx_value; 187 + track->zb_dirty = true; 187 188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 188 189 break; 189 190 case RADEON_RB3D_COLOROFFSET: ··· 197 196 } 198 197 track->cb[0].robj = reloc->robj; 199 198 track->cb[0].offset = idx_value; 199 + track->cb_dirty = true; 200 200 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 201 201 break; 202 202 case R200_PP_TXOFFSET_0: ··· 216 214 } 217 215 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 218 216 track->textures[i].robj = reloc->robj; 217 + track->tex_dirty = true; 219 218 break; 220 219 case R200_PP_CUBIC_OFFSET_F1_0: 221 220 case R200_PP_CUBIC_OFFSET_F2_0: ··· 260 257 track->textures[i].cube_info[face - 1].offset = idx_value; 261 258 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 262 259 track->textures[i].cube_info[face - 1].robj = reloc->robj; 260 + track->tex_dirty = true; 263 261 break; 264 262 case RADEON_RE_WIDTH_HEIGHT: 265 263 track->maxy = ((idx_value >> 16) & 0x7FF); 264 + track->cb_dirty = true; 265 + track->zb_dirty = true; 266 266 break; 267 267 case RADEON_RB3D_COLORPITCH: 268 268 r = r100_cs_packet_next_reloc(p, &reloc); ··· 286 280 ib[idx] = tmp; 287 281 288 282 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 283 + track->cb_dirty = true; 289 284 break; 290 285 case RADEON_RB3D_DEPTHPITCH: 291 286 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 287 + track->zb_dirty = true; 292 288 break; 293 289 case RADEON_RB3D_CNTL: 294 290 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { ··· 320 312 } 321 313 322 314 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 315 + track->cb_dirty = true; 316 + track->zb_dirty = true; 323 317 break; 324 318 case RADEON_RB3D_ZSTENCILCNTL: 325 319 switch (idx_value & 0xf) { ··· 339 329 default: 340 330 break; 341 331 } 332 + track->zb_dirty = true; 342 333 break; 343 334 case RADEON_RB3D_ZPASS_ADDR: 344 335 r = r100_cs_packet_next_reloc(p, &reloc); ··· 356 345 uint32_t temp = idx_value >> 4; 357 346 for (i = 0; i < track->num_texture; i++) 358 347 track->textures[i].enabled = !!(temp & (1 << i)); 348 + track->tex_dirty = true; 359 349 } 360 350 break; 361 351 case RADEON_SE_VF_CNTL: ··· 381 369 i = (reg - R200_PP_TXSIZE_0) / 32; 382 370 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 383 371 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 372 + track->tex_dirty = true; 384 373 break; 385 374 case R200_PP_TXPITCH_0: 386 375 case R200_PP_TXPITCH_1: ··· 391 378 case R200_PP_TXPITCH_5: 392 379 i = (reg - R200_PP_TXPITCH_0) / 32; 393 380 track->textures[i].pitch = idx_value + 32; 381 + track->tex_dirty = true; 394 382 break; 395 383 case R200_PP_TXFILTER_0: 396 384 case R200_PP_TXFILTER_1: ··· 408 394 tmp = (idx_value >> 27) & 0x7; 409 395 if (tmp == 2 || tmp == 6) 410 396 track->textures[i].roundup_h = false; 397 + track->tex_dirty = true; 411 398 break; 412 399 case R200_PP_TXMULTI_CTL_0: 413 400 case R200_PP_TXMULTI_CTL_1: ··· 447 432 track->textures[i].tex_coord_type = 1; 448 433 break; 449 434 } 435 + track->tex_dirty = true; 450 436 break; 451 437 case R200_PP_TXFORMAT_0: 452 438 case R200_PP_TXFORMAT_1: ··· 504 488 } 505 489 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 506 490 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 491 + track->tex_dirty = true; 507 492 break; 508 493 case R200_PP_CUBIC_FACES_0: 509 494 case R200_PP_CUBIC_FACES_1: ··· 518 501 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 519 502 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 520 503 } 504 + track->tex_dirty = true; 521 505 break; 522 506 default: 523 507 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",

+40 -2

drivers/gpu/drm/radeon/r300.c

··· 667 667 } 668 668 track->cb[i].robj = reloc->robj; 669 669 track->cb[i].offset = idx_value; 670 + track->cb_dirty = true; 670 671 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 671 672 break; 672 673 case R300_ZB_DEPTHOFFSET: ··· 680 679 } 681 680 track->zb.robj = reloc->robj; 682 681 track->zb.offset = idx_value; 682 + track->zb_dirty = true; 683 683 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 684 684 break; 685 685 case R300_TX_OFFSET_0: ··· 719 717 tmp |= tile_flags; 720 718 ib[idx] = tmp; 721 719 track->textures[i].robj = reloc->robj; 720 + track->tex_dirty = true; 722 721 break; 723 722 /* Tracked registers */ 724 723 case 0x2084: ··· 746 743 if (p->rdev->family < CHIP_RV515) { 747 744 track->maxy -= 1440; 748 745 } 746 + track->cb_dirty = true; 747 + track->zb_dirty = true; 749 748 break; 750 749 case 0x4E00: 751 750 /* RB3D_CCTL */ ··· 757 752 return -EINVAL; 758 753 } 759 754 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 755 + track->cb_dirty = true; 760 756 break; 761 757 case 0x4E38: 762 758 case 0x4E3C: ··· 820 814 ((idx_value >> 21) & 0xF)); 821 815 return -EINVAL; 822 816 } 817 + track->cb_dirty = true; 823 818 break; 824 819 case 0x4F00: 825 820 /* ZB_CNTL */ ··· 829 822 } else { 830 823 track->z_enabled = false; 831 824 } 825 + track->zb_dirty = true; 832 826 break; 833 827 case 0x4F10: 834 828 /* ZB_FORMAT */ ··· 846 838 (idx_value & 0xF)); 847 839 return -EINVAL; 848 840 } 841 + track->zb_dirty = true; 849 842 break; 850 843 case 0x4F24: 851 844 /* ZB_DEPTHPITCH */ ··· 870 861 ib[idx] = tmp; 871 862 872 863 track->zb.pitch = idx_value & 0x3FFC; 864 + track->zb_dirty = true; 873 865 break; 874 866 case 0x4104: 867 + /* TX_ENABLE */ 875 868 for (i = 0; i < 16; i++) { 876 869 bool enabled; 877 870 878 871 enabled = !!(idx_value & (1 << i)); 879 872 track->textures[i].enabled = enabled; 880 873 } 874 + track->tex_dirty = true; 881 875 break; 882 876 case 0x44C0: 883 877 case 0x44C4: ··· 963 951 DRM_ERROR("Invalid texture format %u\n", 964 952 (idx_value & 0x1F)); 965 953 return -EINVAL; 966 - break; 967 954 } 955 + track->tex_dirty = true; 968 956 break; 969 957 case 0x4400: 970 958 case 0x4404: ··· 992 980 if (tmp == 2 || tmp == 4 || tmp == 6) { 993 981 track->textures[i].roundup_h = false; 994 982 } 983 + track->tex_dirty = true; 995 984 break; 996 985 case 0x4500: 997 986 case 0x4504: ··· 1030 1017 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1031 1018 return -EINVAL; 1032 1019 } 1020 + track->tex_dirty = true; 1033 1021 break; 1034 1022 case 0x4480: 1035 1023 case 0x4484: ··· 1060 1046 track->textures[i].use_pitch = !!tmp; 1061 1047 tmp = (idx_value >> 22) & 0xF; 1062 1048 track->textures[i].txdepth = tmp; 1049 + track->tex_dirty = true; 1063 1050 break; 1064 1051 case R300_ZB_ZPASS_ADDR: 1065 1052 r = r100_cs_packet_next_reloc(p, &reloc); ··· 1075 1060 case 0x4e0c: 1076 1061 /* RB3D_COLOR_CHANNEL_MASK */ 1077 1062 track->color_channel_mask = idx_value; 1063 + track->cb_dirty = true; 1078 1064 break; 1079 1065 case 0x43a4: 1080 1066 /* SC_HYPERZ_EN */ ··· 1089 1073 case 0x4f1c: 1090 1074 /* ZB_BW_CNTL */ 1091 1075 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1076 + track->cb_dirty = true; 1077 + track->zb_dirty = true; 1092 1078 if (p->rdev->hyperz_filp != p->filp) { 1093 1079 if (idx_value & (R300_HIZ_ENABLE | 1094 1080 R300_RD_COMP_ENABLE | ··· 1102 1084 case 0x4e04: 1103 1085 /* RB3D_BLENDCNTL */ 1104 1086 track->blend_read_enable = !!(idx_value & (1 << 2)); 1087 + track->cb_dirty = true; 1105 1088 break; 1106 - case 0x4f28: /* ZB_DEPTHCLEARVALUE */ 1089 + case R300_RB3D_AARESOLVE_OFFSET: 1090 + r = r100_cs_packet_next_reloc(p, &reloc); 1091 + if (r) { 1092 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1093 + idx, reg); 1094 + r100_cs_dump_packet(p, pkt); 1095 + return r; 1096 + } 1097 + track->aa.robj = reloc->robj; 1098 + track->aa.offset = idx_value; 1099 + track->aa_dirty = true; 1100 + ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1101 + break; 1102 + case R300_RB3D_AARESOLVE_PITCH: 1103 + track->aa.pitch = idx_value & 0x3FFE; 1104 + track->aa_dirty = true; 1105 + break; 1106 + case R300_RB3D_AARESOLVE_CTL: 1107 + track->aaresolve = idx_value & 0x1; 1108 + track->aa_dirty = true; 1107 1109 break; 1108 1110 case 0x4f30: /* ZB_MASK_OFFSET */ 1109 1111 case 0x4f34: /* ZB_ZMASK_PITCH */

+2

drivers/gpu/drm/radeon/r300_reg.h

··· 1371 1371 #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ 1372 1372 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ 1373 1373 1374 + #define R300_RB3D_AARESOLVE_OFFSET 0x4E80 1375 + #define R300_RB3D_AARESOLVE_PITCH 0x4E84 1374 1376 #define R300_RB3D_AARESOLVE_CTL 0x4E88 1375 1377 /* gap */ 1376 1378

+17 -5

drivers/gpu/drm/radeon/r600.c

··· 2105 2105 2106 2106 r600_cp_stop(rdev); 2107 2107 2108 - WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2108 + WREG32(CP_RB_CNTL, 2109 + #ifdef __BIG_ENDIAN 2110 + BUF_SWAP_32BIT | 2111 + #endif 2112 + RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2109 2113 2110 2114 /* Reset cp */ 2111 2115 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); ··· 2196 2192 WREG32(CP_RB_WPTR, 0); 2197 2193 2198 2194 /* set the wb address whether it's enabled or not */ 2199 - WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 2195 + WREG32(CP_RB_RPTR_ADDR, 2196 + #ifdef __BIG_ENDIAN 2197 + RB_RPTR_SWAP(2) | 2198 + #endif 2199 + ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2200 2200 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2201 2201 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2202 2202 ··· 2636 2628 { 2637 2629 /* FIXME: implement */ 2638 2630 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2639 - radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); 2631 + radeon_ring_write(rdev, 2632 + #ifdef __BIG_ENDIAN 2633 + (2 << 0) | 2634 + #endif 2635 + (ib->gpu_addr & 0xFFFFFFFC)); 2640 2636 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 2641 2637 radeon_ring_write(rdev, ib->length_dw); 2642 2638 } ··· 3309 3297 while (rptr != wptr) { 3310 3298 /* wptr/rptr are in bytes! */ 3311 3299 ring_index = rptr / 4; 3312 - src_id = rdev->ih.ring[ring_index] & 0xff; 3313 - src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; 3300 + src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3301 + src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3314 3302 3315 3303 switch (src_id) { 3316 3304 case 1: /* D1 vblank/vline */

+9 -2

drivers/gpu/drm/radeon/r600_blit.c

··· 137 137 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); 138 138 139 139 for (i = 0; i < r6xx_vs_size; i++) 140 - vs[i] = r6xx_vs[i]; 140 + vs[i] = cpu_to_le32(r6xx_vs[i]); 141 141 for (i = 0; i < r6xx_ps_size; i++) 142 - ps[i] = r6xx_ps[i]; 142 + ps[i] = cpu_to_le32(r6xx_ps[i]); 143 143 144 144 dev_priv->blit_vb->used = 512; 145 145 ··· 192 192 DRM_DEBUG("\n"); 193 193 194 194 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); 195 + #ifdef __BIG_ENDIAN 196 + sq_vtx_constant_word2 |= (2 << 30); 197 + #endif 195 198 196 199 BEGIN_RING(9); 197 200 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); ··· 294 291 OUT_RING(DI_PT_RECTLIST); 295 292 296 293 OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); 294 + #ifdef __BIG_ENDIAN 295 + OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT); 296 + #else 297 297 OUT_RING(DI_INDEX_SIZE_16_BIT); 298 + #endif 298 299 299 300 OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); 300 301 OUT_RING(1);

+21 -8

drivers/gpu/drm/radeon/r600_blit_kms.c

··· 54 54 if (h < 8) 55 55 h = 8; 56 56 57 - cb_color_info = ((format << 2) | (1 << 27)); 57 + cb_color_info = ((format << 2) | (1 << 27) | (1 << 8)); 58 58 pitch = (w / 8) - 1; 59 59 slice = ((w * h) / 64) - 1; 60 60 ··· 165 165 u32 sq_vtx_constant_word2; 166 166 167 167 sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); 168 + #ifdef __BIG_ENDIAN 169 + sq_vtx_constant_word2 |= (2 << 30); 170 + #endif 168 171 169 172 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); 170 173 radeon_ring_write(rdev, 0x460); ··· 202 199 if (h < 1) 203 200 h = 1; 204 201 205 - sq_tex_resource_word0 = (1 << 0); 202 + sq_tex_resource_word0 = (1 << 0) | (1 << 3); 206 203 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | 207 204 ((w - 1) << 19)); 208 205 ··· 256 253 radeon_ring_write(rdev, DI_PT_RECTLIST); 257 254 258 255 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); 259 - radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); 256 + radeon_ring_write(rdev, 257 + #ifdef __BIG_ENDIAN 258 + (2 << 2) | 259 + #endif 260 + DI_INDEX_SIZE_16_BIT); 260 261 261 262 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); 262 263 radeon_ring_write(rdev, 1); ··· 431 424 dwords = ALIGN(rdev->r600_blit.state_len, 0x10); 432 425 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; 433 426 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 434 - radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); 427 + radeon_ring_write(rdev, 428 + #ifdef __BIG_ENDIAN 429 + (2 << 0) | 430 + #endif 431 + (gpu_addr & 0xFFFFFFFC)); 435 432 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); 436 433 radeon_ring_write(rdev, dwords); 437 434 ··· 478 467 int r600_blit_init(struct radeon_device *rdev) 479 468 { 480 469 u32 obj_size; 481 - int r, dwords; 470 + int i, r, dwords; 482 471 void *ptr; 483 472 u32 packet2s[16]; 484 473 int num_packet2s = 0; ··· 497 486 498 487 dwords = rdev->r600_blit.state_len; 499 488 while (dwords & 0xf) { 500 - packet2s[num_packet2s++] = PACKET2(0); 489 + packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); 501 490 dwords++; 502 491 } 503 492 ··· 540 529 if (num_packet2s) 541 530 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), 542 531 packet2s, num_packet2s * 4); 543 - memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); 544 - memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); 532 + for (i = 0; i < r6xx_vs_size; i++) 533 + *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]); 534 + for (i = 0; i < r6xx_ps_size; i++) 535 + *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); 545 536 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 546 537 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 547 538

+4

drivers/gpu/drm/radeon/r600_blit_shaders.c

··· 684 684 0x00000000, 685 685 0x3c000000, 686 686 0x68cd1000, 687 + #ifdef __BIG_ENDIAN 688 + 0x000a0000, 689 + #else 687 690 0x00080000, 691 + #endif 688 692 0x00000000, 689 693 }; 690 694

+24 -7

drivers/gpu/drm/radeon/r600_cp.c

··· 396 396 r600_do_cp_stop(dev_priv); 397 397 398 398 RADEON_WRITE(R600_CP_RB_CNTL, 399 + #ifdef __BIG_ENDIAN 400 + R600_BUF_SWAP_32BIT | 401 + #endif 399 402 R600_RB_NO_UPDATE | 400 403 R600_RB_BLKSZ(15) | 401 404 R600_RB_BUFSZ(3)); ··· 489 486 r600_do_cp_stop(dev_priv); 490 487 491 488 RADEON_WRITE(R600_CP_RB_CNTL, 489 + #ifdef __BIG_ENDIAN 490 + R600_BUF_SWAP_32BIT | 491 + #endif 492 492 R600_RB_NO_UPDATE | 493 - (15 << 8) | 494 - (3 << 0)); 493 + R600_RB_BLKSZ(15) | 494 + R600_RB_BUFSZ(3)); 495 495 496 496 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 497 497 RADEON_READ(R600_GRBM_SOFT_RESET); ··· 556 550 557 551 if (!dev_priv->writeback_works) { 558 552 /* Disable writeback to avoid unnecessary bus master transfer */ 559 - RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 560 - RADEON_RB_NO_UPDATE); 553 + RADEON_WRITE(R600_CP_RB_CNTL, 554 + #ifdef __BIG_ENDIAN 555 + R600_BUF_SWAP_32BIT | 556 + #endif 557 + RADEON_READ(R600_CP_RB_CNTL) | 558 + R600_RB_NO_UPDATE); 561 559 RADEON_WRITE(R600_SCRATCH_UMSK, 0); 562 560 } 563 561 } ··· 585 575 586 576 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 587 577 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 588 - RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 578 + RADEON_WRITE(R600_CP_RB_CNTL, 579 + #ifdef __BIG_ENDIAN 580 + R600_BUF_SWAP_32BIT | 581 + #endif 582 + R600_RB_RPTR_WR_ENA); 589 583 590 584 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 591 585 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); ··· 1852 1838 + dev_priv->gart_vm_start; 1853 1839 } 1854 1840 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1855 - rptr_addr & 0xffffffff); 1841 + #ifdef __BIG_ENDIAN 1842 + (2 << 0) | 1843 + #endif 1844 + (rptr_addr & 0xfffffffc)); 1856 1845 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 1857 1846 upper_32_bits(rptr_addr)); 1858 1847 ··· 1906 1889 { 1907 1890 u64 scratch_addr; 1908 1891 1909 - scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); 1892 + scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC; 1910 1893 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1911 1894 scratch_addr += R600_SCRATCH_REG_OFFSET; 1912 1895 scratch_addr >>= 8;

+26 -20

drivers/gpu/drm/radeon/r600_cs.c

··· 295 295 } 296 296 297 297 if (!IS_ALIGNED(pitch, pitch_align)) { 298 - dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", 299 - __func__, __LINE__, pitch); 298 + dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 299 + __func__, __LINE__, pitch, pitch_align, array_mode); 300 300 return -EINVAL; 301 301 } 302 302 if (!IS_ALIGNED(height, height_align)) { 303 - dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", 304 - __func__, __LINE__, height); 303 + dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 304 + __func__, __LINE__, height, height_align, array_mode); 305 305 return -EINVAL; 306 306 } 307 307 if (!IS_ALIGNED(base_offset, base_align)) { 308 - dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); 308 + dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, 309 + base_offset, base_align, array_mode); 309 310 return -EINVAL; 310 311 } 311 312 ··· 321 320 * broken userspace. 322 321 */ 323 322 } else { 324 - dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); 323 + dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i, 324 + array_mode, 325 + track->cb_color_bo_offset[i], tmp, 326 + radeon_bo_size(track->cb_color_bo[i])); 325 327 return -EINVAL; 326 328 } 327 329 } ··· 459 455 } 460 456 461 457 if (!IS_ALIGNED(pitch, pitch_align)) { 462 - dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", 463 - __func__, __LINE__, pitch); 458 + dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 459 + __func__, __LINE__, pitch, pitch_align, array_mode); 464 460 return -EINVAL; 465 461 } 466 462 if (!IS_ALIGNED(height, height_align)) { 467 - dev_warn(p->dev, "%s:%d db height (%d) invalid\n", 468 - __func__, __LINE__, height); 463 + dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 464 + __func__, __LINE__, height, height_align, array_mode); 469 465 return -EINVAL; 470 466 } 471 467 if (!IS_ALIGNED(base_offset, base_align)) { 472 - dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); 468 + dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i, 469 + base_offset, base_align, array_mode); 473 470 return -EINVAL; 474 471 } 475 472 ··· 478 473 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 479 474 tmp = ntiles * bpe * 64 * nviews; 480 475 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 481 - dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n", 482 - track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 483 - radeon_bo_size(track->db_bo)); 476 + dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 477 + array_mode, 478 + track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 479 + radeon_bo_size(track->db_bo)); 484 480 return -EINVAL; 485 481 } 486 482 } ··· 1233 1227 /* XXX check height as well... */ 1234 1228 1235 1229 if (!IS_ALIGNED(pitch, pitch_align)) { 1236 - dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", 1237 - __func__, __LINE__, pitch); 1230 + dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", 1231 + __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); 1238 1232 return -EINVAL; 1239 1233 } 1240 1234 if (!IS_ALIGNED(base_offset, base_align)) { 1241 - dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n", 1242 - __func__, __LINE__, base_offset); 1235 + dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", 1236 + __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); 1243 1237 return -EINVAL; 1244 1238 } 1245 1239 if (!IS_ALIGNED(mip_offset, base_align)) { 1246 - dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n", 1247 - __func__, __LINE__, mip_offset); 1240 + dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", 1241 + __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); 1248 1242 return -EINVAL; 1249 1243 } 1250 1244

+5 -4

drivers/gpu/drm/radeon/r600d.h

··· 154 154 #define ROQ_IB2_START(x) ((x) << 8) 155 155 #define CP_RB_BASE 0xC100 156 156 #define CP_RB_CNTL 0xC104 157 - #define RB_BUFSZ(x) ((x)<<0) 158 - #define RB_BLKSZ(x) ((x)<<8) 159 - #define RB_NO_UPDATE (1<<27) 160 - #define RB_RPTR_WR_ENA (1<<31) 157 + #define RB_BUFSZ(x) ((x) << 0) 158 + #define RB_BLKSZ(x) ((x) << 8) 159 + #define RB_NO_UPDATE (1 << 27) 160 + #define RB_RPTR_WR_ENA (1 << 31) 161 161 #define BUF_SWAP_32BIT (2 << 16) 162 162 #define CP_RB_RPTR 0x8700 163 163 #define CP_RB_RPTR_ADDR 0xC10C 164 + #define RB_RPTR_SWAP(x) ((x) << 0) 164 165 #define CP_RB_RPTR_ADDR_HI 0xC110 165 166 #define CP_RB_RPTR_WR 0xC108 166 167 #define CP_RB_WPTR 0xC114

+24 -24

drivers/gpu/drm/radeon/radeon_atombios.c

··· 88 88 /* some evergreen boards have bad data for this entry */ 89 89 if (ASIC_IS_DCE4(rdev)) { 90 90 if ((i == 7) && 91 - (gpio->usClkMaskRegisterIndex == 0x1936) && 91 + (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 92 92 (gpio->sucI2cId.ucAccess == 0)) { 93 93 gpio->sucI2cId.ucAccess = 0x97; 94 94 gpio->ucDataMaskShift = 8; ··· 101 101 /* some DCE3 boards have bad data for this entry */ 102 102 if (ASIC_IS_DCE3(rdev)) { 103 103 if ((i == 4) && 104 - (gpio->usClkMaskRegisterIndex == 0x1fda) && 104 + (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 105 105 (gpio->sucI2cId.ucAccess == 0x94)) 106 106 gpio->sucI2cId.ucAccess = 0x14; 107 107 } ··· 172 172 /* some evergreen boards have bad data for this entry */ 173 173 if (ASIC_IS_DCE4(rdev)) { 174 174 if ((i == 7) && 175 - (gpio->usClkMaskRegisterIndex == 0x1936) && 175 + (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 176 176 (gpio->sucI2cId.ucAccess == 0)) { 177 177 gpio->sucI2cId.ucAccess = 0x97; 178 178 gpio->ucDataMaskShift = 8; ··· 185 185 /* some DCE3 boards have bad data for this entry */ 186 186 if (ASIC_IS_DCE3(rdev)) { 187 187 if ((i == 4) && 188 - (gpio->usClkMaskRegisterIndex == 0x1fda) && 188 + (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 189 189 (gpio->sucI2cId.ucAccess == 0x94)) 190 190 gpio->sucI2cId.ucAccess = 0x14; 191 191 } ··· 252 252 pin = &gpio_info->asGPIO_Pin[i]; 253 253 if (id == pin->ucGPIO_ID) { 254 254 gpio.id = pin->ucGPIO_ID; 255 - gpio.reg = pin->usGpioPin_AIndex * 4; 255 + gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 256 256 gpio.mask = (1 << pin->ucGpioPinBitShift); 257 257 gpio.valid = true; 258 258 break; ··· 1274 1274 data_offset); 1275 1275 switch (crev) { 1276 1276 case 1: 1277 - if (igp_info->info.ulBootUpMemoryClock) 1277 + if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1278 1278 return true; 1279 1279 break; 1280 1280 case 2: 1281 - if (igp_info->info_2.ulBootUpSidePortClock) 1281 + if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1282 1282 return true; 1283 1283 break; 1284 1284 default: ··· 1442 1442 1443 1443 for (i = 0; i < num_indices; i++) { 1444 1444 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && 1445 - (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) { 1445 + (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) { 1446 1446 ss->percentage = 1447 1447 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1448 1448 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; ··· 1456 1456 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1457 1457 for (i = 0; i < num_indices; i++) { 1458 1458 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && 1459 - (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) { 1459 + (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) { 1460 1460 ss->percentage = 1461 1461 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1462 1462 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; ··· 1470 1470 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1471 1471 for (i = 0; i < num_indices; i++) { 1472 1472 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && 1473 - (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) { 1473 + (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) { 1474 1474 ss->percentage = 1475 1475 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1476 1476 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; ··· 1553 1553 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1554 1554 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1555 1555 1556 - lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize; 1557 - lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize; 1556 + lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1557 + lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1558 1558 1559 1559 /* set crtc values */ 1560 1560 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); ··· 1569 1569 lvds->linkb = false; 1570 1570 1571 1571 /* parse the lcd record table */ 1572 - if (lvds_info->info.usModePatchTableOffset) { 1572 + if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1573 1573 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1574 1574 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1575 1575 bool bad_record = false; 1576 1576 u8 *record = (u8 *)(mode_info->atom_context->bios + 1577 1577 data_offset + 1578 - lvds_info->info.usModePatchTableOffset); 1578 + le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1579 1579 while (*record != ATOM_RECORD_END_TYPE) { 1580 1580 switch (*record) { 1581 1581 case LCD_MODE_PATCH_RECORD_MODE_TYPE: ··· 2189 2189 firmware_info = 2190 2190 (union firmware_info *)(mode_info->atom_context->bios + 2191 2191 data_offset); 2192 - vddc = firmware_info->info_14.usBootUpVDDCVoltage; 2192 + vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2193 2193 } 2194 2194 2195 2195 return vddc; ··· 2284 2284 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2285 2285 VOLTAGE_SW; 2286 2286 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2287 - clock_info->evergreen.usVDDC; 2287 + le16_to_cpu(clock_info->evergreen.usVDDC); 2288 2288 } else { 2289 2289 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2290 2290 sclk |= clock_info->r600.ucEngineClockHigh << 16; ··· 2295 2295 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2296 2296 VOLTAGE_SW; 2297 2297 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2298 - clock_info->r600.usVDDC; 2298 + le16_to_cpu(clock_info->r600.usVDDC); 2299 2299 } 2300 2300 2301 2301 if (rdev->flags & RADEON_IS_IGP) { ··· 2408 2408 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2409 2409 state_array = (struct StateArray *) 2410 2410 (mode_info->atom_context->bios + data_offset + 2411 - power_info->pplib.usStateArrayOffset); 2411 + le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2412 2412 clock_info_array = (struct ClockInfoArray *) 2413 2413 (mode_info->atom_context->bios + data_offset + 2414 - power_info->pplib.usClockInfoArrayOffset); 2414 + le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2415 2415 non_clock_info_array = (struct NonClockInfoArray *) 2416 2416 (mode_info->atom_context->bios + data_offset + 2417 - power_info->pplib.usNonClockInfoArrayOffset); 2417 + le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2418 2418 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2419 2419 state_array->ucNumEntries, GFP_KERNEL); 2420 2420 if (!rdev->pm.power_state) ··· 2533 2533 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 2534 2534 2535 2535 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2536 - return args.ulReturnEngineClock; 2536 + return le32_to_cpu(args.ulReturnEngineClock); 2537 2537 } 2538 2538 2539 2539 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) ··· 2542 2542 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 2543 2543 2544 2544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2545 - return args.ulReturnMemoryClock; 2545 + return le32_to_cpu(args.ulReturnMemoryClock); 2546 2546 } 2547 2547 2548 2548 void radeon_atom_set_engine_clock(struct radeon_device *rdev, ··· 2551 2551 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2552 2552 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 2553 2553 2554 - args.ulTargetEngineClock = eng_clock; /* 10 khz */ 2554 + args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 2555 2555 2556 2556 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2557 2557 } ··· 2565 2565 if (rdev->flags & RADEON_IS_IGP) 2566 2566 return; 2567 2567 2568 - args.ulTargetMemoryClock = mem_clock; /* 10 khz */ 2568 + args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 2569 2569 2570 2570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2571 2571 }

+47

drivers/gpu/drm/radeon/radeon_combios.c

··· 1504 1504 (rdev->pdev->subsystem_device == 0x4a48)) { 1505 1505 /* Mac X800 */ 1506 1506 rdev->mode_info.connector_table = CT_MAC_X800; 1507 + } else if ((rdev->pdev->device == 0x4150) && 1508 + (rdev->pdev->subsystem_vendor == 0x1002) && 1509 + (rdev->pdev->subsystem_device == 0x4150)) { 1510 + /* Mac G5 9600 */ 1511 + rdev->mode_info.connector_table = CT_MAC_G5_9600; 1507 1512 } else 1508 1513 #endif /* CONFIG_PPC_PMAC */ 1509 1514 #ifdef CONFIG_PPC64 ··· 2025 2020 ATOM_DEVICE_CRT2_SUPPORT, 2026 2021 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2027 2022 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2023 + &hpd); 2024 + break; 2025 + case CT_MAC_G5_9600: 2026 + DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2027 + rdev->mode_info.connector_table); 2028 + /* DVI - tv dac, dvo */ 2029 + ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2030 + hpd.hpd = RADEON_HPD_1; /* ??? */ 2031 + radeon_add_legacy_encoder(dev, 2032 + radeon_get_encoder_enum(dev, 2033 + ATOM_DEVICE_DFP2_SUPPORT, 2034 + 0), 2035 + ATOM_DEVICE_DFP2_SUPPORT); 2036 + radeon_add_legacy_encoder(dev, 2037 + radeon_get_encoder_enum(dev, 2038 + ATOM_DEVICE_CRT2_SUPPORT, 2039 + 2), 2040 + ATOM_DEVICE_CRT2_SUPPORT); 2041 + radeon_add_legacy_connector(dev, 0, 2042 + ATOM_DEVICE_DFP2_SUPPORT | 2043 + ATOM_DEVICE_CRT2_SUPPORT, 2044 + DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2045 + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2046 + &hpd); 2047 + /* ADC - primary dac, internal tmds */ 2048 + ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2049 + hpd.hpd = RADEON_HPD_2; /* ??? */ 2050 + radeon_add_legacy_encoder(dev, 2051 + radeon_get_encoder_enum(dev, 2052 + ATOM_DEVICE_DFP1_SUPPORT, 2053 + 0), 2054 + ATOM_DEVICE_DFP1_SUPPORT); 2055 + radeon_add_legacy_encoder(dev, 2056 + radeon_get_encoder_enum(dev, 2057 + ATOM_DEVICE_CRT1_SUPPORT, 2058 + 1), 2059 + ATOM_DEVICE_CRT1_SUPPORT); 2060 + radeon_add_legacy_connector(dev, 1, 2061 + ATOM_DEVICE_DFP1_SUPPORT | 2062 + ATOM_DEVICE_CRT1_SUPPORT, 2063 + DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2064 + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2028 2065 &hpd); 2029 2066 break; 2030 2067 default:

+4

drivers/gpu/drm/radeon/radeon_device.c

··· 936 936 int radeon_gpu_reset(struct radeon_device *rdev) 937 937 { 938 938 int r; 939 + int resched; 939 940 940 941 radeon_save_bios_scratch_regs(rdev); 942 + /* block TTM */ 943 + resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 941 944 radeon_suspend(rdev); 942 945 943 946 r = radeon_asic_reset(rdev); ··· 949 946 radeon_resume(rdev); 950 947 radeon_restore_bios_scratch_regs(rdev); 951 948 drm_helper_resume_force_mode(rdev->ddev); 949 + ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 952 950 return 0; 953 951 } 954 952 /* bad news, how to tell it to userspace ? */

+10

drivers/gpu/drm/radeon/radeon_display.c

··· 793 793 tmp *= target_clock; 794 794 *fb_div = tmp / pll->reference_freq; 795 795 *frac_fb_div = tmp % pll->reference_freq; 796 + 797 + if (*fb_div > pll->max_feedback_div) 798 + *fb_div = pll->max_feedback_div; 799 + else if (*fb_div < pll->min_feedback_div) 800 + *fb_div = pll->min_feedback_div; 796 801 } 797 802 798 803 static u32 avivo_get_post_div(struct radeon_pll *pll, ··· 830 825 if (!tmp) 831 826 post_div--; 832 827 } 828 + 829 + if (post_div > pll->max_post_div) 830 + post_div = pll->max_post_div; 831 + else if (post_div < pll->min_post_div) 832 + post_div = pll->min_post_div; 833 833 834 834 return post_div; 835 835 }

+1

drivers/gpu/drm/radeon/radeon_drv.h

··· 1524 1524 #define R600_CP_RB_CNTL 0xc104 1525 1525 # define R600_RB_BUFSZ(x) ((x) << 0) 1526 1526 # define R600_RB_BLKSZ(x) ((x) << 8) 1527 + # define R600_BUF_SWAP_32BIT (2 << 16) 1527 1528 # define R600_RB_NO_UPDATE (1 << 27) 1528 1529 # define R600_RB_RPTR_WR_ENA (1 << 31) 1529 1530 #define R600_CP_RB_RPTR_WR 0xc108

+17 -7

drivers/gpu/drm/radeon/radeon_encoders.c

··· 910 910 911 911 args.v1.ucAction = action; 912 912 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 913 - args.v1.usInitInfo = connector_object_id; 913 + args.v1.usInitInfo = cpu_to_le16(connector_object_id); 914 914 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 915 915 args.v1.asMode.ucLaneSel = lane_num; 916 916 args.v1.asMode.ucLaneSet = lane_set; ··· 1140 1140 case 3: 1141 1141 args.v3.sExtEncoder.ucAction = action; 1142 1142 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1143 - args.v3.sExtEncoder.usConnectorId = connector_object_id; 1143 + args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1144 1144 else 1145 1145 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1146 1146 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); ··· 1570 1570 } 1571 1571 1572 1572 /* set scaler clears this on some chips */ 1573 - /* XXX check DCE4 */ 1574 - if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { 1575 - if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) 1576 - WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1577 - AVIVO_D1MODE_INTERLEAVE_EN); 1573 + if (ASIC_IS_AVIVO(rdev) && 1574 + (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1575 + if (ASIC_IS_DCE4(rdev)) { 1576 + if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1577 + WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1578 + EVERGREEN_INTERLEAVE_EN); 1579 + else 1580 + WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1581 + } else { 1582 + if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1583 + WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1584 + AVIVO_D1MODE_INTERLEAVE_EN); 1585 + else 1586 + WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1587 + } 1578 1588 } 1579 1589 } 1580 1590

+1

drivers/gpu/drm/radeon/radeon_mode.h

··· 209 209 CT_EMAC, 210 210 CT_RN50_POWER, 211 211 CT_MAC_X800, 212 + CT_MAC_G5_9600, 212 213 }; 213 214 214 215 enum radeon_dvo_chip {

+2 -2

drivers/gpu/drm/radeon/radeon_ttm.c

··· 787 787 radeon_mem_types_list[i].show = &radeon_mm_dump_table; 788 788 radeon_mem_types_list[i].driver_features = 0; 789 789 if (i == 0) 790 - radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].priv; 790 + radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; 791 791 else 792 - radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].priv; 792 + radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; 793 793 794 794 } 795 795 /* Add ttm page pool to debugfs */

+1 -5

drivers/gpu/drm/radeon/reg_srcs/r300

··· 683 683 0x4DF4 US_ALU_CONST_G_31 684 684 0x4DF8 US_ALU_CONST_B_31 685 685 0x4DFC US_ALU_CONST_A_31 686 - 0x4E04 RB3D_BLENDCNTL_R3 687 686 0x4E08 RB3D_ABLENDCNTL_R3 688 - 0x4E0C RB3D_COLOR_CHANNEL_MASK 689 687 0x4E10 RB3D_CONSTANT_COLOR 690 688 0x4E14 RB3D_COLOR_CLEAR_VALUE 691 689 0x4E18 RB3D_ROPCNTL_R3 ··· 704 706 0x4E74 RB3D_CMASK_WRINDEX 705 707 0x4E78 RB3D_CMASK_DWORD 706 708 0x4E7C RB3D_CMASK_RDINDEX 707 - 0x4E80 RB3D_AARESOLVE_OFFSET 708 - 0x4E84 RB3D_AARESOLVE_PITCH 709 - 0x4E88 RB3D_AARESOLVE_CTL 710 709 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 711 710 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 712 711 0x4F04 ZB_ZSTENCILCNTL 713 712 0x4F08 ZB_STENCILREFMASK 714 713 0x4F14 ZB_ZTOP 715 714 0x4F18 ZB_ZCACHE_CTLSTAT 715 + 0x4F28 ZB_DEPTHCLEARVALUE 716 716 0x4F58 ZB_ZPASS_DATA

+1 -6

drivers/gpu/drm/radeon/reg_srcs/r420

··· 130 130 0x401C GB_SELECT 131 131 0x4020 GB_AA_CONFIG 132 132 0x4024 GB_FIFO_SIZE 133 - 0x4028 GB_Z_PEQ_CONFIG 134 133 0x4100 TX_INVALTAGS 135 134 0x4200 GA_POINT_S0 136 135 0x4204 GA_POINT_T0 ··· 749 750 0x4DF4 US_ALU_CONST_G_31 750 751 0x4DF8 US_ALU_CONST_B_31 751 752 0x4DFC US_ALU_CONST_A_31 752 - 0x4E04 RB3D_BLENDCNTL_R3 753 753 0x4E08 RB3D_ABLENDCNTL_R3 754 - 0x4E0C RB3D_COLOR_CHANNEL_MASK 755 754 0x4E10 RB3D_CONSTANT_COLOR 756 755 0x4E14 RB3D_COLOR_CLEAR_VALUE 757 756 0x4E18 RB3D_ROPCNTL_R3 ··· 770 773 0x4E74 RB3D_CMASK_WRINDEX 771 774 0x4E78 RB3D_CMASK_DWORD 772 775 0x4E7C RB3D_CMASK_RDINDEX 773 - 0x4E80 RB3D_AARESOLVE_OFFSET 774 - 0x4E84 RB3D_AARESOLVE_PITCH 775 - 0x4E88 RB3D_AARESOLVE_CTL 776 776 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 777 777 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 778 778 0x4F04 ZB_ZSTENCILCNTL 779 779 0x4F08 ZB_STENCILREFMASK 780 780 0x4F14 ZB_ZTOP 781 781 0x4F18 ZB_ZCACHE_CTLSTAT 782 + 0x4F28 ZB_DEPTHCLEARVALUE 782 783 0x4F58 ZB_ZPASS_DATA

+1 -5

drivers/gpu/drm/radeon/reg_srcs/rs600

··· 749 749 0x4DF4 US_ALU_CONST_G_31 750 750 0x4DF8 US_ALU_CONST_B_31 751 751 0x4DFC US_ALU_CONST_A_31 752 - 0x4E04 RB3D_BLENDCNTL_R3 753 752 0x4E08 RB3D_ABLENDCNTL_R3 754 - 0x4E0C RB3D_COLOR_CHANNEL_MASK 755 753 0x4E10 RB3D_CONSTANT_COLOR 756 754 0x4E14 RB3D_COLOR_CLEAR_VALUE 757 755 0x4E18 RB3D_ROPCNTL_R3 ··· 770 772 0x4E74 RB3D_CMASK_WRINDEX 771 773 0x4E78 RB3D_CMASK_DWORD 772 774 0x4E7C RB3D_CMASK_RDINDEX 773 - 0x4E80 RB3D_AARESOLVE_OFFSET 774 - 0x4E84 RB3D_AARESOLVE_PITCH 775 - 0x4E88 RB3D_AARESOLVE_CTL 776 775 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 777 776 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 778 777 0x4F04 ZB_ZSTENCILCNTL 779 778 0x4F08 ZB_STENCILREFMASK 780 779 0x4F14 ZB_ZTOP 781 780 0x4F18 ZB_ZCACHE_CTLSTAT 781 + 0x4F28 ZB_DEPTHCLEARVALUE 782 782 0x4F58 ZB_ZPASS_DATA

+1 -6

drivers/gpu/drm/radeon/reg_srcs/rv515

··· 164 164 0x401C GB_SELECT 165 165 0x4020 GB_AA_CONFIG 166 166 0x4024 GB_FIFO_SIZE 167 - 0x4028 GB_Z_PEQ_CONFIG 168 167 0x4100 TX_INVALTAGS 169 168 0x4114 SU_TEX_WRAP_PS3 170 169 0x4118 PS3_ENABLE ··· 460 461 0x4DF4 US_ALU_CONST_G_31 461 462 0x4DF8 US_ALU_CONST_B_31 462 463 0x4DFC US_ALU_CONST_A_31 463 - 0x4E04 RB3D_BLENDCNTL_R3 464 464 0x4E08 RB3D_ABLENDCNTL_R3 465 - 0x4E0C RB3D_COLOR_CHANNEL_MASK 466 465 0x4E10 RB3D_CONSTANT_COLOR 467 466 0x4E14 RB3D_COLOR_CLEAR_VALUE 468 467 0x4E18 RB3D_ROPCNTL_R3 ··· 481 484 0x4E74 RB3D_CMASK_WRINDEX 482 485 0x4E78 RB3D_CMASK_DWORD 483 486 0x4E7C RB3D_CMASK_RDINDEX 484 - 0x4E80 RB3D_AARESOLVE_OFFSET 485 - 0x4E84 RB3D_AARESOLVE_PITCH 486 - 0x4E88 RB3D_AARESOLVE_CTL 487 487 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 488 488 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 489 489 0x4EF8 RB3D_CONSTANT_COLOR_AR ··· 490 496 0x4F14 ZB_ZTOP 491 497 0x4F18 ZB_ZCACHE_CTLSTAT 492 498 0x4F58 ZB_ZPASS_DATA 499 + 0x4F28 ZB_DEPTHCLEARVALUE 493 500 0x4FD4 ZB_STENCILREFMASK_BF

+6 -6

drivers/gpu/drm/radeon/rs690.c

··· 77 77 switch (crev) { 78 78 case 1: 79 79 tmp.full = dfixed_const(100); 80 - rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock); 80 + rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 81 81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 82 - if (info->info.usK8MemoryClock) 82 + if (le16_to_cpu(info->info.usK8MemoryClock)) 83 83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 84 84 else if (rdev->clock.default_mclk) { 85 85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); ··· 91 91 break; 92 92 case 2: 93 93 tmp.full = dfixed_const(100); 94 - rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock); 94 + rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 95 95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 96 - if (info->info_v2.ulBootUpUMAClock) 97 - rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock); 96 + if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 97 + rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 98 98 else if (rdev->clock.default_mclk) 99 99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 100 100 else 101 101 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 102 102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 103 - rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq); 103 + rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 104 104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 105 105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 106 106 break;

+5 -1

drivers/gpu/drm/radeon/rv770.c

··· 321 321 return -EINVAL; 322 322 323 323 r700_cp_stop(rdev); 324 - WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 324 + WREG32(CP_RB_CNTL, 325 + #ifdef __BIG_ENDIAN 326 + BUF_SWAP_32BIT | 327 + #endif 328 + RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 325 329 326 330 /* Reset cp */ 327 331 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);

+4 -4

drivers/gpu/drm/radeon/rv770d.h

··· 76 76 #define ROQ_IB1_START(x) ((x) << 0) 77 77 #define ROQ_IB2_START(x) ((x) << 8) 78 78 #define CP_RB_CNTL 0xC104 79 - #define RB_BUFSZ(x) ((x)<<0) 80 - #define RB_BLKSZ(x) ((x)<<8) 81 - #define RB_NO_UPDATE (1<<27) 82 - #define RB_RPTR_WR_ENA (1<<31) 79 + #define RB_BUFSZ(x) ((x) << 0) 80 + #define RB_BLKSZ(x) ((x) << 8) 81 + #define RB_NO_UPDATE (1 << 27) 82 + #define RB_RPTR_WR_ENA (1 << 31) 83 83 #define BUF_SWAP_32BIT (2 << 16) 84 84 #define CP_RB_RPTR 0x8700 85 85 #define CP_RB_RPTR_ADDR 0xC10C

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