Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next
- Speed up clk_core_lookup() by using a hashtable
* clk-microchip:
ARM: at91: remove default values for PMC_PLL_ACR
clk: at91: add ACR in all PLL settings
clk: at91: sam9x7: Add peripheral clock id for pmecc
clk: at91: clk-master: Add check for divide by 3
clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
ARM: at91: pm: save and restore ACR during PLL disable/enable
* clk-lookup:
clk: Use hashtable for global clk lookups
clk: Sort include statements
* clk-st:
dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
clk: stm32: introduce clocks for STM32MP21 platform
dt-bindings: stm32: add STM32MP21 clocks and reset bindings
+3106
-91
+199
Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml
+199
Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: STM32MP21 Reset Clock Controller
8
+
9
+
maintainers:
10
+
- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
11
+
12
+
description: |
13
+
The RCC hardware block is both a reset and a clock controller.
14
+
RCC makes also power management (resume/suspend).
15
+
16
+
See also:
17
+
include/dt-bindings/clock/st,stm32mp21-rcc.h
18
+
include/dt-bindings/reset/st,stm32mp21-rcc.h
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- st,stm32mp21-rcc
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
'#clock-cells':
29
+
const: 1
30
+
31
+
'#reset-cells':
32
+
const: 1
33
+
34
+
clocks:
35
+
items:
36
+
- description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37
+
- description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38
+
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
39
+
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
40
+
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41
+
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
42
+
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43
+
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44
+
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
45
+
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
46
+
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
47
+
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
48
+
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
49
+
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
50
+
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
51
+
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
52
+
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
53
+
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
54
+
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
55
+
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
56
+
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
57
+
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
58
+
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
59
+
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
60
+
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
61
+
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
62
+
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
63
+
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
64
+
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
65
+
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
66
+
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
67
+
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
68
+
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
69
+
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
70
+
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
71
+
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
72
+
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
73
+
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
74
+
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
75
+
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
76
+
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
77
+
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
78
+
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
79
+
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
80
+
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
81
+
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
82
+
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
83
+
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
84
+
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
85
+
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
86
+
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
87
+
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
88
+
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
89
+
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
90
+
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
91
+
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
92
+
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
93
+
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
94
+
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
95
+
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
96
+
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
97
+
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
98
+
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
99
+
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
100
+
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
101
+
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
102
+
- description: CK_SCMI_ICN_APB5 Peripheral bridge 5
103
+
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
104
+
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
105
+
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
106
+
107
+
access-controllers:
108
+
maxItems: 1
109
+
110
+
required:
111
+
- compatible
112
+
- reg
113
+
- '#clock-cells'
114
+
- '#reset-cells'
115
+
- clocks
116
+
117
+
additionalProperties: false
118
+
119
+
examples:
120
+
- |
121
+
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
122
+
123
+
clock-controller@44200000 {
124
+
compatible = "st,stm32mp21-rcc";
125
+
reg = <0x44200000 0x10000>;
126
+
#clock-cells = <1>;
127
+
#reset-cells = <1>;
128
+
clocks = <&scmi_clk CK_SCMI_HSE>,
129
+
<&scmi_clk CK_SCMI_HSI>,
130
+
<&scmi_clk CK_SCMI_MSI>,
131
+
<&scmi_clk CK_SCMI_LSE>,
132
+
<&scmi_clk CK_SCMI_LSI>,
133
+
<&scmi_clk CK_SCMI_HSE_DIV2>,
134
+
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
135
+
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
136
+
<&scmi_clk CK_SCMI_ICN_SDMMC>,
137
+
<&scmi_clk CK_SCMI_ICN_DDR>,
138
+
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
139
+
<&scmi_clk CK_SCMI_ICN_HSL>,
140
+
<&scmi_clk CK_SCMI_ICN_NIC>,
141
+
<&scmi_clk CK_SCMI_FLEXGEN_07>,
142
+
<&scmi_clk CK_SCMI_FLEXGEN_08>,
143
+
<&scmi_clk CK_SCMI_FLEXGEN_09>,
144
+
<&scmi_clk CK_SCMI_FLEXGEN_10>,
145
+
<&scmi_clk CK_SCMI_FLEXGEN_11>,
146
+
<&scmi_clk CK_SCMI_FLEXGEN_12>,
147
+
<&scmi_clk CK_SCMI_FLEXGEN_13>,
148
+
<&scmi_clk CK_SCMI_FLEXGEN_14>,
149
+
<&scmi_clk CK_SCMI_FLEXGEN_16>,
150
+
<&scmi_clk CK_SCMI_FLEXGEN_17>,
151
+
<&scmi_clk CK_SCMI_FLEXGEN_18>,
152
+
<&scmi_clk CK_SCMI_FLEXGEN_19>,
153
+
<&scmi_clk CK_SCMI_FLEXGEN_20>,
154
+
<&scmi_clk CK_SCMI_FLEXGEN_21>,
155
+
<&scmi_clk CK_SCMI_FLEXGEN_22>,
156
+
<&scmi_clk CK_SCMI_FLEXGEN_23>,
157
+
<&scmi_clk CK_SCMI_FLEXGEN_24>,
158
+
<&scmi_clk CK_SCMI_FLEXGEN_25>,
159
+
<&scmi_clk CK_SCMI_FLEXGEN_26>,
160
+
<&scmi_clk CK_SCMI_FLEXGEN_27>,
161
+
<&scmi_clk CK_SCMI_FLEXGEN_29>,
162
+
<&scmi_clk CK_SCMI_FLEXGEN_30>,
163
+
<&scmi_clk CK_SCMI_FLEXGEN_31>,
164
+
<&scmi_clk CK_SCMI_FLEXGEN_33>,
165
+
<&scmi_clk CK_SCMI_FLEXGEN_36>,
166
+
<&scmi_clk CK_SCMI_FLEXGEN_37>,
167
+
<&scmi_clk CK_SCMI_FLEXGEN_38>,
168
+
<&scmi_clk CK_SCMI_FLEXGEN_39>,
169
+
<&scmi_clk CK_SCMI_FLEXGEN_40>,
170
+
<&scmi_clk CK_SCMI_FLEXGEN_41>,
171
+
<&scmi_clk CK_SCMI_FLEXGEN_42>,
172
+
<&scmi_clk CK_SCMI_FLEXGEN_43>,
173
+
<&scmi_clk CK_SCMI_FLEXGEN_44>,
174
+
<&scmi_clk CK_SCMI_FLEXGEN_45>,
175
+
<&scmi_clk CK_SCMI_FLEXGEN_46>,
176
+
<&scmi_clk CK_SCMI_FLEXGEN_47>,
177
+
<&scmi_clk CK_SCMI_FLEXGEN_48>,
178
+
<&scmi_clk CK_SCMI_FLEXGEN_50>,
179
+
<&scmi_clk CK_SCMI_FLEXGEN_51>,
180
+
<&scmi_clk CK_SCMI_FLEXGEN_52>,
181
+
<&scmi_clk CK_SCMI_FLEXGEN_53>,
182
+
<&scmi_clk CK_SCMI_FLEXGEN_54>,
183
+
<&scmi_clk CK_SCMI_FLEXGEN_55>,
184
+
<&scmi_clk CK_SCMI_FLEXGEN_56>,
185
+
<&scmi_clk CK_SCMI_FLEXGEN_57>,
186
+
<&scmi_clk CK_SCMI_FLEXGEN_58>,
187
+
<&scmi_clk CK_SCMI_FLEXGEN_61>,
188
+
<&scmi_clk CK_SCMI_FLEXGEN_62>,
189
+
<&scmi_clk CK_SCMI_FLEXGEN_63>,
190
+
<&scmi_clk CK_SCMI_ICN_APB1>,
191
+
<&scmi_clk CK_SCMI_ICN_APB2>,
192
+
<&scmi_clk CK_SCMI_ICN_APB3>,
193
+
<&scmi_clk CK_SCMI_ICN_APB4>,
194
+
<&scmi_clk CK_SCMI_ICN_APB5>,
195
+
<&scmi_clk CK_SCMI_ICN_APBDBG>,
196
+
<&scmi_clk CK_SCMI_TIMG1>,
197
+
<&scmi_clk CK_SCMI_TIMG2>;
198
+
};
199
+
...
+6
-7
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
+6
-7
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
···
11
11
12
12
description: |
13
13
The RCC hardware block is both a reset and a clock controller.
14
-
RCC makes also power management (resume/supend).
14
+
RCC makes also power management (resume/suspend).
15
15
16
-
See also::
16
+
See also:
17
17
include/dt-bindings/clock/st,stm32mp25-rcc.h
18
18
include/dt-bindings/reset/st,stm32mp25-rcc.h
19
19
···
38
38
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
39
39
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
40
40
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41
-
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
41
+
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
42
42
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43
43
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44
44
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
···
108
108
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
109
109
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
110
110
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
111
-
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
111
+
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
112
112
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
113
113
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
114
114
- description: CK_SCMI_PLL3 PLL3 clock
115
115
- description: clk_dsi_txbyte DSI byte clock
116
116
117
117
access-controllers:
118
-
minItems: 1
119
-
maxItems: 2
118
+
maxItems: 1
120
119
121
120
required:
122
121
- compatible
···
130
131
- |
131
132
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
132
133
133
-
rcc: clock-controller@44200000 {
134
+
clock-controller@44200000 {
134
135
compatible = "st,stm32mp25-rcc";
135
136
reg = <0x44200000 0x10000>;
136
137
#clock-cells = <1>;
+7
-1
arch/arm/mach-at91/pm_suspend.S
+7
-1
arch/arm/mach-at91/pm_suspend.S
···
689
689
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
690
690
str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
691
691
692
+
/* save acr */
693
+
ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
694
+
str tmp2, .saved_acr
695
+
692
696
/* save div. */
693
697
mov tmp1, #0
694
698
ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
···
762
758
str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
763
759
764
760
/* step 2. */
765
-
ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
761
+
ldr tmp1, .saved_acr
766
762
str tmp1, [pmc, #AT91_PMC_PLL_ACR]
767
763
768
764
/* step 3. */
···
1210
1206
.word 0
1211
1207
#endif
1212
1208
.saved_mckr:
1209
+
.word 0
1210
+
.saved_acr:
1213
1211
.word 0
1214
1212
.saved_pllar:
1215
1213
.word 0
+3
drivers/clk/at91/clk-master.c
+3
drivers/clk/at91/clk-master.c
+41
-41
drivers/clk/at91/clk-sam9x60-pll.c
+41
-41
drivers/clk/at91/clk-sam9x60-pll.c
···
93
93
94
94
spin_lock_irqsave(core->lock, flags);
95
95
96
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
97
-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
96
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
97
+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
98
98
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
99
99
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
100
100
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
···
103
103
(cmul == frac->mul && cfrac == frac->frac))
104
104
goto unlock;
105
105
106
-
/* Recommended value for PMC_PLL_ACR */
107
-
if (core->characteristics->upll)
108
-
val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
109
-
else
110
-
val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
106
+
/* Load recommended value for PMC_PLL_ACR */
107
+
val = core->characteristics->acr;
111
108
regmap_write(regmap, AT91_PMC_PLL_ACR, val);
112
109
113
110
regmap_write(regmap, AT91_PMC_PLL_CTRL1,
···
125
128
udelay(10);
126
129
}
127
130
128
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
129
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
130
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
131
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
132
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
133
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
131
134
132
135
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
133
136
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
134
137
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
135
138
136
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
137
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
138
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
139
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
140
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
141
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
139
142
140
143
while (!sam9x60_pll_ready(regmap, core->id))
141
144
cpu_relax();
···
161
164
162
165
spin_lock_irqsave(core->lock, flags);
163
166
164
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
165
-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
167
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
168
+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
166
169
167
170
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
168
171
···
170
173
regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
171
174
AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
172
175
173
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
174
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
175
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
176
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
177
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
178
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
176
179
177
180
spin_unlock_irqrestore(core->lock, flags);
178
181
}
···
259
262
260
263
spin_lock_irqsave(core->lock, irqflags);
261
264
262
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
263
-
core->id);
265
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
266
+
core->id);
264
267
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
265
268
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
266
269
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
···
272
275
(frac->mul << core->layout->mul_shift) |
273
276
(frac->frac << core->layout->frac_shift));
274
277
275
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
276
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
277
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
278
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
279
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
280
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
278
281
279
282
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
280
283
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
281
284
AT91_PMC_PLL_CTRL0_ENLOCK |
282
285
AT91_PMC_PLL_CTRL0_ENPLL);
283
286
284
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
285
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
286
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
287
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
288
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
289
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
287
290
288
291
while (!sam9x60_pll_ready(regmap, core->id))
289
292
cpu_relax();
···
335
338
.restore_context = sam9x60_frac_pll_restore_context,
336
339
};
337
340
338
-
/* This function should be called with spinlock acquired. */
341
+
/* This function should be called with spinlock acquired.
342
+
* Warning: this function must be called only if the same PLL ID was set in
343
+
* PLL_UPDT register previously.
344
+
*/
339
345
static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
340
346
bool enable)
341
347
{
···
350
350
core->layout->div_mask | ena_msk,
351
351
(div << core->layout->div_shift) | ena_val);
352
352
353
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
354
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
355
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
353
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
354
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
355
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
356
356
357
357
while (!sam9x60_pll_ready(regmap, core->id))
358
358
cpu_relax();
···
366
366
unsigned int val, cdiv;
367
367
368
368
spin_lock_irqsave(core->lock, flags);
369
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
370
-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
369
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
370
+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
371
371
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
372
372
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
373
373
···
398
398
399
399
spin_lock_irqsave(core->lock, flags);
400
400
401
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
402
-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
401
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
402
+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
403
403
404
404
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
405
405
core->layout->endiv_mask, 0);
406
406
407
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
408
-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
409
-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
407
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
408
+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
409
+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
410
410
411
411
spin_unlock_irqrestore(core->lock, flags);
412
412
}
···
518
518
div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
519
519
520
520
spin_lock_irqsave(core->lock, irqflags);
521
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
522
-
core->id);
521
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
522
+
core->id);
523
523
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
524
524
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
525
525
···
574
574
div->div = div->safe_div;
575
575
576
576
spin_lock_irqsave(core.lock, irqflags);
577
-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
578
-
core.id);
577
+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
578
+
core.id);
579
579
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
580
580
cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
581
581
+1
drivers/clk/at91/pmc.h
+1
drivers/clk/at91/pmc.h
+2
drivers/clk/at91/sam9x60.c
+2
drivers/clk/at91/sam9x60.c
···
36
36
.num_output = ARRAY_SIZE(plla_outputs),
37
37
.output = plla_outputs,
38
38
.core_output = core_outputs,
39
+
.acr = UL(0x00020010),
39
40
};
40
41
41
42
static const struct clk_range upll_outputs[] = {
···
49
48
.output = upll_outputs,
50
49
.core_output = core_outputs,
51
50
.upll = true,
51
+
.acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/
52
52
};
53
53
54
54
static const struct clk_pll_layout pll_frac_layout = {
+6
drivers/clk/at91/sam9x7.c
+6
drivers/clk/at91/sam9x7.c
···
107
107
.num_output = ARRAY_SIZE(plla_outputs),
108
108
.output = plla_outputs,
109
109
.core_output = plla_core_outputs,
110
+
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
110
111
};
111
112
112
113
static const struct clk_pll_characteristics upll_characteristics = {
···
116
115
.output = upll_outputs,
117
116
.core_output = upll_core_outputs,
118
117
.upll = true,
118
+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
119
119
};
120
120
121
121
static const struct clk_pll_characteristics lvdspll_characteristics = {
···
124
122
.num_output = ARRAY_SIZE(lvdspll_outputs),
125
123
.output = lvdspll_outputs,
126
124
.core_output = lvdspll_core_outputs,
125
+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
127
126
};
128
127
129
128
static const struct clk_pll_characteristics audiopll_characteristics = {
···
132
129
.num_output = ARRAY_SIZE(audiopll_outputs),
133
130
.output = audiopll_outputs,
134
131
.core_output = audiopll_core_outputs,
132
+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
135
133
};
136
134
137
135
static const struct clk_pll_characteristics plladiv2_characteristics = {
···
140
136
.num_output = ARRAY_SIZE(plladiv2_outputs),
141
137
.output = plladiv2_outputs,
142
138
.core_output = plladiv2_core_outputs,
139
+
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
143
140
};
144
141
145
142
/* Layout for fractional PLL ID PLLA. */
···
408
403
{ .n = "pioD_clk", .id = 44, },
409
404
{ .n = "tcb1_clk", .id = 45, },
410
405
{ .n = "dbgu_clk", .id = 47, },
406
+
{ .n = "pmecc_clk", .id = 48, },
411
407
/*
412
408
* mpddr_clk feeds DDR controller and is enabled by bootloader thus we
413
409
* need to keep it enabled in case there is no Linux consumer for it.
+4
drivers/clk/at91/sama7d65.c
+4
drivers/clk/at91/sama7d65.c
···
138
138
.num_output = ARRAY_SIZE(cpu_pll_outputs),
139
139
.output = cpu_pll_outputs,
140
140
.core_output = core_outputs,
141
+
.acr = UL(0x00070010),
141
142
};
142
143
143
144
/* PLL characteristics. */
···
147
146
.num_output = ARRAY_SIZE(pll_outputs),
148
147
.output = pll_outputs,
149
148
.core_output = core_outputs,
149
+
.acr = UL(0x00070010),
150
150
};
151
151
152
152
static const struct clk_pll_characteristics lvdspll_characteristics = {
···
155
153
.num_output = ARRAY_SIZE(lvdspll_outputs),
156
154
.output = lvdspll_outputs,
157
155
.core_output = lvdspll_core_outputs,
156
+
.acr = UL(0x00070010),
158
157
};
159
158
160
159
static const struct clk_pll_characteristics upll_characteristics = {
···
163
160
.num_output = ARRAY_SIZE(upll_outputs),
164
161
.output = upll_outputs,
165
162
.core_output = upll_core_outputs,
163
+
.acr = UL(0x12020010),
166
164
.upll = true,
167
165
};
168
166
+2
drivers/clk/at91/sama7g5.c
+2
drivers/clk/at91/sama7g5.c
···
113
113
.num_output = ARRAY_SIZE(cpu_pll_outputs),
114
114
.output = cpu_pll_outputs,
115
115
.core_output = core_outputs,
116
+
.acr = UL(0x00070010),
116
117
};
117
118
118
119
/* PLL characteristics. */
···
122
121
.num_output = ARRAY_SIZE(pll_outputs),
123
122
.output = pll_outputs,
124
123
.core_output = core_outputs,
124
+
.acr = UL(0x00070010),
125
125
};
126
126
127
127
/*
+26
-40
drivers/clk/clk.c
+26
-40
drivers/clk/clk.c
···
6
6
* Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
7
7
*/
8
8
9
+
#include <linux/clk/clk-conf.h>
10
+
#include <linux/clkdev.h>
9
11
#include <linux/clk.h>
10
12
#include <linux/clk-provider.h>
11
-
#include <linux/clk/clk-conf.h>
13
+
#include <linux/device.h>
14
+
#include <linux/err.h>
15
+
#include <linux/hashtable.h>
16
+
#include <linux/init.h>
17
+
#include <linux/list.h>
12
18
#include <linux/module.h>
13
19
#include <linux/mutex.h>
14
-
#include <linux/spinlock.h>
15
-
#include <linux/err.h>
16
-
#include <linux/list.h>
17
-
#include <linux/slab.h>
18
20
#include <linux/of.h>
19
-
#include <linux/device.h>
20
-
#include <linux/init.h>
21
21
#include <linux/pm_runtime.h>
22
22
#include <linux/sched.h>
23
-
#include <linux/clkdev.h>
23
+
#include <linux/slab.h>
24
+
#include <linux/spinlock.h>
25
+
#include <linux/string.h>
26
+
#include <linux/stringhash.h>
24
27
25
28
#include "clk.h"
26
29
···
35
32
36
33
static int prepare_refcnt;
37
34
static int enable_refcnt;
35
+
36
+
#define CLK_HASH_BITS 9
37
+
static DEFINE_HASHTABLE(clk_hashtable, CLK_HASH_BITS);
38
38
39
39
static HLIST_HEAD(clk_root_list);
40
40
static HLIST_HEAD(clk_orphan_list);
···
93
87
struct clk_duty duty;
94
88
struct hlist_head children;
95
89
struct hlist_node child_node;
90
+
struct hlist_node hashtable_node;
96
91
struct hlist_head clks;
97
92
unsigned int notifier_count;
98
93
#ifdef CONFIG_DEBUG_FS
···
402
395
}
403
396
EXPORT_SYMBOL_GPL(clk_hw_get_parent);
404
397
405
-
static struct clk_core *__clk_lookup_subtree(const char *name,
406
-
struct clk_core *core)
407
-
{
408
-
struct clk_core *child;
409
-
struct clk_core *ret;
410
-
411
-
if (!strcmp(core->name, name))
412
-
return core;
413
-
414
-
hlist_for_each_entry(child, &core->children, child_node) {
415
-
ret = __clk_lookup_subtree(name, child);
416
-
if (ret)
417
-
return ret;
418
-
}
419
-
420
-
return NULL;
421
-
}
422
-
423
398
static struct clk_core *clk_core_lookup(const char *name)
424
399
{
425
-
struct clk_core *root_clk;
426
-
struct clk_core *ret;
400
+
struct clk_core *core;
401
+
u32 hash;
427
402
428
403
if (!name)
429
404
return NULL;
430
405
431
-
/* search the 'proper' clk tree first */
432
-
hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
433
-
ret = __clk_lookup_subtree(name, root_clk);
434
-
if (ret)
435
-
return ret;
436
-
}
406
+
hash = full_name_hash(NULL, name, strlen(name));
437
407
438
-
/* if not found, then search the orphan tree */
439
-
hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
440
-
ret = __clk_lookup_subtree(name, root_clk);
441
-
if (ret)
442
-
return ret;
443
-
}
408
+
/* search the hashtable */
409
+
hash_for_each_possible(clk_hashtable, core, hashtable_node, hash)
410
+
if (!strcmp(core->name, name))
411
+
return core;
444
412
445
413
return NULL;
446
414
}
···
3995
4013
hlist_add_head(&core->child_node, &clk_orphan_list);
3996
4014
core->orphan = true;
3997
4015
}
4016
+
hash_add(clk_hashtable, &core->hashtable_node,
4017
+
full_name_hash(NULL, core->name, strlen(core->name)));
3998
4018
3999
4019
/*
4000
4020
* Set clk's accuracy. The preferred method is to use
···
4073
4089
clk_pm_runtime_put(core);
4074
4090
unlock:
4075
4091
if (ret) {
4092
+
hash_del(&core->hashtable_node);
4076
4093
hlist_del_init(&core->child_node);
4077
4094
core->hw->core = NULL;
4078
4095
}
···
4595
4610
4596
4611
clk_core_evict_parent_cache(clk->core);
4597
4612
4613
+
hash_del(&clk->core->hashtable_node);
4598
4614
hlist_del_init(&clk->core->child_node);
4599
4615
4600
4616
if (clk->core->prepare_count)
+7
drivers/clk/stm32/Kconfig
+7
drivers/clk/stm32/Kconfig
···
25
25
help
26
26
Support for stm32mp15x SoC family clocks.
27
27
28
+
config COMMON_CLK_STM32MP215
29
+
bool "Clock driver for stm32mp21x clocks"
30
+
depends on ARM || ARM64 || COMPILE_TEST
31
+
default y
32
+
help
33
+
Support for stm32mp21x SoC family clocks
34
+
28
35
config COMMON_CLK_STM32MP257
29
36
bool "Clock driver for stm32mp25x clocks"
30
37
depends on ARM64 || COMPILE_TEST
+1
drivers/clk/stm32/Makefile
+1
drivers/clk/stm32/Makefile
···
1
1
obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
2
2
obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
3
+
obj-$(CONFIG_COMMON_CLK_STM32MP215) += clk-stm32mp21.o clk-stm32-core.o reset-stm32.o
3
4
obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o clk-stm32-core.o reset-stm32.o
+1586
drivers/clk/stm32/clk-stm32mp21.c
+1586
drivers/clk/stm32/clk-stm32mp21.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4
+
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5
+
*/
6
+
7
+
#include <linux/bus/stm32_firewall_device.h>
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/io.h>
10
+
#include <linux/platform_device.h>
11
+
12
+
#include "clk-stm32-core.h"
13
+
#include "reset-stm32.h"
14
+
#include "stm32mp21_rcc.h"
15
+
16
+
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
17
+
#include <dt-bindings/reset/st,stm32mp21-rcc.h>
18
+
19
+
/* Max clock binding value */
20
+
#define STM32MP21_LAST_CLK CK_SCMI_KER_ETR
21
+
22
+
/* Clock security definition */
23
+
#define SECF_NONE -1
24
+
25
+
#define RCC_REG_SIZE 32
26
+
#define RCC_SECCFGR(x) (((x) / RCC_REG_SIZE) * 0x4 + RCC_SECCFGR0)
27
+
#define RCC_CIDCFGR(x) ((x) * 0x8 + RCC_R0CIDCFGR)
28
+
#define RCC_SEMCR(x) ((x) * 0x8 + RCC_R0SEMCR)
29
+
#define RCC_CID1 1
30
+
31
+
/* Register: RIFSC_CIDCFGR */
32
+
#define RCC_CIDCFGR_CFEN BIT(0)
33
+
#define RCC_CIDCFGR_SEM_EN BIT(1)
34
+
#define RCC_CIDCFGR_SEMWLC1_EN BIT(17)
35
+
#define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4)
36
+
37
+
/* Register: RIFSC_SEMCR */
38
+
#define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4)
39
+
40
+
#define MP21_RIF_RCC_MCO1 108
41
+
#define MP21_RIF_RCC_MCO2 109
42
+
43
+
#define SEC_RIFSC_FLAG BIT(31)
44
+
#define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG)
45
+
46
+
enum {
47
+
HSE,
48
+
HSI,
49
+
MSI,
50
+
LSE,
51
+
LSI,
52
+
HSE_DIV2,
53
+
ICN_HS_MCU,
54
+
ICN_LS_MCU,
55
+
ICN_SDMMC,
56
+
ICN_DDR,
57
+
ICN_DISPLAY,
58
+
ICN_HSL,
59
+
ICN_NIC,
60
+
FLEXGEN_07,
61
+
FLEXGEN_08,
62
+
FLEXGEN_09,
63
+
FLEXGEN_10,
64
+
FLEXGEN_11,
65
+
FLEXGEN_12,
66
+
FLEXGEN_13,
67
+
FLEXGEN_14,
68
+
FLEXGEN_16,
69
+
FLEXGEN_17,
70
+
FLEXGEN_18,
71
+
FLEXGEN_19,
72
+
FLEXGEN_20,
73
+
FLEXGEN_21,
74
+
FLEXGEN_22,
75
+
FLEXGEN_23,
76
+
FLEXGEN_24,
77
+
FLEXGEN_25,
78
+
FLEXGEN_26,
79
+
FLEXGEN_27,
80
+
FLEXGEN_29,
81
+
FLEXGEN_30,
82
+
FLEXGEN_31,
83
+
FLEXGEN_33,
84
+
FLEXGEN_36,
85
+
FLEXGEN_37,
86
+
FLEXGEN_38,
87
+
FLEXGEN_39,
88
+
FLEXGEN_40,
89
+
FLEXGEN_41,
90
+
FLEXGEN_42,
91
+
FLEXGEN_43,
92
+
FLEXGEN_44,
93
+
FLEXGEN_45,
94
+
FLEXGEN_46,
95
+
FLEXGEN_47,
96
+
FLEXGEN_48,
97
+
FLEXGEN_50,
98
+
FLEXGEN_51,
99
+
FLEXGEN_52,
100
+
FLEXGEN_53,
101
+
FLEXGEN_54,
102
+
FLEXGEN_55,
103
+
FLEXGEN_56,
104
+
FLEXGEN_57,
105
+
FLEXGEN_58,
106
+
FLEXGEN_61,
107
+
FLEXGEN_62,
108
+
FLEXGEN_63,
109
+
ICN_APB1,
110
+
ICN_APB2,
111
+
ICN_APB3,
112
+
ICN_APB4,
113
+
ICN_APB5,
114
+
ICN_APBDBG,
115
+
TIMG1,
116
+
TIMG2,
117
+
};
118
+
119
+
static const struct clk_parent_data adc1_src[] = {
120
+
{ .index = FLEXGEN_46 },
121
+
{ .index = ICN_LS_MCU },
122
+
};
123
+
124
+
static const struct clk_parent_data adc2_src[] = {
125
+
{ .index = FLEXGEN_47 },
126
+
{ .index = ICN_LS_MCU },
127
+
{ .index = FLEXGEN_46 },
128
+
};
129
+
130
+
static const struct clk_parent_data usb2phy1_src[] = {
131
+
{ .index = FLEXGEN_57 },
132
+
{ .index = HSE_DIV2 },
133
+
};
134
+
135
+
static const struct clk_parent_data usb2phy2_src[] = {
136
+
{ .index = FLEXGEN_58 },
137
+
{ .index = HSE_DIV2 },
138
+
};
139
+
140
+
static const struct clk_parent_data dts_src[] = {
141
+
{ .index = HSI },
142
+
{ .index = HSE },
143
+
{ .index = MSI },
144
+
};
145
+
146
+
static const struct clk_parent_data mco1_src[] = {
147
+
{ .index = FLEXGEN_61 },
148
+
};
149
+
150
+
static const struct clk_parent_data mco2_src[] = {
151
+
{ .index = FLEXGEN_62 },
152
+
};
153
+
154
+
enum enum_mux_cfg {
155
+
MUX_ADC1,
156
+
MUX_ADC2,
157
+
MUX_DTS,
158
+
MUX_MCO1,
159
+
MUX_MCO2,
160
+
MUX_USB2PHY1,
161
+
MUX_USB2PHY2,
162
+
MUX_NB
163
+
};
164
+
165
+
#define MUX_CFG(id, _offset, _shift, _width) \
166
+
[id] = { \
167
+
.offset = (_offset), \
168
+
.shift = (_shift), \
169
+
.width = (_width), \
170
+
}
171
+
172
+
static const struct stm32_mux_cfg stm32mp21_muxes[MUX_NB] = {
173
+
MUX_CFG(MUX_ADC1, RCC_ADC1CFGR, 12, 1),
174
+
MUX_CFG(MUX_ADC2, RCC_ADC2CFGR, 12, 2),
175
+
MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2),
176
+
MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1),
177
+
MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1),
178
+
MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1),
179
+
MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1),
180
+
};
181
+
182
+
enum enum_gate_cfg {
183
+
GATE_ADC1,
184
+
GATE_ADC2,
185
+
GATE_CRC,
186
+
GATE_CRYP1,
187
+
GATE_CRYP2,
188
+
GATE_CSI,
189
+
GATE_DCMIPP,
190
+
GATE_DCMIPSSI,
191
+
GATE_DDRPERFM,
192
+
GATE_DTS,
193
+
GATE_ETH1,
194
+
GATE_ETH1MAC,
195
+
GATE_ETH1RX,
196
+
GATE_ETH1STP,
197
+
GATE_ETH1TX,
198
+
GATE_ETH2,
199
+
GATE_ETH2MAC,
200
+
GATE_ETH2RX,
201
+
GATE_ETH2STP,
202
+
GATE_ETH2TX,
203
+
GATE_FDCAN,
204
+
GATE_HASH1,
205
+
GATE_HASH2,
206
+
GATE_HDP,
207
+
GATE_I2C1,
208
+
GATE_I2C2,
209
+
GATE_I2C3,
210
+
GATE_I3C1,
211
+
GATE_I3C2,
212
+
GATE_I3C3,
213
+
GATE_IWDG1,
214
+
GATE_IWDG2,
215
+
GATE_IWDG3,
216
+
GATE_IWDG4,
217
+
GATE_LPTIM1,
218
+
GATE_LPTIM2,
219
+
GATE_LPTIM3,
220
+
GATE_LPTIM4,
221
+
GATE_LPTIM5,
222
+
GATE_LPUART1,
223
+
GATE_LTDC,
224
+
GATE_MCO1,
225
+
GATE_MCO2,
226
+
GATE_MDF1,
227
+
GATE_OTG,
228
+
GATE_PKA,
229
+
GATE_RNG1,
230
+
GATE_RNG2,
231
+
GATE_SAES,
232
+
GATE_SAI1,
233
+
GATE_SAI2,
234
+
GATE_SAI3,
235
+
GATE_SAI4,
236
+
GATE_SDMMC1,
237
+
GATE_SDMMC2,
238
+
GATE_SDMMC3,
239
+
GATE_SERC,
240
+
GATE_SPDIFRX,
241
+
GATE_SPI1,
242
+
GATE_SPI2,
243
+
GATE_SPI3,
244
+
GATE_SPI4,
245
+
GATE_SPI5,
246
+
GATE_SPI6,
247
+
GATE_TIM1,
248
+
GATE_TIM10,
249
+
GATE_TIM11,
250
+
GATE_TIM12,
251
+
GATE_TIM13,
252
+
GATE_TIM14,
253
+
GATE_TIM15,
254
+
GATE_TIM16,
255
+
GATE_TIM17,
256
+
GATE_TIM2,
257
+
GATE_TIM3,
258
+
GATE_TIM4,
259
+
GATE_TIM5,
260
+
GATE_TIM6,
261
+
GATE_TIM7,
262
+
GATE_TIM8,
263
+
GATE_UART4,
264
+
GATE_UART5,
265
+
GATE_UART7,
266
+
GATE_USART1,
267
+
GATE_USART2,
268
+
GATE_USART3,
269
+
GATE_USART6,
270
+
GATE_USB2PHY1,
271
+
GATE_USB2PHY2,
272
+
GATE_USBH,
273
+
GATE_VREF,
274
+
GATE_WWDG1,
275
+
GATE_NB
276
+
};
277
+
278
+
#define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \
279
+
[id] = { \
280
+
.offset = (_offset), \
281
+
.bit_idx = (_bit_idx), \
282
+
.set_clr = (_offset_clr), \
283
+
}
284
+
285
+
static const struct stm32_gate_cfg stm32mp21_gates[GATE_NB] = {
286
+
GATE_CFG(GATE_ADC1, RCC_ADC1CFGR, 1, 0),
287
+
GATE_CFG(GATE_ADC2, RCC_ADC2CFGR, 1, 0),
288
+
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
289
+
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
290
+
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
291
+
GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
292
+
GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
293
+
GATE_CFG(GATE_DCMIPSSI, RCC_DCMIPSSICFGR, 1, 0),
294
+
GATE_CFG(GATE_DDRPERFM, RCC_DDRPERFMCFGR, 1, 0),
295
+
GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
296
+
GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
297
+
GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
298
+
GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
299
+
GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
300
+
GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
301
+
GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
302
+
GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
303
+
GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
304
+
GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
305
+
GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
306
+
GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
307
+
GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
308
+
GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
309
+
GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
310
+
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
311
+
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
312
+
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
313
+
GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
314
+
GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
315
+
GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
316
+
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
317
+
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
318
+
GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
319
+
GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
320
+
GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
321
+
GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
322
+
GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
323
+
GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
324
+
GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
325
+
GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
326
+
GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
327
+
GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
328
+
GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
329
+
GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
330
+
GATE_CFG(GATE_OTG, RCC_OTGCFGR, 1, 0),
331
+
GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
332
+
GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
333
+
GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
334
+
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
335
+
GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
336
+
GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
337
+
GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
338
+
GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
339
+
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
340
+
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
341
+
GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
342
+
GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
343
+
GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
344
+
GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
345
+
GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
346
+
GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
347
+
GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
348
+
GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
349
+
GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
350
+
GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
351
+
GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
352
+
GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
353
+
GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
354
+
GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
355
+
GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
356
+
GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
357
+
GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
358
+
GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
359
+
GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
360
+
GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
361
+
GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
362
+
GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
363
+
GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
364
+
GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
365
+
GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
366
+
GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
367
+
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
368
+
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
369
+
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
370
+
GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
371
+
GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
372
+
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
373
+
GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
374
+
GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
375
+
GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),
376
+
GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
377
+
GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
378
+
};
379
+
380
+
#define CLK_HW_INIT_INDEX(_name, _parent, _ops, _flags) \
381
+
(&(struct clk_init_data) { \
382
+
.flags = _flags, \
383
+
.name = _name, \
384
+
.parent_data = (const struct clk_parent_data[]) { \
385
+
{ .index = _parent }, \
386
+
}, \
387
+
.num_parents = 1, \
388
+
.ops = _ops, \
389
+
})
390
+
391
+
/* ADC */
392
+
static struct clk_stm32_gate ck_icn_p_adc1 = {
393
+
.gate_id = GATE_ADC1,
394
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
395
+
};
396
+
397
+
static struct clk_stm32_composite ck_ker_adc1 = {
398
+
.gate_id = GATE_ADC1,
399
+
.mux_id = MUX_ADC1,
400
+
.div_id = NO_STM32_DIV,
401
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc1", adc1_src, &clk_stm32_composite_ops, 0),
402
+
};
403
+
404
+
static struct clk_stm32_gate ck_icn_p_adc2 = {
405
+
.gate_id = GATE_ADC2,
406
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
407
+
};
408
+
409
+
static struct clk_stm32_composite ck_ker_adc2 = {
410
+
.gate_id = GATE_ADC2,
411
+
.mux_id = MUX_ADC2,
412
+
.div_id = NO_STM32_DIV,
413
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc2", adc2_src, &clk_stm32_composite_ops, 0),
414
+
};
415
+
416
+
/* CSI-HOST */
417
+
static struct clk_stm32_gate ck_icn_p_csi = {
418
+
.gate_id = GATE_CSI,
419
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0),
420
+
};
421
+
422
+
static struct clk_stm32_gate ck_ker_csi = {
423
+
.gate_id = GATE_CSI,
424
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0),
425
+
};
426
+
427
+
static struct clk_stm32_gate ck_ker_csitxesc = {
428
+
.gate_id = GATE_CSI,
429
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0),
430
+
};
431
+
432
+
/* CSI-PHY */
433
+
static struct clk_stm32_gate ck_ker_csiphy = {
434
+
.gate_id = GATE_CSI,
435
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csiphy", FLEXGEN_31, &clk_stm32_gate_ops, 0),
436
+
};
437
+
438
+
/* DCMIPP */
439
+
static struct clk_stm32_gate ck_icn_p_dcmipp = {
440
+
.gate_id = GATE_DCMIPP,
441
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipp", ICN_APB4, &clk_stm32_gate_ops, 0),
442
+
};
443
+
444
+
static struct clk_stm32_gate ck_icn_p_dcmipssi = {
445
+
.gate_id = GATE_DCMIPSSI,
446
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipssi", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
447
+
};
448
+
449
+
/* DDRPERMF */
450
+
static struct clk_stm32_gate ck_icn_p_ddrperfm = {
451
+
.gate_id = GATE_DDRPERFM,
452
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ddrperfm", ICN_APB4, &clk_stm32_gate_ops, 0),
453
+
};
454
+
455
+
/* CRC */
456
+
static struct clk_stm32_gate ck_icn_p_crc = {
457
+
.gate_id = GATE_CRC,
458
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_crc", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
459
+
};
460
+
461
+
/* CRYP */
462
+
static struct clk_stm32_gate ck_icn_p_cryp1 = {
463
+
.gate_id = GATE_CRYP1,
464
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
465
+
};
466
+
467
+
static struct clk_stm32_gate ck_icn_p_cryp2 = {
468
+
.gate_id = GATE_CRYP2,
469
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
470
+
};
471
+
472
+
/* DBG & TRACE */
473
+
/* Trace and debug clocks are managed by SCMI */
474
+
475
+
/* LTDC */
476
+
static struct clk_stm32_gate ck_icn_p_ltdc = {
477
+
.gate_id = GATE_LTDC,
478
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ltdc", ICN_APB4, &clk_stm32_gate_ops, 0),
479
+
};
480
+
481
+
static struct clk_stm32_gate ck_ker_ltdc = {
482
+
.gate_id = GATE_LTDC,
483
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ltdc", FLEXGEN_27, &clk_stm32_gate_ops,
484
+
CLK_SET_RATE_PARENT),
485
+
};
486
+
487
+
/* DTS */
488
+
static struct clk_stm32_composite ck_ker_dts = {
489
+
.gate_id = GATE_DTS,
490
+
.mux_id = MUX_DTS,
491
+
.div_id = NO_STM32_DIV,
492
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_dts", dts_src,
493
+
&clk_stm32_composite_ops, 0),
494
+
};
495
+
496
+
/* ETHERNET */
497
+
static struct clk_stm32_gate ck_icn_p_eth1 = {
498
+
.gate_id = GATE_ETH1,
499
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
500
+
};
501
+
502
+
static struct clk_stm32_gate ck_ker_eth1stp = {
503
+
.gate_id = GATE_ETH1STP,
504
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
505
+
};
506
+
507
+
static struct clk_stm32_gate ck_ker_eth1 = {
508
+
.gate_id = GATE_ETH1,
509
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1", FLEXGEN_54, &clk_stm32_gate_ops, 0),
510
+
};
511
+
512
+
static struct clk_stm32_gate ck_ker_eth1ptp = {
513
+
.gate_id = GATE_ETH1,
514
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
515
+
};
516
+
517
+
static struct clk_stm32_gate ck_ker_eth1mac = {
518
+
.gate_id = GATE_ETH1MAC,
519
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
520
+
};
521
+
522
+
static struct clk_stm32_gate ck_ker_eth1tx = {
523
+
.gate_id = GATE_ETH1TX,
524
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
525
+
};
526
+
527
+
static struct clk_stm32_gate ck_ker_eth1rx = {
528
+
.gate_id = GATE_ETH1RX,
529
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
530
+
};
531
+
532
+
static struct clk_stm32_gate ck_icn_p_eth2 = {
533
+
.gate_id = GATE_ETH2,
534
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
535
+
};
536
+
537
+
static struct clk_stm32_gate ck_ker_eth2stp = {
538
+
.gate_id = GATE_ETH2STP,
539
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
540
+
};
541
+
542
+
static struct clk_stm32_gate ck_ker_eth2 = {
543
+
.gate_id = GATE_ETH2,
544
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2", FLEXGEN_55, &clk_stm32_gate_ops, 0),
545
+
};
546
+
547
+
static struct clk_stm32_gate ck_ker_eth2ptp = {
548
+
.gate_id = GATE_ETH2,
549
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
550
+
};
551
+
552
+
static struct clk_stm32_gate ck_ker_eth2mac = {
553
+
.gate_id = GATE_ETH2MAC,
554
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
555
+
};
556
+
557
+
static struct clk_stm32_gate ck_ker_eth2tx = {
558
+
.gate_id = GATE_ETH2TX,
559
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
560
+
};
561
+
562
+
static struct clk_stm32_gate ck_ker_eth2rx = {
563
+
.gate_id = GATE_ETH2RX,
564
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
565
+
};
566
+
567
+
/* FDCAN */
568
+
static struct clk_stm32_gate ck_icn_p_fdcan = {
569
+
.gate_id = GATE_FDCAN,
570
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_fdcan", ICN_APB2, &clk_stm32_gate_ops, 0),
571
+
};
572
+
573
+
static struct clk_stm32_gate ck_ker_fdcan = {
574
+
.gate_id = GATE_FDCAN,
575
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_fdcan", FLEXGEN_26, &clk_stm32_gate_ops, 0),
576
+
};
577
+
578
+
/* HASH */
579
+
static struct clk_stm32_gate ck_icn_p_hash1 = {
580
+
.gate_id = GATE_HASH1,
581
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
582
+
};
583
+
584
+
static struct clk_stm32_gate ck_icn_p_hash2 = {
585
+
.gate_id = GATE_HASH2,
586
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
587
+
};
588
+
589
+
/* HDP */
590
+
static struct clk_stm32_gate ck_icn_p_hdp = {
591
+
.gate_id = GATE_HDP,
592
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hdp", ICN_APB3, &clk_stm32_gate_ops, 0),
593
+
};
594
+
595
+
/* I2C */
596
+
static struct clk_stm32_gate ck_icn_p_i2c1 = {
597
+
.gate_id = GATE_I2C1,
598
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c1", ICN_APB1, &clk_stm32_gate_ops, 0),
599
+
};
600
+
601
+
static struct clk_stm32_gate ck_icn_p_i2c2 = {
602
+
.gate_id = GATE_I2C2,
603
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c2", ICN_APB1, &clk_stm32_gate_ops, 0),
604
+
};
605
+
606
+
static struct clk_stm32_gate ck_icn_p_i2c3 = {
607
+
.gate_id = GATE_I2C3,
608
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c3", ICN_APB5, &clk_stm32_gate_ops, 0),
609
+
};
610
+
611
+
static struct clk_stm32_gate ck_ker_i2c1 = {
612
+
.gate_id = GATE_I2C1,
613
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c1", FLEXGEN_13, &clk_stm32_gate_ops, 0),
614
+
};
615
+
616
+
static struct clk_stm32_gate ck_ker_i2c2 = {
617
+
.gate_id = GATE_I2C2,
618
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c2", FLEXGEN_13, &clk_stm32_gate_ops, 0),
619
+
};
620
+
621
+
static struct clk_stm32_gate ck_ker_i2c3 = {
622
+
.gate_id = GATE_I2C3,
623
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c3", FLEXGEN_38, &clk_stm32_gate_ops, 0),
624
+
};
625
+
626
+
/* I3C */
627
+
static struct clk_stm32_gate ck_icn_p_i3c1 = {
628
+
.gate_id = GATE_I3C1,
629
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c1", ICN_APB1, &clk_stm32_gate_ops, 0),
630
+
};
631
+
632
+
static struct clk_stm32_gate ck_icn_p_i3c2 = {
633
+
.gate_id = GATE_I3C2,
634
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c2", ICN_APB1, &clk_stm32_gate_ops, 0),
635
+
};
636
+
637
+
static struct clk_stm32_gate ck_icn_p_i3c3 = {
638
+
.gate_id = GATE_I3C3,
639
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c3", ICN_APB5, &clk_stm32_gate_ops, 0),
640
+
};
641
+
642
+
static struct clk_stm32_gate ck_ker_i3c1 = {
643
+
.gate_id = GATE_I3C1,
644
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c1", FLEXGEN_14, &clk_stm32_gate_ops, 0),
645
+
};
646
+
647
+
static struct clk_stm32_gate ck_ker_i3c2 = {
648
+
.gate_id = GATE_I3C2,
649
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c2", FLEXGEN_14, &clk_stm32_gate_ops, 0),
650
+
};
651
+
652
+
static struct clk_stm32_gate ck_ker_i3c3 = {
653
+
.gate_id = GATE_I3C3,
654
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c3", FLEXGEN_36, &clk_stm32_gate_ops, 0),
655
+
};
656
+
657
+
/* IWDG */
658
+
static struct clk_stm32_gate ck_icn_p_iwdg1 = {
659
+
.gate_id = GATE_IWDG1,
660
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),
661
+
};
662
+
663
+
static struct clk_stm32_gate ck_icn_p_iwdg2 = {
664
+
.gate_id = GATE_IWDG2,
665
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0),
666
+
};
667
+
668
+
static struct clk_stm32_gate ck_icn_p_iwdg3 = {
669
+
.gate_id = GATE_IWDG3,
670
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg3", ICN_APB3, &clk_stm32_gate_ops, 0),
671
+
};
672
+
673
+
static struct clk_stm32_gate ck_icn_p_iwdg4 = {
674
+
.gate_id = GATE_IWDG4,
675
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg4", ICN_APB3, &clk_stm32_gate_ops, 0),
676
+
};
677
+
678
+
/* LPTIM */
679
+
static struct clk_stm32_gate ck_icn_p_lptim1 = {
680
+
.gate_id = GATE_LPTIM1,
681
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim1", ICN_APB1, &clk_stm32_gate_ops, 0),
682
+
};
683
+
684
+
static struct clk_stm32_gate ck_icn_p_lptim2 = {
685
+
.gate_id = GATE_LPTIM2,
686
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim2", ICN_APB1, &clk_stm32_gate_ops, 0),
687
+
};
688
+
689
+
static struct clk_stm32_gate ck_icn_p_lptim3 = {
690
+
.gate_id = GATE_LPTIM3,
691
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
692
+
};
693
+
694
+
static struct clk_stm32_gate ck_icn_p_lptim4 = {
695
+
.gate_id = GATE_LPTIM4,
696
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
697
+
};
698
+
699
+
static struct clk_stm32_gate ck_icn_p_lptim5 = {
700
+
.gate_id = GATE_LPTIM5,
701
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
702
+
};
703
+
704
+
static struct clk_stm32_gate ck_ker_lptim1 = {
705
+
.gate_id = GATE_LPTIM1,
706
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim1", FLEXGEN_07, &clk_stm32_gate_ops, 0),
707
+
};
708
+
709
+
static struct clk_stm32_gate ck_ker_lptim2 = {
710
+
.gate_id = GATE_LPTIM2,
711
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim2", FLEXGEN_07, &clk_stm32_gate_ops, 0),
712
+
};
713
+
714
+
static struct clk_stm32_gate ck_ker_lptim3 = {
715
+
.gate_id = GATE_LPTIM3,
716
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim3", FLEXGEN_40, &clk_stm32_gate_ops, 0),
717
+
};
718
+
719
+
static struct clk_stm32_gate ck_ker_lptim4 = {
720
+
.gate_id = GATE_LPTIM4,
721
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim4", FLEXGEN_41, &clk_stm32_gate_ops, 0),
722
+
};
723
+
724
+
static struct clk_stm32_gate ck_ker_lptim5 = {
725
+
.gate_id = GATE_LPTIM5,
726
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim5", FLEXGEN_42, &clk_stm32_gate_ops, 0),
727
+
};
728
+
729
+
/* LPUART */
730
+
static struct clk_stm32_gate ck_icn_p_lpuart1 = {
731
+
.gate_id = GATE_LPUART1,
732
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lpuart1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
733
+
};
734
+
735
+
static struct clk_stm32_gate ck_ker_lpuart1 = {
736
+
.gate_id = GATE_LPUART1,
737
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lpuart1", FLEXGEN_39, &clk_stm32_gate_ops, 0),
738
+
};
739
+
740
+
/* MCO1 & MCO2 */
741
+
static struct clk_stm32_composite ck_mco1 = {
742
+
.gate_id = GATE_MCO1,
743
+
.mux_id = MUX_MCO1,
744
+
.div_id = NO_STM32_DIV,
745
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco1", mco1_src, &clk_stm32_composite_ops, 0),
746
+
};
747
+
748
+
static struct clk_stm32_composite ck_mco2 = {
749
+
.gate_id = GATE_MCO2,
750
+
.mux_id = MUX_MCO2,
751
+
.div_id = NO_STM32_DIV,
752
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco2", mco2_src, &clk_stm32_composite_ops, 0),
753
+
};
754
+
755
+
/* MDF */
756
+
static struct clk_stm32_gate ck_icn_p_mdf1 = {
757
+
.gate_id = GATE_MDF1,
758
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_mdf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
759
+
};
760
+
761
+
static struct clk_stm32_gate ck_ker_mdf1 = {
762
+
.gate_id = GATE_MDF1,
763
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_mdf1", FLEXGEN_21, &clk_stm32_gate_ops, 0),
764
+
};
765
+
766
+
/* OTG */
767
+
static struct clk_stm32_gate ck_icn_m_otg = {
768
+
.gate_id = GATE_OTG,
769
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_otg", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
770
+
};
771
+
772
+
/* PKA */
773
+
static struct clk_stm32_gate ck_icn_p_pka = {
774
+
.gate_id = GATE_PKA,
775
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pka", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
776
+
};
777
+
778
+
/* RNG */
779
+
static struct clk_stm32_gate ck_icn_p_rng1 = {
780
+
.gate_id = GATE_RNG1,
781
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_rng1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
782
+
};
783
+
784
+
static struct clk_stm32_gate ck_icn_p_rng2 = {
785
+
.gate_id = GATE_RNG2,
786
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_rng2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
787
+
};
788
+
789
+
/* SAES */
790
+
static struct clk_stm32_gate ck_icn_p_saes = {
791
+
.gate_id = GATE_SAES,
792
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_saes", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
793
+
};
794
+
795
+
/* SAI */
796
+
static struct clk_stm32_gate ck_icn_p_sai1 = {
797
+
.gate_id = GATE_SAI1,
798
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai1", ICN_APB2, &clk_stm32_gate_ops, 0),
799
+
};
800
+
801
+
static struct clk_stm32_gate ck_icn_p_sai2 = {
802
+
.gate_id = GATE_SAI2,
803
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai2", ICN_APB2, &clk_stm32_gate_ops, 0),
804
+
};
805
+
806
+
static struct clk_stm32_gate ck_icn_p_sai3 = {
807
+
.gate_id = GATE_SAI3,
808
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai3", ICN_APB2, &clk_stm32_gate_ops, 0),
809
+
};
810
+
811
+
static struct clk_stm32_gate ck_icn_p_sai4 = {
812
+
.gate_id = GATE_SAI4,
813
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai4", ICN_APB2, &clk_stm32_gate_ops, 0),
814
+
};
815
+
816
+
static struct clk_stm32_gate ck_ker_sai1 = {
817
+
.gate_id = GATE_SAI1,
818
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai1", FLEXGEN_22, &clk_stm32_gate_ops,
819
+
CLK_SET_RATE_PARENT),
820
+
};
821
+
822
+
static struct clk_stm32_gate ck_ker_sai2 = {
823
+
.gate_id = GATE_SAI2,
824
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai2", FLEXGEN_23, &clk_stm32_gate_ops,
825
+
CLK_SET_RATE_PARENT),
826
+
};
827
+
828
+
static struct clk_stm32_gate ck_ker_sai3 = {
829
+
.gate_id = GATE_SAI3,
830
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai3", FLEXGEN_24, &clk_stm32_gate_ops,
831
+
CLK_SET_RATE_PARENT),
832
+
};
833
+
834
+
static struct clk_stm32_gate ck_ker_sai4 = {
835
+
.gate_id = GATE_SAI4,
836
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai4", FLEXGEN_25, &clk_stm32_gate_ops,
837
+
CLK_SET_RATE_PARENT),
838
+
};
839
+
840
+
/* SDMMC */
841
+
static struct clk_stm32_gate ck_icn_m_sdmmc1 = {
842
+
.gate_id = GATE_SDMMC1,
843
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc1", ICN_SDMMC, &clk_stm32_gate_ops, 0),
844
+
};
845
+
846
+
static struct clk_stm32_gate ck_icn_m_sdmmc2 = {
847
+
.gate_id = GATE_SDMMC2,
848
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc2", ICN_SDMMC, &clk_stm32_gate_ops, 0),
849
+
};
850
+
851
+
static struct clk_stm32_gate ck_icn_m_sdmmc3 = {
852
+
.gate_id = GATE_SDMMC3,
853
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc3", ICN_SDMMC, &clk_stm32_gate_ops, 0),
854
+
};
855
+
856
+
static struct clk_stm32_gate ck_ker_sdmmc1 = {
857
+
.gate_id = GATE_SDMMC1,
858
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc1", FLEXGEN_51, &clk_stm32_gate_ops, 0),
859
+
};
860
+
861
+
static struct clk_stm32_gate ck_ker_sdmmc2 = {
862
+
.gate_id = GATE_SDMMC2,
863
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc2", FLEXGEN_52, &clk_stm32_gate_ops, 0),
864
+
};
865
+
866
+
static struct clk_stm32_gate ck_ker_sdmmc3 = {
867
+
.gate_id = GATE_SDMMC3,
868
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0),
869
+
};
870
+
871
+
/* SERC */
872
+
static struct clk_stm32_gate ck_icn_p_serc = {
873
+
.gate_id = GATE_SERC,
874
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_serc", ICN_APB3, &clk_stm32_gate_ops, 0),
875
+
};
876
+
877
+
/* SPDIF */
878
+
static struct clk_stm32_gate ck_icn_p_spdifrx = {
879
+
.gate_id = GATE_SPDIFRX,
880
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spdifrx", ICN_APB1, &clk_stm32_gate_ops, 0),
881
+
};
882
+
883
+
static struct clk_stm32_gate ck_ker_spdifrx = {
884
+
.gate_id = GATE_SPDIFRX,
885
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spdifrx", FLEXGEN_12, &clk_stm32_gate_ops, 0),
886
+
};
887
+
888
+
/* SPI */
889
+
static struct clk_stm32_gate ck_icn_p_spi1 = {
890
+
.gate_id = GATE_SPI1,
891
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi1", ICN_APB2, &clk_stm32_gate_ops, 0),
892
+
};
893
+
894
+
static struct clk_stm32_gate ck_icn_p_spi2 = {
895
+
.gate_id = GATE_SPI2,
896
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi2", ICN_APB1, &clk_stm32_gate_ops, 0),
897
+
};
898
+
899
+
static struct clk_stm32_gate ck_icn_p_spi3 = {
900
+
.gate_id = GATE_SPI3,
901
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi3", ICN_APB1, &clk_stm32_gate_ops, 0),
902
+
};
903
+
904
+
static struct clk_stm32_gate ck_icn_p_spi4 = {
905
+
.gate_id = GATE_SPI4,
906
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi4", ICN_APB2, &clk_stm32_gate_ops, 0),
907
+
};
908
+
909
+
static struct clk_stm32_gate ck_icn_p_spi5 = {
910
+
.gate_id = GATE_SPI5,
911
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi5", ICN_APB2, &clk_stm32_gate_ops, 0),
912
+
};
913
+
914
+
static struct clk_stm32_gate ck_icn_p_spi6 = {
915
+
.gate_id = GATE_SPI6,
916
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi6", ICN_APB2, &clk_stm32_gate_ops, 0),
917
+
};
918
+
919
+
static struct clk_stm32_gate ck_ker_spi1 = {
920
+
.gate_id = GATE_SPI1,
921
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi1", FLEXGEN_16, &clk_stm32_gate_ops,
922
+
CLK_SET_RATE_PARENT),
923
+
};
924
+
925
+
static struct clk_stm32_gate ck_ker_spi2 = {
926
+
.gate_id = GATE_SPI2,
927
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi2", FLEXGEN_10, &clk_stm32_gate_ops,
928
+
CLK_SET_RATE_PARENT),
929
+
};
930
+
931
+
static struct clk_stm32_gate ck_ker_spi3 = {
932
+
.gate_id = GATE_SPI3,
933
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi3", FLEXGEN_11, &clk_stm32_gate_ops,
934
+
CLK_SET_RATE_PARENT),
935
+
};
936
+
937
+
static struct clk_stm32_gate ck_ker_spi4 = {
938
+
.gate_id = GATE_SPI4,
939
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi4", FLEXGEN_17, &clk_stm32_gate_ops, 0),
940
+
};
941
+
942
+
static struct clk_stm32_gate ck_ker_spi5 = {
943
+
.gate_id = GATE_SPI5,
944
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi5", FLEXGEN_17, &clk_stm32_gate_ops, 0),
945
+
};
946
+
947
+
static struct clk_stm32_gate ck_ker_spi6 = {
948
+
.gate_id = GATE_SPI6,
949
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi6", FLEXGEN_37, &clk_stm32_gate_ops, 0),
950
+
};
951
+
952
+
/* Timers */
953
+
static struct clk_stm32_gate ck_icn_p_tim2 = {
954
+
.gate_id = GATE_TIM2,
955
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim2", ICN_APB1, &clk_stm32_gate_ops, 0),
956
+
};
957
+
958
+
static struct clk_stm32_gate ck_icn_p_tim3 = {
959
+
.gate_id = GATE_TIM3,
960
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim3", ICN_APB1, &clk_stm32_gate_ops, 0),
961
+
};
962
+
963
+
static struct clk_stm32_gate ck_icn_p_tim4 = {
964
+
.gate_id = GATE_TIM4,
965
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim4", ICN_APB1, &clk_stm32_gate_ops, 0),
966
+
};
967
+
968
+
static struct clk_stm32_gate ck_icn_p_tim5 = {
969
+
.gate_id = GATE_TIM5,
970
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim5", ICN_APB1, &clk_stm32_gate_ops, 0),
971
+
};
972
+
973
+
static struct clk_stm32_gate ck_icn_p_tim6 = {
974
+
.gate_id = GATE_TIM6,
975
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim6", ICN_APB1, &clk_stm32_gate_ops, 0),
976
+
};
977
+
978
+
static struct clk_stm32_gate ck_icn_p_tim7 = {
979
+
.gate_id = GATE_TIM7,
980
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim7", ICN_APB1, &clk_stm32_gate_ops, 0),
981
+
};
982
+
983
+
static struct clk_stm32_gate ck_icn_p_tim10 = {
984
+
.gate_id = GATE_TIM10,
985
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim10", ICN_APB1, &clk_stm32_gate_ops, 0),
986
+
};
987
+
988
+
static struct clk_stm32_gate ck_icn_p_tim11 = {
989
+
.gate_id = GATE_TIM11,
990
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim11", ICN_APB1, &clk_stm32_gate_ops, 0),
991
+
};
992
+
993
+
static struct clk_stm32_gate ck_icn_p_tim12 = {
994
+
.gate_id = GATE_TIM12,
995
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim12", ICN_APB1, &clk_stm32_gate_ops, 0),
996
+
};
997
+
998
+
static struct clk_stm32_gate ck_icn_p_tim13 = {
999
+
.gate_id = GATE_TIM13,
1000
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim13", ICN_APB1, &clk_stm32_gate_ops, 0),
1001
+
};
1002
+
1003
+
static struct clk_stm32_gate ck_icn_p_tim14 = {
1004
+
.gate_id = GATE_TIM14,
1005
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim14", ICN_APB1, &clk_stm32_gate_ops, 0),
1006
+
};
1007
+
1008
+
static struct clk_stm32_gate ck_icn_p_tim1 = {
1009
+
.gate_id = GATE_TIM1,
1010
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim1", ICN_APB2, &clk_stm32_gate_ops, 0),
1011
+
};
1012
+
1013
+
static struct clk_stm32_gate ck_icn_p_tim8 = {
1014
+
.gate_id = GATE_TIM8,
1015
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim8", ICN_APB2, &clk_stm32_gate_ops, 0),
1016
+
};
1017
+
1018
+
static struct clk_stm32_gate ck_icn_p_tim15 = {
1019
+
.gate_id = GATE_TIM15,
1020
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim15", ICN_APB2, &clk_stm32_gate_ops, 0),
1021
+
};
1022
+
1023
+
static struct clk_stm32_gate ck_icn_p_tim16 = {
1024
+
.gate_id = GATE_TIM16,
1025
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim16", ICN_APB2, &clk_stm32_gate_ops, 0),
1026
+
};
1027
+
1028
+
static struct clk_stm32_gate ck_icn_p_tim17 = {
1029
+
.gate_id = GATE_TIM17,
1030
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim17", ICN_APB2, &clk_stm32_gate_ops, 0),
1031
+
};
1032
+
1033
+
static struct clk_stm32_gate ck_ker_tim2 = {
1034
+
.gate_id = GATE_TIM2,
1035
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim2", TIMG1, &clk_stm32_gate_ops, 0),
1036
+
};
1037
+
1038
+
static struct clk_stm32_gate ck_ker_tim3 = {
1039
+
.gate_id = GATE_TIM3,
1040
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim3", TIMG1, &clk_stm32_gate_ops, 0),
1041
+
};
1042
+
1043
+
static struct clk_stm32_gate ck_ker_tim4 = {
1044
+
.gate_id = GATE_TIM4,
1045
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim4", TIMG1, &clk_stm32_gate_ops, 0),
1046
+
};
1047
+
1048
+
static struct clk_stm32_gate ck_ker_tim5 = {
1049
+
.gate_id = GATE_TIM5,
1050
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim5", TIMG1, &clk_stm32_gate_ops, 0),
1051
+
};
1052
+
1053
+
static struct clk_stm32_gate ck_ker_tim6 = {
1054
+
.gate_id = GATE_TIM6,
1055
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim6", TIMG1, &clk_stm32_gate_ops, 0),
1056
+
};
1057
+
1058
+
static struct clk_stm32_gate ck_ker_tim7 = {
1059
+
.gate_id = GATE_TIM7,
1060
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim7", TIMG1, &clk_stm32_gate_ops, 0),
1061
+
};
1062
+
1063
+
static struct clk_stm32_gate ck_ker_tim10 = {
1064
+
.gate_id = GATE_TIM10,
1065
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim10", TIMG1, &clk_stm32_gate_ops, 0),
1066
+
};
1067
+
1068
+
static struct clk_stm32_gate ck_ker_tim11 = {
1069
+
.gate_id = GATE_TIM11,
1070
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim11", TIMG1, &clk_stm32_gate_ops, 0),
1071
+
};
1072
+
1073
+
static struct clk_stm32_gate ck_ker_tim12 = {
1074
+
.gate_id = GATE_TIM12,
1075
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim12", TIMG1, &clk_stm32_gate_ops, 0),
1076
+
};
1077
+
1078
+
static struct clk_stm32_gate ck_ker_tim13 = {
1079
+
.gate_id = GATE_TIM13,
1080
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim13", TIMG1, &clk_stm32_gate_ops, 0),
1081
+
};
1082
+
1083
+
static struct clk_stm32_gate ck_ker_tim14 = {
1084
+
.gate_id = GATE_TIM14,
1085
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim14", TIMG1, &clk_stm32_gate_ops, 0),
1086
+
};
1087
+
1088
+
static struct clk_stm32_gate ck_ker_tim1 = {
1089
+
.gate_id = GATE_TIM1,
1090
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim1", TIMG2, &clk_stm32_gate_ops, 0),
1091
+
};
1092
+
1093
+
static struct clk_stm32_gate ck_ker_tim8 = {
1094
+
.gate_id = GATE_TIM8,
1095
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim8", TIMG2, &clk_stm32_gate_ops, 0),
1096
+
};
1097
+
1098
+
static struct clk_stm32_gate ck_ker_tim15 = {
1099
+
.gate_id = GATE_TIM15,
1100
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim15", TIMG2, &clk_stm32_gate_ops, 0),
1101
+
};
1102
+
1103
+
static struct clk_stm32_gate ck_ker_tim16 = {
1104
+
.gate_id = GATE_TIM16,
1105
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim16", TIMG2, &clk_stm32_gate_ops, 0),
1106
+
};
1107
+
1108
+
static struct clk_stm32_gate ck_ker_tim17 = {
1109
+
.gate_id = GATE_TIM17,
1110
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim17", TIMG2, &clk_stm32_gate_ops, 0),
1111
+
};
1112
+
1113
+
/* UART/USART */
1114
+
static struct clk_stm32_gate ck_icn_p_usart2 = {
1115
+
.gate_id = GATE_USART2,
1116
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart2", ICN_APB1, &clk_stm32_gate_ops, 0),
1117
+
};
1118
+
1119
+
static struct clk_stm32_gate ck_icn_p_usart3 = {
1120
+
.gate_id = GATE_USART3,
1121
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart3", ICN_APB1, &clk_stm32_gate_ops, 0),
1122
+
};
1123
+
1124
+
static struct clk_stm32_gate ck_icn_p_uart4 = {
1125
+
.gate_id = GATE_UART4,
1126
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart4", ICN_APB1, &clk_stm32_gate_ops, 0),
1127
+
};
1128
+
1129
+
static struct clk_stm32_gate ck_icn_p_uart5 = {
1130
+
.gate_id = GATE_UART5,
1131
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart5", ICN_APB1, &clk_stm32_gate_ops, 0),
1132
+
};
1133
+
1134
+
static struct clk_stm32_gate ck_icn_p_usart1 = {
1135
+
.gate_id = GATE_USART1,
1136
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart1", ICN_APB2, &clk_stm32_gate_ops, 0),
1137
+
};
1138
+
1139
+
static struct clk_stm32_gate ck_icn_p_usart6 = {
1140
+
.gate_id = GATE_USART6,
1141
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart6", ICN_APB2, &clk_stm32_gate_ops, 0),
1142
+
};
1143
+
1144
+
static struct clk_stm32_gate ck_icn_p_uart7 = {
1145
+
.gate_id = GATE_UART7,
1146
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart7", ICN_APB2, &clk_stm32_gate_ops, 0),
1147
+
};
1148
+
1149
+
static struct clk_stm32_gate ck_ker_usart2 = {
1150
+
.gate_id = GATE_USART2,
1151
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart2", FLEXGEN_08, &clk_stm32_gate_ops, 0),
1152
+
};
1153
+
1154
+
static struct clk_stm32_gate ck_ker_uart4 = {
1155
+
.gate_id = GATE_UART4,
1156
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart4", FLEXGEN_08, &clk_stm32_gate_ops, 0),
1157
+
};
1158
+
1159
+
static struct clk_stm32_gate ck_ker_usart3 = {
1160
+
.gate_id = GATE_USART3,
1161
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart3", FLEXGEN_09, &clk_stm32_gate_ops, 0),
1162
+
};
1163
+
1164
+
static struct clk_stm32_gate ck_ker_uart5 = {
1165
+
.gate_id = GATE_UART5,
1166
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart5", FLEXGEN_09, &clk_stm32_gate_ops, 0),
1167
+
};
1168
+
1169
+
static struct clk_stm32_gate ck_ker_usart1 = {
1170
+
.gate_id = GATE_USART1,
1171
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart1", FLEXGEN_18, &clk_stm32_gate_ops, 0),
1172
+
};
1173
+
1174
+
static struct clk_stm32_gate ck_ker_usart6 = {
1175
+
.gate_id = GATE_USART6,
1176
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart6", FLEXGEN_19, &clk_stm32_gate_ops, 0),
1177
+
};
1178
+
1179
+
static struct clk_stm32_gate ck_ker_uart7 = {
1180
+
.gate_id = GATE_UART7,
1181
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart7", FLEXGEN_20, &clk_stm32_gate_ops, 0),
1182
+
};
1183
+
1184
+
/* USB2PHY1 */
1185
+
static struct clk_stm32_composite ck_ker_usb2phy1 = {
1186
+
.gate_id = GATE_USB2PHY1,
1187
+
.mux_id = MUX_USB2PHY1,
1188
+
.div_id = NO_STM32_DIV,
1189
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy1", usb2phy1_src,
1190
+
&clk_stm32_composite_ops, 0),
1191
+
};
1192
+
1193
+
/* USBH */
1194
+
static struct clk_stm32_gate ck_icn_m_usbhehci = {
1195
+
.gate_id = GATE_USBH,
1196
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usbhehci", ICN_HSL, &clk_stm32_gate_ops, 0),
1197
+
};
1198
+
1199
+
static struct clk_stm32_gate ck_icn_m_usbhohci = {
1200
+
.gate_id = GATE_USBH,
1201
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usbhohci", ICN_HSL, &clk_stm32_gate_ops, 0),
1202
+
};
1203
+
1204
+
/* USB2PHY2 */
1205
+
static struct clk_stm32_composite ck_ker_usb2phy2_en = {
1206
+
.gate_id = GATE_USB2PHY2,
1207
+
.mux_id = MUX_USB2PHY2,
1208
+
.div_id = NO_STM32_DIV,
1209
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy2_en", usb2phy2_src,
1210
+
&clk_stm32_composite_ops, 0),
1211
+
};
1212
+
1213
+
/* VREF */
1214
+
static struct clk_stm32_gate ck_icn_p_vref = {
1215
+
.gate_id = GATE_VREF,
1216
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vref", ICN_APB3, &clk_stm32_gate_ops, 0),
1217
+
};
1218
+
1219
+
/* WWDG */
1220
+
static struct clk_stm32_gate ck_icn_p_wwdg1 = {
1221
+
.gate_id = GATE_WWDG1,
1222
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),
1223
+
};
1224
+
1225
+
static int stm32_rcc_get_access(void __iomem *base, u32 index)
1226
+
{
1227
+
u32 seccfgr, cidcfgr, semcr;
1228
+
int bit, cid;
1229
+
1230
+
bit = index % RCC_REG_SIZE;
1231
+
1232
+
seccfgr = readl(base + RCC_SECCFGR(index));
1233
+
if (seccfgr & BIT(bit))
1234
+
return -EACCES;
1235
+
1236
+
cidcfgr = readl(base + RCC_CIDCFGR(index));
1237
+
if (!(cidcfgr & RCC_CIDCFGR_CFEN))
1238
+
/* CID filtering is turned off: access granted */
1239
+
return 0;
1240
+
1241
+
if (!(cidcfgr & RCC_CIDCFGR_SEM_EN)) {
1242
+
/* Static CID mode */
1243
+
cid = FIELD_GET(RCC_CIDCFGR_SCID_MASK, cidcfgr);
1244
+
if (cid != RCC_CID1)
1245
+
return -EACCES;
1246
+
return 0;
1247
+
}
1248
+
1249
+
/* Pass-list with semaphore mode */
1250
+
if (!(cidcfgr & RCC_CIDCFGR_SEMWLC1_EN))
1251
+
return -EACCES;
1252
+
1253
+
semcr = readl(base + RCC_SEMCR(index));
1254
+
1255
+
cid = FIELD_GET(RCC_SEMCR_SEMCID_MASK, semcr);
1256
+
if (cid != RCC_CID1)
1257
+
return -EACCES;
1258
+
1259
+
return 0;
1260
+
}
1261
+
1262
+
static int stm32mp21_check_security(struct device_node *np, void __iomem *base,
1263
+
const struct clock_config *cfg)
1264
+
{
1265
+
int ret = 0;
1266
+
1267
+
if (cfg->sec_id != SECF_NONE) {
1268
+
struct stm32_firewall firewall;
1269
+
u32 index = (u32)cfg->sec_id;
1270
+
1271
+
if (index & SEC_RIFSC_FLAG) {
1272
+
ret = stm32_firewall_get_firewall(np, &firewall, 1);
1273
+
if (ret)
1274
+
return ret;
1275
+
ret = stm32_firewall_grant_access_by_id(&firewall, index & ~SEC_RIFSC_FLAG);
1276
+
} else {
1277
+
ret = stm32_rcc_get_access(base, cfg->sec_id & ~SEC_RIFSC_FLAG);
1278
+
}
1279
+
}
1280
+
1281
+
return ret;
1282
+
}
1283
+
1284
+
static const struct clock_config stm32mp21_clock_cfg[] = {
1285
+
STM32_GATE_CFG(CK_BUS_ETH1, ck_icn_p_eth1, SEC_RIFSC(60)),
1286
+
STM32_GATE_CFG(CK_BUS_ETH2, ck_icn_p_eth2, SEC_RIFSC(61)),
1287
+
STM32_GATE_CFG(CK_BUS_ADC1, ck_icn_p_adc1, SEC_RIFSC(58)),
1288
+
STM32_GATE_CFG(CK_BUS_ADC2, ck_icn_p_adc2, SEC_RIFSC(59)),
1289
+
STM32_GATE_CFG(CK_BUS_CRC, ck_icn_p_crc, SEC_RIFSC(109)),
1290
+
STM32_GATE_CFG(CK_BUS_MDF1, ck_icn_p_mdf1, SEC_RIFSC(54)),
1291
+
STM32_GATE_CFG(CK_BUS_HASH1, ck_icn_p_hash1, SEC_RIFSC(96)),
1292
+
STM32_GATE_CFG(CK_BUS_HASH2, ck_icn_p_hash2, SEC_RIFSC(97)),
1293
+
STM32_GATE_CFG(CK_BUS_RNG1, ck_icn_p_rng1, SEC_RIFSC(92)),
1294
+
STM32_GATE_CFG(CK_BUS_RNG2, ck_icn_p_rng2, SEC_RIFSC(93)),
1295
+
STM32_GATE_CFG(CK_BUS_CRYP1, ck_icn_p_cryp1, SEC_RIFSC(98)),
1296
+
STM32_GATE_CFG(CK_BUS_CRYP2, ck_icn_p_cryp2, SEC_RIFSC(99)),
1297
+
STM32_GATE_CFG(CK_BUS_SAES, ck_icn_p_saes, SEC_RIFSC(95)),
1298
+
STM32_GATE_CFG(CK_BUS_PKA, ck_icn_p_pka, SEC_RIFSC(94)),
1299
+
STM32_GATE_CFG(CK_BUS_LPUART1, ck_icn_p_lpuart1, SEC_RIFSC(40)),
1300
+
STM32_GATE_CFG(CK_BUS_LPTIM3, ck_icn_p_lptim3, SEC_RIFSC(19)),
1301
+
STM32_GATE_CFG(CK_BUS_LPTIM4, ck_icn_p_lptim4, SEC_RIFSC(20)),
1302
+
STM32_GATE_CFG(CK_BUS_LPTIM5, ck_icn_p_lptim5, SEC_RIFSC(21)),
1303
+
STM32_GATE_CFG(CK_BUS_SDMMC1, ck_icn_m_sdmmc1, SEC_RIFSC(76)),
1304
+
STM32_GATE_CFG(CK_BUS_SDMMC2, ck_icn_m_sdmmc2, SEC_RIFSC(77)),
1305
+
STM32_GATE_CFG(CK_BUS_SDMMC3, ck_icn_m_sdmmc3, SEC_RIFSC(78)),
1306
+
STM32_GATE_CFG(CK_BUS_USBHOHCI, ck_icn_m_usbhohci, SEC_RIFSC(63)),
1307
+
STM32_GATE_CFG(CK_BUS_USBHEHCI, ck_icn_m_usbhehci, SEC_RIFSC(63)),
1308
+
STM32_GATE_CFG(CK_BUS_OTG, ck_icn_m_otg, SEC_RIFSC(66)),
1309
+
STM32_GATE_CFG(CK_BUS_TIM2, ck_icn_p_tim2, SEC_RIFSC(1)),
1310
+
STM32_GATE_CFG(CK_BUS_TIM3, ck_icn_p_tim3, SEC_RIFSC(2)),
1311
+
STM32_GATE_CFG(CK_BUS_TIM4, ck_icn_p_tim4, SEC_RIFSC(3)),
1312
+
STM32_GATE_CFG(CK_BUS_TIM5, ck_icn_p_tim5, SEC_RIFSC(4)),
1313
+
STM32_GATE_CFG(CK_BUS_TIM6, ck_icn_p_tim6, SEC_RIFSC(5)),
1314
+
STM32_GATE_CFG(CK_BUS_TIM7, ck_icn_p_tim7, SEC_RIFSC(6)),
1315
+
STM32_GATE_CFG(CK_BUS_TIM10, ck_icn_p_tim10, SEC_RIFSC(8)),
1316
+
STM32_GATE_CFG(CK_BUS_TIM11, ck_icn_p_tim11, SEC_RIFSC(9)),
1317
+
STM32_GATE_CFG(CK_BUS_TIM12, ck_icn_p_tim12, SEC_RIFSC(10)),
1318
+
STM32_GATE_CFG(CK_BUS_TIM13, ck_icn_p_tim13, SEC_RIFSC(11)),
1319
+
STM32_GATE_CFG(CK_BUS_TIM14, ck_icn_p_tim14, SEC_RIFSC(12)),
1320
+
STM32_GATE_CFG(CK_BUS_LPTIM1, ck_icn_p_lptim1, SEC_RIFSC(17)),
1321
+
STM32_GATE_CFG(CK_BUS_LPTIM2, ck_icn_p_lptim2, SEC_RIFSC(18)),
1322
+
STM32_GATE_CFG(CK_BUS_SPI2, ck_icn_p_spi2, SEC_RIFSC(23)),
1323
+
STM32_GATE_CFG(CK_BUS_SPI3, ck_icn_p_spi3, SEC_RIFSC(24)),
1324
+
STM32_GATE_CFG(CK_BUS_SPDIFRX, ck_icn_p_spdifrx, SEC_RIFSC(30)),
1325
+
STM32_GATE_CFG(CK_BUS_USART2, ck_icn_p_usart2, SEC_RIFSC(32)),
1326
+
STM32_GATE_CFG(CK_BUS_USART3, ck_icn_p_usart3, SEC_RIFSC(33)),
1327
+
STM32_GATE_CFG(CK_BUS_UART4, ck_icn_p_uart4, SEC_RIFSC(34)),
1328
+
STM32_GATE_CFG(CK_BUS_UART5, ck_icn_p_uart5, SEC_RIFSC(35)),
1329
+
STM32_GATE_CFG(CK_BUS_I2C1, ck_icn_p_i2c1, SEC_RIFSC(41)),
1330
+
STM32_GATE_CFG(CK_BUS_I2C2, ck_icn_p_i2c2, SEC_RIFSC(42)),
1331
+
STM32_GATE_CFG(CK_BUS_I2C3, ck_icn_p_i2c3, SEC_RIFSC(43)),
1332
+
STM32_GATE_CFG(CK_BUS_I3C1, ck_icn_p_i3c1, SEC_RIFSC(114)),
1333
+
STM32_GATE_CFG(CK_BUS_I3C2, ck_icn_p_i3c2, SEC_RIFSC(115)),
1334
+
STM32_GATE_CFG(CK_BUS_I3C3, ck_icn_p_i3c3, SEC_RIFSC(116)),
1335
+
STM32_GATE_CFG(CK_BUS_TIM1, ck_icn_p_tim1, SEC_RIFSC(0)),
1336
+
STM32_GATE_CFG(CK_BUS_TIM8, ck_icn_p_tim8, SEC_RIFSC(7)),
1337
+
STM32_GATE_CFG(CK_BUS_TIM15, ck_icn_p_tim15, SEC_RIFSC(13)),
1338
+
STM32_GATE_CFG(CK_BUS_TIM16, ck_icn_p_tim16, SEC_RIFSC(14)),
1339
+
STM32_GATE_CFG(CK_BUS_TIM17, ck_icn_p_tim17, SEC_RIFSC(15)),
1340
+
STM32_GATE_CFG(CK_BUS_SAI1, ck_icn_p_sai1, SEC_RIFSC(49)),
1341
+
STM32_GATE_CFG(CK_BUS_SAI2, ck_icn_p_sai2, SEC_RIFSC(50)),
1342
+
STM32_GATE_CFG(CK_BUS_SAI3, ck_icn_p_sai3, SEC_RIFSC(51)),
1343
+
STM32_GATE_CFG(CK_BUS_SAI4, ck_icn_p_sai4, SEC_RIFSC(52)),
1344
+
STM32_GATE_CFG(CK_BUS_USART1, ck_icn_p_usart1, SEC_RIFSC(31)),
1345
+
STM32_GATE_CFG(CK_BUS_USART6, ck_icn_p_usart6, SEC_RIFSC(36)),
1346
+
STM32_GATE_CFG(CK_BUS_UART7, ck_icn_p_uart7, SEC_RIFSC(37)),
1347
+
STM32_GATE_CFG(CK_BUS_FDCAN, ck_icn_p_fdcan, SEC_RIFSC(56)),
1348
+
STM32_GATE_CFG(CK_BUS_SPI1, ck_icn_p_spi1, SEC_RIFSC(22)),
1349
+
STM32_GATE_CFG(CK_BUS_SPI4, ck_icn_p_spi4, SEC_RIFSC(25)),
1350
+
STM32_GATE_CFG(CK_BUS_SPI5, ck_icn_p_spi5, SEC_RIFSC(26)),
1351
+
STM32_GATE_CFG(CK_BUS_SPI6, ck_icn_p_spi6, SEC_RIFSC(27)),
1352
+
STM32_GATE_CFG(CK_BUS_IWDG1, ck_icn_p_iwdg1, SEC_RIFSC(100)),
1353
+
STM32_GATE_CFG(CK_BUS_IWDG2, ck_icn_p_iwdg2, SEC_RIFSC(101)),
1354
+
STM32_GATE_CFG(CK_BUS_IWDG3, ck_icn_p_iwdg3, SEC_RIFSC(102)),
1355
+
STM32_GATE_CFG(CK_BUS_IWDG4, ck_icn_p_iwdg4, SEC_RIFSC(103)),
1356
+
STM32_GATE_CFG(CK_BUS_WWDG1, ck_icn_p_wwdg1, SEC_RIFSC(104)),
1357
+
STM32_GATE_CFG(CK_BUS_VREF, ck_icn_p_vref, SEC_RIFSC(106)),
1358
+
STM32_GATE_CFG(CK_BUS_SERC, ck_icn_p_serc, SEC_RIFSC(110)),
1359
+
STM32_GATE_CFG(CK_BUS_HDP, ck_icn_p_hdp, SEC_RIFSC(57)),
1360
+
STM32_GATE_CFG(CK_BUS_LTDC, ck_icn_p_ltdc, SEC_RIFSC(80)),
1361
+
STM32_GATE_CFG(CK_BUS_CSI, ck_icn_p_csi, SEC_RIFSC(86)),
1362
+
STM32_GATE_CFG(CK_BUS_DCMIPP, ck_icn_p_dcmipp, SEC_RIFSC(87)),
1363
+
STM32_GATE_CFG(CK_BUS_DCMIPSSI, ck_icn_p_dcmipssi, SEC_RIFSC(88)),
1364
+
STM32_GATE_CFG(CK_BUS_DDRPERFM, ck_icn_p_ddrperfm, SEC_RIFSC(67)),
1365
+
STM32_GATE_CFG(CK_KER_TIM2, ck_ker_tim2, SEC_RIFSC(1)),
1366
+
STM32_GATE_CFG(CK_KER_TIM3, ck_ker_tim3, SEC_RIFSC(2)),
1367
+
STM32_GATE_CFG(CK_KER_TIM4, ck_ker_tim4, SEC_RIFSC(3)),
1368
+
STM32_GATE_CFG(CK_KER_TIM5, ck_ker_tim5, SEC_RIFSC(4)),
1369
+
STM32_GATE_CFG(CK_KER_TIM6, ck_ker_tim6, SEC_RIFSC(5)),
1370
+
STM32_GATE_CFG(CK_KER_TIM7, ck_ker_tim7, SEC_RIFSC(6)),
1371
+
STM32_GATE_CFG(CK_KER_TIM10, ck_ker_tim10, SEC_RIFSC(8)),
1372
+
STM32_GATE_CFG(CK_KER_TIM11, ck_ker_tim11, SEC_RIFSC(9)),
1373
+
STM32_GATE_CFG(CK_KER_TIM12, ck_ker_tim12, SEC_RIFSC(10)),
1374
+
STM32_GATE_CFG(CK_KER_TIM13, ck_ker_tim13, SEC_RIFSC(11)),
1375
+
STM32_GATE_CFG(CK_KER_TIM14, ck_ker_tim14, SEC_RIFSC(12)),
1376
+
STM32_GATE_CFG(CK_KER_TIM1, ck_ker_tim1, SEC_RIFSC(0)),
1377
+
STM32_GATE_CFG(CK_KER_TIM8, ck_ker_tim8, SEC_RIFSC(7)),
1378
+
STM32_GATE_CFG(CK_KER_TIM15, ck_ker_tim15, SEC_RIFSC(13)),
1379
+
STM32_GATE_CFG(CK_KER_TIM16, ck_ker_tim16, SEC_RIFSC(14)),
1380
+
STM32_GATE_CFG(CK_KER_TIM17, ck_ker_tim17, SEC_RIFSC(15)),
1381
+
STM32_GATE_CFG(CK_KER_LPTIM1, ck_ker_lptim1, SEC_RIFSC(17)),
1382
+
STM32_GATE_CFG(CK_KER_LPTIM2, ck_ker_lptim2, SEC_RIFSC(18)),
1383
+
STM32_GATE_CFG(CK_KER_USART2, ck_ker_usart2, SEC_RIFSC(32)),
1384
+
STM32_GATE_CFG(CK_KER_UART4, ck_ker_uart4, SEC_RIFSC(34)),
1385
+
STM32_GATE_CFG(CK_KER_USART3, ck_ker_usart3, SEC_RIFSC(33)),
1386
+
STM32_GATE_CFG(CK_KER_UART5, ck_ker_uart5, SEC_RIFSC(35)),
1387
+
STM32_GATE_CFG(CK_KER_SPI2, ck_ker_spi2, SEC_RIFSC(23)),
1388
+
STM32_GATE_CFG(CK_KER_SPI3, ck_ker_spi3, SEC_RIFSC(24)),
1389
+
STM32_GATE_CFG(CK_KER_SPDIFRX, ck_ker_spdifrx, SEC_RIFSC(30)),
1390
+
STM32_GATE_CFG(CK_KER_I2C1, ck_ker_i2c1, SEC_RIFSC(41)),
1391
+
STM32_GATE_CFG(CK_KER_I2C2, ck_ker_i2c2, SEC_RIFSC(42)),
1392
+
STM32_GATE_CFG(CK_KER_I3C1, ck_ker_i3c1, SEC_RIFSC(114)),
1393
+
STM32_GATE_CFG(CK_KER_I3C2, ck_ker_i3c2, SEC_RIFSC(115)),
1394
+
STM32_GATE_CFG(CK_KER_I2C3, ck_ker_i2c3, SEC_RIFSC(43)),
1395
+
STM32_GATE_CFG(CK_KER_I3C3, ck_ker_i3c3, SEC_RIFSC(116)),
1396
+
STM32_GATE_CFG(CK_KER_SPI1, ck_ker_spi1, SEC_RIFSC(22)),
1397
+
STM32_GATE_CFG(CK_KER_SPI4, ck_ker_spi4, SEC_RIFSC(25)),
1398
+
STM32_GATE_CFG(CK_KER_SPI5, ck_ker_spi5, SEC_RIFSC(26)),
1399
+
STM32_GATE_CFG(CK_KER_SPI6, ck_ker_spi6, SEC_RIFSC(27)),
1400
+
STM32_GATE_CFG(CK_KER_USART1, ck_ker_usart1, SEC_RIFSC(31)),
1401
+
STM32_GATE_CFG(CK_KER_USART6, ck_ker_usart6, SEC_RIFSC(36)),
1402
+
STM32_GATE_CFG(CK_KER_UART7, ck_ker_uart7, SEC_RIFSC(37)),
1403
+
STM32_GATE_CFG(CK_KER_MDF1, ck_ker_mdf1, SEC_RIFSC(54)),
1404
+
STM32_GATE_CFG(CK_KER_SAI1, ck_ker_sai1, SEC_RIFSC(49)),
1405
+
STM32_GATE_CFG(CK_KER_SAI2, ck_ker_sai2, SEC_RIFSC(50)),
1406
+
STM32_GATE_CFG(CK_KER_SAI3, ck_ker_sai3, SEC_RIFSC(51)),
1407
+
STM32_GATE_CFG(CK_KER_SAI4, ck_ker_sai4, SEC_RIFSC(52)),
1408
+
STM32_GATE_CFG(CK_KER_FDCAN, ck_ker_fdcan, SEC_RIFSC(56)),
1409
+
STM32_GATE_CFG(CK_KER_CSI, ck_ker_csi, SEC_RIFSC(86)),
1410
+
STM32_GATE_CFG(CK_KER_CSITXESC, ck_ker_csitxesc, SEC_RIFSC(86)),
1411
+
STM32_GATE_CFG(CK_KER_CSIPHY, ck_ker_csiphy, SEC_RIFSC(86)),
1412
+
STM32_GATE_CFG(CK_KER_LPUART1, ck_ker_lpuart1, SEC_RIFSC(40)),
1413
+
STM32_GATE_CFG(CK_KER_LPTIM3, ck_ker_lptim3, SEC_RIFSC(19)),
1414
+
STM32_GATE_CFG(CK_KER_LPTIM4, ck_ker_lptim4, SEC_RIFSC(20)),
1415
+
STM32_GATE_CFG(CK_KER_LPTIM5, ck_ker_lptim5, SEC_RIFSC(21)),
1416
+
STM32_GATE_CFG(CK_KER_SDMMC1, ck_ker_sdmmc1, SEC_RIFSC(76)),
1417
+
STM32_GATE_CFG(CK_KER_SDMMC2, ck_ker_sdmmc2, SEC_RIFSC(77)),
1418
+
STM32_GATE_CFG(CK_KER_SDMMC3, ck_ker_sdmmc3, SEC_RIFSC(78)),
1419
+
STM32_GATE_CFG(CK_KER_ETH1, ck_ker_eth1, SEC_RIFSC(60)),
1420
+
STM32_GATE_CFG(CK_ETH1_STP, ck_ker_eth1stp, SEC_RIFSC(60)),
1421
+
STM32_GATE_CFG(CK_KER_ETH2, ck_ker_eth2, SEC_RIFSC(61)),
1422
+
STM32_GATE_CFG(CK_ETH2_STP, ck_ker_eth2stp, SEC_RIFSC(61)),
1423
+
STM32_GATE_CFG(CK_KER_ETH1PTP, ck_ker_eth1ptp, SEC_RIFSC(60)),
1424
+
STM32_GATE_CFG(CK_KER_ETH2PTP, ck_ker_eth2ptp, SEC_RIFSC(61)),
1425
+
STM32_GATE_CFG(CK_ETH1_MAC, ck_ker_eth1mac, SEC_RIFSC(60)),
1426
+
STM32_GATE_CFG(CK_ETH1_TX, ck_ker_eth1tx, SEC_RIFSC(60)),
1427
+
STM32_GATE_CFG(CK_ETH1_RX, ck_ker_eth1rx, SEC_RIFSC(60)),
1428
+
STM32_GATE_CFG(CK_ETH2_MAC, ck_ker_eth2mac, SEC_RIFSC(61)),
1429
+
STM32_GATE_CFG(CK_ETH2_TX, ck_ker_eth2tx, SEC_RIFSC(61)),
1430
+
STM32_GATE_CFG(CK_ETH2_RX, ck_ker_eth2rx, SEC_RIFSC(61)),
1431
+
STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, MP21_RIF_RCC_MCO1),
1432
+
STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, MP21_RIF_RCC_MCO2),
1433
+
STM32_COMPOSITE_CFG(CK_KER_ADC1, ck_ker_adc1, SEC_RIFSC(58)),
1434
+
STM32_COMPOSITE_CFG(CK_KER_ADC2, ck_ker_adc2, SEC_RIFSC(59)),
1435
+
STM32_COMPOSITE_CFG(CK_KER_USB2PHY1, ck_ker_usb2phy1, SEC_RIFSC(63)),
1436
+
STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN, ck_ker_usb2phy2_en, SEC_RIFSC(66)),
1437
+
STM32_COMPOSITE_CFG(CK_KER_DTS, ck_ker_dts, SEC_RIFSC(107)),
1438
+
STM32_GATE_CFG(CK_KER_LTDC, ck_ker_ltdc, SEC_RIFSC(80)),
1439
+
};
1440
+
1441
+
#define RESET_MP21(id, _offset, _bit_idx, _set_clr) \
1442
+
[id] = &(struct stm32_reset_cfg){ \
1443
+
.offset = (_offset), \
1444
+
.bit_idx = (_bit_idx), \
1445
+
.set_clr = (_set_clr), \
1446
+
}
1447
+
1448
+
static const struct stm32_reset_cfg *stm32mp21_reset_cfg[] = {
1449
+
RESET_MP21(TIM1_R, RCC_TIM1CFGR, 0, 0),
1450
+
RESET_MP21(TIM2_R, RCC_TIM2CFGR, 0, 0),
1451
+
RESET_MP21(TIM3_R, RCC_TIM3CFGR, 0, 0),
1452
+
RESET_MP21(TIM4_R, RCC_TIM4CFGR, 0, 0),
1453
+
RESET_MP21(TIM5_R, RCC_TIM5CFGR, 0, 0),
1454
+
RESET_MP21(TIM6_R, RCC_TIM6CFGR, 0, 0),
1455
+
RESET_MP21(TIM7_R, RCC_TIM7CFGR, 0, 0),
1456
+
RESET_MP21(TIM8_R, RCC_TIM8CFGR, 0, 0),
1457
+
RESET_MP21(TIM10_R, RCC_TIM10CFGR, 0, 0),
1458
+
RESET_MP21(TIM11_R, RCC_TIM11CFGR, 0, 0),
1459
+
RESET_MP21(TIM12_R, RCC_TIM12CFGR, 0, 0),
1460
+
RESET_MP21(TIM13_R, RCC_TIM13CFGR, 0, 0),
1461
+
RESET_MP21(TIM14_R, RCC_TIM14CFGR, 0, 0),
1462
+
RESET_MP21(TIM15_R, RCC_TIM15CFGR, 0, 0),
1463
+
RESET_MP21(TIM16_R, RCC_TIM16CFGR, 0, 0),
1464
+
RESET_MP21(TIM17_R, RCC_TIM17CFGR, 0, 0),
1465
+
RESET_MP21(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0),
1466
+
RESET_MP21(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0),
1467
+
RESET_MP21(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0),
1468
+
RESET_MP21(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0),
1469
+
RESET_MP21(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0),
1470
+
RESET_MP21(SPI1_R, RCC_SPI1CFGR, 0, 0),
1471
+
RESET_MP21(SPI2_R, RCC_SPI2CFGR, 0, 0),
1472
+
RESET_MP21(SPI3_R, RCC_SPI3CFGR, 0, 0),
1473
+
RESET_MP21(SPI4_R, RCC_SPI4CFGR, 0, 0),
1474
+
RESET_MP21(SPI5_R, RCC_SPI5CFGR, 0, 0),
1475
+
RESET_MP21(SPI6_R, RCC_SPI6CFGR, 0, 0),
1476
+
RESET_MP21(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0),
1477
+
RESET_MP21(USART1_R, RCC_USART1CFGR, 0, 0),
1478
+
RESET_MP21(USART2_R, RCC_USART2CFGR, 0, 0),
1479
+
RESET_MP21(USART3_R, RCC_USART3CFGR, 0, 0),
1480
+
RESET_MP21(UART4_R, RCC_UART4CFGR, 0, 0),
1481
+
RESET_MP21(UART5_R, RCC_UART5CFGR, 0, 0),
1482
+
RESET_MP21(USART6_R, RCC_USART6CFGR, 0, 0),
1483
+
RESET_MP21(UART7_R, RCC_UART7CFGR, 0, 0),
1484
+
RESET_MP21(LPUART1_R, RCC_LPUART1CFGR, 0, 0),
1485
+
RESET_MP21(I2C1_R, RCC_I2C1CFGR, 0, 0),
1486
+
RESET_MP21(I2C2_R, RCC_I2C2CFGR, 0, 0),
1487
+
RESET_MP21(I2C3_R, RCC_I2C3CFGR, 0, 0),
1488
+
RESET_MP21(SAI1_R, RCC_SAI1CFGR, 0, 0),
1489
+
RESET_MP21(SAI2_R, RCC_SAI2CFGR, 0, 0),
1490
+
RESET_MP21(SAI3_R, RCC_SAI3CFGR, 0, 0),
1491
+
RESET_MP21(SAI4_R, RCC_SAI4CFGR, 0, 0),
1492
+
RESET_MP21(MDF1_R, RCC_MDF1CFGR, 0, 0),
1493
+
RESET_MP21(FDCAN_R, RCC_FDCANCFGR, 0, 0),
1494
+
RESET_MP21(HDP_R, RCC_HDPCFGR, 0, 0),
1495
+
RESET_MP21(ADC1_R, RCC_ADC1CFGR, 0, 0),
1496
+
RESET_MP21(ADC2_R, RCC_ADC2CFGR, 0, 0),
1497
+
RESET_MP21(ETH1_R, RCC_ETH1CFGR, 0, 0),
1498
+
RESET_MP21(ETH2_R, RCC_ETH2CFGR, 0, 0),
1499
+
RESET_MP21(OTG_R, RCC_OTGCFGR, 0, 0),
1500
+
RESET_MP21(USBH_R, RCC_USBHCFGR, 0, 0),
1501
+
RESET_MP21(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0),
1502
+
RESET_MP21(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0),
1503
+
RESET_MP21(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0),
1504
+
RESET_MP21(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0),
1505
+
RESET_MP21(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0),
1506
+
RESET_MP21(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0),
1507
+
RESET_MP21(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0),
1508
+
RESET_MP21(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0),
1509
+
RESET_MP21(LTDC_R, RCC_LTDCCFGR, 0, 0),
1510
+
RESET_MP21(CSI_R, RCC_CSICFGR, 0, 0),
1511
+
RESET_MP21(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0),
1512
+
RESET_MP21(DCMIPSSI_R, RCC_DCMIPSSICFGR, 0, 0),
1513
+
RESET_MP21(WWDG1_R, RCC_WWDG1CFGR, 0, 0),
1514
+
RESET_MP21(VREF_R, RCC_VREFCFGR, 0, 0),
1515
+
RESET_MP21(DTS_R, RCC_DTSCFGR, 0, 0),
1516
+
RESET_MP21(CRC_R, RCC_CRCCFGR, 0, 0),
1517
+
RESET_MP21(SERC_R, RCC_SERCCFGR, 0, 0),
1518
+
RESET_MP21(I3C1_R, RCC_I3C1CFGR, 0, 0),
1519
+
RESET_MP21(I3C2_R, RCC_I3C2CFGR, 0, 0),
1520
+
RESET_MP21(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1),
1521
+
RESET_MP21(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1),
1522
+
RESET_MP21(RNG1_R, RCC_RNG1CFGR, 0, 0),
1523
+
RESET_MP21(RNG2_R, RCC_RNG2CFGR, 0, 0),
1524
+
RESET_MP21(PKA_R, RCC_PKACFGR, 0, 0),
1525
+
RESET_MP21(SAES_R, RCC_SAESCFGR, 0, 0),
1526
+
RESET_MP21(HASH1_R, RCC_HASH1CFGR, 0, 0),
1527
+
RESET_MP21(HASH2_R, RCC_HASH2CFGR, 0, 0),
1528
+
RESET_MP21(CRYP1_R, RCC_CRYP1CFGR, 0, 0),
1529
+
RESET_MP21(CRYP2_R, RCC_CRYP2CFGR, 0, 0),
1530
+
};
1531
+
1532
+
static u16 stm32mp21_cpt_gate[GATE_NB];
1533
+
1534
+
static struct clk_stm32_clock_data stm32mp21_clock_data = {
1535
+
.gate_cpt = stm32mp21_cpt_gate,
1536
+
.gates = stm32mp21_gates,
1537
+
.muxes = stm32mp21_muxes,
1538
+
};
1539
+
1540
+
static struct clk_stm32_reset_data stm32mp21_reset_data = {
1541
+
.reset_lines = stm32mp21_reset_cfg,
1542
+
.nr_lines = ARRAY_SIZE(stm32mp21_reset_cfg),
1543
+
};
1544
+
1545
+
static const struct stm32_rcc_match_data stm32mp21_data = {
1546
+
.tab_clocks = stm32mp21_clock_cfg,
1547
+
.num_clocks = ARRAY_SIZE(stm32mp21_clock_cfg),
1548
+
.maxbinding = STM32MP21_LAST_CLK,
1549
+
.clock_data = &stm32mp21_clock_data,
1550
+
.reset_data = &stm32mp21_reset_data,
1551
+
.check_security = &stm32mp21_check_security,
1552
+
};
1553
+
1554
+
static const struct of_device_id stm32mp21_match_data[] = {
1555
+
{ .compatible = "st,stm32mp21-rcc", .data = &stm32mp21_data, },
1556
+
{ }
1557
+
};
1558
+
MODULE_DEVICE_TABLE(of, stm32mp21_match_data);
1559
+
1560
+
static int stm32mp21_rcc_clocks_probe(struct platform_device *pdev)
1561
+
{
1562
+
struct device *dev = &pdev->dev;
1563
+
void __iomem *base;
1564
+
1565
+
base = devm_platform_ioremap_resource(pdev, 0);
1566
+
if (WARN_ON(IS_ERR(base)))
1567
+
return PTR_ERR(base);
1568
+
1569
+
return stm32_rcc_init(dev, stm32mp21_match_data, base);
1570
+
}
1571
+
1572
+
static struct platform_driver stm32mp21_rcc_clocks_driver = {
1573
+
.driver = {
1574
+
.name = "stm32mp21_rcc",
1575
+
.of_match_table = stm32mp21_match_data,
1576
+
},
1577
+
.probe = stm32mp21_rcc_clocks_probe,
1578
+
};
1579
+
1580
+
static int __init stm32mp21_clocks_init(void)
1581
+
{
1582
+
return platform_driver_register(&stm32mp21_rcc_clocks_driver);
1583
+
}
1584
+
1585
+
core_initcall(stm32mp21_clocks_init);
1586
+
+651
drivers/clk/stm32/stm32mp21_rcc.h
+651
drivers/clk/stm32/stm32mp21_rcc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4
+
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5
+
*/
6
+
7
+
#ifndef STM32MP21_RCC_H
8
+
#define STM32MP21_RCC_H
9
+
10
+
#define RCC_SECCFGR0 0x0
11
+
#define RCC_SECCFGR1 0x4
12
+
#define RCC_SECCFGR2 0x8
13
+
#define RCC_SECCFGR3 0xC
14
+
#define RCC_PRIVCFGR0 0x10
15
+
#define RCC_PRIVCFGR1 0x14
16
+
#define RCC_PRIVCFGR2 0x18
17
+
#define RCC_PRIVCFGR3 0x1C
18
+
#define RCC_RCFGLOCKR0 0x20
19
+
#define RCC_RCFGLOCKR1 0x24
20
+
#define RCC_RCFGLOCKR2 0x28
21
+
#define RCC_RCFGLOCKR3 0x2C
22
+
#define RCC_R0CIDCFGR 0x30
23
+
#define RCC_R0SEMCR 0x34
24
+
#define RCC_R1CIDCFGR 0x38
25
+
#define RCC_R1SEMCR 0x3C
26
+
#define RCC_R2CIDCFGR 0x40
27
+
#define RCC_R2SEMCR 0x44
28
+
#define RCC_R3CIDCFGR 0x48
29
+
#define RCC_R3SEMCR 0x4C
30
+
#define RCC_R4CIDCFGR 0x50
31
+
#define RCC_R4SEMCR 0x54
32
+
#define RCC_R5CIDCFGR 0x58
33
+
#define RCC_R5SEMCR 0x5C
34
+
#define RCC_R6CIDCFGR 0x60
35
+
#define RCC_R6SEMCR 0x64
36
+
#define RCC_R7CIDCFGR 0x68
37
+
#define RCC_R7SEMCR 0x6C
38
+
#define RCC_R8CIDCFGR 0x70
39
+
#define RCC_R8SEMCR 0x74
40
+
#define RCC_R9CIDCFGR 0x78
41
+
#define RCC_R9SEMCR 0x7C
42
+
#define RCC_R10CIDCFGR 0x80
43
+
#define RCC_R10SEMCR 0x84
44
+
#define RCC_R11CIDCFGR 0x88
45
+
#define RCC_R11SEMCR 0x8C
46
+
#define RCC_R12CIDCFGR 0x90
47
+
#define RCC_R12SEMCR 0x94
48
+
#define RCC_R13CIDCFGR 0x98
49
+
#define RCC_R13SEMCR 0x9C
50
+
#define RCC_R14CIDCFGR 0xA0
51
+
#define RCC_R14SEMCR 0xA4
52
+
#define RCC_R15CIDCFGR 0xA8
53
+
#define RCC_R15SEMCR 0xAC
54
+
#define RCC_R16CIDCFGR 0xB0
55
+
#define RCC_R16SEMCR 0xB4
56
+
#define RCC_R17CIDCFGR 0xB8
57
+
#define RCC_R17SEMCR 0xBC
58
+
#define RCC_R18CIDCFGR 0xC0
59
+
#define RCC_R18SEMCR 0xC4
60
+
#define RCC_R19CIDCFGR 0xC8
61
+
#define RCC_R19SEMCR 0xCC
62
+
#define RCC_R20CIDCFGR 0xD0
63
+
#define RCC_R20SEMCR 0xD4
64
+
#define RCC_R21CIDCFGR 0xD8
65
+
#define RCC_R21SEMCR 0xDC
66
+
#define RCC_R22CIDCFGR 0xE0
67
+
#define RCC_R22SEMCR 0xE4
68
+
#define RCC_R23CIDCFGR 0xE8
69
+
#define RCC_R23SEMCR 0xEC
70
+
#define RCC_R24CIDCFGR 0xF0
71
+
#define RCC_R24SEMCR 0xF4
72
+
#define RCC_R25CIDCFGR 0xF8
73
+
#define RCC_R25SEMCR 0xFC
74
+
#define RCC_R26CIDCFGR 0x100
75
+
#define RCC_R26SEMCR 0x104
76
+
#define RCC_R27CIDCFGR 0x108
77
+
#define RCC_R27SEMCR 0x10C
78
+
#define RCC_R28CIDCFGR 0x110
79
+
#define RCC_R28SEMCR 0x114
80
+
#define RCC_R29CIDCFGR 0x118
81
+
#define RCC_R29SEMCR 0x11C
82
+
#define RCC_R30CIDCFGR 0x120
83
+
#define RCC_R30SEMCR 0x124
84
+
#define RCC_R31CIDCFGR 0x128
85
+
#define RCC_R31SEMCR 0x12C
86
+
#define RCC_R32CIDCFGR 0x130
87
+
#define RCC_R32SEMCR 0x134
88
+
#define RCC_R33CIDCFGR 0x138
89
+
#define RCC_R33SEMCR 0x13C
90
+
#define RCC_R34CIDCFGR 0x140
91
+
#define RCC_R34SEMCR 0x144
92
+
#define RCC_R35CIDCFGR 0x148
93
+
#define RCC_R35SEMCR 0x14C
94
+
#define RCC_R36CIDCFGR 0x150
95
+
#define RCC_R36SEMCR 0x154
96
+
#define RCC_R37CIDCFGR 0x158
97
+
#define RCC_R37SEMCR 0x15C
98
+
#define RCC_R38CIDCFGR 0x160
99
+
#define RCC_R38SEMCR 0x164
100
+
#define RCC_R39CIDCFGR 0x168
101
+
#define RCC_R39SEMCR 0x16C
102
+
#define RCC_R40CIDCFGR 0x170
103
+
#define RCC_R40SEMCR 0x174
104
+
#define RCC_R41CIDCFGR 0x178
105
+
#define RCC_R41SEMCR 0x17C
106
+
#define RCC_R42CIDCFGR 0x180
107
+
#define RCC_R42SEMCR 0x184
108
+
#define RCC_R43CIDCFGR 0x188
109
+
#define RCC_R43SEMCR 0x18C
110
+
#define RCC_R44CIDCFGR 0x190
111
+
#define RCC_R44SEMCR 0x194
112
+
#define RCC_R45CIDCFGR 0x198
113
+
#define RCC_R45SEMCR 0x19C
114
+
#define RCC_R46CIDCFGR 0x1A0
115
+
#define RCC_R46SEMCR 0x1A4
116
+
#define RCC_R47CIDCFGR 0x1A8
117
+
#define RCC_R47SEMCR 0x1AC
118
+
#define RCC_R48CIDCFGR 0x1B0
119
+
#define RCC_R48SEMCR 0x1B4
120
+
#define RCC_R49CIDCFGR 0x1B8
121
+
#define RCC_R49SEMCR 0x1BC
122
+
#define RCC_R50CIDCFGR 0x1C0
123
+
#define RCC_R50SEMCR 0x1C4
124
+
#define RCC_R51CIDCFGR 0x1C8
125
+
#define RCC_R51SEMCR 0x1CC
126
+
#define RCC_R52CIDCFGR 0x1D0
127
+
#define RCC_R52SEMCR 0x1D4
128
+
#define RCC_R53CIDCFGR 0x1D8
129
+
#define RCC_R53SEMCR 0x1DC
130
+
#define RCC_R54CIDCFGR 0x1E0
131
+
#define RCC_R54SEMCR 0x1E4
132
+
#define RCC_R55CIDCFGR 0x1E8
133
+
#define RCC_R55SEMCR 0x1EC
134
+
#define RCC_R56CIDCFGR 0x1F0
135
+
#define RCC_R56SEMCR 0x1F4
136
+
#define RCC_R57CIDCFGR 0x1F8
137
+
#define RCC_R57SEMCR 0x1FC
138
+
#define RCC_R58CIDCFGR 0x200
139
+
#define RCC_R58SEMCR 0x204
140
+
#define RCC_R59CIDCFGR 0x208
141
+
#define RCC_R59SEMCR 0x20C
142
+
#define RCC_R60CIDCFGR 0x210
143
+
#define RCC_R60SEMCR 0x214
144
+
#define RCC_R61CIDCFGR 0x218
145
+
#define RCC_R61SEMCR 0x21C
146
+
#define RCC_R62CIDCFGR 0x220
147
+
#define RCC_R62SEMCR 0x224
148
+
#define RCC_R63CIDCFGR 0x228
149
+
#define RCC_R63SEMCR 0x22C
150
+
#define RCC_R64CIDCFGR 0x230
151
+
#define RCC_R64SEMCR 0x234
152
+
#define RCC_R65CIDCFGR 0x238
153
+
#define RCC_R65SEMCR 0x23C
154
+
#define RCC_R66CIDCFGR 0x240
155
+
#define RCC_R66SEMCR 0x244
156
+
#define RCC_R67CIDCFGR 0x248
157
+
#define RCC_R67SEMCR 0x24C
158
+
#define RCC_R68CIDCFGR 0x250
159
+
#define RCC_R68SEMCR 0x254
160
+
#define RCC_R69CIDCFGR 0x258
161
+
#define RCC_R69SEMCR 0x25C
162
+
#define RCC_R70CIDCFGR 0x260
163
+
#define RCC_R70SEMCR 0x264
164
+
#define RCC_R71CIDCFGR 0x268
165
+
#define RCC_R71SEMCR 0x26C
166
+
#define RCC_R73CIDCFGR 0x278
167
+
#define RCC_R73SEMCR 0x27C
168
+
#define RCC_R74CIDCFGR 0x280
169
+
#define RCC_R74SEMCR 0x284
170
+
#define RCC_R75CIDCFGR 0x288
171
+
#define RCC_R75SEMCR 0x28C
172
+
#define RCC_R76CIDCFGR 0x290
173
+
#define RCC_R76SEMCR 0x294
174
+
#define RCC_R77CIDCFGR 0x298
175
+
#define RCC_R77SEMCR 0x29C
176
+
#define RCC_R78CIDCFGR 0x2A0
177
+
#define RCC_R78SEMCR 0x2A4
178
+
#define RCC_R79CIDCFGR 0x2A8
179
+
#define RCC_R79SEMCR 0x2AC
180
+
#define RCC_R83CIDCFGR 0x2C8
181
+
#define RCC_R83SEMCR 0x2CC
182
+
#define RCC_R84CIDCFGR 0x2D0
183
+
#define RCC_R84SEMCR 0x2D4
184
+
#define RCC_R85CIDCFGR 0x2D8
185
+
#define RCC_R85SEMCR 0x2DC
186
+
#define RCC_R86CIDCFGR 0x2E0
187
+
#define RCC_R86SEMCR 0x2E4
188
+
#define RCC_R87CIDCFGR 0x2E8
189
+
#define RCC_R87SEMCR 0x2EC
190
+
#define RCC_R88CIDCFGR 0x2F0
191
+
#define RCC_R88SEMCR 0x2F4
192
+
#define RCC_R90CIDCFGR 0x300
193
+
#define RCC_R90SEMCR 0x304
194
+
#define RCC_R91CIDCFGR 0x308
195
+
#define RCC_R91SEMCR 0x30C
196
+
#define RCC_R92CIDCFGR 0x310
197
+
#define RCC_R92SEMCR 0x314
198
+
#define RCC_R93CIDCFGR 0x318
199
+
#define RCC_R93SEMCR 0x31C
200
+
#define RCC_R94CIDCFGR 0x320
201
+
#define RCC_R94SEMCR 0x324
202
+
#define RCC_R95CIDCFGR 0x328
203
+
#define RCC_R95SEMCR 0x32C
204
+
#define RCC_R96CIDCFGR 0x330
205
+
#define RCC_R96SEMCR 0x334
206
+
#define RCC_R97CIDCFGR 0x338
207
+
#define RCC_R97SEMCR 0x33C
208
+
#define RCC_R98CIDCFGR 0x340
209
+
#define RCC_R98SEMCR 0x344
210
+
#define RCC_R101CIDCFGR 0x358
211
+
#define RCC_R101SEMCR 0x35C
212
+
#define RCC_R102CIDCFGR 0x360
213
+
#define RCC_R102SEMCR 0x364
214
+
#define RCC_R103CIDCFGR 0x368
215
+
#define RCC_R103SEMCR 0x36C
216
+
#define RCC_R104CIDCFGR 0x370
217
+
#define RCC_R104SEMCR 0x374
218
+
#define RCC_R105CIDCFGR 0x378
219
+
#define RCC_R105SEMCR 0x37C
220
+
#define RCC_R106CIDCFGR 0x380
221
+
#define RCC_R106SEMCR 0x384
222
+
#define RCC_R108CIDCFGR 0x390
223
+
#define RCC_R108SEMCR 0x394
224
+
#define RCC_R109CIDCFGR 0x398
225
+
#define RCC_R109SEMCR 0x39C
226
+
#define RCC_R110CIDCFGR 0x3A0
227
+
#define RCC_R110SEMCR 0x3A4
228
+
#define RCC_R111CIDCFGR 0x3A8
229
+
#define RCC_R111SEMCR 0x3AC
230
+
#define RCC_R112CIDCFGR 0x3B0
231
+
#define RCC_R112SEMCR 0x3B4
232
+
#define RCC_R113CIDCFGR 0x3B8
233
+
#define RCC_R113SEMCR 0x3BC
234
+
#define RCC_GRSTCSETR 0x400
235
+
#define RCC_C1RSTCSETR 0x404
236
+
#define RCC_C2RSTCSETR 0x40C
237
+
#define RCC_HWRSTSCLRR 0x410
238
+
#define RCC_C1HWRSTSCLRR 0x414
239
+
#define RCC_C2HWRSTSCLRR 0x418
240
+
#define RCC_C1BOOTRSTSSETR 0x41C
241
+
#define RCC_C1BOOTRSTSCLRR 0x420
242
+
#define RCC_C2BOOTRSTSSETR 0x424
243
+
#define RCC_C2BOOTRSTSCLRR 0x428
244
+
#define RCC_C1SREQSETR 0x42C
245
+
#define RCC_C1SREQCLRR 0x430
246
+
#define RCC_CPUBOOTCR 0x434
247
+
#define RCC_STBYBOOTCR 0x438
248
+
#define RCC_LEGBOOTCR 0x43C
249
+
#define RCC_BDCR 0x440
250
+
#define RCC_RDCR 0x44C
251
+
#define RCC_C1MSRDCR 0x450
252
+
#define RCC_PWRLPDLYCR 0x454
253
+
#define RCC_C1CIESETR 0x458
254
+
#define RCC_C1CIFCLRR 0x45C
255
+
#define RCC_C2CIESETR 0x460
256
+
#define RCC_C2CIFCLRR 0x464
257
+
#define RCC_IWDGC1FZSETR 0x468
258
+
#define RCC_IWDGC1FZCLRR 0x46C
259
+
#define RCC_IWDGC1CFGSETR 0x470
260
+
#define RCC_IWDGC1CFGCLRR 0x474
261
+
#define RCC_IWDGC2FZSETR 0x478
262
+
#define RCC_IWDGC2FZCLRR 0x47C
263
+
#define RCC_IWDGC2CFGSETR 0x480
264
+
#define RCC_IWDGC2CFGCLRR 0x484
265
+
#define RCC_MCO1CFGR 0x488
266
+
#define RCC_MCO2CFGR 0x48C
267
+
#define RCC_OCENSETR 0x490
268
+
#define RCC_OCENCLRR 0x494
269
+
#define RCC_OCRDYR 0x498
270
+
#define RCC_HSICFGR 0x49C
271
+
#define RCC_MSICFGR 0x4A0
272
+
#define RCC_LSICR 0x4A4
273
+
#define RCC_RTCDIVR 0x4A8
274
+
#define RCC_APB1DIVR 0x4AC
275
+
#define RCC_APB2DIVR 0x4B0
276
+
#define RCC_APB3DIVR 0x4B4
277
+
#define RCC_APB4DIVR 0x4B8
278
+
#define RCC_APB5DIVR 0x4BC
279
+
#define RCC_APBDBGDIVR 0x4C0
280
+
#define RCC_TIMG1PRER 0x4C8
281
+
#define RCC_TIMG2PRER 0x4CC
282
+
#define RCC_LSMCUDIVR 0x4D0
283
+
#define RCC_DDRCPCFGR 0x4D4
284
+
#define RCC_DDRCAPBCFGR 0x4D8
285
+
#define RCC_DDRPHYCAPBCFGR 0x4DC
286
+
#define RCC_DDRPHYCCFGR 0x4E0
287
+
#define RCC_DDRCFGR 0x4E4
288
+
#define RCC_DDRITFCFGR 0x4E8
289
+
#define RCC_SYSRAMCFGR 0x4F0
290
+
#define RCC_SRAM1CFGR 0x4F8
291
+
#define RCC_RETRAMCFGR 0x500
292
+
#define RCC_BKPSRAMCFGR 0x504
293
+
#define RCC_OSPI1CFGR 0x514
294
+
#define RCC_FMCCFGR 0x51C
295
+
#define RCC_DBGCFGR 0x520
296
+
#define RCC_STMCFGR 0x524
297
+
#define RCC_ETRCFGR 0x528
298
+
#define RCC_GPIOACFGR 0x52C
299
+
#define RCC_GPIOBCFGR 0x530
300
+
#define RCC_GPIOCCFGR 0x534
301
+
#define RCC_GPIODCFGR 0x538
302
+
#define RCC_GPIOECFGR 0x53C
303
+
#define RCC_GPIOFCFGR 0x540
304
+
#define RCC_GPIOGCFGR 0x544
305
+
#define RCC_GPIOHCFGR 0x548
306
+
#define RCC_GPIOICFGR 0x54C
307
+
#define RCC_GPIOZCFGR 0x558
308
+
#define RCC_HPDMA1CFGR 0x55C
309
+
#define RCC_HPDMA2CFGR 0x560
310
+
#define RCC_HPDMA3CFGR 0x564
311
+
#define RCC_IPCC1CFGR 0x570
312
+
#define RCC_RTCCFGR 0x578
313
+
#define RCC_SYSCPU1CFGR 0x580
314
+
#define RCC_BSECCFGR 0x584
315
+
#define RCC_PLL2CFGR1 0x590
316
+
#define RCC_PLL2CFGR2 0x594
317
+
#define RCC_PLL2CFGR3 0x598
318
+
#define RCC_PLL2CFGR4 0x59C
319
+
#define RCC_PLL2CFGR5 0x5A0
320
+
#define RCC_PLL2CFGR6 0x5A8
321
+
#define RCC_PLL2CFGR7 0x5AC
322
+
#define RCC_HSIFMONCR 0x5E0
323
+
#define RCC_HSIFVALR 0x5E4
324
+
#define RCC_MSIFMONCR 0x5E8
325
+
#define RCC_MSIFVALR 0x5EC
326
+
#define RCC_TIM1CFGR 0x700
327
+
#define RCC_TIM2CFGR 0x704
328
+
#define RCC_TIM3CFGR 0x708
329
+
#define RCC_TIM4CFGR 0x70C
330
+
#define RCC_TIM5CFGR 0x710
331
+
#define RCC_TIM6CFGR 0x714
332
+
#define RCC_TIM7CFGR 0x718
333
+
#define RCC_TIM8CFGR 0x71C
334
+
#define RCC_TIM10CFGR 0x720
335
+
#define RCC_TIM11CFGR 0x724
336
+
#define RCC_TIM12CFGR 0x728
337
+
#define RCC_TIM13CFGR 0x72C
338
+
#define RCC_TIM14CFGR 0x730
339
+
#define RCC_TIM15CFGR 0x734
340
+
#define RCC_TIM16CFGR 0x738
341
+
#define RCC_TIM17CFGR 0x73C
342
+
#define RCC_LPTIM1CFGR 0x744
343
+
#define RCC_LPTIM2CFGR 0x748
344
+
#define RCC_LPTIM3CFGR 0x74C
345
+
#define RCC_LPTIM4CFGR 0x750
346
+
#define RCC_LPTIM5CFGR 0x754
347
+
#define RCC_SPI1CFGR 0x758
348
+
#define RCC_SPI2CFGR 0x75C
349
+
#define RCC_SPI3CFGR 0x760
350
+
#define RCC_SPI4CFGR 0x764
351
+
#define RCC_SPI5CFGR 0x768
352
+
#define RCC_SPI6CFGR 0x76C
353
+
#define RCC_SPDIFRXCFGR 0x778
354
+
#define RCC_USART1CFGR 0x77C
355
+
#define RCC_USART2CFGR 0x780
356
+
#define RCC_USART3CFGR 0x784
357
+
#define RCC_UART4CFGR 0x788
358
+
#define RCC_UART5CFGR 0x78C
359
+
#define RCC_USART6CFGR 0x790
360
+
#define RCC_UART7CFGR 0x794
361
+
#define RCC_LPUART1CFGR 0x7A0
362
+
#define RCC_I2C1CFGR 0x7A4
363
+
#define RCC_I2C2CFGR 0x7A8
364
+
#define RCC_I2C3CFGR 0x7AC
365
+
#define RCC_SAI1CFGR 0x7C4
366
+
#define RCC_SAI2CFGR 0x7C8
367
+
#define RCC_SAI3CFGR 0x7CC
368
+
#define RCC_SAI4CFGR 0x7D0
369
+
#define RCC_MDF1CFGR 0x7D8
370
+
#define RCC_FDCANCFGR 0x7E0
371
+
#define RCC_HDPCFGR 0x7E4
372
+
#define RCC_ADC1CFGR 0x7E8
373
+
#define RCC_ADC2CFGR 0x7EC
374
+
#define RCC_ETH1CFGR 0x7F0
375
+
#define RCC_ETH2CFGR 0x7F4
376
+
#define RCC_USBHCFGR 0x7FC
377
+
#define RCC_USB2PHY1CFGR 0x800
378
+
#define RCC_OTGCFGR 0x808
379
+
#define RCC_USB2PHY2CFGR 0x80C
380
+
#define RCC_STGENCFGR 0x824
381
+
#define RCC_SDMMC1CFGR 0x830
382
+
#define RCC_SDMMC2CFGR 0x834
383
+
#define RCC_SDMMC3CFGR 0x838
384
+
#define RCC_LTDCCFGR 0x840
385
+
#define RCC_CSICFGR 0x858
386
+
#define RCC_DCMIPPCFGR 0x85C
387
+
#define RCC_DCMIPSSICFGR 0x860
388
+
#define RCC_RNG1CFGR 0x870
389
+
#define RCC_RNG2CFGR 0x874
390
+
#define RCC_PKACFGR 0x878
391
+
#define RCC_SAESCFGR 0x87C
392
+
#define RCC_HASH1CFGR 0x880
393
+
#define RCC_HASH2CFGR 0x884
394
+
#define RCC_CRYP1CFGR 0x888
395
+
#define RCC_CRYP2CFGR 0x88C
396
+
#define RCC_IWDG1CFGR 0x894
397
+
#define RCC_IWDG2CFGR 0x898
398
+
#define RCC_IWDG3CFGR 0x89C
399
+
#define RCC_IWDG4CFGR 0x8A0
400
+
#define RCC_WWDG1CFGR 0x8A4
401
+
#define RCC_VREFCFGR 0x8AC
402
+
#define RCC_DTSCFGR 0x8B0
403
+
#define RCC_CRCCFGR 0x8B4
404
+
#define RCC_SERCCFGR 0x8B8
405
+
#define RCC_DDRPERFMCFGR 0x8C0
406
+
#define RCC_I3C1CFGR 0x8C8
407
+
#define RCC_I3C2CFGR 0x8CC
408
+
#define RCC_I3C3CFGR 0x8D0
409
+
#define RCC_MUXSELCFGR 0x1000
410
+
#define RCC_XBAR0CFGR 0x1018
411
+
#define RCC_XBAR1CFGR 0x101C
412
+
#define RCC_XBAR2CFGR 0x1020
413
+
#define RCC_XBAR3CFGR 0x1024
414
+
#define RCC_XBAR4CFGR 0x1028
415
+
#define RCC_XBAR5CFGR 0x102C
416
+
#define RCC_XBAR6CFGR 0x1030
417
+
#define RCC_XBAR7CFGR 0x1034
418
+
#define RCC_XBAR8CFGR 0x1038
419
+
#define RCC_XBAR9CFGR 0x103C
420
+
#define RCC_XBAR10CFGR 0x1040
421
+
#define RCC_XBAR11CFGR 0x1044
422
+
#define RCC_XBAR12CFGR 0x1048
423
+
#define RCC_XBAR13CFGR 0x104C
424
+
#define RCC_XBAR14CFGR 0x1050
425
+
#define RCC_XBAR15CFGR 0x1054
426
+
#define RCC_XBAR16CFGR 0x1058
427
+
#define RCC_XBAR17CFGR 0x105C
428
+
#define RCC_XBAR18CFGR 0x1060
429
+
#define RCC_XBAR19CFGR 0x1064
430
+
#define RCC_XBAR20CFGR 0x1068
431
+
#define RCC_XBAR21CFGR 0x106C
432
+
#define RCC_XBAR22CFGR 0x1070
433
+
#define RCC_XBAR23CFGR 0x1074
434
+
#define RCC_XBAR24CFGR 0x1078
435
+
#define RCC_XBAR25CFGR 0x107C
436
+
#define RCC_XBAR26CFGR 0x1080
437
+
#define RCC_XBAR27CFGR 0x1084
438
+
#define RCC_XBAR28CFGR 0x1088
439
+
#define RCC_XBAR29CFGR 0x108C
440
+
#define RCC_XBAR30CFGR 0x1090
441
+
#define RCC_XBAR31CFGR 0x1094
442
+
#define RCC_XBAR32CFGR 0x1098
443
+
#define RCC_XBAR33CFGR 0x109C
444
+
#define RCC_XBAR34CFGR 0x10A0
445
+
#define RCC_XBAR35CFGR 0x10A4
446
+
#define RCC_XBAR36CFGR 0x10A8
447
+
#define RCC_XBAR37CFGR 0x10AC
448
+
#define RCC_XBAR38CFGR 0x10B0
449
+
#define RCC_XBAR39CFGR 0x10B4
450
+
#define RCC_XBAR40CFGR 0x10B8
451
+
#define RCC_XBAR41CFGR 0x10BC
452
+
#define RCC_XBAR42CFGR 0x10C0
453
+
#define RCC_XBAR43CFGR 0x10C4
454
+
#define RCC_XBAR44CFGR 0x10C8
455
+
#define RCC_XBAR45CFGR 0x10CC
456
+
#define RCC_XBAR46CFGR 0x10D0
457
+
#define RCC_XBAR47CFGR 0x10D4
458
+
#define RCC_XBAR48CFGR 0x10D8
459
+
#define RCC_XBAR49CFGR 0x10DC
460
+
#define RCC_XBAR50CFGR 0x10E0
461
+
#define RCC_XBAR51CFGR 0x10E4
462
+
#define RCC_XBAR52CFGR 0x10E8
463
+
#define RCC_XBAR53CFGR 0x10EC
464
+
#define RCC_XBAR54CFGR 0x10F0
465
+
#define RCC_XBAR55CFGR 0x10F4
466
+
#define RCC_XBAR56CFGR 0x10F8
467
+
#define RCC_XBAR57CFGR 0x10FC
468
+
#define RCC_XBAR58CFGR 0x1100
469
+
#define RCC_XBAR59CFGR 0x1104
470
+
#define RCC_XBAR60CFGR 0x1108
471
+
#define RCC_XBAR61CFGR 0x110C
472
+
#define RCC_XBAR62CFGR 0x1110
473
+
#define RCC_XBAR63CFGR 0x1114
474
+
#define RCC_PREDIV0CFGR 0x1118
475
+
#define RCC_PREDIV1CFGR 0x111C
476
+
#define RCC_PREDIV2CFGR 0x1120
477
+
#define RCC_PREDIV3CFGR 0x1124
478
+
#define RCC_PREDIV4CFGR 0x1128
479
+
#define RCC_PREDIV5CFGR 0x112C
480
+
#define RCC_PREDIV6CFGR 0x1130
481
+
#define RCC_PREDIV7CFGR 0x1134
482
+
#define RCC_PREDIV8CFGR 0x1138
483
+
#define RCC_PREDIV9CFGR 0x113C
484
+
#define RCC_PREDIV10CFGR 0x1140
485
+
#define RCC_PREDIV11CFGR 0x1144
486
+
#define RCC_PREDIV12CFGR 0x1148
487
+
#define RCC_PREDIV13CFGR 0x114C
488
+
#define RCC_PREDIV14CFGR 0x1150
489
+
#define RCC_PREDIV15CFGR 0x1154
490
+
#define RCC_PREDIV16CFGR 0x1158
491
+
#define RCC_PREDIV17CFGR 0x115C
492
+
#define RCC_PREDIV18CFGR 0x1160
493
+
#define RCC_PREDIV19CFGR 0x1164
494
+
#define RCC_PREDIV20CFGR 0x1168
495
+
#define RCC_PREDIV21CFGR 0x116C
496
+
#define RCC_PREDIV22CFGR 0x1170
497
+
#define RCC_PREDIV23CFGR 0x1174
498
+
#define RCC_PREDIV24CFGR 0x1178
499
+
#define RCC_PREDIV25CFGR 0x117C
500
+
#define RCC_PREDIV26CFGR 0x1180
501
+
#define RCC_PREDIV27CFGR 0x1184
502
+
#define RCC_PREDIV28CFGR 0x1188
503
+
#define RCC_PREDIV29CFGR 0x118C
504
+
#define RCC_PREDIV30CFGR 0x1190
505
+
#define RCC_PREDIV31CFGR 0x1194
506
+
#define RCC_PREDIV32CFGR 0x1198
507
+
#define RCC_PREDIV33CFGR 0x119C
508
+
#define RCC_PREDIV34CFGR 0x11A0
509
+
#define RCC_PREDIV35CFGR 0x11A4
510
+
#define RCC_PREDIV36CFGR 0x11A8
511
+
#define RCC_PREDIV37CFGR 0x11AC
512
+
#define RCC_PREDIV38CFGR 0x11B0
513
+
#define RCC_PREDIV39CFGR 0x11B4
514
+
#define RCC_PREDIV40CFGR 0x11B8
515
+
#define RCC_PREDIV41CFGR 0x11BC
516
+
#define RCC_PREDIV42CFGR 0x11C0
517
+
#define RCC_PREDIV43CFGR 0x11C4
518
+
#define RCC_PREDIV44CFGR 0x11C8
519
+
#define RCC_PREDIV45CFGR 0x11CC
520
+
#define RCC_PREDIV46CFGR 0x11D0
521
+
#define RCC_PREDIV47CFGR 0x11D4
522
+
#define RCC_PREDIV48CFGR 0x11D8
523
+
#define RCC_PREDIV49CFGR 0x11DC
524
+
#define RCC_PREDIV50CFGR 0x11E0
525
+
#define RCC_PREDIV51CFGR 0x11E4
526
+
#define RCC_PREDIV52CFGR 0x11E8
527
+
#define RCC_PREDIV53CFGR 0x11EC
528
+
#define RCC_PREDIV54CFGR 0x11F0
529
+
#define RCC_PREDIV55CFGR 0x11F4
530
+
#define RCC_PREDIV56CFGR 0x11F8
531
+
#define RCC_PREDIV57CFGR 0x11FC
532
+
#define RCC_PREDIV58CFGR 0x1200
533
+
#define RCC_PREDIV59CFGR 0x1204
534
+
#define RCC_PREDIV60CFGR 0x1208
535
+
#define RCC_PREDIV61CFGR 0x120C
536
+
#define RCC_PREDIV62CFGR 0x1210
537
+
#define RCC_PREDIV63CFGR 0x1214
538
+
#define RCC_PREDIVSR1 0x1218
539
+
#define RCC_PREDIVSR2 0x121C
540
+
#define RCC_FINDIV0CFGR 0x1224
541
+
#define RCC_FINDIV1CFGR 0x1228
542
+
#define RCC_FINDIV2CFGR 0x122C
543
+
#define RCC_FINDIV3CFGR 0x1230
544
+
#define RCC_FINDIV4CFGR 0x1234
545
+
#define RCC_FINDIV5CFGR 0x1238
546
+
#define RCC_FINDIV6CFGR 0x123C
547
+
#define RCC_FINDIV7CFGR 0x1240
548
+
#define RCC_FINDIV8CFGR 0x1244
549
+
#define RCC_FINDIV9CFGR 0x1248
550
+
#define RCC_FINDIV10CFGR 0x124C
551
+
#define RCC_FINDIV11CFGR 0x1250
552
+
#define RCC_FINDIV12CFGR 0x1254
553
+
#define RCC_FINDIV13CFGR 0x1258
554
+
#define RCC_FINDIV14CFGR 0x125C
555
+
#define RCC_FINDIV15CFGR 0x1260
556
+
#define RCC_FINDIV16CFGR 0x1264
557
+
#define RCC_FINDIV17CFGR 0x1268
558
+
#define RCC_FINDIV18CFGR 0x126C
559
+
#define RCC_FINDIV19CFGR 0x1270
560
+
#define RCC_FINDIV20CFGR 0x1274
561
+
#define RCC_FINDIV21CFGR 0x1278
562
+
#define RCC_FINDIV22CFGR 0x127C
563
+
#define RCC_FINDIV23CFGR 0x1280
564
+
#define RCC_FINDIV24CFGR 0x1284
565
+
#define RCC_FINDIV25CFGR 0x1288
566
+
#define RCC_FINDIV26CFGR 0x128C
567
+
#define RCC_FINDIV27CFGR 0x1290
568
+
#define RCC_FINDIV28CFGR 0x1294
569
+
#define RCC_FINDIV29CFGR 0x1298
570
+
#define RCC_FINDIV30CFGR 0x129C
571
+
#define RCC_FINDIV31CFGR 0x12A0
572
+
#define RCC_FINDIV32CFGR 0x12A4
573
+
#define RCC_FINDIV33CFGR 0x12A8
574
+
#define RCC_FINDIV34CFGR 0x12AC
575
+
#define RCC_FINDIV35CFGR 0x12B0
576
+
#define RCC_FINDIV36CFGR 0x12B4
577
+
#define RCC_FINDIV37CFGR 0x12B8
578
+
#define RCC_FINDIV38CFGR 0x12BC
579
+
#define RCC_FINDIV39CFGR 0x12C0
580
+
#define RCC_FINDIV40CFGR 0x12C4
581
+
#define RCC_FINDIV41CFGR 0x12C8
582
+
#define RCC_FINDIV42CFGR 0x12CC
583
+
#define RCC_FINDIV43CFGR 0x12D0
584
+
#define RCC_FINDIV44CFGR 0x12D4
585
+
#define RCC_FINDIV45CFGR 0x12D8
586
+
#define RCC_FINDIV46CFGR 0x12DC
587
+
#define RCC_FINDIV47CFGR 0x12E0
588
+
#define RCC_FINDIV48CFGR 0x12E4
589
+
#define RCC_FINDIV49CFGR 0x12E8
590
+
#define RCC_FINDIV50CFGR 0x12EC
591
+
#define RCC_FINDIV51CFGR 0x12F0
592
+
#define RCC_FINDIV52CFGR 0x12F4
593
+
#define RCC_FINDIV53CFGR 0x12F8
594
+
#define RCC_FINDIV54CFGR 0x12FC
595
+
#define RCC_FINDIV55CFGR 0x1300
596
+
#define RCC_FINDIV56CFGR 0x1304
597
+
#define RCC_FINDIV57CFGR 0x1308
598
+
#define RCC_FINDIV58CFGR 0x130C
599
+
#define RCC_FINDIV59CFGR 0x1310
600
+
#define RCC_FINDIV60CFGR 0x1314
601
+
#define RCC_FINDIV61CFGR 0x1318
602
+
#define RCC_FINDIV62CFGR 0x131C
603
+
#define RCC_FINDIV63CFGR 0x1320
604
+
#define RCC_FINDIVSR1 0x1324
605
+
#define RCC_FINDIVSR2 0x1328
606
+
#define RCC_FCALCOBS0CFGR 0x1340
607
+
#define RCC_FCALCOBS1CFGR 0x1344
608
+
#define RCC_FCALCREFCFGR 0x1348
609
+
#define RCC_FCALCCR1 0x134C
610
+
#define RCC_FCALCCR2 0x1354
611
+
#define RCC_FCALCSR 0x1358
612
+
#define RCC_PLL4CFGR1 0x1360
613
+
#define RCC_PLL4CFGR2 0x1364
614
+
#define RCC_PLL4CFGR3 0x1368
615
+
#define RCC_PLL4CFGR4 0x136C
616
+
#define RCC_PLL4CFGR5 0x1370
617
+
#define RCC_PLL4CFGR6 0x1378
618
+
#define RCC_PLL4CFGR7 0x137C
619
+
#define RCC_PLL5CFGR1 0x1388
620
+
#define RCC_PLL5CFGR2 0x138C
621
+
#define RCC_PLL5CFGR3 0x1390
622
+
#define RCC_PLL5CFGR4 0x1394
623
+
#define RCC_PLL5CFGR5 0x1398
624
+
#define RCC_PLL5CFGR6 0x13A0
625
+
#define RCC_PLL5CFGR7 0x13A4
626
+
#define RCC_PLL6CFGR1 0x13B0
627
+
#define RCC_PLL6CFGR2 0x13B4
628
+
#define RCC_PLL6CFGR3 0x13B8
629
+
#define RCC_PLL6CFGR4 0x13BC
630
+
#define RCC_PLL6CFGR5 0x13C0
631
+
#define RCC_PLL6CFGR6 0x13C8
632
+
#define RCC_PLL6CFGR7 0x13CC
633
+
#define RCC_PLL7CFGR1 0x13D8
634
+
#define RCC_PLL7CFGR2 0x13DC
635
+
#define RCC_PLL7CFGR3 0x13E0
636
+
#define RCC_PLL7CFGR4 0x13E4
637
+
#define RCC_PLL7CFGR5 0x13E8
638
+
#define RCC_PLL7CFGR6 0x13F0
639
+
#define RCC_PLL7CFGR7 0x13F4
640
+
#define RCC_PLL8CFGR1 0x1400
641
+
#define RCC_PLL8CFGR2 0x1404
642
+
#define RCC_PLL8CFGR3 0x1408
643
+
#define RCC_PLL8CFGR4 0x140C
644
+
#define RCC_PLL8CFGR5 0x1410
645
+
#define RCC_PLL8CFGR6 0x1418
646
+
#define RCC_PLL8CFGR7 0x141C
647
+
#define RCC_VERR 0xFFF4
648
+
#define RCC_IDR 0xFFF8
649
+
#define RCC_SIDR 0xFFFC
650
+
651
+
#endif /* STM32MP21_RCC_H */
+426
include/dt-bindings/clock/st,stm32mp21-rcc.h
+426
include/dt-bindings/clock/st,stm32mp21-rcc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4
+
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
8
+
#define _DT_BINDINGS_STM32MP21_CLKS_H_
9
+
10
+
/* INTERNAL/EXTERNAL OSCILLATORS */
11
+
#define HSI_CK 0
12
+
#define HSE_CK 1
13
+
#define MSI_CK 2
14
+
#define LSI_CK 3
15
+
#define LSE_CK 4
16
+
#define I2S_CK 5
17
+
#define RTC_CK 6
18
+
#define SPDIF_CK_SYMB 7
19
+
20
+
/* PLL CLOCKS */
21
+
#define PLL1_CK 8
22
+
#define PLL2_CK 9
23
+
#define PLL4_CK 10
24
+
#define PLL5_CK 11
25
+
#define PLL6_CK 12
26
+
#define PLL7_CK 13
27
+
#define PLL8_CK 14
28
+
29
+
#define CK_CPU1 15
30
+
31
+
/* APB DIV CLOCKS */
32
+
#define CK_ICN_APB1 16
33
+
#define CK_ICN_APB2 17
34
+
#define CK_ICN_APB3 18
35
+
#define CK_ICN_APB4 19
36
+
#define CK_ICN_APB5 20
37
+
#define CK_ICN_APBDBG 21
38
+
39
+
/* GLOBAL TIMER */
40
+
#define TIMG1_CK 22
41
+
#define TIMG2_CK 23
42
+
43
+
/* FLEXGEN CLOCKS */
44
+
#define CK_ICN_HS_MCU 24
45
+
#define CK_ICN_SDMMC 25
46
+
#define CK_ICN_DDR 26
47
+
#define CK_ICN_DISPLAY 27
48
+
#define CK_ICN_HSL 28
49
+
#define CK_ICN_NIC 29
50
+
#define CK_ICN_VID 30
51
+
#define CK_FLEXGEN_07 31
52
+
#define CK_FLEXGEN_08 32
53
+
#define CK_FLEXGEN_09 33
54
+
#define CK_FLEXGEN_10 34
55
+
#define CK_FLEXGEN_11 35
56
+
#define CK_FLEXGEN_12 36
57
+
#define CK_FLEXGEN_13 37
58
+
#define CK_FLEXGEN_14 38
59
+
#define CK_FLEXGEN_15 39
60
+
#define CK_FLEXGEN_16 40
61
+
#define CK_FLEXGEN_17 41
62
+
#define CK_FLEXGEN_18 42
63
+
#define CK_FLEXGEN_19 43
64
+
#define CK_FLEXGEN_20 44
65
+
#define CK_FLEXGEN_21 45
66
+
#define CK_FLEXGEN_22 46
67
+
#define CK_FLEXGEN_23 47
68
+
#define CK_FLEXGEN_24 48
69
+
#define CK_FLEXGEN_25 49
70
+
#define CK_FLEXGEN_26 50
71
+
#define CK_FLEXGEN_27 51
72
+
#define CK_FLEXGEN_28 52
73
+
#define CK_FLEXGEN_29 53
74
+
#define CK_FLEXGEN_30 54
75
+
#define CK_FLEXGEN_31 55
76
+
#define CK_FLEXGEN_32 56
77
+
#define CK_FLEXGEN_33 57
78
+
#define CK_FLEXGEN_34 58
79
+
#define CK_FLEXGEN_35 59
80
+
#define CK_FLEXGEN_36 60
81
+
#define CK_FLEXGEN_37 61
82
+
#define CK_FLEXGEN_38 62
83
+
#define CK_FLEXGEN_39 63
84
+
#define CK_FLEXGEN_40 64
85
+
#define CK_FLEXGEN_41 65
86
+
#define CK_FLEXGEN_42 66
87
+
#define CK_FLEXGEN_43 67
88
+
#define CK_FLEXGEN_44 68
89
+
#define CK_FLEXGEN_45 69
90
+
#define CK_FLEXGEN_46 70
91
+
#define CK_FLEXGEN_47 71
92
+
#define CK_FLEXGEN_48 72
93
+
#define CK_FLEXGEN_49 73
94
+
#define CK_FLEXGEN_50 74
95
+
#define CK_FLEXGEN_51 75
96
+
#define CK_FLEXGEN_52 76
97
+
#define CK_FLEXGEN_53 77
98
+
#define CK_FLEXGEN_54 78
99
+
#define CK_FLEXGEN_55 79
100
+
#define CK_FLEXGEN_56 80
101
+
#define CK_FLEXGEN_57 81
102
+
#define CK_FLEXGEN_58 82
103
+
#define CK_FLEXGEN_59 83
104
+
#define CK_FLEXGEN_60 84
105
+
#define CK_FLEXGEN_61 85
106
+
#define CK_FLEXGEN_62 86
107
+
#define CK_FLEXGEN_63 87
108
+
109
+
/* LOW SPEED MCU CLOCK */
110
+
#define CK_ICN_LS_MCU 88
111
+
112
+
#define CK_BUS_STM 89
113
+
#define CK_BUS_FMC 90
114
+
#define CK_BUS_ETH1 91
115
+
#define CK_BUS_ETH2 92
116
+
#define CK_BUS_DDRPHYC 93
117
+
#define CK_BUS_SYSCPU1 94
118
+
#define CK_BUS_HPDMA1 95
119
+
#define CK_BUS_HPDMA2 96
120
+
#define CK_BUS_HPDMA3 97
121
+
#define CK_BUS_ADC1 98
122
+
#define CK_BUS_ADC2 99
123
+
#define CK_BUS_IPCC1 100
124
+
#define CK_BUS_DCMIPSSI 101
125
+
#define CK_BUS_CRC 102
126
+
#define CK_BUS_MDF1 103
127
+
#define CK_BUS_BKPSRAM 104
128
+
#define CK_BUS_HASH1 105
129
+
#define CK_BUS_HASH2 106
130
+
#define CK_BUS_RNG1 107
131
+
#define CK_BUS_RNG2 108
132
+
#define CK_BUS_CRYP1 109
133
+
#define CK_BUS_CRYP2 110
134
+
#define CK_BUS_SAES 111
135
+
#define CK_BUS_PKA 112
136
+
#define CK_BUS_GPIOA 113
137
+
#define CK_BUS_GPIOB 114
138
+
#define CK_BUS_GPIOC 115
139
+
#define CK_BUS_GPIOD 116
140
+
#define CK_BUS_GPIOE 117
141
+
#define CK_BUS_GPIOF 118
142
+
#define CK_BUS_GPIOG 119
143
+
#define CK_BUS_GPIOH 120
144
+
#define CK_BUS_GPIOI 121
145
+
#define CK_BUS_GPIOZ 122
146
+
#define CK_BUS_RTC 124
147
+
#define CK_BUS_LPUART1 125
148
+
#define CK_BUS_LPTIM3 126
149
+
#define CK_BUS_LPTIM4 127
150
+
#define CK_BUS_LPTIM5 128
151
+
#define CK_BUS_TIM2 129
152
+
#define CK_BUS_TIM3 130
153
+
#define CK_BUS_TIM4 131
154
+
#define CK_BUS_TIM5 132
155
+
#define CK_BUS_TIM6 133
156
+
#define CK_BUS_TIM7 134
157
+
#define CK_BUS_TIM10 135
158
+
#define CK_BUS_TIM11 136
159
+
#define CK_BUS_TIM12 137
160
+
#define CK_BUS_TIM13 138
161
+
#define CK_BUS_TIM14 139
162
+
#define CK_BUS_LPTIM1 140
163
+
#define CK_BUS_LPTIM2 141
164
+
#define CK_BUS_SPI2 142
165
+
#define CK_BUS_SPI3 143
166
+
#define CK_BUS_SPDIFRX 144
167
+
#define CK_BUS_USART2 145
168
+
#define CK_BUS_USART3 146
169
+
#define CK_BUS_UART4 147
170
+
#define CK_BUS_UART5 148
171
+
#define CK_BUS_I2C1 149
172
+
#define CK_BUS_I2C2 150
173
+
#define CK_BUS_I2C3 151
174
+
#define CK_BUS_I3C1 152
175
+
#define CK_BUS_I3C2 153
176
+
#define CK_BUS_I3C3 154
177
+
#define CK_BUS_TIM1 155
178
+
#define CK_BUS_TIM8 156
179
+
#define CK_BUS_TIM15 157
180
+
#define CK_BUS_TIM16 158
181
+
#define CK_BUS_TIM17 159
182
+
#define CK_BUS_SAI1 160
183
+
#define CK_BUS_SAI2 161
184
+
#define CK_BUS_SAI3 162
185
+
#define CK_BUS_SAI4 163
186
+
#define CK_BUS_USART1 164
187
+
#define CK_BUS_USART6 165
188
+
#define CK_BUS_UART7 166
189
+
#define CK_BUS_FDCAN 167
190
+
#define CK_BUS_SPI1 168
191
+
#define CK_BUS_SPI4 169
192
+
#define CK_BUS_SPI5 170
193
+
#define CK_BUS_SPI6 171
194
+
#define CK_BUS_BSEC 172
195
+
#define CK_BUS_IWDG1 173
196
+
#define CK_BUS_IWDG2 174
197
+
#define CK_BUS_IWDG3 175
198
+
#define CK_BUS_IWDG4 176
199
+
#define CK_BUS_WWDG1 177
200
+
#define CK_BUS_VREF 178
201
+
#define CK_BUS_DTS 179
202
+
#define CK_BUS_SERC 180
203
+
#define CK_BUS_HDP 181
204
+
#define CK_BUS_DDRPERFM 182
205
+
#define CK_BUS_OTG 183
206
+
#define CK_BUS_LTDC 184
207
+
#define CK_BUS_CSI 185
208
+
#define CK_BUS_DCMIPP 186
209
+
#define CK_BUS_DDRC 187
210
+
#define CK_BUS_DDRCFG 188
211
+
#define CK_BUS_STGEN 189
212
+
#define CK_SYSDBG 190
213
+
#define CK_KER_TIM2 191
214
+
#define CK_KER_TIM3 192
215
+
#define CK_KER_TIM4 193
216
+
#define CK_KER_TIM5 194
217
+
#define CK_KER_TIM6 195
218
+
#define CK_KER_TIM7 196
219
+
#define CK_KER_TIM10 197
220
+
#define CK_KER_TIM11 198
221
+
#define CK_KER_TIM12 199
222
+
#define CK_KER_TIM13 200
223
+
#define CK_KER_TIM14 201
224
+
#define CK_KER_TIM1 202
225
+
#define CK_KER_TIM8 203
226
+
#define CK_KER_TIM15 204
227
+
#define CK_KER_TIM16 205
228
+
#define CK_KER_TIM17 206
229
+
#define CK_BUS_SYSRAM 207
230
+
#define CK_BUS_RETRAM 208
231
+
#define CK_BUS_OSPI1 209
232
+
#define CK_BUS_OTFD1 210
233
+
#define CK_BUS_SRAM1 211
234
+
#define CK_BUS_SDMMC1 212
235
+
#define CK_BUS_SDMMC2 213
236
+
#define CK_BUS_SDMMC3 214
237
+
#define CK_BUS_DDR 215
238
+
#define CK_BUS_RISAF4 216
239
+
#define CK_BUS_USBHOHCI 217
240
+
#define CK_BUS_USBHEHCI 218
241
+
#define CK_KER_LPTIM1 219
242
+
#define CK_KER_LPTIM2 220
243
+
#define CK_KER_USART2 221
244
+
#define CK_KER_UART4 222
245
+
#define CK_KER_USART3 223
246
+
#define CK_KER_UART5 224
247
+
#define CK_KER_SPI2 225
248
+
#define CK_KER_SPI3 226
249
+
#define CK_KER_SPDIFRX 227
250
+
#define CK_KER_I2C1 228
251
+
#define CK_KER_I2C2 229
252
+
#define CK_KER_I3C1 230
253
+
#define CK_KER_I3C2 231
254
+
#define CK_KER_I2C3 232
255
+
#define CK_KER_I3C3 233
256
+
#define CK_KER_SPI1 234
257
+
#define CK_KER_SPI4 235
258
+
#define CK_KER_SPI5 236
259
+
#define CK_KER_SPI6 237
260
+
#define CK_KER_USART1 238
261
+
#define CK_KER_USART6 239
262
+
#define CK_KER_UART7 240
263
+
#define CK_KER_MDF1 241
264
+
#define CK_KER_SAI1 242
265
+
#define CK_KER_SAI2 243
266
+
#define CK_KER_SAI3 244
267
+
#define CK_KER_SAI4 245
268
+
#define CK_KER_FDCAN 246
269
+
#define CK_KER_CSI 247
270
+
#define CK_KER_CSITXESC 248
271
+
#define CK_KER_CSIPHY 249
272
+
#define CK_KER_STGEN 250
273
+
#define CK_KER_USB2PHY2EN 251
274
+
#define CK_KER_LPUART1 252
275
+
#define CK_KER_LPTIM3 253
276
+
#define CK_KER_LPTIM4 254
277
+
#define CK_KER_LPTIM5 255
278
+
#define CK_KER_TSDBG 256
279
+
#define CK_KER_TPIU 257
280
+
#define CK_BUS_ETR 258
281
+
#define CK_BUS_SYSATB 259
282
+
#define CK_KER_ADC1 260
283
+
#define CK_KER_ADC2 261
284
+
#define CK_KER_OSPI1 262
285
+
#define CK_KER_FMC 263
286
+
#define CK_KER_SDMMC1 264
287
+
#define CK_KER_SDMMC2 265
288
+
#define CK_KER_SDMMC3 266
289
+
#define CK_KER_ETH1 267
290
+
#define CK_KER_ETH2 268
291
+
#define CK_KER_ETH1PTP 269
292
+
#define CK_KER_ETH2PTP 270
293
+
#define CK_KER_USB2PHY1 271
294
+
#define CK_KER_USB2PHY2 272
295
+
#define CK_MCO1 273
296
+
#define CK_MCO2 274
297
+
#define CK_KER_DTS 275
298
+
#define CK_ETH1_RX 276
299
+
#define CK_ETH1_TX 277
300
+
#define CK_ETH1_MAC 278
301
+
#define CK_ETH2_RX 279
302
+
#define CK_ETH2_TX 280
303
+
#define CK_ETH2_MAC 281
304
+
#define CK_ETH1_STP 282
305
+
#define CK_ETH2_STP 283
306
+
#define CK_KER_LTDC 284
307
+
#define HSE_DIV2_CK 285
308
+
#define CK_DBGMCU 286
309
+
#define CK_DAP 287
310
+
#define CK_KER_ETR 288
311
+
#define CK_KER_STM 289
312
+
313
+
#define CK_SCMI_ICN_HS_MCU 0
314
+
#define CK_SCMI_ICN_SDMMC 1
315
+
#define CK_SCMI_ICN_DDR 2
316
+
#define CK_SCMI_ICN_DISPLAY 3
317
+
#define CK_SCMI_ICN_HSL 4
318
+
#define CK_SCMI_ICN_NIC 5
319
+
#define CK_SCMI_FLEXGEN_07 7
320
+
#define CK_SCMI_FLEXGEN_08 8
321
+
#define CK_SCMI_FLEXGEN_09 9
322
+
#define CK_SCMI_FLEXGEN_10 10
323
+
#define CK_SCMI_FLEXGEN_11 11
324
+
#define CK_SCMI_FLEXGEN_12 12
325
+
#define CK_SCMI_FLEXGEN_13 13
326
+
#define CK_SCMI_FLEXGEN_14 14
327
+
#define CK_SCMI_FLEXGEN_15 15
328
+
#define CK_SCMI_FLEXGEN_16 16
329
+
#define CK_SCMI_FLEXGEN_17 17
330
+
#define CK_SCMI_FLEXGEN_18 18
331
+
#define CK_SCMI_FLEXGEN_19 19
332
+
#define CK_SCMI_FLEXGEN_20 20
333
+
#define CK_SCMI_FLEXGEN_21 21
334
+
#define CK_SCMI_FLEXGEN_22 22
335
+
#define CK_SCMI_FLEXGEN_23 23
336
+
#define CK_SCMI_FLEXGEN_24 24
337
+
#define CK_SCMI_FLEXGEN_25 25
338
+
#define CK_SCMI_FLEXGEN_26 26
339
+
#define CK_SCMI_FLEXGEN_27 27
340
+
#define CK_SCMI_FLEXGEN_28 28
341
+
#define CK_SCMI_FLEXGEN_29 29
342
+
#define CK_SCMI_FLEXGEN_30 30
343
+
#define CK_SCMI_FLEXGEN_31 31
344
+
#define CK_SCMI_FLEXGEN_32 32
345
+
#define CK_SCMI_FLEXGEN_33 33
346
+
#define CK_SCMI_FLEXGEN_34 34
347
+
#define CK_SCMI_FLEXGEN_35 35
348
+
#define CK_SCMI_FLEXGEN_36 36
349
+
#define CK_SCMI_FLEXGEN_37 37
350
+
#define CK_SCMI_FLEXGEN_38 38
351
+
#define CK_SCMI_FLEXGEN_39 39
352
+
#define CK_SCMI_FLEXGEN_40 40
353
+
#define CK_SCMI_FLEXGEN_41 41
354
+
#define CK_SCMI_FLEXGEN_42 42
355
+
#define CK_SCMI_FLEXGEN_43 43
356
+
#define CK_SCMI_FLEXGEN_44 44
357
+
#define CK_SCMI_FLEXGEN_45 45
358
+
#define CK_SCMI_FLEXGEN_46 46
359
+
#define CK_SCMI_FLEXGEN_47 47
360
+
#define CK_SCMI_FLEXGEN_48 48
361
+
#define CK_SCMI_FLEXGEN_49 49
362
+
#define CK_SCMI_FLEXGEN_50 50
363
+
#define CK_SCMI_FLEXGEN_51 51
364
+
#define CK_SCMI_FLEXGEN_52 52
365
+
#define CK_SCMI_FLEXGEN_53 53
366
+
#define CK_SCMI_FLEXGEN_54 54
367
+
#define CK_SCMI_FLEXGEN_55 55
368
+
#define CK_SCMI_FLEXGEN_56 56
369
+
#define CK_SCMI_FLEXGEN_57 57
370
+
#define CK_SCMI_FLEXGEN_58 58
371
+
#define CK_SCMI_FLEXGEN_59 59
372
+
#define CK_SCMI_FLEXGEN_60 60
373
+
#define CK_SCMI_FLEXGEN_61 61
374
+
#define CK_SCMI_FLEXGEN_62 62
375
+
#define CK_SCMI_FLEXGEN_63 63
376
+
#define CK_SCMI_ICN_LS_MCU 64
377
+
#define CK_SCMI_HSE 65
378
+
#define CK_SCMI_LSE 66
379
+
#define CK_SCMI_HSI 67
380
+
#define CK_SCMI_LSI 68
381
+
#define CK_SCMI_MSI 69
382
+
#define CK_SCMI_HSE_DIV2 70
383
+
#define CK_SCMI_CPU1 71
384
+
#define CK_SCMI_SYSCPU1 72
385
+
#define CK_SCMI_PLL2 73
386
+
#define CK_SCMI_RTC 74
387
+
#define CK_SCMI_RTCCK 75
388
+
#define CK_SCMI_ICN_APB1 76
389
+
#define CK_SCMI_ICN_APB2 77
390
+
#define CK_SCMI_ICN_APB3 78
391
+
#define CK_SCMI_ICN_APB4 79
392
+
#define CK_SCMI_ICN_APB5 80
393
+
#define CK_SCMI_ICN_APBDBG 81
394
+
#define CK_SCMI_TIMG1 82
395
+
#define CK_SCMI_TIMG2 83
396
+
#define CK_SCMI_BKPSRAM 84
397
+
#define CK_SCMI_BSEC 85
398
+
#define CK_SCMI_BUS_ETR 86
399
+
#define CK_SCMI_FMC 87
400
+
#define CK_SCMI_GPIOA 88
401
+
#define CK_SCMI_GPIOB 89
402
+
#define CK_SCMI_GPIOC 90
403
+
#define CK_SCMI_GPIOD 91
404
+
#define CK_SCMI_GPIOE 92
405
+
#define CK_SCMI_GPIOF 93
406
+
#define CK_SCMI_GPIOG 94
407
+
#define CK_SCMI_GPIOH 95
408
+
#define CK_SCMI_GPIOI 96
409
+
#define CK_SCMI_GPIOZ 97
410
+
#define CK_SCMI_HPDMA1 98
411
+
#define CK_SCMI_HPDMA2 99
412
+
#define CK_SCMI_HPDMA3 100
413
+
#define CK_SCMI_IPCC1 101
414
+
#define CK_SCMI_RETRAM 102
415
+
#define CK_SCMI_SRAM1 103
416
+
#define CK_SCMI_SYSRAM 104
417
+
#define CK_SCMI_OSPI1 105
418
+
#define CK_SCMI_TPIU 106
419
+
#define CK_SCMI_SYSDBG 107
420
+
#define CK_SCMI_SYSATB 108
421
+
#define CK_SCMI_TSDBG 109
422
+
#define CK_SCMI_BUS_STM 110
423
+
#define CK_SCMI_KER_STM 111
424
+
#define CK_SCMI_KER_ETR 112
425
+
426
+
#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */
+138
include/dt-bindings/reset/st,stm32mp21-rcc.h
+138
include/dt-bindings/reset/st,stm32mp21-rcc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4
+
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
8
+
#define _DT_BINDINGS_STM32MP21_RESET_H_
9
+
10
+
#define TIM1_R 0
11
+
#define TIM2_R 1
12
+
#define TIM3_R 2
13
+
#define TIM4_R 3
14
+
#define TIM5_R 4
15
+
#define TIM6_R 5
16
+
#define TIM7_R 6
17
+
#define TIM8_R 7
18
+
#define TIM10_R 8
19
+
#define TIM11_R 9
20
+
#define TIM12_R 10
21
+
#define TIM13_R 11
22
+
#define TIM14_R 12
23
+
#define TIM15_R 13
24
+
#define TIM16_R 14
25
+
#define TIM17_R 15
26
+
#define LPTIM1_R 16
27
+
#define LPTIM2_R 17
28
+
#define LPTIM3_R 18
29
+
#define LPTIM4_R 19
30
+
#define LPTIM5_R 20
31
+
#define SPI1_R 21
32
+
#define SPI2_R 22
33
+
#define SPI3_R 23
34
+
#define SPI4_R 24
35
+
#define SPI5_R 25
36
+
#define SPI6_R 26
37
+
#define SPDIFRX_R 27
38
+
#define USART1_R 28
39
+
#define USART2_R 29
40
+
#define USART3_R 30
41
+
#define UART4_R 31
42
+
#define UART5_R 32
43
+
#define USART6_R 33
44
+
#define UART7_R 34
45
+
#define LPUART1_R 35
46
+
#define I2C1_R 36
47
+
#define I2C2_R 37
48
+
#define I2C3_R 38
49
+
#define SAI1_R 39
50
+
#define SAI2_R 40
51
+
#define SAI3_R 41
52
+
#define SAI4_R 42
53
+
#define MDF1_R 43
54
+
#define FDCAN_R 44
55
+
#define HDP_R 45
56
+
#define ADC1_R 46
57
+
#define ADC2_R 47
58
+
#define ETH1_R 48
59
+
#define ETH2_R 49
60
+
#define USBH_R 50
61
+
#define USB2PHY1_R 51
62
+
#define USB2PHY2_R 52
63
+
#define SDMMC1_R 53
64
+
#define SDMMC1DLL_R 54
65
+
#define SDMMC2_R 55
66
+
#define SDMMC2DLL_R 56
67
+
#define SDMMC3_R 57
68
+
#define SDMMC3DLL_R 58
69
+
#define LTDC_R 59
70
+
#define CSI_R 60
71
+
#define DCMIPP_R 61
72
+
#define DCMIPSSI_R 62
73
+
#define WWDG1_R 63
74
+
#define VREF_R 64
75
+
#define DTS_R 65
76
+
#define CRC_R 66
77
+
#define SERC_R 67
78
+
#define I3C1_R 68
79
+
#define I3C2_R 69
80
+
#define I3C3_R 70
81
+
#define IWDG2_KER_R 71
82
+
#define IWDG4_KER_R 72
83
+
#define RNG1_R 73
84
+
#define RNG2_R 74
85
+
#define PKA_R 75
86
+
#define SAES_R 76
87
+
#define HASH1_R 77
88
+
#define HASH2_R 78
89
+
#define CRYP1_R 79
90
+
#define CRYP2_R 80
91
+
#define OSPI1_R 81
92
+
#define OSPI1DLL_R 82
93
+
#define OTG_R 83
94
+
#define FMC_R 84
95
+
#define DBG_R 85
96
+
#define GPIOA_R 86
97
+
#define GPIOB_R 87
98
+
#define GPIOC_R 88
99
+
#define GPIOD_R 89
100
+
#define GPIOE_R 90
101
+
#define GPIOF_R 91
102
+
#define GPIOG_R 92
103
+
#define GPIOH_R 93
104
+
#define GPIOI_R 94
105
+
#define GPIOZ_R 95
106
+
#define HPDMA1_R 96
107
+
#define HPDMA2_R 97
108
+
#define HPDMA3_R 98
109
+
#define IPCC1_R 99
110
+
#define C2_HOLDBOOT_R 100
111
+
#define C1_HOLDBOOT_R 101
112
+
#define C1_R 102
113
+
#define C1P1POR_R 103
114
+
#define C1P1_R 104
115
+
#define C2_R 105
116
+
#define SYS_R 106
117
+
#define VSW_R 107
118
+
#define C1MS_R 108
119
+
#define DDRCP_R 109
120
+
#define DDRCAPB_R 110
121
+
#define DDRPHYCAPB_R 111
122
+
#define DDRCFG_R 112
123
+
#define DDR_R 113
124
+
#define DDRPERFM_R 114
125
+
#define IWDG1_SYS_R 116
126
+
#define IWDG2_SYS_R 117
127
+
#define IWDG3_SYS_R 118
128
+
#define IWDG4_SYS_R 119
129
+
130
+
#define RST_SCMI_C1_R 0
131
+
#define RST_SCMI_C2_R 1
132
+
#define RST_SCMI_C1_HOLDBOOT_R 2
133
+
#define RST_SCMI_C2_HOLDBOOT_R 3
134
+
#define RST_SCMI_FMC 4
135
+
#define RST_SCMI_OSPI1 5
136
+
#define RST_SCMI_OSPI1DLL 6
137
+
138
+
#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
-2
include/linux/clk/at91_pmc.h
-2
include/linux/clk/at91_pmc.h
···
47
47
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
48
48
49
49
#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
50
-
#define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
51
-
#define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */
52
50
#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
53
51
#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
54
52