Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/{i915, xe}/display: duplicate gen2 irq/error init/reset in display irq
Duplicate gen2_irq_reset(), gen2_assert_iir_is_zero(), gen2_irq_init(),
gen2_error_reset(), and gen2_error_init() in intel_display_irq.c.
This allows us to drop the duplicates from xe, and prepares for future
cleanups. Although duplication is undesirable in general, in this case
the local duplicates lead to a cleaner end result.
There's a slight wrinkle in gen2_assert_iir_is_zero(). We need to use
non-device based logging until we pass in struct intel_display in a
separate change.
v2:
- Keep xe compat stuff due to series reorder and rebase
- Keep the WARN as regular WARN
- Rename the functions in the same go
Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/296d74731cce57ab7534c57969d3146294adda57.1763370931.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+73
-76
+73
-9
drivers/gpu/drm/i915/display/intel_display_irq.c
+73
-9
drivers/gpu/drm/i915/display/intel_display_irq.c
···
33
33
#include "intel_psr_regs.h"
34
34
#include "intel_uncore.h"
35
35
36
+
static void irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
37
+
{
38
+
intel_uncore_write(uncore, regs.imr, 0xffffffff);
39
+
intel_uncore_posting_read(uncore, regs.imr);
40
+
41
+
intel_uncore_write(uncore, regs.ier, 0);
42
+
43
+
/* IIR can theoretically queue up two events. Be paranoid. */
44
+
intel_uncore_write(uncore, regs.iir, 0xffffffff);
45
+
intel_uncore_posting_read(uncore, regs.iir);
46
+
intel_uncore_write(uncore, regs.iir, 0xffffffff);
47
+
intel_uncore_posting_read(uncore, regs.iir);
48
+
}
49
+
50
+
/*
51
+
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
52
+
*/
53
+
static void assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
54
+
{
55
+
u32 val = intel_uncore_read(uncore, reg);
56
+
57
+
if (val == 0)
58
+
return;
59
+
60
+
WARN(1,
61
+
"Interrupt register 0x%x is not zero: 0x%08x\n",
62
+
i915_mmio_reg_offset(reg), val);
63
+
intel_uncore_write(uncore, reg, 0xffffffff);
64
+
intel_uncore_posting_read(uncore, reg);
65
+
intel_uncore_write(uncore, reg, 0xffffffff);
66
+
intel_uncore_posting_read(uncore, reg);
67
+
}
68
+
69
+
static void irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
70
+
u32 imr_val, u32 ier_val)
71
+
{
72
+
assert_iir_is_zero(uncore, regs.iir);
73
+
74
+
intel_uncore_write(uncore, regs.ier, ier_val);
75
+
intel_uncore_write(uncore, regs.imr, imr_val);
76
+
intel_uncore_posting_read(uncore, regs.imr);
77
+
}
78
+
79
+
static void error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
80
+
{
81
+
intel_uncore_write(uncore, regs.emr, 0xffffffff);
82
+
intel_uncore_posting_read(uncore, regs.emr);
83
+
84
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
85
+
intel_uncore_posting_read(uncore, regs.eir);
86
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
87
+
intel_uncore_posting_read(uncore, regs.eir);
88
+
}
89
+
90
+
static void error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
91
+
u32 emr_val)
92
+
{
93
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
94
+
intel_uncore_posting_read(uncore, regs.eir);
95
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
96
+
intel_uncore_posting_read(uncore, regs.eir);
97
+
98
+
intel_uncore_write(uncore, regs.emr, emr_val);
99
+
intel_uncore_posting_read(uncore, regs.emr);
100
+
}
101
+
36
102
static void
37
103
intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs,
38
104
u32 imr_val, u32 ier_val)
···
107
41
intel_dmc_wl_get(display, regs.ier);
108
42
intel_dmc_wl_get(display, regs.iir);
109
43
110
-
gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val);
44
+
irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val);
111
45
112
46
intel_dmc_wl_put(display, regs.iir);
113
47
intel_dmc_wl_put(display, regs.ier);
···
121
55
intel_dmc_wl_get(display, regs.ier);
122
56
intel_dmc_wl_get(display, regs.iir);
123
57
124
-
gen2_irq_reset(to_intel_uncore(display->drm), regs);
58
+
irq_reset(to_intel_uncore(display->drm), regs);
125
59
126
60
intel_dmc_wl_put(display, regs.iir);
127
61
intel_dmc_wl_put(display, regs.ier);
···
133
67
{
134
68
intel_dmc_wl_get(display, reg);
135
69
136
-
gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg);
70
+
assert_iir_is_zero(to_intel_uncore(display->drm), reg);
137
71
138
72
intel_dmc_wl_put(display, reg);
139
73
}
···
1984
1918
else
1985
1919
intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
1986
1920
1987
-
gen2_error_reset(to_intel_uncore(display->drm),
1988
-
VLV_ERROR_REGS);
1921
+
error_reset(to_intel_uncore(display->drm), VLV_ERROR_REGS);
1989
1922
1990
1923
i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);
1991
1924
intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
···
2079
2014
DPINVGTT_STATUS_MASK_VLV |
2080
2015
DPINVGTT_EN_MASK_VLV);
2081
2016
2082
-
gen2_error_init(to_intel_uncore(display->drm),
2083
-
VLV_ERROR_REGS, ~vlv_error_mask());
2017
+
error_init(to_intel_uncore(display->drm), VLV_ERROR_REGS, ~vlv_error_mask());
2084
2018
2085
2019
pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2086
2020
···
2118
2054
if (HAS_PCH_NOP(display))
2119
2055
return;
2120
2056
2121
-
gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS);
2057
+
irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS);
2122
2058
2123
2059
if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))
2124
2060
intel_de_write(display, SERR_INT, 0xffffffff);
···
2128
2064
{
2129
2065
struct intel_uncore *uncore = to_intel_uncore(display->drm);
2130
2066
2131
-
gen2_irq_reset(uncore, DE_IRQ_REGS);
2067
+
irq_reset(uncore, DE_IRQ_REGS);
2132
2068
display->irq.ilk_de_imr_mask = ~0u;
2133
2069
2134
2070
if (DISPLAY_VER(display) == 7)
-67
drivers/gpu/drm/xe/display/ext/i915_irq.c
-67
drivers/gpu/drm/xe/display/ext/i915_irq.c
···
7
7
#include "i915_reg.h"
8
8
#include "intel_uncore.h"
9
9
10
-
void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
11
-
{
12
-
intel_uncore_write(uncore, regs.imr, 0xffffffff);
13
-
intel_uncore_posting_read(uncore, regs.imr);
14
-
15
-
intel_uncore_write(uncore, regs.ier, 0);
16
-
17
-
/* IIR can theoretically queue up two events. Be paranoid. */
18
-
intel_uncore_write(uncore, regs.iir, 0xffffffff);
19
-
intel_uncore_posting_read(uncore, regs.iir);
20
-
intel_uncore_write(uncore, regs.iir, 0xffffffff);
21
-
intel_uncore_posting_read(uncore, regs.iir);
22
-
}
23
-
24
-
/*
25
-
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
26
-
*/
27
-
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
28
-
{
29
-
struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
30
-
u32 val = intel_uncore_read(uncore, reg);
31
-
32
-
if (val == 0)
33
-
return;
34
-
35
-
drm_WARN(&xe->drm, 1,
36
-
"Interrupt register 0x%x is not zero: 0x%08x\n",
37
-
i915_mmio_reg_offset(reg), val);
38
-
intel_uncore_write(uncore, reg, 0xffffffff);
39
-
intel_uncore_posting_read(uncore, reg);
40
-
intel_uncore_write(uncore, reg, 0xffffffff);
41
-
intel_uncore_posting_read(uncore, reg);
42
-
}
43
-
44
-
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
45
-
u32 imr_val, u32 ier_val)
46
-
{
47
-
gen2_assert_iir_is_zero(uncore, regs.iir);
48
-
49
-
intel_uncore_write(uncore, regs.ier, ier_val);
50
-
intel_uncore_write(uncore, regs.imr, imr_val);
51
-
intel_uncore_posting_read(uncore, regs.imr);
52
-
}
53
-
54
-
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
55
-
{
56
-
intel_uncore_write(uncore, regs.emr, 0xffffffff);
57
-
intel_uncore_posting_read(uncore, regs.emr);
58
-
59
-
intel_uncore_write(uncore, regs.eir, 0xffffffff);
60
-
intel_uncore_posting_read(uncore, regs.eir);
61
-
intel_uncore_write(uncore, regs.eir, 0xffffffff);
62
-
intel_uncore_posting_read(uncore, regs.eir);
63
-
}
64
-
65
-
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
66
-
u32 emr_val)
67
-
{
68
-
intel_uncore_write(uncore, regs.eir, 0xffffffff);
69
-
intel_uncore_posting_read(uncore, regs.eir);
70
-
intel_uncore_write(uncore, regs.eir, 0xffffffff);
71
-
intel_uncore_posting_read(uncore, regs.eir);
72
-
73
-
intel_uncore_write(uncore, regs.emr, emr_val);
74
-
intel_uncore_posting_read(uncore, regs.emr);
75
-
}
76
-
77
10
bool intel_irqs_enabled(struct xe_device *xe)
78
11
{
79
12
return atomic_read(&xe->irq.enabled);