Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Nothing controversial, just another batch of fixes:
- Samsung/exynos fixes for more merge window fallout: build errors
and warnings mostly, but also some clock/device setup issues on
exynos4/5
- PXA bug and warning fixes related to gpio and pinmux
- IRQ domain conversion bugfixes for U300 and MSM
- A regulator setup fix for U300"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: PXA2xx: MFP: fix potential direction bug
ARM: PXA2xx: MFP: fix bug with MFP_LPM_KEEP_OUTPUT
arm/sa1100: fix sa1100-rtc memory resource
ARM: pxa: fix gpio wakeup setting
ARM: SAMSUNG: add missing MMC_CAP2_BROKEN_VOLTAGE capability
ARM: EXYNOS: Fix compilation error when CONFIG_OF is not defined
ARM: EXYNOS: Fix resource on dev-dwmci.c
ARM: S3C24XX: Fix build warning for S3C2410_PM
ARM: mini2440_defconfig: Fix build error
ARM: msm: Fix gic irqdomain support
ARM: EXYNOS: Fix incorrect initialization of GIC
ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers
ARM: u300: bump all IRQ numbers by one
ARM: ux300: Fix unimplementable regulation constraints
+230
-142
+2
-2
arch/arm/boot/dts/msm8660-surf.dts
+2
-2
arch/arm/boot/dts/msm8660-surf.dts
···
10
10
intc: interrupt-controller@02080000 {
11
11
compatible = "qcom,msm-8660-qgic";
12
12
interrupt-controller;
13
-
#interrupt-cells = <1>;
13
+
#interrupt-cells = <3>;
14
14
reg = < 0x02080000 0x1000 >,
15
15
< 0x02081000 0x1000 >;
16
16
};
···
19
19
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
20
20
reg = <0x19c40000 0x1000>,
21
21
<0x19c00000 0x1000>;
22
-
interrupts = <195>;
22
+
interrupts = <0 195 0x0>;
23
23
};
24
24
};
+2
arch/arm/configs/mini2440_defconfig
+2
arch/arm/configs/mini2440_defconfig
+12
-12
arch/arm/mach-exynos/clock-exynos4.c
+12
-12
arch/arm/mach-exynos/clock-exynos4.c
···
497
497
.ctrlbit = (1 << 3),
498
498
}, {
499
499
.name = "hsmmc",
500
-
.devname = "s3c-sdhci.0",
500
+
.devname = "exynos4-sdhci.0",
501
501
.parent = &exynos4_clk_aclk_133.clk,
502
502
.enable = exynos4_clk_ip_fsys_ctrl,
503
503
.ctrlbit = (1 << 5),
504
504
}, {
505
505
.name = "hsmmc",
506
-
.devname = "s3c-sdhci.1",
506
+
.devname = "exynos4-sdhci.1",
507
507
.parent = &exynos4_clk_aclk_133.clk,
508
508
.enable = exynos4_clk_ip_fsys_ctrl,
509
509
.ctrlbit = (1 << 6),
510
510
}, {
511
511
.name = "hsmmc",
512
-
.devname = "s3c-sdhci.2",
512
+
.devname = "exynos4-sdhci.2",
513
513
.parent = &exynos4_clk_aclk_133.clk,
514
514
.enable = exynos4_clk_ip_fsys_ctrl,
515
515
.ctrlbit = (1 << 7),
516
516
}, {
517
517
.name = "hsmmc",
518
-
.devname = "s3c-sdhci.3",
518
+
.devname = "exynos4-sdhci.3",
519
519
.parent = &exynos4_clk_aclk_133.clk,
520
520
.enable = exynos4_clk_ip_fsys_ctrl,
521
521
.ctrlbit = (1 << 8),
···
1202
1202
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1203
1203
.clk = {
1204
1204
.name = "sclk_mmc",
1205
-
.devname = "s3c-sdhci.0",
1205
+
.devname = "exynos4-sdhci.0",
1206
1206
.parent = &exynos4_clk_dout_mmc0.clk,
1207
1207
.enable = exynos4_clksrc_mask_fsys_ctrl,
1208
1208
.ctrlbit = (1 << 0),
···
1213
1213
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1214
1214
.clk = {
1215
1215
.name = "sclk_mmc",
1216
-
.devname = "s3c-sdhci.1",
1216
+
.devname = "exynos4-sdhci.1",
1217
1217
.parent = &exynos4_clk_dout_mmc1.clk,
1218
1218
.enable = exynos4_clksrc_mask_fsys_ctrl,
1219
1219
.ctrlbit = (1 << 4),
···
1224
1224
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1225
1225
.clk = {
1226
1226
.name = "sclk_mmc",
1227
-
.devname = "s3c-sdhci.2",
1227
+
.devname = "exynos4-sdhci.2",
1228
1228
.parent = &exynos4_clk_dout_mmc2.clk,
1229
1229
.enable = exynos4_clksrc_mask_fsys_ctrl,
1230
1230
.ctrlbit = (1 << 8),
···
1235
1235
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1236
1236
.clk = {
1237
1237
.name = "sclk_mmc",
1238
-
.devname = "s3c-sdhci.3",
1238
+
.devname = "exynos4-sdhci.3",
1239
1239
.parent = &exynos4_clk_dout_mmc3.clk,
1240
1240
.enable = exynos4_clksrc_mask_fsys_ctrl,
1241
1241
.ctrlbit = (1 << 12),
···
1340
1340
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1341
1341
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1342
1342
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1343
-
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1344
-
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1345
-
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1346
-
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1343
+
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1344
+
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1345
+
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1346
+
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1347
1347
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1348
1348
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1349
1349
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+12
-12
arch/arm/mach-exynos/clock-exynos5.c
+12
-12
arch/arm/mach-exynos/clock-exynos5.c
···
455
455
.ctrlbit = (1 << 20),
456
456
}, {
457
457
.name = "hsmmc",
458
-
.devname = "s3c-sdhci.0",
458
+
.devname = "exynos4-sdhci.0",
459
459
.parent = &exynos5_clk_aclk_200.clk,
460
460
.enable = exynos5_clk_ip_fsys_ctrl,
461
461
.ctrlbit = (1 << 12),
462
462
}, {
463
463
.name = "hsmmc",
464
-
.devname = "s3c-sdhci.1",
464
+
.devname = "exynos4-sdhci.1",
465
465
.parent = &exynos5_clk_aclk_200.clk,
466
466
.enable = exynos5_clk_ip_fsys_ctrl,
467
467
.ctrlbit = (1 << 13),
468
468
}, {
469
469
.name = "hsmmc",
470
-
.devname = "s3c-sdhci.2",
470
+
.devname = "exynos4-sdhci.2",
471
471
.parent = &exynos5_clk_aclk_200.clk,
472
472
.enable = exynos5_clk_ip_fsys_ctrl,
473
473
.ctrlbit = (1 << 14),
474
474
}, {
475
475
.name = "hsmmc",
476
-
.devname = "s3c-sdhci.3",
476
+
.devname = "exynos4-sdhci.3",
477
477
.parent = &exynos5_clk_aclk_200.clk,
478
478
.enable = exynos5_clk_ip_fsys_ctrl,
479
479
.ctrlbit = (1 << 15),
···
813
813
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
814
814
.clk = {
815
815
.name = "sclk_mmc",
816
-
.devname = "s3c-sdhci.0",
816
+
.devname = "exynos4-sdhci.0",
817
817
.parent = &exynos5_clk_dout_mmc0.clk,
818
818
.enable = exynos5_clksrc_mask_fsys_ctrl,
819
819
.ctrlbit = (1 << 0),
···
824
824
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
825
825
.clk = {
826
826
.name = "sclk_mmc",
827
-
.devname = "s3c-sdhci.1",
827
+
.devname = "exynos4-sdhci.1",
828
828
.parent = &exynos5_clk_dout_mmc1.clk,
829
829
.enable = exynos5_clksrc_mask_fsys_ctrl,
830
830
.ctrlbit = (1 << 4),
···
835
835
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
836
836
.clk = {
837
837
.name = "sclk_mmc",
838
-
.devname = "s3c-sdhci.2",
838
+
.devname = "exynos4-sdhci.2",
839
839
.parent = &exynos5_clk_dout_mmc2.clk,
840
840
.enable = exynos5_clksrc_mask_fsys_ctrl,
841
841
.ctrlbit = (1 << 8),
···
846
846
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
847
847
.clk = {
848
848
.name = "sclk_mmc",
849
-
.devname = "s3c-sdhci.3",
849
+
.devname = "exynos4-sdhci.3",
850
850
.parent = &exynos5_clk_dout_mmc3.clk,
851
851
.enable = exynos5_clksrc_mask_fsys_ctrl,
852
852
.ctrlbit = (1 << 12),
···
990
990
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
991
991
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
992
992
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
993
-
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
994
-
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
995
-
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
996
-
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
993
+
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
994
+
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
995
+
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
996
+
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
997
997
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
998
998
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
999
999
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+13
-1
arch/arm/mach-exynos/common.c
+13
-1
arch/arm/mach-exynos/common.c
···
326
326
s3c_fimc_setname(2, "exynos4-fimc");
327
327
s3c_fimc_setname(3, "exynos4-fimc");
328
328
329
+
s3c_sdhci_setname(0, "exynos4-sdhci");
330
+
s3c_sdhci_setname(1, "exynos4-sdhci");
331
+
s3c_sdhci_setname(2, "exynos4-sdhci");
332
+
s3c_sdhci_setname(3, "exynos4-sdhci");
333
+
329
334
/* The I2C bus controllers are directly compatible with s3c2440 */
330
335
s3c_i2c0_setname("s3c2440-i2c");
331
336
s3c_i2c1_setname("s3c2440-i2c");
···
348
343
s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
349
344
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
350
345
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
346
+
347
+
s3c_sdhci_setname(0, "exynos4-sdhci");
348
+
s3c_sdhci_setname(1, "exynos4-sdhci");
349
+
s3c_sdhci_setname(2, "exynos4-sdhci");
350
+
s3c_sdhci_setname(3, "exynos4-sdhci");
351
351
352
352
/* The I2C bus controllers are directly compatible with s3c2440 */
353
353
s3c_i2c0_setname("s3c2440-i2c");
···
547
537
{
548
538
int irq;
549
539
550
-
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
540
+
#ifdef CONFIG_OF
541
+
of_irq_init(exynos4_dt_irq_match);
542
+
#endif
551
543
552
544
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
553
545
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+3
-10
arch/arm/mach-exynos/dev-dwmci.c
+3
-10
arch/arm/mach-exynos/dev-dwmci.c
···
16
16
#include <linux/dma-mapping.h>
17
17
#include <linux/platform_device.h>
18
18
#include <linux/interrupt.h>
19
+
#include <linux/ioport.h>
19
20
#include <linux/mmc/dw_mmc.h>
20
21
21
22
#include <plat/devs.h>
···
34
33
}
35
34
36
35
static struct resource exynos4_dwmci_resource[] = {
37
-
[0] = {
38
-
.start = EXYNOS4_PA_DWMCI,
39
-
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
40
-
.flags = IORESOURCE_MEM,
41
-
},
42
-
[1] = {
43
-
.start = IRQ_DWMCI,
44
-
.end = IRQ_DWMCI,
45
-
.flags = IORESOURCE_IRQ,
46
-
}
36
+
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
37
+
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
47
38
};
48
39
49
40
static struct dw_mci_board exynos4_dwci_pdata = {
+1
arch/arm/mach-exynos/mach-nuri.c
+1
arch/arm/mach-exynos/mach-nuri.c
+1
arch/arm/mach-exynos/mach-universal_c210.c
+1
arch/arm/mach-exynos/mach-universal_c210.c
+15
-10
arch/arm/mach-msm/board-msm8x60.c
+15
-10
arch/arm/mach-msm/board-msm8x60.c
···
17
17
#include <linux/irqdomain.h>
18
18
#include <linux/of.h>
19
19
#include <linux/of_address.h>
20
+
#include <linux/of_irq.h>
20
21
#include <linux/of_platform.h>
21
22
#include <linux/memblock.h>
22
23
···
50
49
msm_map_msm8x60_io();
51
50
}
52
51
52
+
#ifdef CONFIG_OF
53
+
static struct of_device_id msm_dt_gic_match[] __initdata = {
54
+
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
55
+
{}
56
+
};
57
+
#endif
58
+
53
59
static void __init msm8x60_init_irq(void)
54
60
{
55
-
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
56
-
(void *)MSM_QGIC_CPU_BASE);
61
+
if (!of_have_populated_dt())
62
+
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
63
+
(void *)MSM_QGIC_CPU_BASE);
64
+
#ifdef CONFIG_OF
65
+
else
66
+
of_irq_init(msm_dt_gic_match);
67
+
#endif
57
68
58
69
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
59
70
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
···
86
73
{}
87
74
};
88
75
89
-
static struct of_device_id msm_dt_gic_match[] __initdata = {
90
-
{ .compatible = "qcom,msm-8660-qgic", },
91
-
{}
92
-
};
93
-
94
76
static void __init msm8x60_dt_init(void)
95
77
{
96
-
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
97
-
GIC_SPI_START);
98
-
99
78
if (of_machine_is_compatible("qcom,msm8660-surf")) {
100
79
printk(KERN_INFO "Init surf UART registers\n");
101
80
msm8x60_init_uart12dm();
+7
arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+7
arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
···
17
17
*
18
18
* bit 23 - Input/Output (PXA2xx specific)
19
19
* bit 24 - Wakeup Enable(PXA2xx specific)
20
+
* bit 25 - Keep Output (PXA2xx specific)
20
21
*/
21
22
22
23
#define MFP_DIR_IN (0x0 << 23)
···
26
25
#define MFP_DIR(x) (((x) >> 23) & 0x1)
27
26
28
27
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
28
+
29
+
/*
30
+
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
31
+
* retain their last output level (low or high).
32
+
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
33
+
*/
29
34
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
30
35
31
36
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
+19
-2
arch/arm/mach-pxa/mfp-pxa2xx.c
+19
-2
arch/arm/mach-pxa/mfp-pxa2xx.c
···
33
33
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
34
34
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
35
35
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
36
+
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
37
+
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
36
38
37
39
#define PWER_WE35 (1 << 24)
38
40
···
350
348
#ifdef CONFIG_PM
351
349
static unsigned long saved_gafr[2][4];
352
350
static unsigned long saved_gpdr[4];
351
+
static unsigned long saved_gplr[4];
353
352
static unsigned long saved_pgsr[4];
354
353
355
354
static int pxa2xx_mfp_suspend(void)
···
369
366
}
370
367
371
368
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
372
-
373
369
saved_gafr[0][i] = GAFR_L(i);
374
370
saved_gafr[1][i] = GAFR_U(i);
375
371
saved_gpdr[i] = GPDR(i * 32);
372
+
saved_gplr[i] = GPLR(i * 32);
376
373
saved_pgsr[i] = PGSR(i);
377
374
378
-
GPDR(i * 32) = gpdr_lpm[i];
375
+
GPSR(i * 32) = PGSR(i);
376
+
GPCR(i * 32) = ~PGSR(i);
379
377
}
378
+
379
+
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
380
+
for (i = 0; i < pxa_last_gpio; i++) {
381
+
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
382
+
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
383
+
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
384
+
GPDR(i) |= GPIO_bit(i);
385
+
else
386
+
GPDR(i) &= ~GPIO_bit(i);
387
+
}
388
+
380
389
return 0;
381
390
}
382
391
···
399
384
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
400
385
GAFR_L(i) = saved_gafr[0][i];
401
386
GAFR_U(i) = saved_gafr[1][i];
387
+
GPSR(i * 32) = saved_gplr[i];
388
+
GPCR(i * 32) = ~saved_gplr[i];
402
389
GPDR(i * 32) = saved_gpdr[i];
403
390
PGSR(i) = saved_pgsr[i];
404
391
}
+5
-1
arch/arm/mach-pxa/pxa27x.c
+5
-1
arch/arm/mach-pxa/pxa27x.c
···
421
421
pxa_register_device(&pxa27x_device_i2c_power, info);
422
422
}
423
423
424
+
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
425
+
.gpio_set_wake = gpio_set_wake,
426
+
};
427
+
424
428
static struct platform_device *devices[] __initdata = {
425
-
&pxa_device_gpio,
426
429
&pxa27x_device_udc,
427
430
&pxa_device_pmu,
428
431
&pxa_device_i2s,
···
461
458
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
462
459
register_syscore_ops(&pxa2xx_clock_syscore_ops);
463
460
461
+
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
464
462
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
465
463
}
466
464
+4
-4
arch/arm/mach-s3c24xx/Kconfig
+4
-4
arch/arm/mach-s3c24xx/Kconfig
···
111
111
help
112
112
Compile in platform device definition for Samsung TouchScreen.
113
113
114
-
# cpu-specific sections
115
-
116
-
if CPU_S3C2410
117
-
118
114
config S3C2410_DMA
119
115
bool
120
116
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
···
122
126
bool
123
127
help
124
128
Power Management code common to S3C2410 and better
129
+
130
+
# cpu-specific sections
131
+
132
+
if CPU_S3C2410
125
133
126
134
config S3C24XX_SIMTEC_NOR
127
135
bool
+2
arch/arm/mach-s5pv210/mach-goni.c
+2
arch/arm/mach-s5pv210/mach-goni.c
···
25
25
#include <linux/gpio_keys.h>
26
26
#include <linux/input.h>
27
27
#include <linux/gpio.h>
28
+
#include <linux/mmc/host.h>
28
29
#include <linux/interrupt.h>
29
30
30
31
#include <asm/hardware/vic.h>
···
766
765
/* MoviNAND */
767
766
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
768
767
.max_width = 4,
768
+
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
769
769
.cd_type = S3C_SDHCI_CD_PERMANENT,
770
770
};
771
771
+1
-1
arch/arm/mach-sa1100/generic.c
+1
-1
arch/arm/mach-sa1100/generic.c
+4
-2
arch/arm/mach-u300/core.c
+4
-2
arch/arm/mach-u300/core.c
···
1667
1667
1668
1668
for (i = 0; i < U300_VIC_IRQS_END; i++)
1669
1669
set_bit(i, (unsigned long *) &mask[0]);
1670
-
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1671
-
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1670
+
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1671
+
mask[0], mask[0]);
1672
+
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1673
+
mask[1], mask[1]);
1672
1674
}
1673
1675
1674
1676
+1
-8
arch/arm/mach-u300/i2c.c
+1
-8
arch/arm/mach-u300/i2c.c
···
146
146
.min_uV = 1800000,
147
147
.max_uV = 1800000,
148
148
.valid_modes_mask = REGULATOR_MODE_NORMAL,
149
-
.valid_ops_mask =
150
-
REGULATOR_CHANGE_VOLTAGE |
151
-
REGULATOR_CHANGE_STATUS,
152
149
.always_on = 1,
153
150
.boot_on = 1,
154
151
},
···
157
160
.min_uV = 2500000,
158
161
.max_uV = 2500000,
159
162
.valid_modes_mask = REGULATOR_MODE_NORMAL,
160
-
.valid_ops_mask =
161
-
REGULATOR_CHANGE_VOLTAGE |
162
-
REGULATOR_CHANGE_STATUS,
163
163
.always_on = 1,
164
164
.boot_on = 1,
165
165
},
···
224
230
.max_uV = 1800000,
225
231
.valid_modes_mask = REGULATOR_MODE_NORMAL,
226
232
.valid_ops_mask =
227
-
REGULATOR_CHANGE_VOLTAGE |
228
-
REGULATOR_CHANGE_STATUS,
233
+
REGULATOR_CHANGE_VOLTAGE,
229
234
.always_on = 1,
230
235
.boot_on = 1,
231
236
},
+75
-75
arch/arm/mach-u300/include/mach/irqs.h
+75
-75
arch/arm/mach-u300/include/mach/irqs.h
···
12
12
#ifndef __MACH_IRQS_H
13
13
#define __MACH_IRQS_H
14
14
15
-
#define IRQ_U300_INTCON0_START 0
16
-
#define IRQ_U300_INTCON1_START 32
15
+
#define IRQ_U300_INTCON0_START 1
16
+
#define IRQ_U300_INTCON1_START 33
17
17
/* These are on INTCON0 - 30 lines */
18
-
#define IRQ_U300_IRQ0_EXT 0
19
-
#define IRQ_U300_IRQ1_EXT 1
20
-
#define IRQ_U300_DMA 2
21
-
#define IRQ_U300_VIDEO_ENC_0 3
22
-
#define IRQ_U300_VIDEO_ENC_1 4
23
-
#define IRQ_U300_AAIF_RX 5
24
-
#define IRQ_U300_AAIF_TX 6
25
-
#define IRQ_U300_AAIF_VGPIO 7
26
-
#define IRQ_U300_AAIF_WAKEUP 8
27
-
#define IRQ_U300_PCM_I2S0_FRAME 9
28
-
#define IRQ_U300_PCM_I2S0_FIFO 10
29
-
#define IRQ_U300_PCM_I2S1_FRAME 11
30
-
#define IRQ_U300_PCM_I2S1_FIFO 12
31
-
#define IRQ_U300_XGAM_GAMCON 13
32
-
#define IRQ_U300_XGAM_CDI 14
33
-
#define IRQ_U300_XGAM_CDICON 15
18
+
#define IRQ_U300_IRQ0_EXT 1
19
+
#define IRQ_U300_IRQ1_EXT 2
20
+
#define IRQ_U300_DMA 3
21
+
#define IRQ_U300_VIDEO_ENC_0 4
22
+
#define IRQ_U300_VIDEO_ENC_1 5
23
+
#define IRQ_U300_AAIF_RX 6
24
+
#define IRQ_U300_AAIF_TX 7
25
+
#define IRQ_U300_AAIF_VGPIO 8
26
+
#define IRQ_U300_AAIF_WAKEUP 9
27
+
#define IRQ_U300_PCM_I2S0_FRAME 10
28
+
#define IRQ_U300_PCM_I2S0_FIFO 11
29
+
#define IRQ_U300_PCM_I2S1_FRAME 12
30
+
#define IRQ_U300_PCM_I2S1_FIFO 13
31
+
#define IRQ_U300_XGAM_GAMCON 14
32
+
#define IRQ_U300_XGAM_CDI 15
33
+
#define IRQ_U300_XGAM_CDICON 16
34
34
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
35
35
/* MMIACC not used on the DB3210 or DB3350 chips */
36
-
#define IRQ_U300_XGAM_MMIACC 16
36
+
#define IRQ_U300_XGAM_MMIACC 17
37
37
#endif
38
-
#define IRQ_U300_XGAM_PDI 17
39
-
#define IRQ_U300_XGAM_PDICON 18
40
-
#define IRQ_U300_XGAM_GAMEACC 19
41
-
#define IRQ_U300_XGAM_MCIDCT 20
42
-
#define IRQ_U300_APEX 21
43
-
#define IRQ_U300_UART0 22
44
-
#define IRQ_U300_SPI 23
45
-
#define IRQ_U300_TIMER_APP_OS 24
46
-
#define IRQ_U300_TIMER_APP_DD 25
47
-
#define IRQ_U300_TIMER_APP_GP1 26
48
-
#define IRQ_U300_TIMER_APP_GP2 27
49
-
#define IRQ_U300_TIMER_OS 28
50
-
#define IRQ_U300_TIMER_MS 29
51
-
#define IRQ_U300_KEYPAD_KEYBF 30
52
-
#define IRQ_U300_KEYPAD_KEYBR 31
38
+
#define IRQ_U300_XGAM_PDI 18
39
+
#define IRQ_U300_XGAM_PDICON 19
40
+
#define IRQ_U300_XGAM_GAMEACC 20
41
+
#define IRQ_U300_XGAM_MCIDCT 21
42
+
#define IRQ_U300_APEX 22
43
+
#define IRQ_U300_UART0 23
44
+
#define IRQ_U300_SPI 24
45
+
#define IRQ_U300_TIMER_APP_OS 25
46
+
#define IRQ_U300_TIMER_APP_DD 26
47
+
#define IRQ_U300_TIMER_APP_GP1 27
48
+
#define IRQ_U300_TIMER_APP_GP2 28
49
+
#define IRQ_U300_TIMER_OS 29
50
+
#define IRQ_U300_TIMER_MS 30
51
+
#define IRQ_U300_KEYPAD_KEYBF 31
52
+
#define IRQ_U300_KEYPAD_KEYBR 32
53
53
/* These are on INTCON1 - 32 lines */
54
-
#define IRQ_U300_GPIO_PORT0 32
55
-
#define IRQ_U300_GPIO_PORT1 33
56
-
#define IRQ_U300_GPIO_PORT2 34
54
+
#define IRQ_U300_GPIO_PORT0 33
55
+
#define IRQ_U300_GPIO_PORT1 34
56
+
#define IRQ_U300_GPIO_PORT2 35
57
57
58
58
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
59
59
defined(CONFIG_MACH_U300_BS335)
60
60
/* These are for DB3150, DB3200 and DB3350 */
61
-
#define IRQ_U300_WDOG 35
62
-
#define IRQ_U300_EVHIST 36
63
-
#define IRQ_U300_MSPRO 37
64
-
#define IRQ_U300_MMCSD_MCIINTR0 38
65
-
#define IRQ_U300_MMCSD_MCIINTR1 39
66
-
#define IRQ_U300_I2C0 40
67
-
#define IRQ_U300_I2C1 41
68
-
#define IRQ_U300_RTC 42
69
-
#define IRQ_U300_NFIF 43
70
-
#define IRQ_U300_NFIF2 44
61
+
#define IRQ_U300_WDOG 36
62
+
#define IRQ_U300_EVHIST 37
63
+
#define IRQ_U300_MSPRO 38
64
+
#define IRQ_U300_MMCSD_MCIINTR0 39
65
+
#define IRQ_U300_MMCSD_MCIINTR1 40
66
+
#define IRQ_U300_I2C0 41
67
+
#define IRQ_U300_I2C1 42
68
+
#define IRQ_U300_RTC 43
69
+
#define IRQ_U300_NFIF 44
70
+
#define IRQ_U300_NFIF2 45
71
71
#endif
72
72
73
73
/* DB3150 and DB3200 have only 45 IRQs */
74
74
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
75
-
#define U300_VIC_IRQS_END 45
75
+
#define U300_VIC_IRQS_END 46
76
76
#endif
77
77
78
78
/* The DB3350-specific interrupt lines */
79
79
#ifdef CONFIG_MACH_U300_BS335
80
-
#define IRQ_U300_ISP_F0 45
81
-
#define IRQ_U300_ISP_F1 46
82
-
#define IRQ_U300_ISP_F2 47
83
-
#define IRQ_U300_ISP_F3 48
84
-
#define IRQ_U300_ISP_F4 49
85
-
#define IRQ_U300_GPIO_PORT3 50
86
-
#define IRQ_U300_SYSCON_PLL_LOCK 51
87
-
#define IRQ_U300_UART1 52
88
-
#define IRQ_U300_GPIO_PORT4 53
89
-
#define IRQ_U300_GPIO_PORT5 54
90
-
#define IRQ_U300_GPIO_PORT6 55
91
-
#define U300_VIC_IRQS_END 56
80
+
#define IRQ_U300_ISP_F0 46
81
+
#define IRQ_U300_ISP_F1 47
82
+
#define IRQ_U300_ISP_F2 48
83
+
#define IRQ_U300_ISP_F3 49
84
+
#define IRQ_U300_ISP_F4 50
85
+
#define IRQ_U300_GPIO_PORT3 51
86
+
#define IRQ_U300_SYSCON_PLL_LOCK 52
87
+
#define IRQ_U300_UART1 53
88
+
#define IRQ_U300_GPIO_PORT4 54
89
+
#define IRQ_U300_GPIO_PORT5 55
90
+
#define IRQ_U300_GPIO_PORT6 56
91
+
#define U300_VIC_IRQS_END 57
92
92
#endif
93
93
94
94
/* The DB3210-specific interrupt lines */
95
95
#ifdef CONFIG_MACH_U300_BS365
96
-
#define IRQ_U300_GPIO_PORT3 35
97
-
#define IRQ_U300_GPIO_PORT4 36
98
-
#define IRQ_U300_WDOG 37
99
-
#define IRQ_U300_EVHIST 38
100
-
#define IRQ_U300_MSPRO 39
101
-
#define IRQ_U300_MMCSD_MCIINTR0 40
102
-
#define IRQ_U300_MMCSD_MCIINTR1 41
103
-
#define IRQ_U300_I2C0 42
104
-
#define IRQ_U300_I2C1 43
105
-
#define IRQ_U300_RTC 44
106
-
#define IRQ_U300_NFIF 45
107
-
#define IRQ_U300_NFIF2 46
108
-
#define IRQ_U300_SYSCON_PLL_LOCK 47
109
-
#define U300_VIC_IRQS_END 48
96
+
#define IRQ_U300_GPIO_PORT3 36
97
+
#define IRQ_U300_GPIO_PORT4 37
98
+
#define IRQ_U300_WDOG 38
99
+
#define IRQ_U300_EVHIST 39
100
+
#define IRQ_U300_MSPRO 40
101
+
#define IRQ_U300_MMCSD_MCIINTR0 41
102
+
#define IRQ_U300_MMCSD_MCIINTR1 42
103
+
#define IRQ_U300_I2C0 43
104
+
#define IRQ_U300_I2C1 44
105
+
#define IRQ_U300_RTC 45
106
+
#define IRQ_U300_NFIF 46
107
+
#define IRQ_U300_NFIF2 47
108
+
#define IRQ_U300_SYSCON_PLL_LOCK 48
109
+
#define U300_VIC_IRQS_END 49
110
110
#endif
111
111
112
112
/* Maximum 8*7 GPIO lines */
···
117
117
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
118
118
#endif
119
119
120
-
#define NR_IRQS (IRQ_U300_GPIO_END)
120
+
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
121
121
122
122
#endif
+28
arch/arm/plat-samsung/include/plat/sdhci.h
+28
arch/arm/plat-samsung/include/plat/sdhci.h
···
18
18
#ifndef __PLAT_S3C_SDHCI_H
19
19
#define __PLAT_S3C_SDHCI_H __FILE__
20
20
21
+
#include <plat/devs.h>
22
+
21
23
struct platform_device;
22
24
struct mmc_host;
23
25
struct mmc_card;
···
357
355
static inline void exynos4_default_sdhci3(void) { }
358
356
359
357
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
358
+
359
+
static inline void s3c_sdhci_setname(int id, char *name)
360
+
{
361
+
switch (id) {
362
+
#ifdef CONFIG_S3C_DEV_HSMMC
363
+
case 0:
364
+
s3c_device_hsmmc0.name = name;
365
+
break;
366
+
#endif
367
+
#ifdef CONFIG_S3C_DEV_HSMMC1
368
+
case 1:
369
+
s3c_device_hsmmc1.name = name;
370
+
break;
371
+
#endif
372
+
#ifdef CONFIG_S3C_DEV_HSMMC2
373
+
case 2:
374
+
s3c_device_hsmmc2.name = name;
375
+
break;
376
+
#endif
377
+
#ifdef CONFIG_S3C_DEV_HSMMC3
378
+
case 3:
379
+
s3c_device_hsmmc3.name = name;
380
+
break;
381
+
#endif
382
+
}
383
+
}
360
384
361
385
#endif /* __PLAT_S3C_SDHCI_H */
+19
-2
drivers/gpio/gpio-pxa.c
+19
-2
drivers/gpio/gpio-pxa.c
···
64
64
unsigned long irq_mask;
65
65
unsigned long irq_edge_rise;
66
66
unsigned long irq_edge_fall;
67
+
int (*set_wake)(unsigned int gpio, unsigned int on);
67
68
68
69
#ifdef CONFIG_PM
69
70
unsigned long saved_gplr;
···
270
269
(value ? GPSR_OFFSET : GPCR_OFFSET));
271
270
}
272
271
273
-
static int __devinit pxa_init_gpio_chip(int gpio_end)
272
+
static int __devinit pxa_init_gpio_chip(int gpio_end,
273
+
int (*set_wake)(unsigned int, unsigned int))
274
274
{
275
275
int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
276
276
struct pxa_gpio_chip *chips;
···
287
285
288
286
sprintf(chips[i].label, "gpio-%d", i);
289
287
chips[i].regbase = gpio_reg_base + BANK_OFF(i);
288
+
chips[i].set_wake = set_wake;
290
289
291
290
c->base = gpio;
292
291
c->label = chips[i].label;
···
415
412
writel_relaxed(gfer, c->regbase + GFER_OFFSET);
416
413
}
417
414
415
+
static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
416
+
{
417
+
int gpio = pxa_irq_to_gpio(d->irq);
418
+
struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
419
+
420
+
if (c->set_wake)
421
+
return c->set_wake(gpio, on);
422
+
else
423
+
return 0;
424
+
}
425
+
418
426
static void pxa_unmask_muxed_gpio(struct irq_data *d)
419
427
{
420
428
int gpio = pxa_irq_to_gpio(d->irq);
···
441
427
.irq_mask = pxa_mask_muxed_gpio,
442
428
.irq_unmask = pxa_unmask_muxed_gpio,
443
429
.irq_set_type = pxa_gpio_irq_type,
430
+
.irq_set_wake = pxa_gpio_set_wake,
444
431
};
445
432
446
433
static int pxa_gpio_nums(void)
···
486
471
struct pxa_gpio_chip *c;
487
472
struct resource *res;
488
473
struct clk *clk;
474
+
struct pxa_gpio_platform_data *info;
489
475
int gpio, irq, ret;
490
476
int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
491
477
···
532
516
}
533
517
534
518
/* Initialize GPIO chips */
535
-
pxa_init_gpio_chip(pxa_last_gpio);
519
+
info = dev_get_platdata(&pdev->dev);
520
+
pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
536
521
537
522
/* clear all GPIO edge detects */
538
523
for_each_gpio_chip(gpio, c) {