Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i3c: mipi-i3c-hci: Add optional Runtime PM support
Implement optional Runtime PM support for the MIPI I3C HCI driver.
Introduce runtime suspend and resume callbacks to manage bus state and
restore hardware configuration after resume. Optionally enable autosuspend
with a default delay of 1 second, and add helper functions to control
Runtime PM during probe and remove.
Read quirks from i3c_hci_driver_ids[] and set new quirk
HCI_QUIRK_RPM_ALLOWED for intel-lpss-i3c devices to enable runtime PM for
them.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260113072702.16268-21-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
authored by
Adrian Hunter
and committed by
Alexandre Belloni
b9a15012
990c149c
+72
-6
+70
-6
drivers/i3c/master/mipi-i3c-hci/core.c
+70
-6
drivers/i3c/master/mipi-i3c-hci/core.c
···
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#include <linux/module.h>
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#include <linux/platform_data/mipi-i3c-hci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "hci.h"
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#include "ext_caps.h"
···
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int irq = platform_get_irq(pdev, 0);
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reg_write(INTR_SIGNAL_ENABLE, 0x0);
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hci->irq_inactive = true;
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synchronize_irq(irq);
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}
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···
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irqreturn_t result = IRQ_NONE;
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u32 val;
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/*
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* The IRQ can be shared, so the handler may be called when the IRQ is
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* due to a different device. That could happen when runtime suspended,
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* so exit immediately if IRQs are not expected for this device.
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*/
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if (hci->irq_inactive)
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return IRQ_NONE;
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val = reg_read(INTR_STATUS);
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reg_write(INTR_STATUS, val);
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dev_dbg(&hci->master.dev, "INTR_STATUS %#x", val);
···
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return 0;
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}
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static int i3c_hci_runtime_suspend(struct device *dev)
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{
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struct i3c_hci *hci = dev_get_drvdata(dev);
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int ret;
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ret = i3c_hci_bus_disable(hci);
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if (ret)
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return ret;
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hci->io->suspend(hci);
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return 0;
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}
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static int i3c_hci_runtime_resume(struct device *dev)
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{
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struct i3c_hci *hci = dev_get_drvdata(dev);
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int ret;
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ret = i3c_hci_reset_and_init(hci);
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if (ret)
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return -EIO;
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i3c_hci_set_master_dyn_addr(hci);
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mipi_i3c_hci_dat_v1.restore(hci);
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hci->irq_inactive = false;
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hci->io->resume(hci);
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reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
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return 0;
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}
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#define DEFAULT_AUTOSUSPEND_DELAY_MS 1000
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static void i3c_hci_rpm_enable(struct device *dev)
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{
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struct i3c_hci *hci = dev_get_drvdata(dev);
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pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY_MS);
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pm_runtime_use_autosuspend(dev);
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devm_pm_runtime_set_active_enabled(dev);
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hci->master.rpm_allowed = true;
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}
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static int i3c_hci_init(struct i3c_hci *hci)
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{
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bool size_in_dwords;
···
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hci->master.dev.init_name = dev_name(&pdev->dev);
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hci->quirks = (unsigned long)device_get_match_data(&pdev->dev);
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if (!hci->quirks && platform_get_device_id(pdev))
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hci->quirks = platform_get_device_id(pdev)->driver_data;
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ret = i3c_hci_init(hci);
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if (ret)
···
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if (ret)
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return ret;
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ret = i3c_master_register(&hci->master, &pdev->dev,
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&i3c_hci_ops, false);
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if (ret)
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return ret;
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if (hci->quirks & HCI_QUIRK_RPM_ALLOWED)
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i3c_hci_rpm_enable(&pdev->dev);
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return 0;
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return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false);
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}
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static void i3c_hci_remove(struct platform_device *pdev)
···
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MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match);
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static const struct platform_device_id i3c_hci_driver_ids[] = {
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{ .name = "intel-lpss-i3c" },
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{ .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
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static const struct dev_pm_ops i3c_hci_pm_ops = {
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RUNTIME_PM_OPS(i3c_hci_runtime_suspend, i3c_hci_runtime_resume, NULL)
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};
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static struct platform_driver i3c_hci_driver = {
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.probe = i3c_hci_probe,
···
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.name = "mipi-i3c-hci",
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.of_match_table = of_match_ptr(i3c_hci_of_match),
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.acpi_match_table = i3c_hci_acpi_match,
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.pm = pm_ptr(&i3c_hci_pm_ops),
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},
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};
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module_platform_driver(i3c_hci_driver);
+2
drivers/i3c/master/mipi-i3c-hci/hci.h
+2
drivers/i3c/master/mipi-i3c-hci/hci.h
···
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void *io_data;
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const struct hci_cmd_ops *cmd;
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atomic_t next_cmd_tid;
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bool irq_inactive;
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u32 caps;
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unsigned int quirks;
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unsigned int DAT_entries;
···
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#define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */
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#define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */
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#define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */
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#define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */
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/* global functions */
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void mipi_i3c_hci_resume(struct i3c_hci *hci);